JP4728032B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Semiconductor device and manufacturing method of semiconductor device Download PDF

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JP4728032B2
JP4728032B2 JP2005118565A JP2005118565A JP4728032B2 JP 4728032 B2 JP4728032 B2 JP 4728032B2 JP 2005118565 A JP2005118565 A JP 2005118565A JP 2005118565 A JP2005118565 A JP 2005118565A JP 4728032 B2 JP4728032 B2 JP 4728032B2
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substrate
layer
cutting line
metal layer
original substrate
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JP2006302957A (en
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泰正 糟谷
貞雅 藤井
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Rohm Co Ltd
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Priority to JP2005118565A priority Critical patent/JP4728032B2/en
Priority to PCT/JP2006/307777 priority patent/WO2006112337A1/en
Priority to US11/918,211 priority patent/US20090289342A1/en
Priority to KR1020077023205A priority patent/KR20080003802A/en
Priority to CN2006800121029A priority patent/CN101160657B/en
Priority to TW095113539A priority patent/TW200707666A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

この発明は、半導体チップおよびこの半導体チップを支持する支持基板を備える半導体装置およびこのような半導体装置の製造方法に関する。   The present invention relates to a semiconductor device including a semiconductor chip, a support substrate that supports the semiconductor chip, and a method of manufacturing such a semiconductor device.

従来から、半導体チップおよびこの半導体チップを一方面上に支持する支持基板を備え、その支持基板の他方面を実装基板(配線基板)の表面に対向させて、実装基板に実装される半導体装置が知られている。
支持基板は、その半導体チップが接合される一方面に、半導体チップと電気接続される内部端子が形成され、その一方面と反対側の他方面に、実装基板上のランド(電極)との電気接続のための外部端子が形成されている。また、支持基板の端面には、溝が形成されており、内部端子と外部端子とは、その溝の内面に沿って形成された接続配線によって電気的に接続されている。
2. Description of the Related Art Conventionally, a semiconductor device is provided that includes a semiconductor chip and a support substrate that supports the semiconductor chip on one surface, and the other surface of the support substrate faces the surface of the mounting substrate (wiring substrate). Are known.
The support substrate has an internal terminal electrically connected to the semiconductor chip formed on one surface to which the semiconductor chip is bonded, and an electrical connection with a land (electrode) on the mounting substrate on the other surface opposite to the one surface. External terminals for connection are formed. Further, a groove is formed on the end face of the support substrate, and the internal terminal and the external terminal are electrically connected by a connection wiring formed along the inner surface of the groove.

このような支持基板は、内部端子、外部端子および接続配線などがパターン形成された絶縁性を有する元基板を、格子状に設定された切断ライン(ダイシングライン)に沿って、ダイシングブレードなどの切断工具で切断することにより得られる。より具体的には、元基板の状態において、内部端子は、元基板の一方面上において、切断ラインに跨って形成されている。また、外部端子は、元基板の他方面上において、内部端子と対向する位置に形成されている。さらに、内部端子、元基板および外部端子を貫通するスルーホールが切断ラインを跨いで形成されており、そのスルーホールの内面には、金属めっき層が被着されている。そのため、元基板が切断ラインに沿って切断されると、内部端子および外部端子が切断ラインの両側の支持基板に分断されるとともに、スルーホールが切断ラインの両側の支持基板の端面の溝に分割されて、その溝の内面に被着した接続配線によって内部端子と外部端子とを接続された構成の支持基板が得られる。半導体チップは、たとえば、元基板が支持基板に切り分けられる前に、切断ラインに囲まれた接合領域に接合される。
特許第3214619号公報
Such a support substrate cuts a dicing blade or the like along a cutting line (dicing line) set in a lattice shape from an insulating original substrate on which internal terminals, external terminals, and connection wirings are patterned. It is obtained by cutting with a tool. More specifically, in the state of the original substrate, the internal terminal is formed across the cutting line on one surface of the original substrate. Further, the external terminal is formed at a position facing the internal terminal on the other surface of the original substrate. Furthermore, a through hole penetrating the internal terminal, the original substrate and the external terminal is formed across the cutting line, and a metal plating layer is deposited on the inner surface of the through hole. Therefore, when the original board is cut along the cutting line, the internal terminals and the external terminals are divided into the supporting boards on both sides of the cutting line, and the through holes are divided into grooves on the end faces of the supporting boards on both sides of the cutting line. Thus, a support substrate having a configuration in which the internal terminal and the external terminal are connected by the connection wiring attached to the inner surface of the groove is obtained. For example, the semiconductor chip is bonded to a bonding region surrounded by a cutting line before the original substrate is cut into the support substrate.
Japanese Patent No. 3214619

ところが、金属からなる外部端子は、延性を有するため、切断工具により切断される際に、元基板の一方面側から他方面側に抜けるように入れられる切断工具に引きづられて延び、いわゆる金属ばりを生じることがある。このような外部端子の金属ばりは、実装基板に対する半導体装置の実装不良を生じるおそれがある。すなわち、金属ばりが実装基板の表面に当接して、半導体装置を実装基板から浮き上がらせることによって、外部端子と実装基板の表面上のランドとの接続不良を生じるおそれがある。   However, since the external terminal made of metal has ductility, when it is cut by the cutting tool, it extends by being pulled by a cutting tool that is inserted so as to come out from one side of the original substrate to the other side, so-called metal. May cause burrs. Such a metal flash of the external terminal may cause a mounting failure of the semiconductor device on the mounting substrate. That is, when the metal beam comes into contact with the surface of the mounting substrate and the semiconductor device is lifted from the mounting substrate, there is a risk of causing a connection failure between the external terminal and the land on the surface of the mounting substrate.

そこで、この発明の目的は、外部端子の金属ばりによる実装不良(外部端子と実装基板上のランドとの接続不良)を生じるおそれがない半導体装置およびそのような半導体装置の製造方法を提供することである。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device that does not cause a mounting failure (connection failure between an external terminal and a land on a mounting substrate) due to a metal beam of an external terminal, and a method for manufacturing such a semiconductor device. It is.

上記の目的を達成するための請求項1記載の発明は、半導体装置において、半導体チップと、前記半導体チップを一方面上に支持し、直線状の端縁を有するとともに、前記端縁から内方に窪む溝が厚さ方向に貫通して形成された支持基板と、前記支持基板の前記一方面に設けられ、前記半導体チップと電気接続される内部端子と、前記支持基板の前記一方面と反対側の他方面に設けられ、前記支持基板の前記端縁から当該支持基板の内方に向けて延びる外部端子と、前記溝の内面に形成され、前記支持基板の前記一方面および前記他方面間を貫通し、前記内部端子と前記外部端子とを接続する接続配線とを含み、前記外部端子は、前記支持基板の前記端縁に接するように配置され、相対的に小さな厚みを有する薄部と、前記端縁から前記支持基板の内方へ離れた位置に配置され、相対的に大きな厚みを有する厚部とを一体的に備えていることを特徴としている。 According to a first aspect of the present invention for achieving the above object, in the semiconductor device, the semiconductor chip and the semiconductor chip are supported on one surface, have a linear edge, and extend inward from the edge. A support substrate formed by penetrating in a thickness direction, an internal terminal provided on the one surface of the support substrate and electrically connected to the semiconductor chip, and the one surface of the support substrate provided on the other surface opposite to the external terminal from the edge of the supporting substrate and extending inwardly of the supporting substrate, are formed on the inner surface of the groove, the one surface and the other surface of the support substrate passes between the internal terminal and includes a connection wiring and for connecting the external terminals, the external terminals are arranged so as to be in contact with the edge of the supporting substrate, a thin portion having a relatively small thickness When the support from the edge Disposed inwardly away of the plate, it is characterized in that it comprises integrally a thick portion having a relatively large thickness.

この構成によれば、外部端子は、支持基板の端縁に沿って配置され、相対的に小さな厚みを有する薄部と、この薄部に対して内方に配置され、相対的に大きな厚みを有する厚部とを一体的に備えている。すなわち、外部端子は、支持基板の端縁側の部分(薄部)が相対的に薄く形成され、支持基板の内方側の部分(厚部)が相対的に厚く形成されている。そのため、半導体装置の製造時に、外部端子の薄部に金属ばりが生じても、その金属ばりの長さが薄部と厚部との段差以下であれば、半導体装置の実装基板への実装時に、その金属ばりが実装基板の表面に当接することがない。よって、外部端子と実装基板上のランドとの接続不良などの実装不良を生じるおそれがない。   According to this configuration, the external terminal is disposed along the edge of the support substrate, and has a thin portion having a relatively small thickness, and is disposed inward with respect to the thin portion, and has a relatively large thickness. And a thick portion having the same. That is, the external terminal is formed such that a portion (thin portion) on the edge side of the support substrate is relatively thin and a portion (thick portion) on the inner side of the support substrate is relatively thick. Therefore, even when a metal flash occurs in the thin part of the external terminal during the manufacture of the semiconductor device, if the length of the metal flash is equal to or less than the step between the thin part and the thick part, the semiconductor device is mounted on the mounting substrate. The metal beam does not contact the surface of the mounting substrate. Therefore, there is no possibility of causing a mounting failure such as a connection failure between the external terminal and the land on the mounting substrate.

このような構成を有する半導体装置は、たとえば、請求項3に記載されている製造方法により製造することができる。
請求項3に記載の発明は、半導体チップとその半導体チップを支持する支持基板とを備える半導体装置を製造する方法であって、絶縁性を有する元基板の一方面における所定の切断ラインを跨る領域に、一方側金属層を形成する工程と、前記元基板の前記一方面と反対側の他方面において、前記一方側金属層に対して前記一方面と直交する方向に対向する位置に、他方側金属層を形成する工程と、前記切断ラインを跨る位置に、前記他方側金属層および前記元基板を連続して貫通する連続貫通孔を形成する工程と、前記他方側金属層の表面、前記連続貫通孔の内面および前記一方側金属層の前記連続貫通孔に臨む部分に第1金属めっき層を被着させる第1めっき工程と、前記第1金属めっき層の表面において、前記切断ラインに沿って延び、かつ、前記切断ラインを跨る所定幅の領域(前記他方側金属層よりも幅狭な領域)を除く領域に、第2金属めっき層を被着させる第2めっき工程と、前記第2めっき工程後、前記元基板と切断工具とを、前記切断工具が前記元基板の前記一方面側から前記他方面側へ抜けるように相対移動させて、前記元基板を前記切断ラインに沿って切断し、前記元基板を支持基板の個片に切り分ける切断工程とを含むことを特徴としている。
The semiconductor device having such a configuration can be manufactured by, for example, a manufacturing method described in claim 3.
The invention according to claim 3 is a method of manufacturing a semiconductor device comprising a semiconductor chip and a support substrate that supports the semiconductor chip, and is a region straddling a predetermined cutting line on one surface of the original substrate having insulation. And forming the one side metal layer on the other side opposite to the one side of the original substrate at a position facing the one side metal layer in a direction perpendicular to the one side. A step of forming a metal layer, a step of continuously forming the other side metal layer and the original substrate at a position straddling the cutting line, a surface of the other side metal layer, the continuous A first plating step of depositing a first metal plating layer on an inner surface of the through hole and a portion of the one side metal layer facing the continuous through hole; and on the surface of the first metal plating layer, along the cutting line Elongate, A second plating step of depositing a second metal plating layer on a region excluding a region having a predetermined width (a region narrower than the other-side metal layer) straddling the cutting line; and after the second plating step The original substrate and the cutting tool are moved relative to each other so that the cutting tool is pulled out from the one surface side of the original substrate to the other surface side, and the original substrate is cut along the cutting line, And a cutting step of cutting the original substrate into individual pieces of the support substrate.

この方法によれば、元基板の他方面上の他方側金属層の表面に第1金属めっき層が形成された後、その第1金属めっき層の表面において、切断ライン上の所定幅を除く領域に、第2金属めっき層が形成される。その後、切断工具によって、元基板が切断ラインに沿って切断される。
この元基板の切断時に、元基板の他方面において、切断ラインに沿った領域上には、他方側金属層および第1金属めっき層のみが形成され、それ以外の領域上には、他方側金属層、第1金属めっき層および第2金属めっき層が形成されている。すなわち、切断ラインに沿った領域上の金属層は、それ以外の領域上の金属層に比べて、厚みが薄く形成されている。そのため、切断工具を元基板の一方面側から他方面側へ抜けるように移動させることにより、切断ラインに沿った領域上の金属層に金属ばりが生じても、その金属ばりの長さが第2金属めっき層の厚みよりも小さければ、この製造方法によって製造される半導体装置が実装基板に実装される時に、その金属ばりが実装基板の表面に当接することがない。よって、外部端子と実装基板上のランドとの接続不良などの実装不良を生じるおそれがない。
According to this method, after the first metal plating layer is formed on the surface of the other metal layer on the other surface of the original substrate, the region excluding the predetermined width on the cutting line on the surface of the first metal plating layer In addition, a second metal plating layer is formed. Thereafter, the original substrate is cut along the cutting line by the cutting tool.
At the time of cutting the original substrate, only the other side metal layer and the first metal plating layer are formed on the region along the cutting line on the other surface of the original substrate, and the other side metal is formed on the other region. A layer, a first metal plating layer, and a second metal plating layer are formed. That is, the metal layer on the region along the cutting line is formed thinner than the metal layer on the other region. Therefore, by moving the cutting tool so that it can be pulled out from one side of the original substrate to the other side, even if a metal flash occurs in the metal layer on the region along the cutting line, the length of the metal flash is the first. If the thickness is smaller than the thickness of the two metal plating layer, the metal beam does not contact the surface of the mounting substrate when the semiconductor device manufactured by this manufacturing method is mounted on the mounting substrate. Therefore, there is no possibility of causing a mounting failure such as a connection failure between the external terminal and the land on the mounting substrate.

なお、元基板が切断ラインに沿って切断されると、切断ラインに跨る一方側金属層が2つに分断され、その分断後の各部分が切断ラインの両側の支持基板の内部端子となる。また、切断ラインに沿った切断によって、連続貫通孔の内面および一方側金属層の連続貫通孔に被着した第1金属めっき層が2つに分断され、その分断後の各部分が、切断ラインの両側の支持基板の内部端子に接続される接続配線となる。さらに、他方側金属層および第1金属めっき層が2つに分断され、各支持基板において、他方側金属層および第1金属めっき層の分断後の各部分ならびに第1金属めっき層に被着した第2金属めっき層が外部端子となる。   When the original substrate is cut along the cutting line, the one-side metal layer straddling the cutting line is divided into two, and each part after the division becomes an internal terminal of the support substrate on both sides of the cutting line. Further, the first metal plating layer deposited on the inner surface of the continuous through hole and the continuous through hole of the one side metal layer is divided into two by cutting along the cutting line, and each part after the cutting is cut into the cutting line. It becomes a connection wiring connected to the internal terminal of the support substrate on both sides of. Furthermore, the other side metal layer and the first metal plating layer were divided into two parts, and each part of the support substrate was attached to each part after the division of the other side metal layer and the first metal plating layer and the first metal plating layer. The second metal plating layer becomes an external terminal.

また、請求項2記載の発明は、請求項1記載の半導体装置において、前記薄部に対して前記支持基板と反対側に設けられ、前記薄部の厚みと前記厚部の厚みとの差以下の厚みを有するばり防止層をさらに含むことを特徴としている。
このような構成を有する半導体装置は、たとえば、請求項4に記載されている製造方法により製造することができる。
According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the semiconductor device is provided on a side opposite to the support substrate with respect to the thin portion, and is less than or equal to a difference between the thickness of the thin portion and the thickness of the thick portion. It further comprises a flash preventing layer having a thickness of 5 mm.
The semiconductor device having such a configuration can be manufactured by, for example, a manufacturing method described in claim 4.

請求項4記載の発明は、半導体チップとその半導体チップを支持する支持基板とを備える半導体装置を製造する方法であって、絶縁性を有する元基板の一方面における所定の切断ラインを跨る領域に、一方側金属層を形成する工程と、前記元基板の前記一方面と反対側の他方面において、前記一方側金属層に対して前記一方面と直交する方向に対向する位置に、他方側金属層を形成する工程と、前記切断ラインを跨る位置に、前記他方側金属層および前記元基板を連続して貫通する連続貫通孔を形成する工程と、前記他方側金属層の表面、前記連続貫通孔の内面および前記一方側金属層の前記連続貫通孔に臨む部分に第1金属めっき層を被着させる第1めっき工程と、前記第1めっき工程後、前記元基板の前記他方面上に、前記切断ラインを跨り、かつ、前記他方側金属層上の前記第1金属めっき層を前記切断ラインに沿う方向の全幅にわたって覆うように、絶縁性樹脂からなる絶縁樹脂層を形成する絶縁樹脂層形成工程と、前記第1金属めっき層の表面に第2金属めっき層を被着させる第2めっき工程と、前記第2めっき工程後、前記元基板と切断工具とを、前記切断工具が前記元基板の前記一方面側から前記他方面側へ抜けるように相対移動させて、前記元基板を前記切断ラインに沿って切断し、前記元基板を支持基板の個片に切り分ける切断工程とを含むことを特徴としている。 The invention according to claim 4 is a method of manufacturing a semiconductor device including a semiconductor chip and a support substrate that supports the semiconductor chip, and is provided in a region straddling a predetermined cutting line on one surface of the insulating original substrate. , The step of forming the one side metal layer, and the other side metal at a position facing the one side metal layer in a direction perpendicular to the one side on the other side opposite to the one side of the original substrate. Forming a layer, forming a continuous through hole continuously passing through the other metal layer and the original substrate at a position across the cutting line, a surface of the other metal layer, and the continuous through A first plating step of depositing a first metal plating layer on an inner surface of the hole and a portion of the one side metal layer facing the continuous through hole; and on the other surface of the original substrate after the first plating step, The cutting line And an insulating resin layer forming step of forming an insulating resin layer made of an insulating resin so as to cover the first metal plating layer on the other metal layer over the entire width in the direction along the cutting line, A second plating step for depositing a second metal plating layer on the surface of the first metal plating layer; and after the second plating step, the original substrate and the cutting tool are connected to each other side of the original substrate. And a cutting step of cutting the original substrate along the cutting line and cutting the original substrate into individual pieces of a support substrate.

この方法によれば、元基板の他方面上の他方側金属層の表面に第1金属めっき層が形成された後、切断ライン上において、その第1金属めっき層を切断ラインに沿う方向の全幅にわたって覆うように絶縁樹脂層が形成される。そして、第1金属めっき層の表面に第2金属めっき層が形成された後、元基板が切断ラインに沿って切断されることにより支持基板の個片に切り分けられる。   According to this method, after the first metal plating layer is formed on the surface of the other side metal layer on the other side of the original substrate, the first metal plating layer is formed on the cutting line so that the first metal plating layer has a full width in the direction along the cutting line. An insulating resin layer is formed so as to cover the entire surface. Then, after the second metal plating layer is formed on the surface of the first metal plating layer, the original substrate is cut along the cutting line, thereby being cut into individual pieces of the support substrate.

元基板が切断ラインに沿って切断されると、切断ラインに跨る一方側金属層が2つに分断され、その分断後の各部分が切断ラインの両側の支持基板の内部端子となる。また、切断ラインに沿った切断によって、連続貫通孔の内面および一方側金属層の連続貫通孔に被着した第1金属めっき層および第2金属めっき層が2つに分断され、その分断後の各部分が、切断ラインの両側の支持基板の内部端子に接続される接続配線となる。さらに、他方側金属層および第1金属めっき層が2つに分断され、各支持基板において、他方側金属層および第1金属めっき層の分断後の各部分ならびに第1金属めっき層に被着した第2金属めっき層が外部端子となる。そして、他方側金属層および第1金属めっき層が分断されるときに、第1金属めっき層上の絶縁樹脂層も2つに分断され、その分断後の絶縁樹脂層の各部分がばり防止層となる。   When the original substrate is cut along the cutting line, the one-side metal layer straddling the cutting line is divided into two, and each part after the division becomes an internal terminal of the support substrate on both sides of the cutting line. Further, by cutting along the cutting line, the first metal plating layer and the second metal plating layer deposited on the inner surface of the continuous through hole and the continuous through hole of the one side metal layer are divided into two, and after the division Each part becomes a connection wiring connected to the internal terminals of the support substrate on both sides of the cutting line. Furthermore, the other side metal layer and the first metal plating layer were divided into two parts, and each part of the support substrate was attached to each part after the division of the other side metal layer and the first metal plating layer and the first metal plating layer. The second metal plating layer becomes an external terminal. And when the other side metal layer and the 1st metal plating layer are divided, the insulating resin layer on the 1st metal plating layer is also divided into two, and each part of the insulating resin layer after the division is a flash prevention layer. It becomes.

元基板の切断時に、切断工具が元基板の一方面側から他方面側へ抜けるように移動される。この元基板に対する切断工具の移動方向において、絶縁樹脂層は、第1金属めっき層の下流側に存在している。そのため、第1金属めっき層を構成する金属が切断工具に引きづられて延びることを防止することができ、外部端子に金属ばりが発生することを防止することができる。よって、この方法によって製造される半導体装置は、外部端子に金属ばりを有しておらず、実装基板への実装時に、外部端子と実装基板上のランドとの接続不良などの実装不良を生じるおそれがない。また、金属ばりによる外部端子間での電気的短絡のような不具合を生じるおそれもない。   When cutting the original substrate, the cutting tool is moved so as to come out from the one surface side of the original substrate to the other surface side. In the moving direction of the cutting tool with respect to the original substrate, the insulating resin layer exists on the downstream side of the first metal plating layer. Therefore, it can prevent that the metal which comprises a 1st metal plating layer is pulled by the cutting tool, and can extend, and it can prevent that a metal flash generate | occur | produces in an external terminal. Therefore, the semiconductor device manufactured by this method does not have a metal beam on the external terminal, and may cause a mounting failure such as a connection failure between the external terminal and the land on the mounting substrate when mounted on the mounting substrate. There is no. Further, there is no possibility of causing a problem such as an electrical short circuit between external terminals due to a metal beam.

以下では、この発明の実施の形態を、添付図面を参照して詳細に説明する。
図1は、この発明の一実施形態に係る半導体装置の構成を図解的に示す斜視図である。この半導体装置は、支持基板1と、支持基板1の一方面1A(図1における上面。以下「上面1A」という。)上に支持される半導体チップ2と、支持基板1の上面1Aおよび半導体チップ2を封止する封止樹脂3とを備えている。
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a perspective view schematically showing a configuration of a semiconductor device according to an embodiment of the present invention. The semiconductor device includes a support substrate 1, a semiconductor chip 2 supported on one surface 1A of the support substrate 1 (upper surface in FIG. 1, hereinafter referred to as “upper surface 1A”), an upper surface 1A of the support substrate 1, and the semiconductor chip. 2 and a sealing resin 3 for sealing 2.

支持基板1は、絶縁性を有する樹脂(たとえば、ガラスエポキシ樹脂)からなり、矩形板状をなしていて、4つの直線状の端縁を有している。
支持基板1の上面1Aには、その一方側および他方側の各端部に、複数(この実施形態では、3個)の内部端子4が各側端縁に沿う方向に所定間隔を空けて配置されている。各内部端子4は、たとえば、銅からなり、支持基板1の上面1Aの端縁から内方に向けて延びる矩形薄板状に形成されている。
Supporting substrate 1, a resin having an insulating property (for example, glass epoxy resin) consists, have a rectangular plate shape, that has four straight edges.
On the upper surface 1A of the support substrate 1, a plurality of (in this embodiment, three) internal terminals 4 are arranged at predetermined intervals in the direction along each side edge at each end of one side and the other side. Has been. Each internal terminal 4 is made of, for example, copper and is formed in a rectangular thin plate shape extending inwardly from an edge of the upper surface 1A of the support substrate 1.

また、支持基板1の上面1Aには、それぞれ内部端子4が形成された両端部間の中央部に、たとえば、銅からなる平面視矩形状のダイパッド5が形成されている。このダイパッド5は、各端部における複数の内部端子4の配列方向に沿う方向において、支持基板1とほぼ同じ幅(寸法)を有し、その配列方向と直交する方向において、半導体チップ2とほぼ同じ幅を有している。   Further, on the upper surface 1A of the support substrate 1, a die pad 5 having a rectangular shape in a plan view made of copper, for example, is formed in the center between both end portions where the internal terminals 4 are formed. The die pad 5 has substantially the same width (dimension) as the support substrate 1 in the direction along the arrangement direction of the plurality of internal terminals 4 at each end, and substantially the same as the semiconductor chip 2 in the direction orthogonal to the arrangement direction. Have the same width.

一方、支持基板1の上面1Aと反対側の他方面1B(図1における下面。以下「下面1B」という。)には、支持基板1の厚さ方向(上面1Aおよび下面1Bに直交する方向)において各内部端子4と対向する位置およびダイパッド5に対向する複数の位置に、それぞれ外部端子6が形成されている。
各外部端子6は、図2に示すように、支持基板1の下面1Bの直線状の各端縁から支持基板1の内方に向けて延びている。各外部端子6は、支持基板1の下面1Bの直線状の端縁に沿って設けられ、相対的に小さな厚みを有する薄部61と、この薄部61に対して内方に配置され、相対的に大きな厚みを有する厚部62とを一体的に備えている。すなわち、薄部61は、支持基板1の下面1Bの直線状の端縁に接するように配置され、厚部62は、当該直線状の端縁から支持基板1の内方へ離れた位置に配置されている。
On the other hand, in the other surface 1B opposite to the upper surface 1A of the support substrate 1 (the lower surface in FIG. 1, hereinafter referred to as “lower surface 1B”), the thickness direction of the support substrate 1 (the direction orthogonal to the upper surface 1A and the lower surface 1B). The external terminals 6 are formed at positions facing the internal terminals 4 and at a plurality of positions facing the die pad 5, respectively.
As shown in FIG. 2, each external terminal 6 extends inward of the support substrate 1 from each linear end edge of the lower surface 1 </ b> B of the support substrate 1 . Each external terminal 6 is provided along the linear edge of the lower surface 1B of the support substrate 1 and is disposed inward with respect to the thin portion 61 having a relatively small thickness, And a thick portion 62 having a large thickness. That is, the thin part 61 is disposed so as to contact the linear edge of the lower surface 1B of the support substrate 1, and the thick part 62 is disposed at a position away from the linear edge toward the inside of the support substrate 1. Has been.

各外部端子6の薄部61の下方には、絶縁性樹脂(たとえば、ソルダレジスト)からなるばり防止層18が設けられている。このばり防止層18は、薄部61の厚みと厚部62の厚みとの差(薄部61と厚部62との段差)にほぼ等しい厚みを有し、かつ、外部端子6の長手方向において薄部61と同じ幅を有している。これによって、ばり防止層18の表面(下面)は、外部端子6の厚部62の表面(下面)と同一平面上に位置し、その厚部62の表面に段差なく連続している。   A flash prevention layer 18 made of an insulating resin (for example, solder resist) is provided below the thin portion 61 of each external terminal 6. The flash prevention layer 18 has a thickness substantially equal to the difference between the thickness of the thin portion 61 and the thickness of the thick portion 62 (step difference between the thin portion 61 and the thick portion 62), and in the longitudinal direction of the external terminal 6. It has the same width as the thin part 61. Thus, the surface (lower surface) of the flash prevention layer 18 is located on the same plane as the surface (lower surface) of the thick portion 62 of the external terminal 6 and is continuous with the surface of the thick portion 62 without a step.

支持基板1の4つの端面1Cには、各外部端子6および支持基板1を厚さ方向に貫通しつつ、支持基板1の直線状の端縁から支持基板1の内方に窪む断面半円形状の溝7が形成されている。
各溝7の内面には、金属薄層からなる接続配線8が形成されている。各接続配線8は、支持基板1の上面1A側の端部(上端部)が内部端子4またはダイパッド5に接続されている。また、各接続配線8は、図2に示すように、下面1B側の端部(下端部)が外部端子6に接続されている。これにより、内部端子4とこれに対向する外部端子6とが接続配線8を介して電気的に接続され、ダイパッド5とこれに対向する外部端子6とが接続配線8を介して電気的に接続されている。
The four end faces 1C of the support substrate 1 have semicircular cross-sections that pass through the external terminals 6 and the support substrate 1 in the thickness direction and are recessed inwardly from the linear edge of the support substrate 1. A groove 7 having a shape is formed.
A connection wiring 8 made of a thin metal layer is formed on the inner surface of each groove 7. Each connection wiring 8 has an end portion (upper end portion) on the upper surface 1 </ b> A side of the support substrate 1 connected to the internal terminal 4 or the die pad 5. In addition, as shown in FIG. 2, each connection wiring 8 has an end (lower end) on the lower surface 1 </ b> B side connected to the external terminal 6. As a result, the internal terminal 4 and the external terminal 6 facing this are electrically connected via the connection wiring 8, and the die pad 5 and the external terminal 6 facing this are electrically connected via the connection wiring 8. Has been.

半導体チップ2は、図1に示すように、その機能素子が形成されている側の表面(デバイス形成面)を上方に向けた状態で、ダイパッド5上にダイボンディングされている。半導体チップ2の表面には、複数(この実施形態では、6個)のパッド9が形成されている。各パッド9は、ボンディングワイヤ10によって内部端子4に電気接続(ワイヤボンディング)されている。   As shown in FIG. 1, the semiconductor chip 2 is die-bonded on the die pad 5 with the surface (device forming surface) on which the functional element is formed facing upward. A plurality of (six in this embodiment) pads 9 are formed on the surface of the semiconductor chip 2. Each pad 9 is electrically connected (wire bonded) to the internal terminal 4 by a bonding wire 10.

そして、この半導体装置は、支持基板1の下面1Bを図示しない実装基板(配線基板)に対向させて、その実装基板上のランド(電極)に外部端子6を接合させることにより、実装基板に対する実装が達成される。
図3A〜図3Gは、この半導体装置の製造方法を説明するための図である。この半導体装置は、たとえば、支持基板1に切り分けられる前のより大きな元基板11の状態において、その元基板11の一方面(上面)11A上に半導体チップ2を接合した後、各半導体チップ2の周囲を取り囲む格子状に設定された切断ライン(ダイシングライン)Lに沿って、ダイシングブレードなどの切断工具12で元基板11を切断することにより得られる。
The semiconductor device is mounted on the mounting substrate by causing the lower surface 1B of the support substrate 1 to face a mounting substrate (wiring substrate) (not shown) and bonding the external terminals 6 to lands (electrodes) on the mounting substrate. Is achieved.
3A to 3G are views for explaining a method of manufacturing this semiconductor device. In the semiconductor device, for example, in a state of a larger original substrate 11 before being cut into the support substrate 1, after the semiconductor chip 2 is bonded onto one surface (upper surface) 11 </ b> A of the original substrate 11, It is obtained by cutting the original substrate 11 with a cutting tool 12 such as a dicing blade along a cutting line (dicing line) L set in a lattice shape surrounding the periphery.

たとえば、元基板11の上面11Aおよびその反対側の他方面(下面)11Bには、当初、それぞれ全面に金属層(たとえば、銅層)が形成されている。そして、各金属層をパターニングすることによって、元基板11の上面11Aには、複数の上側金属層13が切断ラインLに跨って形成され、下面11Bには、各上側金属層13と元基板11の厚さ方向(上面11Aおよび下面11Bと直交する方向)に対向する位置に、それぞれ下側金属層14が切断ラインLに跨って形成される。   For example, a metal layer (for example, a copper layer) is initially formed on the entire upper surface 11A of the original substrate 11 and the other surface (lower surface) 11B on the opposite side. Then, by patterning each metal layer, a plurality of upper metal layers 13 are formed across the cutting line L on the upper surface 11A of the original substrate 11, and each upper metal layer 13 and the original substrate 11 are formed on the lower surface 11B. The lower metal layer 14 is formed across the cutting line L at positions facing each other in the thickness direction (direction orthogonal to the upper surface 11A and the lower surface 11B).

その後、図3Aおよび図3Bに示すように、各下側金属層14および元基板11を連続して貫通する断面楕円形状の連続貫通孔15が切断ラインLに跨る位置に形成される。この連続貫通孔15は、たとえば、元基板11の下面11B側からのレーザ加工またはエッチング加工によって形成することができる。
つづいて、元基板11の下面11B側からの銅めっきによって、図3Cに示すように、下側金属層14の表面(下面)、連続貫通孔15の内面および上側金属層13の連続貫通孔15に臨む部分に、銅めっき層16が形成(被着)される。
Thereafter, as shown in FIGS. 3A and 3B, a continuous through hole 15 having an elliptical cross section continuously penetrating each lower metal layer 14 and the original substrate 11 is formed at a position straddling the cutting line L. The continuous through hole 15 can be formed by, for example, laser processing or etching processing from the lower surface 11B side of the original substrate 11.
Subsequently, as shown in FIG. 3C, by copper plating from the lower surface 11 </ b> B side of the original substrate 11, the surface (lower surface) of the lower metal layer 14, the inner surface of the continuous through hole 15, and the continuous through hole 15 of the upper metal layer 13. A copper plating layer 16 is formed (deposited) on the portion facing the surface.

その後、図3Dおよび図3Eに示すように、切断ラインLを跨り、かつ、下側金属層14の表面に被着している銅めっき層16を切断ラインLに沿う方向の全幅にわたって覆うように、絶縁性樹脂からなる絶縁樹脂層19が形成される。
この絶縁樹脂層19の形成後は、元基板11の下面11B側からのニッケルめっきおよび金めっきが連続して行われる。これによって、図3Fに示すように、銅めっき層16の表面に、ニッケルめっき層および金めっき層が積層されてなるニッケル/金めっき層17が形成(被着)される。このめっき工程は、元基板11の下面11B上におけるニッケル/金めっき層17の表面(下面)が絶縁樹脂層19の表面(下面)とほぼ同一平面上に位置するまで続けられる。
Thereafter, as shown in FIGS. 3D and 3E, the copper plating layer 16 straddling the cutting line L and covering the surface of the lower metal layer 14 is covered over the entire width in the direction along the cutting line L. Then, an insulating resin layer 19 made of an insulating resin is formed.
After the formation of the insulating resin layer 19, nickel plating and gold plating from the lower surface 11B side of the original substrate 11 are continuously performed. As a result, as shown in FIG. 3F, a nickel / gold plating layer 17 in which a nickel plating layer and a gold plating layer are laminated is formed (deposited) on the surface of the copper plating layer 16. This plating process is continued until the surface (lower surface) of the nickel / gold plating layer 17 on the lower surface 11B of the original substrate 11 is positioned substantially on the same plane as the surface (lower surface) of the insulating resin layer 19.

そして、ニッケル/金めっき層17の形成後は、元基板11の上面11Aの各ダイパッド5上に半導体チップ2が接合され、各半導体チップ2のパッド9がボンディングワイヤ10によって内部端子4に電気接続された後、図3Gに示すように、切断工具12が元基板11の上面11A側から下面11B側に抜けるように入れられて、元基板11が切断ラインLに沿って切断されて、元基板11が支持基板1の個片に切り分けられる。   After the nickel / gold plating layer 17 is formed, the semiconductor chip 2 is bonded onto each die pad 5 on the upper surface 11A of the original substrate 11, and the pad 9 of each semiconductor chip 2 is electrically connected to the internal terminal 4 by the bonding wire 10. 3G, the cutting tool 12 is inserted so as to come out from the upper surface 11A side of the original substrate 11 to the lower surface 11B side, and the original substrate 11 is cut along the cutting line L. 11 is cut into individual pieces of the support substrate 1.

この切断によって、図4に示すように、切断ラインLに跨る上側金属層13が2つに分断され、その分断後の各部分が切断ラインLの両側の支持基板1の内部端子4となる。また、切断ラインLに沿った切断によって、切断ラインLに跨る連続貫通孔15は、その切断ラインLの両側の支持基板1の端面1Cの溝7として分割される。このとき、連続貫通孔15(溝7)の内面および上側金属層13の連続貫通孔15に被着した銅めっき層16およびニッケル/金めっき層17が2つに分断され、その分断後の各部分が、切断ラインLの両側の支持基板1の内部端子4に接続される接続配線8となる。さらに、下側金属層14および銅めっき層16が2つに分断され、各支持基板1において、それらの分断後の各部分およびその表面に被着したニッケル/金めっき層17が外部端子6となる。さらにまた、下側金属層14および銅めっき層16とともに、切断ラインLに跨る絶縁樹脂層19が2つに分断され、その分断後の各部分が切断ラインLの両側の支持基板1のばり防止層18となる。そして、外部端子6において、支持基板1の下面1Bとばり防止層18とに挟まれた部分が、相対的に小さな厚みを有する薄部61となり、ばり防止層18と接触していない部分が、相対的に大きな厚みを有する厚部62となる。   As shown in FIG. 4, the upper metal layer 13 straddling the cutting line L is divided into two by this cutting, and each part after the cutting becomes the internal terminals 4 of the support substrate 1 on both sides of the cutting line L. Further, by cutting along the cutting line L, the continuous through hole 15 straddling the cutting line L is divided as the grooves 7 on the end surface 1C of the support substrate 1 on both sides of the cutting line L. At this time, the copper plating layer 16 and the nickel / gold plating layer 17 deposited on the inner surface of the continuous through hole 15 (groove 7) and the continuous through hole 15 of the upper metal layer 13 are divided into two parts. The portion becomes the connection wiring 8 connected to the internal terminal 4 of the support substrate 1 on both sides of the cutting line L. Further, the lower metal layer 14 and the copper plating layer 16 are divided into two parts. In each support substrate 1, the parts after the division and the nickel / gold plating layer 17 deposited on the surface thereof are connected to the external terminals 6. Become. Furthermore, together with the lower metal layer 14 and the copper plating layer 16, the insulating resin layer 19 straddling the cutting line L is divided into two parts, and each part after the division is prevented from flashing the support substrate 1 on both sides of the cutting line L. Layer 18 is formed. In the external terminal 6, the portion sandwiched between the lower surface 1B of the support substrate 1 and the flash prevention layer 18 becomes a thin portion 61 having a relatively small thickness, and the portion not in contact with the flash prevention layer 18 is The thick portion 62 has a relatively large thickness.

以上のように、元基板11の下面11B上の下側金属層14の表面に銅めっき層16が形成された後、切断ラインL上において、その銅めっき層16を切断ラインLに沿う方向の全幅にわたって覆うように絶縁樹脂層19が形成される。そして、銅めっき層16の表面にニッケル/金めっき層17が形成された後、元基板11が切断ラインLに沿って切断されることにより支持基板1の個片に切り分けられる。   As described above, after the copper plating layer 16 is formed on the surface of the lower metal layer 14 on the lower surface 11B of the original substrate 11, on the cutting line L, the copper plating layer 16 is moved along the cutting line L. An insulating resin layer 19 is formed so as to cover the entire width. Then, after the nickel / gold plating layer 17 is formed on the surface of the copper plating layer 16, the original substrate 11 is cut along the cutting line L to be cut into individual pieces of the support substrate 1.

元基板11の切断時に、切断工具12が元基板11の上面11A側から下面11B側へ抜けるように移動される。この元基板11に対する切断工具12の移動方向において、絶縁樹脂層19は、銅めっき層16の下流側に存在している。そのため、銅めっき層16を構成する金属が切断工具12に引きづられて延びることを防止することができ、外部端子6に金属ばりが発生することを防止することができる。よって、この半導体装置は、外部端子6に金属ばりを有しておらず、実装基板への実装時に、外部端子6と実装基板上のランドとの接続不良などの実装不良を生じるおそれがない。また、金属ばりによる外部端子間での電気的短絡のような不具合を生じるおそれもない。   When the original substrate 11 is cut, the cutting tool 12 is moved so as to come out from the upper surface 11A side of the original substrate 11 to the lower surface 11B side. In the moving direction of the cutting tool 12 relative to the original substrate 11, the insulating resin layer 19 exists on the downstream side of the copper plating layer 16. Therefore, it is possible to prevent the metal constituting the copper plating layer 16 from being pulled and extended by the cutting tool 12, and it is possible to prevent the metal flash from being generated on the external terminal 6. Therefore, this semiconductor device does not have a metal beam on the external terminal 6, and there is no possibility of causing a mounting failure such as a connection failure between the external terminal 6 and a land on the mounting substrate when mounted on the mounting substrate. Further, there is no possibility of causing a problem such as an electrical short circuit between external terminals due to a metal beam.

以上、この発明の一実施形態を説明したが、この発明は他の形態で実施することもできる。たとえば、上記の実施形態では、各外部端子6の薄部61の下方に設けられているばり防止層18が、薄部61の厚みと厚部62の厚みとの差にほぼ等しい厚みを有し、かつ、外部端子6の長手方向において薄部61と同じ幅を有しているとした。しかしながら、ばり防止層18の厚みは、薄部61の厚みと厚部62の厚みとの差よりも小さくてもよい。また、外部端子6の長手方向において、ばり防止層18の幅は、薄部61の幅よりも小さくてもよい。すなわち、ばり防止層18は、外部端子6の薄部61と厚部62との段差によって形成される空間内に収まるように設けられていればよい。   Although one embodiment of the present invention has been described above, the present invention can be implemented in other forms. For example, in the above embodiment, the flash prevention layer 18 provided below the thin portion 61 of each external terminal 6 has a thickness substantially equal to the difference between the thickness of the thin portion 61 and the thickness of the thick portion 62. In addition, it has the same width as the thin portion 61 in the longitudinal direction of the external terminal 6. However, the thickness of the flash prevention layer 18 may be smaller than the difference between the thickness of the thin part 61 and the thickness of the thick part 62. Further, in the longitudinal direction of the external terminal 6, the width of the flash prevention layer 18 may be smaller than the width of the thin portion 61. That is, the flash prevention layer 18 may be provided so as to be accommodated in the space formed by the step between the thin portion 61 and the thick portion 62 of the external terminal 6.

また、ばり防止層18は必ずしも必要というわけではなく、ばり防止層18が省略されてもよい。ばり防止層18を省略した構成の半導体装置は、たとえば、図3Cに示すように、下側金属層14の表面、連続貫通孔15の内面および上側金属層13の連続貫通孔15に臨む部分に、銅めっき層16を形成した後、図3Dおよび図3Eに示す絶縁樹脂層19を形成する工程を行わずに、その銅めっき層16の表面において、切断ラインLに沿って延び、かつ、切断ラインLを跨る所定幅の領域を除く領域に、ニッケル/金めっき層17を形成することによって作製することができる。ばり防止層18を省略した構成であっても、外部端子6が薄部61および厚部62を有しているので、半導体装置の製造時に、たとえ外部端子6の薄部61に金属ばりが生じたとしても、その金属ばりの長さが薄部61と厚部62との段差以下であれば、半導体装置の実装基板への実装時に、その金属ばりが実装基板の表面に当接することがない。よって、外部端子と実装基板上のランドとの接続不良などの実装不良を生じるおそれがない。   Further, the flash prevention layer 18 is not necessarily required, and the flash prevention layer 18 may be omitted. For example, as shown in FIG. 3C, the semiconductor device having the configuration in which the flash prevention layer 18 is omitted is provided on the surface of the lower metal layer 14, the inner surface of the continuous through hole 15, and the portion facing the continuous through hole 15 of the upper metal layer 13. After the copper plating layer 16 is formed, the surface of the copper plating layer 16 extends along the cutting line L and is cut without performing the step of forming the insulating resin layer 19 shown in FIGS. 3D and 3E. It can be manufactured by forming the nickel / gold plating layer 17 in a region excluding a region having a predetermined width across the line L. Even in the configuration in which the flash prevention layer 18 is omitted, the external terminal 6 has the thin portion 61 and the thick portion 62, and therefore, a metal flash occurs in the thin portion 61 of the external terminal 6 when the semiconductor device is manufactured. Even if the length of the metal beam is equal to or less than the step between the thin portion 61 and the thick portion 62, the metal beam does not contact the surface of the mounting substrate when the semiconductor device is mounted on the mounting substrate. . Therefore, there is no possibility of causing a mounting failure such as a connection failure between the external terminal and the land on the mounting substrate.

その他、特許請求の範囲に記載された事項の範囲で種々の設計変更を施すことが可能である。   In addition, various design changes can be made within the scope of matters described in the claims.

この発明の一実施形態に係る半導体装置の構成を図解的に示す斜視図である。1 is a perspective view schematically showing a configuration of a semiconductor device according to an embodiment of the present invention. 図1に示す半導体装置の接続配線の近傍の斜視図である。FIG. 2 is a perspective view of the vicinity of a connection wiring of the semiconductor device shown in FIG. 1. 図1に示す半導体装置の製造方法(連続貫通孔を形成する工程)を説明するための図であって、支持基板の下面を図解的に示している。It is a figure for demonstrating the manufacturing method (process of forming a continuous through-hole) of the semiconductor device shown in FIG. 1, Comprising: The lower surface of the support substrate is shown schematically. 図1に示す半導体装置の製造方法(連続貫通孔を形成する工程)を説明するための図であって、図3Aに示す切断線A−Aで半導体装置を切断したときの断面図である。FIG. 3B is a view for explaining the method for manufacturing the semiconductor device shown in FIG. 1 (step of forming a continuous through hole), and is a cross-sectional view when the semiconductor device is cut along a cutting line AA shown in FIG. 3A. 図1に示す半導体装置の製造方法(銅めっき層を形成する工程(第1めっき工程))を説明するための図であって、図3Aに示す切断線A−Aで半導体装置を切断したときの断面図である。It is a figure for demonstrating the manufacturing method (The process (1st plating process) of forming a copper plating layer) of the semiconductor device shown in FIG. 1, Comprising: When the semiconductor device is cut | disconnected by the cutting line AA shown to FIG. 3A FIG. 図1に示す半導体装置の製造方法(絶縁樹脂層を形成する工程(絶縁樹脂層形成工程))を説明するための図であって、支持基板の下面を図解的に示している。It is a figure for demonstrating the manufacturing method (The process of forming an insulating resin layer (insulating resin layer forming process)) of the semiconductor device shown in FIG. 1, Comprising: The lower surface of the support substrate is shown schematically. 図1に示す半導体装置の製造方法(絶縁樹脂層形成工程)を説明するための図であって、図3Dに示す切断線B−Bで半導体装置を切断したときの断面図である。It is a figure for demonstrating the manufacturing method (insulation resin layer formation process) of the semiconductor device shown in FIG. 1, Comprising: It is sectional drawing when a semiconductor device is cut | disconnected by the cutting line BB shown to FIG. 3D. 図1に示す半導体装置の製造方法(ニッケル/金めっき層を形成する工程(第2めっき工程))を説明するための図であって、図3Dに示す切断線B−Bで半導体装置を切断したときの断面図である。FIG. 3 is a diagram for explaining a method of manufacturing the semiconductor device shown in FIG. 1 (step of forming a nickel / gold plating layer (second plating step)), and cutting the semiconductor device along a cutting line BB shown in FIG. 3D It is sectional drawing when doing. 図1に示す半導体装置の製造方法(元基板を支持基板の個片に切り分ける工程(切断工程))を説明するための図であって、図3Dに示す切断線B−Bで半導体装置を切断したときの断面図である。FIG. 3 is a diagram for explaining a method for manufacturing the semiconductor device shown in FIG. 1 (step of cutting an original substrate into individual pieces of a support substrate (cutting step)), and cutting the semiconductor device along a cutting line BB shown in FIG. 3D It is sectional drawing when doing. 図1に示す半導体装置の端部の断面図である。It is sectional drawing of the edge part of the semiconductor device shown in FIG.

符号の説明Explanation of symbols

1 支持基板
1A 上面(一方面)
1B 下面(他方面)
2 半導体チップ
4 内部端子
5 ダイパッド(内部端子)
6 外部端子
8 接続配線
11 元基板
11A 上面(一方面)
11B 下面(他方面)
12 切断工具
13 上側金属層(一方側金属層)
14 下側金属層(他方側金属層)
15 連続貫通孔
16 銅めっき層(第1金属めっき層)
17 ニッケル/金めっき層(第2金属めっき層)
18 ばり防止層
19 絶縁樹脂層
61 薄部
62 厚部
L 切断ライン
1 Support substrate 1A Upper surface (one surface)
1B Lower surface (the other surface)
2 Semiconductor chip 4 Internal terminal 5 Die pad (internal terminal)
6 External terminal 8 Connection wiring 11 Original substrate 11A Upper surface (one surface)
11B Lower surface (the other surface)
12 Cutting tool 13 Upper metal layer (one side metal layer)
14 Lower metal layer (other metal layer)
15 Continuous through hole 16 Copper plating layer (first metal plating layer)
17 Nickel / gold plating layer (second metal plating layer)
18 Burr prevention layer 19 Insulating resin layer 61 Thin part 62 Thick part L Cutting line

Claims (4)

半導体チップと、
前記半導体チップを一方面上に支持し、直線状の端縁を有するとともに、前記端縁から内方に窪む溝が厚さ方向に貫通して形成された支持基板と、
前記支持基板の前記一方面に設けられ、前記半導体チップと電気接続される内部端子と、
前記支持基板の前記一方面と反対側の他方面に設けられ、前記支持基板の前記端縁から当該支持基板の内方に向けて延びる外部端子と、
前記溝の内面に形成され、前記支持基板の前記一方面および前記他方面間を貫通し、前記内部端子と前記外部端子とを接続する接続配線とを含み、
前記外部端子は、前記支持基板の前記端縁に接するように配置され、相対的に小さな厚みを有する薄部と、前記端縁から前記支持基板の内方へ離れた位置に配置され、相対的に大きな厚みを有する厚部とを一体的に備えていることを特徴とする、半導体装置。
A semiconductor chip;
A support substrate that supports the semiconductor chip on one surface, has a linear edge, and a groove recessed inwardly from the edge is formed through the thickness direction; and
An internal terminal provided on the one surface of the support substrate and electrically connected to the semiconductor chip;
Provided on the other surface opposite to the one surface of the supporting substrate, and external terminals extending from said end edge of said supporting substrate toward the inside of the support substrate,
A wiring formed on the inner surface of the groove, penetrating between the one surface and the other surface of the support substrate, and connecting the internal terminal and the external terminal;
The external terminal, the are arranged in contact with the edge of the supporting substrate, and a thin portion having a relatively small thickness, disposed inwardly away of the supporting substrate from the edge, relative And a thick portion having a large thickness integrally therewith.
前記薄部に対して前記支持基板と反対側に設けられ、前記薄部の厚みと前記厚部の厚みとの差以下の厚みを有するばり防止層をさらに含むことを特徴とする、請求項1記載の半導体装置。   2. The flash prevention layer according to claim 1, further comprising a flash prevention layer provided on a side opposite to the support substrate with respect to the thin portion and having a thickness equal to or less than a difference between the thickness of the thin portion and the thickness of the thick portion. The semiconductor device described. 半導体チップとその半導体チップを支持する支持基板とを備える半導体装置を製造する方法であって、
絶縁性を有する元基板の一方面における所定の切断ラインを跨る領域に、一方側金属層を形成する工程と、
前記元基板の前記一方面と反対側の他方面において、前記一方側金属層に対して前記一方面と直交する方向に対向する位置に、他方側金属層を形成する工程と、
前記切断ラインを跨る位置に、前記他方側金属層および前記元基板を連続して貫通する連続貫通孔を形成する工程と、
前記他方側金属層の表面、前記連続貫通孔の内面および前記一方側金属層の前記連続貫通孔に臨む部分に第1金属めっき層を被着させる第1めっき工程と、
前記第1金属めっき層の表面において、前記切断ラインに沿って延び、かつ、前記切断ラインを跨る所定幅の領域を除く領域に、第2金属めっき層を被着させる第2めっき工程と、
前記第2めっき工程後、前記元基板と切断工具とを、前記切断工具が前記元基板の前記一方面側から前記他方面側へ抜けるように相対移動させて、前記元基板を前記切断ラインに沿って切断し、前記元基板を支持基板の個片に切り分ける切断工程とを含むことを特徴とする、半導体装置の製造方法。
A method of manufacturing a semiconductor device comprising a semiconductor chip and a support substrate that supports the semiconductor chip,
Forming one side metal layer in a region straddling a predetermined cutting line on one side of the original substrate having insulation; and
Forming the other side metal layer at a position opposite to the one side metal layer in a direction orthogonal to the one side on the other side opposite to the one side of the original substrate;
Forming a continuous through hole that continuously penetrates the other metal layer and the original substrate at a position across the cutting line;
A first plating step of depositing a first metal plating layer on a surface of the other side metal layer, an inner surface of the continuous through hole, and a portion of the one side metal layer facing the continuous through hole;
A second plating step of depositing a second metal plating layer on the surface of the first metal plating layer, excluding a region having a predetermined width extending along the cutting line and straddling the cutting line;
After the second plating step, the original substrate and the cutting tool are moved relative to each other so that the cutting tool comes out from the one surface side of the original substrate to the other surface side, and the original substrate is moved to the cutting line. And a cutting step of cutting the original substrate into individual pieces of the supporting substrate.
半導体チップとその半導体チップを支持する支持基板とを備える半導体装置を製造する方法であって、
絶縁性を有する元基板の一方面における所定の切断ラインを跨る領域に、一方側金属層を形成する工程と、
前記元基板の前記一方面と反対側の他方面において、前記一方側金属層に対して前記一方面と直交する方向に対向する位置に、他方側金属層を形成する工程と、
前記切断ラインを跨る位置に、前記他方側金属層および前記元基板を連続して貫通する連続貫通孔を形成する工程と、
前記他方側金属層の表面、前記連続貫通孔の内面および前記一方側金属層の前記連続貫通孔に臨む部分に第1金属めっき層を被着させる第1めっき工程と、
前記第1めっき工程後、前記元基板の前記他方面上に、前記切断ラインを跨り、かつ、前記他方側金属層上の前記第1金属めっき層を前記切断ラインに沿う方向の全幅にわたって覆うように、絶縁性樹脂からなる絶縁樹脂層を形成する絶縁樹脂層形成工程と、
前記第1金属めっき層の表面に第2金属めっき層を被着させる第2めっき工程と、
前記第2めっき工程後、前記元基板と切断工具とを、前記切断工具が前記元基板の前記一方面側から前記他方面側へ抜けるように相対移動させて、前記元基板を前記切断ラインに沿って切断し、前記元基板を支持基板の個片に切り分ける切断工程とを含むことを特徴とする、半導体装置の製造方法。
A method of manufacturing a semiconductor device comprising a semiconductor chip and a support substrate that supports the semiconductor chip,
Forming one side metal layer in a region straddling a predetermined cutting line on one side of the original substrate having insulation; and
Forming the other side metal layer at a position opposite to the one side metal layer in a direction orthogonal to the one side on the other side opposite to the one side of the original substrate;
Forming a continuous through hole that continuously penetrates the other metal layer and the original substrate at a position across the cutting line;
A first plating step of depositing a first metal plating layer on a surface of the other side metal layer, an inner surface of the continuous through hole, and a portion of the one side metal layer facing the continuous through hole;
After the first plating step, on the other surface of the original substrate, straddling the cutting line and covering the first metal plating layer on the other metal layer over the entire width in the direction along the cutting line. And an insulating resin layer forming step of forming an insulating resin layer made of an insulating resin,
A second plating step of depositing a second metal plating layer on the surface of the first metal plating layer;
After the second plating step, the original substrate and the cutting tool are moved relative to each other so that the cutting tool comes out from the one surface side of the original substrate to the other surface side, and the original substrate is moved to the cutting line. And a cutting step of cutting the original substrate into individual pieces of the supporting substrate.
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