WO2017141983A1

WO2017141983A1 - Printed circuit board production method

Info

Publication number: WO2017141983A1
Application number: PCT/JP2017/005572
Authority: WO
Inventors: 光由松田; 哲聡 ▲高▼梨; 浩人飯田; 吉川　和広; 翼加藤; 金子　智一
Original assignee: 三井金属鉱業株式会社
Priority date: 2016-02-18
Filing date: 2017-02-15
Publication date: 2017-08-24
Also published as: KR20180113987A; TWI650240B; JPWO2017141983A1; TW201741145A; JP6836579B2; CN108464062B; CN108464062A

Abstract

Provided is a printed circuit board production method that makes it possible to uniformly Cu etch a copper layer in-plane without the need for a separate additional etching step and that also makes it possible to suppress the occurrence of local circuit depressions. This production method includes: a step for obtaining a support using a metal foil that comprises, in order, a surface copper layer and an etching sacrificial layer or a metal foil that comprises, in order, a surface copper layer, an etching sacrificial layer, and an additional copper layer; a step for obtaining a laminate with a buildup wiring layer by forming, upon the surface copper layer, a buildup wiring layer that includes at least a copper first wiring layer and an insulating layer; and a step for exposing the first wiring layer by using an etching liquid to remove the surface copper layer and the etching sacrificial layer or the surface copper layer, the etching sacrificial layer, and the additional copper layer and thereby obtaining a printed circuit board that includes a buildup wiring layer. The etching rate of the etching sacrificial layer is higher than the etching rate of Cu.

Description

Method for manufacturing printed wiring board

The present invention relates to a method for manufacturing a printed wiring board.

Recently, in order to increase the mounting density of printed wiring boards and reduce the size, multilayered printed wiring boards have been widely used. Such a printed wiring board is used for the purpose of weight reduction and size reduction in many portable electronic devices. This printed wiring board is required to further reduce the thickness of the interlayer insulating layer and to further reduce the weight as a wiring board.

As a technique for satisfying such a requirement, a printed wiring board method for forming an insulating layer and a wiring layer as a build-up layer on a support (core) has been proposed, and one of them is a metal layer on the support surface. A manufacturing method using a coreless buildup method in which a wiring layer is formed thereon, a buildup layer is further formed, and then a support is separated is employed. 8 and 9 show a conventional example of a method for manufacturing a printed wiring board by a coreless buildup method using a copper foil with a carrier as a member for a support having a metal layer on the surface. In the example shown in FIGS. 8 and 9, first, a copper foil 110 with a carrier including a carrier 112, a release layer 114, and a copper foil 116 in this order is laminated on a coreless support 118 such as a prepreg. Next, a photoresist pattern 120 is formed on the copper foil 116, and a wiring pattern 124 is formed through pattern plating (electro copper plating) 122 and peeling of the photoresist pattern 120. Then, a pre-stacking process such as a roughening process is performed on the pattern plating as necessary to form the first wiring layer 126. Next, as shown in FIG. 9, a copper foil 130 with a carrier (a carrier 132, a release layer 134, and a seed layer of the insulating layer 128 and, if necessary, the second wiring layer 138 to form the build-up layer 142). The copper foil 136 is provided), the carrier 132 is peeled off, and the copper foil 136 and the insulating layer 128 immediately below it are punched with a laser or the like. Subsequently, patterning is performed by electroless copper plating, photoresist processing, electrolytic copper plating, photoresist stripping, flash etching, and the like to form the second wiring layer 138, and this patterning is repeated as necessary to repeat the nth wiring layer. Up to 140 (n is an integer of 2 or more). Then, the coreless support 118 is peeled off together with the carrier 112 to form a build-up wiring board 144 (also referred to as a coreless wiring board), and the copper foil 116 exposed between the wiring patterns of the first wiring layer 126 and the build if present. The copper foil 136 exposed between the wiring patterns of the n-th wiring layer 140 of the up layer 142 is removed by flash etching to obtain a predetermined wiring pattern, and a printed wiring board 146 is obtained.

By the way, in such a flash etching process in the manufacturing process of the coreless wiring board, there are influences such as minute pinholes existing in the exposed copper foil 116 and unevenness of the in-plane liquid deposition pressure of the flash etching liquid. Therefore, the amount of flash etching in the plane of the first wiring layer 126 tends to be non-uniform. In this case, as conceptually shown in FIG. 6, not only the copper foil 116 to be removed but also a part of the copper circuit (the first wiring layer 126) to be left is etched unevenly. As a result, a non-uniform circuit recess 126a exceeding the standard value is generated. Such a non-uniform circuit recess 126a may lead to defects such as poor connection or disconnection in the printed wiring board mounting process or reliability test environment. Therefore, an attempt to reduce the etching of the wiring layer has been proposed. For example, in Patent Document 1 (Japanese Patent Laid-Open No. 2014-63950), an etching stopper layer formed of nickel is provided, and this etching stopper layer is removed by selective etching, thereby suppressing uneven dissolution of the copper circuit. However, it is disclosed to suppress a circuit dent that occurs non-uniformly in a plane.

JP 2014-63950 A

However, when the method of Patent Document 1 is employed, as conceptually shown in FIG. 7, not only the copper foil 116 that should be removed but also the etching stopper layer 115 that should not be removed in the copper etching process is slightly present. Elution may occur. In addition, if pinholes are present slightly when the etching stopper layer 115 is formed, the copper circuit (first wiring layer 126) may be locally exposed in the copper etching process. Thus, if the copper circuit (first wiring layer 126) is locally exposed due to non-uniform elution, dissolution of Cu constituting the copper circuit is accelerated, and a large circuit recess 126a is locally generated. In the first place, when the etching stopper layer 115 is provided, a selective etching step for removing the etching stopper layer 115 is separately required, and thus the number of manufacturing steps is increased.

By adopting an etching sacrificial layer whose etching rate is higher than that of Cu instead of the etching stopper layer, the present inventors have been able to uniformly perform copper in-plane by Cu etching without requiring an additional etching step. It was found that the etching of the layer can be performed and the occurrence of local circuit dents can be suppressed.

Therefore, an object of the present invention is to provide a printed wiring board capable of uniformly etching a copper layer in a plane by Cu etching and suppressing the occurrence of local circuit dents without requiring an additional etching step. It is to provide a manufacturing method.

According to one aspect of the present invention, a support is obtained using a metal foil having a surface copper layer and an etching sacrificial layer in this order, or a metal foil having a surface copper layer, an etching sacrificial layer and an additional copper layer in this order. Process,
Forming a buildup wiring layer including at least a copper first wiring layer and an insulating layer on the surface copper layer to obtain a laminate with a buildup wiring layer;
The surface copper layer and the etching sacrificial layer, or the surface copper layer, the etching sacrificial layer, and the additional copper layer are removed with an etching solution to expose the first wiring layer, thereby forming the build-up wiring layer. Obtaining a printed wiring board including:
And a method for producing a printed wiring board, wherein the etching sacrificial layer has an etching rate higher than that of Cu.

It is a cross-sectional schematic diagram which shows an example of the metal foil with a carrier containing the metal foil used for the method of this invention. It is a cross-sectional schematic diagram which shows another example of the metal foil with a carrier containing the metal foil used for the method of this invention. It is a cross-sectional schematic diagram for demonstrating the function of the etching sacrificial layer in the method of this invention. It is a figure which shows the process of the first half in an example of the manufacturing method of the printed wiring board using the coreless buildup method to which the method of this invention was applied. The latter half process following the process shown by FIG. 4 in an example of the manufacturing method of the printed wiring board using the coreless buildup method to which the method of this invention was applied is shown. It is a cross-sectional schematic diagram for demonstrating the non-uniform etching of the copper circuit in the conventional method. It is a cross-sectional schematic diagram for demonstrating the non-uniform etching of the etching stopper layer and copper circuit in the conventional method. It is a figure which shows the process of the first half in the prior art example of the manufacturing method of the printed wiring board using a coreless buildup method. The latter half process following the process shown by FIG. 8 in the prior art example of the manufacturing method of the printed wiring board using a coreless buildup method is shown.

TECHNICAL FIELD The present invention of a printed wiring board is a method for manufacturing a printed wiring board. In the method of the present invention, a support is first obtained using a metal foil having at least a surface copper layer and an etching sacrificial layer. Specifically, this metal foil may be provided with a surface copper layer 11 and an etching sacrificial layer 12 in this order, like the metal foil 10 shown in FIG. Like the metal foil 10 ′ shown in a), the surface copper layer 11, the etching sacrificial layer 12, and the additional copper layer 13 may be provided in this order. That is, the additional copper layer 13 is an arbitrary copper layer provided as desired. Next, as schematically shown in FIG. 3, a build-up wiring layer including at least a copper first wiring layer 26 and an insulating layer 28 is formed on the surface copper layer 11 to form a laminate with a build-up wiring layer. Get. In FIG. 3, only the first wiring layer 26 is drawn for the sake of simplification. However, as shown in FIG. 5 to be described later, the nth wiring layer 40 (n is an integer of 2 or more) is formed. Needless to say, a multilayer build-up wiring layer can be used. Thereafter, the surface copper layer 11, the etching sacrificial layer 12, and the additional copper layer 13 (if present) are removed with an etching solution to expose the first wiring layer 26, thereby obtaining a printed wiring board including a build-up wiring layer. . The etching sacrificial layer 12 is characterized by its etching rate being higher than that of Cu. Thus, by using the etching sacrificial layer 12 whose etching rate is higher than that of Cu instead of the etching stopper layer as described in the cited document 1, Cu etching can be performed without requiring an additional etching process. The copper layer can be uniformly etched in the plane, and the occurrence of local circuit dents can be suppressed.

That is, as conceptually shown in FIGS. 3B and 3C, the etching sacrificial layer 12 may be non-uniformly dissolved and / or accidentally exist in the etching sacrificial layer 12 during Cu etching. Even if Cu (Cu of the surface copper layer 11 or the first wiring layer 26) is locally exposed due to pinholes or the like, the underlying surface copper layer 11 or the first wiring layer 26 (copper layer) is caused by a local battery reaction. ) Is suppressed. As a result, the surface copper layer 11 is etched uniformly in the plane, and the occurrence of local circuit dents in the first wiring layer 26 can be suppressed. In addition, according to this method, the etching sacrificial layer 12 is dissolved and removed along with the Cu etching, so that an additional step for removing the etching sacrificial layer 12 is not required, and the productivity is improved. Furthermore, there is an advantage that the circuit dents can be reduced on the average in the plane of the first wiring layer 26 by the effect of the high etching rate itself. In this regard, as described above, when the method of Patent Document 1 is adopted, as conceptually shown in FIG. 7, not only the copper foil 116 to be removed but also not originally removed in the copper etching process. The etching stopper layer 115 elutes slightly, and the underlying copper circuit (first wiring layer 126) is locally exposed due to pinholes or the like generated at the stage of forming the etching stopper layer 115. There is a fear. When the copper circuit (first wiring layer 126) is locally exposed in this way, dissolution of Cu constituting the copper circuit is accelerated, and a large circuit recess 126a is locally generated. In the first place, when the etching stopper layer 115 is provided, a selective etching step for removing the etching stopper layer 115 is separately required, and thus the number of manufacturing steps is increased. On the other hand, according to the method for manufacturing a printed wiring board of the present invention, these technical problems can be solved conveniently.

Hereinafter, an embodiment of the method of the present invention will be described with reference to the process diagrams shown in FIGS. 4 and 5 in addition to FIGS. 4 and 5 are drawn so that the build-up wiring layer 42 is formed by providing the metal foil 14 with a carrier on one side of the coreless support 18 for the sake of simplicity of explanation. It is desirable to provide the metal foil 14 with a carrier on both surfaces of the support 18 and form the build-up wiring layer 42 on both surfaces.

(1) Preparation of support using metal foil In the method of the present invention, metal foil 10 provided with surface copper layer 11 and etching sacrificial layer 12 in this order, or surface copper layer 11, etching sacrificial layer 12 and additional copper layer. A support is obtained using a metal foil 10 ′ having 13 in this order. That is, the additional copper layer 13 is an arbitrary layer provided as desired. The metal foil 10 or the metal foil 14 with a carrier including the metal foil 10 itself may be used as a support, or the surface copper layer 11 or the metal foil with a carrier 14 is laminated on one side or both sides of the coreless support 18 as described later. The laminate obtained in this way may be used as a support.

The etching sacrificial layer 12 is not particularly limited as long as the etching rate is higher than that of Cu. If the etching rate is higher than Cu, it can be simultaneously dissolved and removed by Cu etching, and even if the etching sacrificial layer 12 is dissolved non-uniformly and Cu is locally exposed, the underlying first wiring layer is caused by local cell reaction. The dissolution of 26 (copper layer) is suppressed, whereby the surface copper layer 11 can be etched uniformly in the plane and the occurrence of local circuit dents can be suppressed. This etching rate is the same as that of the etching sacrificial layer 12 and the copper foil sample as a reference sample is processed for the same time in the etching process, and the change in thickness of each sample due to etching is determined by the dissolution time. It is calculated by dividing. The thickness change may be determined by measuring the weight reduction amount of both samples and converting the thickness from the density of each metal. A preferable etching rate is 1.2 times or more of Cu etching rate, more preferably 1.25 times or more, and further preferably 1.3 times or more. The upper limit of the etching rate is not particularly limited. However, in order to keep the dissolution rate of the etching sacrificial layer 12 in the plane uniform and cause the local cell reaction with the surface copper layer 11 to act uniformly in the plane, it is 5.0 times or less. The etching rate is preferably 4.5 times or less, more preferably 4.0 times or less, particularly preferably 3.5 times or less, and most preferably 3.0 times or less. Here, as the etching solution, a known solution capable of dissolving copper by an oxidation-reduction reaction can be employed. Examples of the etching solution include cupric chloride (CuCl ₂ ) aqueous solution, ferric chloride (FeCl ₃ ) aqueous solution, ammonium persulfate aqueous solution, sodium persulfate aqueous solution, potassium persulfate aqueous solution, sulfuric acid / hydrogen peroxide aqueous solution and the like. Etc. Among these, the Cu etching rate can be precisely controlled, and from the viewpoint of ensuring a difference in etching time with the etching sacrificial layer 12, a sodium persulfate aqueous solution, a potassium persulfate aqueous solution, and a sulfuric acid / hydrogen peroxide solution are preferable. Of these, sulfuric acid / hydrogen peroxide solution is most preferable. As an etching method, a spray method, a dipping method, or the like can be employed. The etching temperature can be appropriately set within the range of 25 to 70 ° C. The etching rate in the present invention is adjusted by a combination of the above etching solution and etching method and the selection of the material of the etching sacrificial layer 12 described below.

The material constituting the etching sacrificial layer 12 is preferably an electrochemically base metal rather than Cu. Examples of such a preferable metal include a Cu—Zn alloy, a Cu—Sn alloy, a Cu—Mn alloy, and Cu—Al. Alloys, Cu—Mg alloys, Zn metals, Co metals, Mo metals, and oxides thereof, and combinations thereof can be mentioned, and Cu—Zn alloys are particularly preferable. From the viewpoint of obtaining a high sacrificial effect, the Cu—Zn alloy that can constitute the etching sacrificial layer 12 preferably contains 40% by weight or more of Zn, more preferably 50% by weight or more, and even more preferably 60% by weight or more. Preferably it is 70 weight% or more. In addition, the Zn content in the Cu—Zn alloy is preferably 98 from the viewpoints of maintaining the uniform in-plane dissolution rate of the etching sacrificial layer 12 and the in-plane uniform action of the local cell reaction with the surface copper layer 11. % By weight or less, more preferably 96% by weight or less, and still more preferably 94% by weight or less. The etching sacrificial layer 12 preferably has a thickness of 0.1 to 5 μm, more preferably 0.1 to 4.5 μm, still more preferably 0.2 to 4 μm, particularly preferably 0.2 to 3.5 μm, Most preferably, it is 0.3 to 3 μm.

The surface copper layer 11 may have a known configuration and is not particularly limited. For example, the surface copper layer 11 may be formed by a wet film formation method such as an electroless plating method and an electrolytic plating method, a dry film formation method such as sputtering and chemical vapor deposition, or a combination thereof. The surface copper layer 11 preferably has a thickness of 0.1 to 2.5 μm, more preferably 0.1 to 2 μm, still more preferably 0.1 to 1.5 μm, particularly preferably 0.2 to 1 μm, Most preferably, it is 0.2 to 0.8 μm.

If desired, the surface copper layer 11 can be roughened. When performing an appearance image inspection after the wiring pattern is formed, the roughened particles formed by the roughening treatment are attached to the surface of the surface copper layer 11, thereby facilitating the image inspection after the wiring pattern is formed and the photoresist pattern. Adhesion with 20 can be improved. The roughened particles preferably have an average particle size D of 0.04 to 0.53 μm by image analysis, more preferably 0.08 to 0.13 μm, still more preferably 0.09 to 0.12 μm. . Within the above preferable range, the roughened surface has an appropriate roughness and ensures excellent adhesion to the photoresist, while achieving good opening of the unnecessary areas of the photoresist during photoresist development. As a result, it is possible to effectively prevent line deficiency of the pattern plating 22 that may be caused by difficulty in plating due to the photoresist that cannot be fully opened. Therefore, it can be said that it is excellent in photoresist developability and pattern plating property within the above-mentioned preferable range, and is therefore suitable for fine formation of the wiring pattern 24. The average particle diameter D by image analysis of the roughened particles is obtained by taking an image at a magnification such that a predetermined number (for example, 1000 to 3000) of particles enters one field of view of a scanning electron microscope (SEM). Measurement is preferably performed by performing image processing with commercially available image analysis software. For example, 200 particles arbitrarily selected may be used as an object, and the average diameter of these particles may be adopted as the average particle diameter D.

The roughened particles preferably have a particle density ρ by image analysis of 4 to 200 particles / μm ² , more preferably 40 to 170 particles / μm ² , and 70 to 100 particles / μm ² . When the roughened particles on the surface copper layer 11 surface are dense and dense, a development residue of the photoresist is likely to be generated, but if it is within the above-mentioned preferred range, such a development residue is difficult to be generated. The developability of the photoresist pattern 20 is also excellent. Therefore, it can be said that it is suitable for fine formation of the wiring pattern 24 within the above-mentioned preferable range. The particle density ρ based on the image analysis of the roughened particles is obtained by taking an image at a magnification such that a predetermined number (for example, 1000 to 3000) of particles enters one field of view of a scanning electron microscope (SEM). It is preferable to perform measurement by performing image processing using commercially available image analysis software. For example, in a field where 200 particles enter, the value obtained by dividing the number of particles (for example, 200) by the field area is used as the particle density ρ. do it.

The surface of the surface copper layer 11 can be subjected to rust prevention treatment such as nickel-zinc / chromate treatment, coupling treatment with a silane coupling agent, etc., in addition to the adhesion of the roughened particles by the roughening treatment described above. By these surface treatments, it is possible to improve the chemical stability of the surface of the metal foil and to improve the adhesion when the insulating layer is laminated.

The additional copper layer 13 may also have a known configuration and is not particularly limited. By providing the additional copper layer 13, it becomes possible to control the sacrificial layer 12 having a high dissolution rate in the pre-treatment in the Cu etching process so as not to be exposed, and the releasability from the following release layer is easy. There is an advantage that can be done. The additional copper layer 13 may be formed by a wet film formation method such as an electroless plating method and an electrolytic plating method, a dry film formation method such as sputtering and chemical vapor deposition, or a combination thereof. The additional copper layer 13 preferably has a thickness of 0.1 to 2.5 μm, more preferably 0.1 to 2 μm, still more preferably 0.2 to 1.5 μm, particularly preferably 0.2 to 1 μm, Most preferably, it is 0.3 to 0.8 μm.

The number of pinholes per unit area of the additional copper layer 13 is preferably ² / mm ² or less. When the number of pinholes in the additional copper layer 13 is small as described above, the number of pinholes that can be generated in the etching sacrificial layer 12 and the surface copper layer 11 plated on the additional copper layer 13 is also small in the manufacturing process of the metal foil 10 ′. can do. As a result, defects such as defects due to chemical erosion during Cu etching can be further reduced.

If desired, between the surface copper layer 11 and the etching sacrificial layer 12 and / or between the additional copper layer 13 (if present) and the etching sacrificial layer 12, as long as the sacrificial effect of the etching sacrificial layer 12 is not disturbed. Another layer may be present.

The surface copper layer 11, the etched sacrificial layer 12, and the additional copper layer 13 (if present) may be provided in the form of a carrierless copper foil or as shown in FIGS. Alternatively, it may be provided in the form of 14 ', but is preferably provided in the form of metal foil with carrier 14 or 14'. In this case, the carrier-attached metal foil may include a carrier 15, a release layer 16, an additional copper layer 13 (if present), an etching sacrificial layer 12, and a surface copper layer 11 in this order, or the carrier 15. The additional copper layer 13 (if present), the etching sacrificial layer 12, and the surface copper layer 11 may be provided in this order. That is, the release layer 16 may be provided, or the release layer 16 may not be provided as a single layer.

The carrier 15 is a layer (typically a foil) for supporting the metal foil and improving its handleability. Examples of the carrier include an aluminum foil, a copper foil, a stainless steel foil, a resin film, a resin film whose surface is metal-coated, a glass plate, and the like, preferably a copper foil. The copper foil may be a rolled copper foil or an electrolytic copper foil. The thickness of the carrier is typically 250 μm or less, preferably 12 μm to 200 μm.

The release layer 16 has a function of reducing the peeling strength of the carrier 15, ensuring the stability of the strength, and further suppressing interdiffusion that may occur between the carrier and the metal foil during press molding at a high temperature. It is. The release layer is generally formed on one side of the carrier, but may be formed on both sides. The release layer may be either an organic release layer or an inorganic release layer. Examples of organic components used in the organic release layer include nitrogen-containing organic compounds, sulfur-containing organic compounds, carboxylic acids and the like. Examples of nitrogen-containing organic compounds include triazole compounds, imidazole compounds, and the like. Among these, triazole compounds are preferred in terms of easy release stability. Examples of triazole compounds include 1,2,3-benzotriazole, carboxybenzotriazole, N ′, N′-bis (benzotriazolylmethyl) urea, 1H-1,2,4-triazole and 3-amino- And 1H-1,2,4-triazole. Examples of the sulfur-containing organic compound include mercaptobenzothiazole, thiocyanuric acid, 2-benzimidazolethiol and the like. Examples of the carboxylic acid include monocarboxylic acid and dicarboxylic acid. On the other hand, examples of inorganic components used in the inorganic release layer include Ni, Mo, Co, Cr, Fe, Ti, W, P, Zn, a chromate-treated film, and a carbon layer. The release layer may be formed by bringing the release layer component-containing solution into contact with at least one surface of the carrier and adsorbing the release layer component on the surface of the carrier in the solution. When the carrier is brought into contact with the release layer component-containing solution, this contact may be performed by immersion in the release layer component-containing solution, spraying of the release layer component-containing solution, flowing down of the release layer component-containing solution, or the like. In addition, it is also possible to employ a method of forming a release layer component by a plating method such as electrolytic plating or electroless plating, or a vapor phase method such as vapor deposition or sputtering. The release layer component may be fixed to the carrier surface by drying the release layer component-containing solution, electrodeposition of the release layer component in the release layer component-containing solution, or the like. The thickness of the release layer is typically 1 nm to 1 μm, preferably 5 nm to 500 nm. The peel strength between the release layer 16 and the carrier is preferably 7 gf / cm to 50 gf / cm, more preferably 10 gf / cm to 40 gf / cm, and more preferably 15 gf / cm to 30 gf / cm.

If desired, prior to the formation of the laminate with the build-up wiring layer, the metal foil 10 or the metal foil 10 ′ or the metal foil 14 with the carrier or the metal foil 14 ′ with the carrier is laminated on one or both sides of the coreless support 18 and laminated. You may form a body. This lamination may be performed in accordance with known conditions and techniques adopted for lamination of copper foil and prepreg in a normal printed wiring board manufacturing process. The coreless support 18 typically comprises a resin, preferably an insulating resin. The coreless support 18 is preferably a prepreg and / or a resin sheet, more preferably a prepreg. The prepreg is a general term for composite materials in which a synthetic resin is impregnated or laminated on a base material such as a synthetic resin plate, a glass plate, a glass woven fabric, a glass nonwoven fabric, and paper. Preferable examples of the insulating resin impregnated in the prepreg include epoxy resin, cyanate resin, bismaleimide triazine resin (BT resin), polyphenylene ether resin, phenol resin, polyamide resin and the like. Examples of the insulating resin constituting the resin sheet include insulating resins such as an epoxy resin, a polyimide resin, and a polyester resin (liquid crystal polymer). The coreless support 18 may contain filler particles made of various inorganic particles such as silica and alumina from the viewpoint of lowering the thermal expansion coefficient and increasing rigidity. The thickness of the coreless support 18 is not particularly limited, but is preferably 3 to 1000 μm, more preferably 5 to 400 μm, and still more preferably 10 to 200 μm.

(2) Formation of a laminate with a buildup wiring layer In the method of the present invention, a buildup wiring layer 42 including at least a copper first wiring layer 26 and an insulating layer 28 is formed on the surface copper layer 11. A laminate with a build-up wiring layer is obtained. The insulating layer 28 may be made of the insulating resin as described above. The build-up wiring layer 42 may be formed according to a known method for manufacturing a printed wiring board, and is not particularly limited. According to a preferred embodiment of the present invention, as described below, the first wiring layer 26 is formed by performing (i) forming a photoresist pattern, (ii) performing electrolytic copper plating, and (iii) stripping the photoresist pattern. After that, (iv) the build-up wiring layer 42 is formed.

(I) Forming a photoresist pattern First, a photoresist pattern 20 is formed on the surface of the surface copper layer 11. The formation of the photoresist pattern 20 may be performed by either a negative resist or a positive resist, and the photoresist may be either a film type or a liquid type. Further, the developing solution may be a developing solution such as sodium carbonate, sodium hydroxide, an amine-based aqueous solution, etc., and may be carried out in accordance with various methods and conditions generally used in the production of printed wiring boards, and is not particularly limited.

(Ii) Electrolytic copper plating Next, electrolytic copper plating 22 is applied to the surface copper layer 11 on which the photoresist pattern 20 is formed. The formation of the electrolytic copper plating 22 is not particularly limited as long as it is performed in accordance with various pattern plating methods and conditions generally used in the production of printed wiring boards such as a copper sulfate plating solution and a copper pyrophosphate plating solution.

(Iii) Stripping of photoresist pattern The photoresist pattern 20 is stripped to form a wiring pattern 24. Stripping of the photoresist pattern 20 is not particularly limited as long as an aqueous sodium hydroxide solution, an amine-based solution or an aqueous solution thereof is employed, and may be performed in accordance with various stripping methods and conditions generally used in the manufacture of printed wiring boards. Thus, a wiring pattern 24 in which wiring portions (lines) made of the first wiring layer 26 are arranged with a gap (space) therebetween is directly formed on the surface of the surface copper layer 11. For example, for circuit miniaturization, the line / space (L / S) is highly fine, such as 13 μm or less / 13 μm or less (for example, 12 μm / 12 μm, 10 μm / 10 μm, 5 μm / 5 μm, 2 μm / 2 μm). It is preferable to form a simplified wiring pattern.

(Iv) Formation of build-up wiring layer Build-up wiring layer 42 is formed on surface copper layer 11, and a laminated body with a build-up wiring layer is produced. For example, in addition to the first wiring layer 26 already formed on the surface copper layer 11, the insulating layer 28 and the second wiring layer 38 can be formed in order to form the build-up wiring layer 42. For example, as shown in FIG. 5, the insulating layer 28 and the carrier-attached copper foil 30 (including the carrier 32, the release layer 34, and the copper foil 36) are laminated to form the build-up wiring layer 42, and the carrier 32 is peeled off. In addition, the copper foil 36 and the insulating layer 28 immediately below it may be laser processed by a carbon dioxide laser or the like. Subsequently, patterning is performed by electroless copper plating, photoresist processing, electrolytic copper plating, photoresist stripping, flash etching, or the like to form the second wiring layer 38, and this patterning is repeated as needed to repeat the nth wiring layer. You may form to 40 (n is an integer greater than or equal to 2).

The method for forming the build-up layer after the second wiring layer 38 is not limited to the above method, but is a subtractive method, an MSAP (Modified Semi-Additive Process) method, an SAP (Semi-Additive) method, or a full additive method. Etc. can be used. For example, when a metal foil typified by a resin layer and a copper foil is bonded together by pressing, the panel plating layer and the metal foil are etched in combination with the formation of interlayer conduction means such as via hole formation and panel plating. Thus, a wiring pattern can be formed. When only the resin layer is bonded to the surface of the surface copper layer 11 by pressing or laminating, a wiring pattern can be formed on the surface by a semi-additive method.

The above process is repeated as necessary to obtain a laminate with a build-up wiring layer. In this process, a build-up wiring layer in which a resin layer and a wiring layer including a wiring pattern are alternately stacked is formed, and the n-th wiring layer 40 (n is an integer of 2 or more) is formed. It is preferable to obtain a laminate. This process may be repeated until a desired number of build-up wiring layers are formed. At this stage, if necessary, solder resist, bumps for mounting such as pillars, and the like may be formed on the outer layer surface. Further, an outer layer wiring pattern may be formed on the outermost layer surface of the build-up wiring layer in a later outer layer processing step.

(3) Formation of printed wiring board including build-up wiring layer (i) Separation of laminate with build-up wiring layer After forming the laminate with build-up wiring layer, the laminate with build-up wiring layer is separated from the release layer 16. Etc. can be separated. When the carrier-attached metal foil comprises the carrier 15, the release layer 16, the additional copper layer 13 (if present), the etching sacrificial layer 12, and the surface copper layer 11 in this order, the method of the present invention can be removed by an etching solution described later. Prior to the step, it is preferable to separate the stacked body with the buildup wiring layer by the release layer 16 to expose the etching sacrificial layer 12 or the additional copper layer 13. As the separation method, physical peeling is preferable, and for this peeling method, a machine or jig, manual work, or a combination thereof may be employed.

On the other hand, when the metal foil with carrier comprises the carrier 15, the additional copper layer 13 (if present), the etching sacrificial layer 12, and the surface copper layer 11 in this order (that is, when the release layer 16 is not provided as a single layer). In the method of the present invention, a build-up wiring layer is attached between the carrier 15 and the etching sacrificial layer 12, between the additional copper layer 13 and the etching sacrificial layer 12, or inside the etching sacrificial layer 12, prior to removal with an etching solution described later. It is preferable to separate the stacked body to expose the etching sacrificial layer 12.

(Ii) Etching of etching sacrificial layer and copper layer In the method of the present invention, the surface copper layer 11, the etching sacrificial layer 12, and the additional copper layer 13 (if present) are removed with an etching solution to remove the first wiring layer 26. The printed wiring board 46 including the build-up wiring layer 42 is obtained by exposing. The printed wiring board 46 is preferably a multilayer printed wiring board. In any case, due to the presence of the etching sacrificial layer 12, it is possible to efficiently remove each layer uniformly by etching in the surface by Cu etching without the need for an additional etching step, and local circuit dents are generated. Can be suppressed. Therefore, according to the method of the present invention, the surface copper layer 11 and the sacrificial etching layer 12 are removed by the etching solution, or the surface copper layer 11, the etching sacrificial layer 12 and the additional copper layer 13 are removed by the etching solution in one step. be able to. The etching solution and etching method used at this time are as described above.

(Iii) Outer layer processing The printed wiring board 46 as shown in FIG. 5 can be processed into an outer layer by various methods. For example, an insulating layer and a wiring layer as build-up wiring layers may be further laminated on the first wiring layer 26 of the printed wiring board 46 as an arbitrary number of layers, or a solder resist layer is formed on the surface of the first wiring layer 26. And surface treatment as an outer layer pad such as Ni—Au plating, Ni—Pd—Au plating, or water-soluble preflux treatment may be performed. Furthermore, a columnar pillar or the like may be provided on the outer layer pad. At this time, the first wiring layer 26 formed using the etching sacrificial layer in the present invention can maintain the uniformity of the circuit thickness in the plane, and the surface of the first wiring layer 26 has a local circuit depression. Is less likely to occur. For this reason, there is a low incidence of defects such as local processing failures and solder-resist residue failures in the surface treatment process caused by extremely thin parts of the circuit thickness, circuit depressions, etc., and mounting failures due to mounting pad irregularities. A printed wiring board having excellent mounting reliability can be obtained.

The present invention will be described more specifically with reference to the following examples.

Examples 1-11
Production and various evaluations of the metal foil of the present invention were performed as follows.

(1) Preparation of carrier A rotating electrode made of titanium whose surface was polished with a buff of # 2000 was prepared as a rotating cathode. Further, a DSA (dimensional stability anode) was prepared for the anode. Rotating cathode and anode are copper sulfate having a copper concentration of 80 g / L, a sulfuric acid concentration of 260 g / L, a bis (3-sulfopropyl) disulfide concentration of 30 mg / L, a diallyldimethylammonium chloride polymer concentration of 50 mg / L, and a chlorine concentration of 40 mg / L. It was immersed in a solution and electrolyzed at a solution temperature of 45 ° C. and a current density of 55 A / dm ² to obtain an electrolytic copper foil having a thickness of 18 μm as a carrier.

(2) Formation of Release Layer The electrode surface side of the pickled carrier is placed in a CBTA aqueous solution having a CBTA (carboxybenzotriazole) concentration of 1 g / L, a sulfuric acid concentration of 150 g / L, and a copper concentration of 10 g / L, at a liquid temperature of 30 ° C. So as to adsorb the CBTA component on the electrode surface of the carrier. Thus, a CBTA layer was formed as an organic release layer on the surface of the electrode surface of the carrier copper foil.

(3) Formation of Auxiliary Metal Layer The carrier on which the organic peeling layer is formed is immersed in a solution having a nickel concentration of 20 g / L prepared using nickel sulfate, and the liquid temperature is 45 ° C., the pH is 3, and the current density is 5 A / dm 2. Under the conditions, nickel having a thickness equivalent to 0.001 μm was deposited on the organic release layer. Thus, a nickel layer was formed as an auxiliary metal layer on the organic release layer.

(4) Formation of additional copper layer (ultra thin copper foil) In Examples 1 to 8 and 11, the carrier on which the auxiliary metal layer was formed was immersed in a copper sulfate solution having a copper concentration of 60 g / L and a sulfuric acid concentration of 200 g / L. Then, electrolysis was performed at a solution temperature of 50 ° C. and a current density of 5 to 30 A / dm ² to form an additional copper layer (ultra thin copper foil) having a thickness of 0.3 μm on the auxiliary metal layer. On the other hand, in Examples 9 and 10, no additional copper layer was formed.

(5) Formation of etching sacrificial layer Table 1 shows carriers (Examples 1 to 8 and 11) on which an additional copper layer (ultra thin copper foil) is formed or carriers (Example 10) on which an auxiliary metal layer is formed. It was immersed in a plating bath and electrolyzed under the plating conditions shown in Table 1, and an etching sacrificial layer having the composition and thickness shown in Table 2 was formed on the additional copper layer or the auxiliary metal layer. On the other hand, in Example 9, the etching sacrificial layer was not formed.

(6) Formation of surface copper layer Carrier (Examples 1 to 8, 10 and 11) on which an etching sacrificial layer was formed or carrier (Example 9) on which an auxiliary metal layer was formed was subjected to a copper concentration of 60 g / L and a sulfuric acid concentration of 145 g. / L copper sulfate solution and electrolysis at a solution temperature of 45 ° C. and a current density of 30 A / dm ² to form a surface copper layer having a thickness shown in Table 2 on the etching sacrificial layer or the auxiliary metal layer. .

(7) Rust prevention treatment The surface of the metal foil with carrier thus formed was subjected to a rust prevention treatment comprising zinc-nickel alloy plating treatment and chromate treatment. First, using an electrolytic solution having a zinc concentration of 0.2 g / L, a nickel concentration of 2 g / L, and a potassium pyrophosphate concentration of 300 g / L, under conditions of a liquid temperature of 40 ° C. and a current density of 0.5 A / dm ² , the metal foil and the carrier A zinc-nickel alloy plating treatment was performed on the surface of the substrate. Next, a chromate treatment was performed on the surface on which the zinc-nickel alloy plating treatment was performed using a 3 g / L aqueous solution of chromic acid under the conditions of pH 10 and a current density of 5 A / dm ² .

(8) Silane coupling agent treatment A silane coupling agent is prepared by adsorbing an aqueous solution containing 2 g / L of 3-glycidoxypropyltrimethoxysilane to the surface of the carrier-side metal foil and evaporating water with an electric heater. Processed. At this time, the silane coupling agent treatment was not performed on the metal foil side.

(9) Evaluation Various evaluations were performed on the metal foil with a carrier thus obtained and its constituent layers as follows.

Evaluation 1 : Etching rate ratio r
In order to measure the ratio r of the etching rate of the etching sacrificial layer 12 to the etching rate of Cu (hereinafter referred to as the etching rate ratio r), Examples 1 to 8, 10 and 11 were obtained in the above (5). A carrier whose outermost surface is an etching sacrificial layer (that is, an intermediate product in which the etching sacrificial layer is formed and the surface copper layer is not formed and processed thereafter) was prepared. Further, for Example 9, a metal foil with a carrier whose outermost surface obtained in (6) is a surface copper layer (that is, an intermediate product in which the surface copper layer is formed and the subsequent treatment is not performed) is prepared. did. On the other hand, commercially available 95 wt% concentrated sulfuric acid and 30 wt% hydrogen peroxide water were dissolved in water to produce an etching solution having a sulfuric acid concentration of 5.9 wt% and a hydrogen peroxide concentration of 2.1 wt%. Each metal foil sample with a carrier is immersed in an etching solution at 25 ° C. for a certain period of time and dissolved, and the thickness change of the plating film before and after dissolution is measured by a fluorescent X-ray film thickness meter (Fischerscope X-Ray XDAL-, manufactured by Fischer Instruments). FD). The etching rate of each target plating film was determined by dividing the obtained thickness change by the dissolution time. The etching rate of Example 9 thus obtained is the etching rate of Cu, and the etching rates of Examples 1 to 8, 10 and 11 are the etching rates of the respective etching sacrificial layers. Then, the etching rate ratio r was calculated by dividing the etching rate of the etching sacrificial layer by the etching rate of Cu. The results were as shown in Table 2.

Evaluation 2 : The number of pinholes per unit area In order to measure the number of pinholes per unit area of the additional copper layer, the carrier whose outermost surface obtained in (4) is an additional copper layer (ultra-thin copper foil) An attached ultra-thin copper foil (that is, an intermediate product in which an additional copper layer having a thickness of 0.3 μm was formed and an etching sacrificial layer was not formed and thereafter processed) was prepared. This ultrathin copper foil with a carrier is laminated so that the additional copper layer (ultrathin copper foil) side is in contact with an insulating resin base material (prepreg made by Panasonic Corporation, R-1661, thickness 0.1 mm), and the pressure is 4.0 MPa. And thermocompression bonded at a temperature of 190 ° C. for 90 minutes. Thereafter, the carrier was peeled off to obtain a laminate. This laminated plate was observed with an optical microscope while applying a backlight in a dark room, and the number of pinholes was counted. Thus, when the number of pinholes per 1 mm ² was measured, in any of Examples 1 to 8 and 11, the number of pinholes per unit area of the additional copper layer was 2 / mm ² or less.

Evaluation 3 : Circuit recess The carrier-side metal foil obtained in (8) above is in contact with the first insulating resin base material (Panasonic Corporation prepreg, R-1661, thickness 0.1 mm) on the carrier side. And thermocompression bonded at a pressure of 4.0 MPa and a temperature of 190 ° C. for 90 minutes. The laminated plate thus obtained was laminated with a 19 μm-thick dry film on the metal foil side, exposed using a line / space (L / S) = 10/10 μm mask, and developed. After pattern development was performed on the laminate after development so that the plating height was 17 μm, the dry film was peeled off to form five linear circuits of L / S = 10/10. Next, a second insulating resin base material (prepreg made by Panasonic Corporation, R-1661, thickness 0.1 mm) was laminated on the surface of the laminated plate on which the five linear circuits were formed, and the pressure was 4.0 MPa, Thermocompression bonding was performed at a temperature of 190 ° C. for 90 minutes. Thereafter, the carrier and the first insulating resin substrate to which it was adhered were peeled off with the release layer as a boundary. Etching was performed on the side of the remaining second insulating resin base material where the metal foil was exposed, using the same etching solution prepared in Evaluation 1 until the metal foil disappeared. In this state, the cross section was observed at 2,000 times using an optical microscope, and the distance from the upper end of the second insulating resin substrate to the upper end of the circuit was measured as a circuit recess for five circuits, and the following criteria were used. Rating rating.
・ Evaluation A: The maximum value among 5 pieces is less than 2.0 μm ・ Evaluation B: The maximum value among 5 pieces is less than 2.0 μm and less than 2.5 μm ・ Evaluation C: Among 5 pieces With a maximum value of 2.5 μm or more (actually 3.0 μm or more)

Claims

A step of obtaining a support using a metal foil provided with a surface copper layer and an etching sacrificial layer in this order, or a metal foil provided with a surface copper layer, an etching sacrificial layer and an additional copper layer in this order;
Forming a buildup wiring layer including at least a copper first wiring layer and an insulating layer on the surface copper layer to obtain a laminate with a buildup wiring layer;
The surface copper layer and the etching sacrificial layer, or the surface copper layer, the etching sacrificial layer, and the additional copper layer are removed with an etching solution to expose the first wiring layer, thereby forming the build-up wiring layer. Obtaining a printed wiring board including:
And the etching sacrificial layer has a higher etching rate than Cu.
The etching sacrificial layer is selected from the group consisting of Cu—Zn alloy, Cu—Sn alloy, Cu—Mn alloy, Cu—Al alloy, Cu—Mg alloy, Zn metal, Co metal, Mo metal and oxides thereof. The method according to claim 1, comprising at least one selected from the group consisting of:
The method according to claim 1 or 2, wherein the etching sacrificial layer is made of a Cu-Zn alloy containing 40 wt% or more of Zn.
The method according to any one of claims 1 to 3, wherein the etching sacrificial layer has a thickness of 0.1 to 5 袖 m.
The method according to any one of claims 1 to 4, wherein the surface copper layer, the etching sacrificial layer, and the additional copper layer, if present, are provided in the form of a metal foil or a metal foil with a carrier. .
The surface copper layer, the etching sacrificial layer, and the additional copper layer, if present, are provided in the form of a metal foil with a carrier, and the metal foil with carrier is a carrier, a release layer, if present An additional copper layer, the etching sacrificial layer, and the surface copper layer in order,
The method further includes the step of separating the stacked body with the buildup wiring layer by the release layer to expose the etching sacrificial layer or the additional copper layer prior to the removal by the etching solution. The method as described in any one of.
The surface copper layer, the etching sacrificial layer, and the additional copper layer, if present, are provided in the form of a metal foil with a carrier, the carrier-added metal foil when present, the additional copper layer. , The etching sacrificial layer, and the surface copper layer in order,
Prior to the removal by the etching solution, the method separates the stacked body with the build-up wiring layer between the carrier and the etching sacrificial layer or between the additional copper layer and the etching sacrificial layer or inside the etching sacrificial layer. The method according to any one of claims 1 to 5, further comprising exposing the etching sacrificial layer.
The removal of the surface copper layer and the etching sacrificial layer with an etchant or the removal of the surface copper layer, the etching sacrificial layer, and the additional copper layer with an etchant is performed in one step. The method according to claim 1.