WO2017141985A1

WO2017141985A1 - Copper foil for printed circuit board production, copper foil with carrier, and copper-clad laminate plate, and printed circuit board production method using copper foil for printed circuit board production, copper foil with carrier, and copper-clad laminate plate

Info

Publication number: WO2017141985A1
Application number: PCT/JP2017/005579
Authority: WO
Inventors: 光由松田; 哲聡 ▲高▼梨; 浩人飯田; 吉川　和広; 翼加藤; 金子　智一
Original assignee: 三井金属鉱業株式会社
Priority date: 2016-02-18
Filing date: 2017-02-15
Publication date: 2017-08-24
Also published as: JP6836580B2; JPWO2017141985A1; KR20180113996A; CN108702847B; TW201733793A; CN108702847A; MY188258A; TWI626151B

Abstract

The purpose of the present invention is to provide a copper foil that is for printed circuit board production and that significantly reduces in-plane Cu etching variations without the need for a separate additional etching step and can thereby suppress the occurrence of damage to a seed layer, circuit depressions, etc. This copper foil comprises, in order, a first copper layer, an etching sacrificial layer, and a second copper layer. The ratio r of the etching rate of the etching sacrificial layer to the etching rate of Cu is higher than 1.0.

Description

Copper foil for manufacturing printed wiring board, copper foil with carrier and copper-clad laminate, and method for manufacturing printed wiring board using them

The present invention relates to a copper foil for producing a printed wiring board, a copper foil with a carrier and a copper clad laminate, and a method for producing a printed wiring board using them.

The MSAP (Modified Semi-Additive Process) method is widely used as a printed wiring board manufacturing method suitable for circuit miniaturization. The MSAP method is a method suitable for forming an extremely fine circuit, and is performed using an ultrathin copper foil with a carrier in order to take advantage of the feature. For example, as shown in FIGS. 4 and 5, an ultrathin copper foil 110 is applied to a primer layer on an insulating resin substrate 111 having a prepreg 111b on a base substrate 111a (a lower circuit 111c may be included if necessary). 112 is used for pressing (step (a)), the carrier (not shown) is peeled off, and then via holes 113 are formed by laser drilling as necessary (step (b)). Next, after applying chemical copper plating 114 (step (c)), masking with a predetermined pattern by exposure and development using a dry film 115 (step (d)) and applying electrolytic copper plating 116 (step (e) )). After the dry film 115 was removed to form the wiring portion 116a (step (f)), unnecessary ultrathin copper foil or the like between the

adjacent wiring portions

116a and 116a was removed by etching over the entire thickness (step). (G)), the wiring 117 formed in a predetermined pattern is obtained. In particular, with the recent reduction in size and weight of electronic circuits, there is a need for MSAP copper foils that are more excellent in circuit formability (for example, can form fine circuits of line / space = 15 μm or less / 15 μm or less). For example, in Patent Document 1 (International Publication No. 2012/046804), a release layer and a copper foil are provided on a carrier having an average spacing Sm of surface irregularities of stipulated in JIS-B-06020-1994 of 25 μm or more. A copper foil obtained by laminating in this order and peeling the copper foil from the carrier has been disclosed. By using this copper foil, the line / space can be reduced to a very narrow width of 15 μm or less without reducing the linearity of the wiring line. It is said that etching is possible.

On the other hand, as a manufacturing method of a printed wiring board suitable for weight reduction and miniaturization, a wiring layer is formed on a metal layer on the surface of a support (core), and a buildup layer is further formed. A manufacturing method using a coreless build-up method is employed. Since a printed wiring board manufactured by such a method is of a type in which a circuit pattern is embedded in an insulating layer, this method is called an ETS (Embedded Trace Substrate) method. 11 and 12 show a conventional example of a method for manufacturing a printed wiring board by a coreless buildup method using a copper foil with a carrier as a member for a support having a metal layer on the surface. In the example shown in FIGS. 11 and 12, first, a copper foil with carrier 210 including a carrier 212, a peeling layer 214, and a copper foil 216 in this order is laminated on a coreless support 218 such as a prepreg. Next, a photoresist pattern 220 is formed on the copper foil 216, and a wiring pattern 224 is formed through formation of pattern plating (electrocopper plating) 222 and peeling of the photoresist pattern 220. Then, a pre-stacking process such as a roughening process is performed on the pattern plating as necessary to form the first wiring layer 226. Next, as shown in FIG. 12, a copper foil 230 with a carrier (a carrier 232, a release layer 234, and a seed layer for the insulating layer 228 and, if necessary, the second wiring layer 238 to form a build-up layer 242). The copper foil 236 is provided), the carrier 232 is peeled off, and the copper foil 236 and the insulating layer 228 immediately below it are punched with a laser or the like. Subsequently, patterning is performed by chemical copper plating, photoresist processing, electrolytic copper plating, photoresist stripping, flash etching, or the like to form the second wiring layer 238, and this patterning is repeated as necessary to repeat the nth wiring layer 240. (N is an integer of 2 or more). Then, the coreless support 218 is peeled off together with the carrier 212 to form a build-up wiring board 244 (also referred to as a coreless wiring board), and the copper foil 216 exposed between the wiring patterns of the first wiring layer 226 and the build if present. The copper foil 236 and the like exposed between the wiring patterns of the n-th wiring layer 240 of the up layer 242 are removed by flash etching to obtain a predetermined wiring pattern, and a printed wiring board 246 is obtained.

International Publication No. 2012/046804 JP 2014-63950 A

By the way, in the MSAP method (see FIGS. 4 and 5), after the formation of the via hole 113 (step (b)) and before the formation of the chemical copper plating 114 (step c)), the lower layer circuit 111c on the bottom surface of the via hole is formed. In some cases, micro-etching (Cu etching) is performed for the purpose of cleaning or removing the splash adhered around the via hole. In recent years, from the viewpoint of circuit miniaturization, the thickness of the ultrathin copper layer 110 is made thinner than before, and the seed layer (ultrathin copper foil 110) at the time after the microetching is about 0.3 μm. It has come to be desired to become the thickness of. However, if the laminated body of the ultrathin copper foil 110 and the insulating resin substrate 111 thus thinned is to be microetched, the in-plane variation of the microetching during the microetching is conceptually shown in FIG. As a result, a defect 110a may partially occur in the ultrathin copper foil 110 (seed layer). For this reason, a technique for suppressing the occurrence of such defects is desired.

On the other hand, in the ETS method, in the flash etching process (see FIGS. 11 and 12) in the coreless wiring board manufacturing process, minute pinholes existing in the exposed copper foil 216 and the in-plane liquid coating of the flash etching liquid are used. The amount of flash etching within the surface of the first wiring layer 226 tends to be non-uniform due to the non-uniformity of the contact pressure. In this case, as conceptually shown in FIG. 9, not only the copper foil 216 to be removed but also a part of the copper circuit (first wiring layer 226) to be left is etched unevenly. As a result, a non-uniform circuit recess 226a exceeding the standard value is generated. Such non-uniform circuit recesses 226a may lead to problems such as poor connection and disconnection in the printed wiring board mounting process and reliability test environment. Therefore, an attempt to reduce the etching of the wiring layer has been proposed. For example, in Patent Document 2 (Japanese Patent Laid-Open No. 2014-63950), an etching stopper layer formed of nickel is provided, and this etching stopper layer is removed by selective etching, thereby suppressing uneven dissolution of the copper circuit. However, it is disclosed to suppress a circuit dent that occurs non-uniformly in a plane. However, when the method of Patent Document 2 is adopted, as shown conceptually in FIG. 10, not only the copper foil 216 to be removed but also the etching stopper layer 215 that should not be removed is slightly present in the copper etching process. Elution may occur. In addition, if pinholes are present slightly when the etching stopper layer 215 is formed, the copper circuit (first wiring layer 226) may be locally exposed in the copper etching process. Thus, if the copper circuit (first wiring layer 226) is locally exposed due to non-uniform elution, dissolution of Cu constituting the copper circuit is accelerated and a large circuit recess 226a is generated locally. In the first place, when the etching stopper layer 215 is provided, a selective etching process for removing the etching stopper layer 215 is separately required, and thus the number of manufacturing processes is increased.

In the manufacture of printed wiring boards, the present inventors have recently used an additional etching step by using a copper foil in which an etching sacrificial layer having a high etching rate is interposed between the first copper layer and the second copper layer. It was found that the in-plane variation of Cu etching was significantly reduced without the necessity, and as a result, generation of seed layer defects and circuit dents as described above could be suppressed.

Accordingly, an object of the present invention is to provide a printed wiring board that can significantly reduce in-plane variation of Cu etching without requiring an additional etching step, and as a result, can suppress seed layer defects and circuit dents. It is to provide a copper foil for production.

According to an aspect of the present invention, the first copper layer, the etching sacrificial layer, and the second copper layer are provided in this order, and a ratio r of the etching sacrificial layer to the etching rate of Cu is less than 1.0. A high copper foil for producing printed wiring boards is provided.

According to another aspect of the present invention, there is provided a copper foil with a carrier provided with a carrier, a release layer, and the copper foil in this order.

According to another aspect of the present invention, a copper clad laminate provided with the copper foil is provided.

According to another aspect of the present invention, there is provided a method for manufacturing a printed wiring board, wherein the printed wiring board is manufactured using the copper foil or the copper foil with a carrier.

It is a cross-sectional schematic diagram which shows an example of the copper foil with a carrier containing the copper foil of this invention. It is a cross-sectional schematic diagram for demonstrating the function of the etching sacrificial layer in a MSAP method. It is a cross-sectional schematic diagram for demonstrating the nonuniform etching of the seed layer (ultra-thin copper foil) in the MSAP method using the conventional copper foil. It is a figure which shows the process of the first half in the prior art example of the manufacturing method of the printed wiring board using MSAP method. The latter half process following the process shown by FIG. 4 in the prior art example of the manufacturing method of the printed wiring board using MSAP method is shown. It is a cross-sectional schematic diagram for demonstrating the function of the etching sacrificial layer in a coreless buildup method (ETS construction method). It is a figure which shows the process of the first half in an example of the manufacturing method of the printed wiring board by the coreless buildup method (ETS construction method) using the copper foil of this invention. The latter half process following the process shown by FIG. 7 in an example of the manufacturing method of the printed wiring board by the coreless buildup method (ETS construction method) using the copper foil of this invention is shown. It is a cross-sectional schematic diagram for demonstrating the non-uniform etching of the copper circuit in the ETS construction method using the conventional copper foil. It is a cross-sectional schematic diagram for demonstrating the etching stopper layer and the non-uniform etching of a copper circuit in the ETS method using the conventional copper foil. It is a figure which shows the process of the first half in the prior art example of the manufacturing method of the printed wiring board using the coreless buildup method (ETS construction method). The latter half process following the process shown by FIG. 11 in the prior art example of the manufacturing method of the printed wiring board using the coreless buildup method (ETS construction method) is shown. It is a figure explaining the etching process in case a defect does not arise in a 2nd copper layer. It is a figure which illustrates notionally the etching process in case the residue of a 1st copper layer causes the defect | deletion of a 2nd copper layer.

Copper foil for manufacturing a printed wiring board The copper foil according to the present invention is a copper foil used for manufacturing a printed wiring board. FIG. 1 shows a schematic cross-sectional view of the copper foil of the present invention. As shown in FIG. 1, the copper foil 10 includes a first copper layer 11, an etching sacrificial layer 12, and a second copper layer 13 in this order. Although the etching sacrificial layer 12 may be a copper alloy layer, it is not a metal copper layer, and thus the copper foil 10 contains a metal or alloy other than copper as its inner layer. For this reason, although the copper foil of this invention can also be called sacrificial layer containing copper foil or metal foil, since both surfaces are comprised with a copper layer, it is recognized as copper foil as a product category. In addition, the names of “first copper layer” and “second copper layer” are generally referred to as “first copper layer” when the copper foil 10 is laminated with the insulating resin, and the copper layer that is not in close contact with the insulating resin. The copper layer that is in close contact with the insulating resin is the “second copper layer”. When the copper foil of the present invention is applied to the ETS method, the copper layer on the side where the circuit pattern is not formed is the “first copper layer”, and the copper layer on the side where the circuit pattern is formed is the “second copper layer”. Layer ". The order contained in these names follows the manufacturing sequence at the time of manufacture. For example, when the copper foil 10 is provided in the form of a copper foil 14 with a carrier as shown in FIG. 1, the carrier 15, the release layer 16, the first copper layer 11, the etching sacrificial layer 12, and the second copper layer 13. Will be manufactured in this order.

The etching sacrificial layer 12 is characterized by a ratio r of the etching rate of the etching sacrificial layer 12 to the etching rate of Cu being higher than 1.0. Thus, in the production of the printed wiring board, an additional etching process is performed by using the copper foil 10 in which the etching sacrificial layer 12 having a high etching rate is interposed between the first copper layer 11 and the second copper layer 13. Without being separately required, the in-plane variation of Cu etching can be significantly reduced, and as a result, generation of seed layer defects and circuit recesses as described above can be suppressed. That is, even if the etching sacrificial layer 12 having an etching rate ratio r higher than 1.0 is sandwiched between the two

copper layers

13 and 11, even if non-uniform dissolution occurs during Cu etching, the second copper layer The etching sacrificial layer 12 is not uniformly dissolved but 13. Therefore, even if the situation where Cu is locally exposed occurs, the etching sacrificial layer 12 can be preferentially dissolved by the local battery reaction, and as a result, dissolution of the underlying second copper layer 13 is suppressed. The

For example, in the case of the MSAP method, as conceptually shown in FIG. 2, the etching sacrificial layer 12 is dissolved non-uniformly during the microetching of the laminated body of the copper foil 10 and the insulating layer 28, and the second copper layer 13. Even if locally exposed, the etching sacrificial layer 12 is preferentially dissolved. As a result, the thickness of the second copper layer 13 is generally kept uniform, and defects are less likely to occur. In this regard, as described above, in the MSAP method using the conventional ultrathin copper foil 110 (see FIGS. 4 and 5), as conceptually shown in FIG. 3, the ultrathin copper foil 110 and the insulating resin substrate During microetching of the laminate with 111, defects 110a may be partially generated in the ultrathin copper foil 110 (seed layer) due to in-plane variation of microetching. On the other hand, the said technical subject can be advantageously eliminated by using the copper foil 10 of this invention.

On the other hand, in the case of the coreless buildup method (ETS method), as conceptually shown in FIGS. 6B and 6C, the etching sacrificial layer 12 is dissolved non-uniformly during the Cu etching and / or Even if Cu (the second copper layer 13 or the Cu of the first wiring layer 26) is locally exposed due to a pinhole or the like that may be accidentally present in the etching sacrificial layer 12, the local cell reaction causes the underlying first layer to be exposed. Dissolution of the two-copper layer 13 or the first wiring layer 26 (copper layer) is suppressed. As a result, the second copper layer 13 is uniformly etched in the plane, and local circuit dents in the first wiring layer 26 can be suppressed. In addition, according to this method, the etching sacrificial layer 12 is dissolved and removed along with the Cu etching, so that an additional step for removing the etching sacrificial layer 12 is not required, and the productivity is improved. Furthermore, there is an advantage that the circuit dents can be reduced on the average in the plane of the first wiring layer 26 by the effect of the high etching rate itself. In this regard, as described above, when the method of Patent Document 2 is adopted, as conceptually shown in FIG. 10, not only the copper foil 216 to be removed but also not originally removed in the copper etching process. The etching stopper layer 215 elutes slightly, and the underlying copper circuit (first wiring layer 226) is locally exposed due to pinholes or the like generated in the stage of forming the etching stopper layer 215. There is a fear. When the copper circuit (first wiring layer 226) is locally exposed in this way, dissolution of Cu constituting the copper circuit is accelerated, and a large circuit recess 226a is locally generated. In the first place, when the etching stopper layer 215 is provided, a selective etching process for removing the etching stopper layer 215 is separately required, and thus the number of manufacturing processes is increased. On the other hand, these technical problems can be advantageously solved by using the copper foil 10 of the present invention.

The 1st copper layer 11 may be a well-known copper foil structure, and is not specifically limited. By providing the first copper layer 11, it becomes possible to control the etching sacrificial layer 12 having a high dissolution rate in the pre-treatment in the Cu etching process so as not to be exposed, and the releasability from the following release layer is easy. There is an advantage that it can be. The first copper layer 11 may be formed by a wet film formation method such as an electroless plating method and an electrolytic plating method, a dry film formation method such as sputtering and chemical vapor deposition, or a combination thereof. The cuprous layer 11 preferably has a thickness d ₁ of 0.1 to 2.5 μm, more preferably 0.1 to 2 μm, still more preferably 0.2 to 1.5 μm, and particularly preferably 0.2. ˜1 μm, most preferably 0.3 to 0.8 μm. When the thickness d ₁ is in such a range, the etching sacrificial layer 12 can be more effectively protected in the previous step of Cu etching (for example, a chemical solution step such as desmear), and d ₂ / d ₁ ≧ r and the later-described / Or d ₁ + d ₂ + d ₃ <3.0 μm is easily satisfied, and as a result, defects such as defects during Cu etching can be more effectively prevented.

By the way, the first copper layer 11 can protect the etching sacrificial layer 12 from dissolution by a chemical solution in a pre-process of Cu etching (for example, a chemical process such as desmear). Defects may occur in the layer 13. From the viewpoint of effectively preventing such defects, it is preferable that d ₂ / d ₁ ≧ r is satisfied when the thickness of the first copper layer 11 is d ₁ and the thickness of the etching sacrificial layer 12 is d _2. . This will be described as follows with reference to a laminate of the copper foils 10 and 10 'and the insulating layer 28 conceptually shown in FIGS. First, as shown in FIG. 14A, when the first copper layer 11 ′ is excessively thick, the first copper layer 11 ′ is dissolved non-uniformly to expose the etching sacrificial layer 12 (FIG. 14 ( b)) The exposed etching sacrificial layer 12 can be immediately dissolved (preferentially over the remaining first copper layer 11 ′) to expose the second copper layer 13 (FIG. 14C). As a result, in parallel with the dissolution of the remaining first copper layer 11 ′, the dissolution of the exposed second copper layer 13 proceeds (FIG. 14D), and the defect 13 a is generated in the second copper layer 13. (See FIG. 14 (e)). On the other hand, as shown in FIG. 13 (a), when the first copper layer 11 is reasonably thin, the first copper layer 11 is thin, so there is little variation at the time of dissolution (FIG. 13 (b)). The first copper layer 11 is completely melted before the etching sacrificial layer 12 is dissolved and the second copper layer 13 is exposed (FIG. 13C). As a result, when the etching sacrificial layer 12 and the second copper layer 13 are simultaneously brought into contact with the etching solution, the sacrificial effect by the etching sacrificial layer 12 appears (FIG. 13D), and the second copper layer 13 has a defect. This will not occur (FIG. 13 (e)). Accordingly, it can be said that it is desirable from the viewpoint of preventing defects that the time for the first copper layer 11 to melt is shorter than the time for the etching sacrificial layer 12 to melt. Therefore, when the etching rate of the first copper layer 11 is v ₁ and the etching rate of the etching sacrificial layer is v ₂ , the following relationship:
d ₂ / v ₂ ≧ d ₁ / v ₁ ⇔d ₂ / d ₁ ≧ v ₂ / v ₁ ｄd ₂ / d ₁ ≧ r
It is desirable to satisfy. That is, since the etching rate v ₁ of the first copper layer 11 is nothing but the etching rate with respect to Cu, v ₂ / v ₁ = r when using the etching rate ratio r described above. Therefore, it can be said that it is preferable to satisfy d ₂ / d ₁ ≧ r as described above.

The number of pinholes per unit area of the first copper layer 11 is preferably ² / mm ² or less. When the number of pinholes in the first copper layer 11 is small as described above, in the manufacturing process of the copper foil 10, there are also pinholes that can be generated in the etching sacrificial layer 12 and the second copper layer 13 plated on the first copper layer 11. It can also be reduced. As a result, defects such as defects due to chemical erosion during Cu etching can be further reduced.

The etching sacrificial layer 12 is not particularly limited as long as the etching rate is higher than that of Cu. In other words, the ratio r of the etching rate of the etching sacrificial layer 12 to the etching rate of Cu (hereinafter referred to as the etching rate ratio r) is higher than 1.0. If the etching rate is higher than Cu (if the etching rate ratio r is higher than 1.0), it can be simultaneously dissolved and removed by Cu etching, and the etching sacrificial layer 12 is unevenly dissolved and Cu is locally exposed. However, the local battery reaction suppresses the dissolution of the underlying copper layer, thereby enabling uniform etching of the copper layer in the surface, and suppressing the occurrence of seed layer defects and local circuit dents and defects. Can do. This etching rate is the same as that of the etching sacrificial layer 12 and the copper foil sample as a reference sample is processed for the same time in the etching process, and the change in thickness of each sample due to etching is determined by the dissolution time. It is calculated by dividing. The thickness change may be determined by measuring the weight reduction amount of both samples and converting the thickness from the density of each metal. A preferable etching rate ratio r is 1.2 or more from the viewpoint of obtaining a high sacrifice effect, more preferably 1.25 or more, and further preferably 1.3 or more. The upper limit of the etching rate ratio r is not particularly limited, but in order to keep the dissolution rate of the etching sacrificial layer 12 in the plane uniform and cause the local cell reaction with the second copper layer 13 to act uniformly in the plane, the etching rate The ratio r is preferably 5.0 or less, more preferably 4.5 or less, still more preferably 4.0 or less, particularly preferably 3.5 or less, and most preferably 3.0 or less. Here, as the etching solution, a known solution capable of dissolving copper by an oxidation-reduction reaction can be employed. Examples of the etching solution include cupric chloride (CuCl ₂ ) aqueous solution, ferric chloride (FeCl ₃ ) aqueous solution, ammonium persulfate aqueous solution, sodium persulfate aqueous solution, potassium persulfate aqueous solution, sulfuric acid / hydrogen peroxide aqueous solution and the like. Etc. Among these, the Cu etching rate can be precisely controlled, and from the viewpoint of ensuring a difference in etching time with the etching sacrificial layer 12, a sodium persulfate aqueous solution, a potassium persulfate aqueous solution, and a sulfuric acid / hydrogen peroxide solution are preferable. Of these, sulfuric acid / hydrogen peroxide solution is most preferable. As an etching method, a spray method, a dipping method, or the like can be employed. The etching temperature can be appropriately set within the range of 25 to 70 ° C. The etching rate in the present invention is adjusted by a combination of the above etching solution and etching method and the selection of the material of the etching sacrificial layer 12 described below.

The material constituting the etching sacrificial layer 12 is preferably an electrochemically base metal rather than Cu. Examples of such a preferable metal include a Cu—Zn alloy, a Cu—Sn alloy, a Cu—Mn alloy, and Cu—Al. Alloys, Cu—Mg alloys, Fe metals, Zn metals, Co metals, Mo metals and oxides thereof, and combinations thereof are particularly preferable, and Cu—Zn alloys are particularly preferable. From the viewpoint of obtaining a high sacrificial effect, the Cu—Zn alloy that can constitute the etching sacrificial layer 12 preferably contains 40% by weight or more of Zn, more preferably 50% by weight or more, and even more preferably 60% by weight or more. Preferably it is 70 weight% or more. In addition, the Zn content in the Cu—Zn alloy is preferably from the viewpoint of the uniform retention of the in-plane dissolution rate of the etching sacrificial layer 12 and the in-plane uniform action of the local cell reaction with the second copper layer 13. It is 98 weight% or less, More preferably, it is 96 weight% or less, More preferably, it is 94% weight% or less. The etching sacrificial layer 12 preferably has a thickness d ₂ of 0.1 to 5 μm, more preferably 0.1 to 4.5 μm, still more preferably 0.2 to 4 μm, and particularly preferably 0.2 to 3. 5 μm, most preferably 0.3 to 3 μm.

The cupric layer 13 may have a known configuration and is not particularly limited. For example, the second copper layer 13 may be formed by a wet film formation method such as an electroless plating method and an electrolytic plating method, a dry film formation method such as sputtering and chemical vapor deposition, or a combination thereof. Cupric layer 13 preferably has a thickness _{d 3} of 0.1 ~ 2.5 [mu] m, more preferably 0.1 ~ 2 [mu] m, more preferably 0.1 ~ 1.5 [mu] m, particularly preferably 0.2 It is ˜1 μm, most preferably 0.2 to 0.8 μm. When a thick d ₃ in such a range, it is also yet convenient thin enough circuit formation, to more effectively prevent a defect of the defect or the like during Cu etching.

It is preferable that the surface of the second copper layer 13 is roughened. In this way, the roughened particles formed by the roughening treatment are attached to the surface of the second copper layer, thereby improving the adhesion with the insulating resin layer at the time of manufacturing the copper-clad laminate or the printed wiring board. Can do. Further, in the ETS method, it is possible to facilitate image inspection after the wiring pattern is formed and to improve the adhesion with the photoresist pattern 20. The roughened particles preferably have an average particle size D of 0.04 to 0.53 μm by image analysis, more preferably 0.08 to 0.13 μm, still more preferably 0.09 to 0.12 μm. . Within the above preferred range, in the ETS method, the roughness of the roughened surface is given an appropriate roughness to ensure excellent adhesion with the photoresist, while opening the unnecessary areas of the photoresist during photoresist development. As a result, it is possible to effectively prevent line deficiency of the pattern plating 22 that may be caused by difficulty in plating due to the photoresist that cannot be fully opened. Therefore, it can be said that it is excellent in photoresist developability and pattern plating property within the above-mentioned preferable range, and is therefore suitable for fine formation of the wiring pattern 24. The average particle diameter D by image analysis of the roughened particles is obtained by taking an image at a magnification such that a predetermined number (for example, 1000 to 3000) of particles enters one field of view of a scanning electron microscope (SEM). Measurement is preferably performed by performing image processing with commercially available image analysis software. For example, 200 particles arbitrarily selected may be used as an object, and the average diameter of these particles may be adopted as the average particle diameter D.

The roughened particles preferably have a particle density ρ by image analysis of 4 to 200 particles / μm ² , more preferably 40 to 170 particles / μm ² , and 70 to 100 particles / μm ² . Also, when the roughened particles on the copper foil surface are dense and dense, photoresist development residues are likely to occur in the ETS method, but such development residues occur when within the above preferred range. Therefore, the developability of the photoresist pattern 20 is also excellent. Therefore, it can be said that it is suitable for fine formation of the wiring pattern 24 within the above-mentioned preferable range. The particle density ρ based on the image analysis of the roughened particles is obtained by taking an image at a magnification such that a predetermined number (for example, 1000 to 3000) of particles enters one field of view of a scanning electron microscope (SEM). It is preferable to perform measurement by performing image processing using commercially available image analysis software. For example, in a field where 200 particles enter, the value obtained by dividing the number of particles (for example, 200) by the field area is used as the particle density ρ. do it.

The surface of the cupric layer 13 is preferably subjected to rust prevention treatment such as nickel-zinc / chromate treatment, coupling treatment with a silane coupling agent, etc. in addition to the adhesion of the roughened particles by the above-mentioned roughening treatment. . By these surface treatments, it is possible to improve the chemical stability of the copper foil surface and to improve the adhesion when laminating the insulating layer.

The thickness _{d 1} of the first copper layer 11, the total thickness _d 1 ₊ d 2 + _{d 3} of the thickness _{d 3} of the thickness _{d 2} and the second copper layer 13 of the etching sacrificial layer 12 is less than 3.0μm of the Preferably, it is 0.3 to 2.8 μm, more preferably 0.6 to 2.8 μm, and particularly preferably 0.9 to 2.6 μm. The total thickness within such a range means that the thickness of the copper foil 10 is sufficiently thin, and the direct laser drilling property of the copper foil 10 is improved.

In particular, the copper foil 10 has a three-layer configuration including the first copper layer 11, the etching sacrificial layer 12, and the second copper layer 13, so that the MSAP is different from the two-layer configuration of the etching sacrificial layer and the copper layer. Benefits at various stages of the law. That is, when considering a two-layer structure composed of an etching sacrificial layer and a copper layer, the etching sacrificial layer is not protected at all, so there is a concern that the etching sacrificial layer may be dissolved and lost in a chemical process such as desmear before microetching. is there. Therefore, if the etching sacrificial layer is made thick in consideration of the dissolved part in the chemical process, direct laser processing becomes difficult due to the thickness. On the other hand, by adopting the three-layer configuration of the copper foil 10 of the present invention, the etching sacrificial layer 12 can be maintained until the microetching process without impairing laser processability, resulting in defects. Without etching. That is, laser processing can be performed without any problem by reducing the total thickness of the copper foil 10 (preferably d ₁ + d ₂ + d ₃ <3.0 μm). In the desmear process after laser processing, the etching sacrificial layer 12 is protected by the outermost first copper layer 11, so that the etching sacrificial layer 12 remains. In microetching, microetching can be performed without causing defects due to the sacrificial effect of the remaining etching sacrificial layer 12.

If desired, another layer may be provided between the first copper layer 11 and the etching sacrificial layer 12 and / or between the second copper layer 13 and the etching sacrificial layer 12 as long as the sacrificial effect of the etching sacrificial layer 12 is not prevented. May be present.

Copper foil 10 (or second copper layer 13, a laminate of etching the sacrificial layer 12 and the first copper layer 11) with a carrier may be provided in the form of free carrier copper foil, as shown in FIG. 1 Thus, it may be provided in the form of the copper foil 14 with a carrier, but is preferably provided in the form of the copper foil 14 with a carrier. In this case, the carrier-attached copper foil 14 may include a carrier 15, a release layer 16, a first copper layer 11, an etching sacrificial layer 12, and a second copper layer 13 in this order, or the carrier 15, The one copper layer 11, the etching sacrificial layer 12, and the second copper layer 13 may be provided in this order. That is, the release layer 16 may be provided, or the release layer 16 may not be provided as a single layer. A preferable copper foil with a carrier comprises a carrier 15, a release layer 16, and a copper foil 10 in this order.

The carrier 15 is a layer (typically a foil) for supporting the copper foil and improving its handleability. Examples of the carrier include an aluminum foil, a copper foil, a stainless steel foil, a resin film, a resin film whose surface is metal-coated, a glass plate, and the like, preferably a copper foil. The copper foil may be a rolled copper foil or an electrolytic copper foil. The thickness of the carrier is typically 250 μm or less, preferably 12 μm to 200 μm.

The release layer 16 has a function of weakening the peeling strength of the carrier 15, ensuring stability of the strength, and further suppressing interdiffusion that may occur between the carrier and the copper foil during press molding at a high temperature. It is. The release layer is generally formed on one side of the carrier, but may be formed on both sides. The release layer may be either an organic release layer or an inorganic release layer. Examples of organic components used in the organic release layer include nitrogen-containing organic compounds, sulfur-containing organic compounds, carboxylic acids and the like. Examples of nitrogen-containing organic compounds include triazole compounds, imidazole compounds, and the like. Among these, triazole compounds are preferred in terms of easy release stability. Examples of triazole compounds include 1,2,3-benzotriazole, carboxybenzotriazole, N ′, N′-bis (benzotriazolylmethyl) urea, 1H-1,2,4-triazole and 3-amino- And 1H-1,2,4-triazole. Examples of the sulfur-containing organic compound include mercaptobenzothiazole, thiocyanuric acid, 2-benzimidazolethiol and the like. Examples of the carboxylic acid include monocarboxylic acid and dicarboxylic acid. On the other hand, examples of inorganic components used in the inorganic release layer include Ni, Mo, Co, Cr, Fe, Ti, W, P, Zn, a chromate-treated film, and a carbon layer. The release layer may be formed by bringing the release layer component-containing solution into contact with at least one surface of the carrier and adsorbing the release layer component on the surface of the carrier in the solution. When the carrier is brought into contact with the release layer component-containing solution, this contact may be performed by immersion in the release layer component-containing solution, spraying of the release layer component-containing solution, flowing down of the release layer component-containing solution, or the like. In addition, it is also possible to employ a method of forming a release layer component by a plating method such as electrolytic plating or electroless plating, or a vapor phase method such as vapor deposition or sputtering. The release layer component may be fixed to the carrier surface by drying the release layer component-containing solution, electrodeposition of the release layer component in the release layer component-containing solution, or the like. The thickness of the release layer is typically 1 nm to 1 μm, preferably 5 nm to 500 nm. The peel strength between the release layer 16 and the carrier is preferably 5 gf / cm to 50 gf / cm, more preferably 5 gf / cm to 40 gf / cm, and still more preferably 6 gf / cm to 30 gf / cm.

Copper- clad laminate The copper foil of the present invention is preferably used for the production of a copper-clad laminate for printed wiring boards. That is, according to the preferable aspect of this invention, the copper clad laminated board provided with the copper foil mentioned above is provided. The copper clad laminate may comprise a copper foil in the form of a copper foil with a carrier. Moreover, copper foil may be provided in the single side | surface of a resin layer, and may be provided in both surfaces. The resin layer typically comprises a resin, preferably an insulating resin. The resin layer is preferably a prepreg and / or a resin sheet, more preferably a prepreg. The prepreg is a general term for composite materials in which a synthetic resin is impregnated or laminated on a base material such as a synthetic resin plate, a glass plate, a glass woven fabric, a glass nonwoven fabric, and paper. Preferable examples of the insulating resin impregnated in the prepreg include epoxy resin, cyanate resin, bismaleimide triazine resin (BT resin), polyphenylene ether resin, phenol resin, polyamide resin and the like. Examples of the insulating resin constituting the resin sheet include insulating resins such as an epoxy resin, a polyimide resin, and a polyester resin (liquid crystal polymer). Further, the resin layer may contain filler particles composed of various inorganic particles such as silica and alumina from the viewpoint of decreasing the thermal expansion coefficient and increasing the rigidity. The thickness of the resin layer is not particularly limited, but is preferably 3 to 1000 μm, more preferably 5 to 400 μm, and still more preferably 10 to 200 μm. The resin layer may be composed of a plurality of layers. A resin layer such as a prepreg and / or a resin sheet may be provided on the copper foil with a carrier via a primer resin layer previously applied to the surface of the copper foil.

Method for Producing Printed Wiring Board A printed wiring board can be preferably produced using the copper foil of the present invention or the copper foil with carrier as described above. Preferred examples of the method for producing a printed wiring board include an MSAP (Modified Semi-Additive Process) method and a coreless build-up method (ETS method), but are not limited to these methods, and the copper foil or carrier of the present invention. The attached copper foil can be used in various methods that can expect some advantage due to the sacrificial effect of the etching sacrificial layer 12.

As an example, a method for manufacturing a printed wiring board by a coreless buildup method (ETS method) employing the copper foil of the present invention will be described below. In this method, first, a support is obtained using a copper foil 10 provided with at least a second copper layer 13, an etching sacrificial layer 12, and a first copper layer 11. Next, as schematically shown in FIG. 6, a buildup wiring layer including at least a copper first wiring layer 26 and an insulating layer 28 is formed on the second copper layer 13 to form a laminate with a buildup wiring layer. Get the body. In FIG. 6, only the first wiring layer 26 is drawn for the sake of simplicity of explanation, but as shown in FIG. 8 described later, the layers are formed up to the n-th wiring layer 40 (n is an integer of 2 or more). Needless to say, a multilayer build-up wiring layer can be used. Thereafter, the first copper layer 11, the etching sacrificial layer 12, and the second copper layer 13 are removed with an etching solution to expose the first wiring layer 26, thereby obtaining a printed wiring board including a build-up wiring layer.

Hereinafter, the manufacturing method will be described with reference to the process diagrams shown in FIGS. 7 and 8 in addition to FIG. 7 and 8 are drawn so as to form the build-up wiring layer 42 by providing the copper foil 14 with a carrier on one side of the coreless support 18 for the sake of simplicity of explanation. It is desirable to provide the copper foil 14 with a carrier on both surfaces of the support 18 and form the build-up wiring layer 42 on both surfaces.

(1) Preparation of support using copper foil The copper foil 10 or the copper foil 14 with a carrier including the same is prepared as a support. If desired, prior to the formation of the laminate with the buildup wiring layer, the copper foil 10 (first copper layer 11 side) or the copper foil with carrier 14 (carrier 15 side) is laminated on one or both surfaces of the coreless support 18. A laminate may be formed. That is, at this stage, the above-described copper-clad laminate may be formed. This lamination may be performed in accordance with known conditions and techniques adopted for lamination of copper foil and prepreg in a normal printed wiring board manufacturing process. The coreless support 18 typically comprises a resin, preferably an insulating resin. The coreless support 18 is preferably a prepreg and / or a resin sheet, more preferably a prepreg. That is, the coreless support 18 corresponds to the resin layer in the above-described copper-clad laminate, and therefore the preferred embodiment described above with respect to the copper-clad laminate or resin layer applies to the coreless support 18 as it is.

(2) Formation of Stack with Build-up Wiring Layer On the second copper layer 13, a build-up wiring layer 42 including at least the first wiring layer 26 made of copper and the insulating layer 28 is formed to laminate with the build-up wiring layer. Get the body. The insulating layer 28 may be made of the insulating resin as described above. The build-up wiring layer 42 may be formed according to a known method for manufacturing a printed wiring board, and is not particularly limited. According to a preferred embodiment of the present invention, as described below, the first wiring layer 26 is formed by performing (i) forming a photoresist pattern, (ii) performing electrolytic copper plating, and (iii) stripping the photoresist pattern. After that, (iv) the build-up wiring layer 42 is formed.

(I) Formation of photoresist pattern First, a photoresist pattern 20 is formed on the surface of the second copper layer 13. The formation of the photoresist pattern 20 may be performed by either a negative resist or a positive resist, and the photoresist may be either a film type or a liquid type. Further, the developing solution may be a developing solution such as sodium carbonate, sodium hydroxide, an amine-based aqueous solution, etc., and may be carried out in accordance with various methods and conditions generally used in the production of printed wiring boards, and is not particularly limited.

(Ii) Electro Copper Plating Next, the electro copper plating 22 is applied to the second copper layer 13 on which the photoresist pattern 20 is formed. The formation of the electrolytic copper plating 22 is not particularly limited as long as it is performed in accordance with various pattern plating methods and conditions generally used in the production of printed wiring boards such as a copper sulfate plating solution and a copper pyrophosphate plating solution.

(Iii) Stripping of photoresist pattern The photoresist pattern 20 is stripped to form a wiring pattern 24. Stripping of the photoresist pattern 20 is not particularly limited as long as an aqueous sodium hydroxide solution, an amine-based solution or an aqueous solution thereof is employed, and may be performed in accordance with various stripping methods and conditions generally used in the manufacture of printed wiring boards. Thus, a wiring pattern 24 in which wiring portions (lines) made of the first wiring layer 26 are arranged with a gap (space) therebetween is directly formed on the surface of the second copper layer 13. For example, for circuit miniaturization, the line / space (L / S) is highly fine, such as 13 μm or less / 13 μm or less (for example, 12 μm / 12 μm, 10 μm / 10 μm, 5 μm / 5 μm, 2 μm / 2 μm). It is preferable to form a simplified wiring pattern.

(Iv) Formation of Build-up Wiring Layer Build-up wiring layer 42 is formed on second copper layer 13 to produce a laminate with build-up wiring layer. For example, in addition to the first wiring layer 26 already formed on the second copper layer 13, the insulating layer 28 and the second wiring layer 38 can be formed in order to form the build-up wiring layer 42. For example, as shown in FIG. 8, an insulating layer 28 and a copper foil 30 with a carrier (including a carrier 32, a release layer 34, and a copper foil 36) are laminated to form a buildup wiring layer 42, and the carrier 32 is peeled off. In addition, the copper foil 36 and the insulating layer 28 immediately below it may be laser processed by a carbon dioxide laser or the like. Subsequently, patterning is performed by chemical copper plating, photoresist processing, electrolytic copper plating, photoresist stripping, flash etching, or the like to form the second wiring layer 38, and this patterning is repeated as necessary to repeat the nth wiring layer 40. You may form to (n is an integer greater than or equal to 2).

The method for forming the build-up layer after the second wiring layer 38 is not limited to the above method, but is a subtractive method, an MSAP (Modified Semi-Additive Process) method, an SAP (Semi-Additive) method, or a full additive method. Etc. can be used. For example, when a metal foil typified by a resin layer and a copper foil is bonded together by pressing, the panel plating layer and the metal foil are etched in combination with the formation of interlayer conduction means such as via hole formation and panel plating. Thus, a wiring pattern can be formed. When only the resin layer is bonded to the surface of the second copper layer 13 by pressing or laminating, a wiring pattern can be formed on the surface by a semi-additive method.

The above process is repeated as necessary to obtain a laminate with a build-up wiring layer. In this process, a build-up wiring layer in which a resin layer and a wiring layer including a wiring pattern are alternately stacked is formed, and the n-th wiring layer 40 (n is an integer of 2 or more) is formed. It is preferable to obtain a laminate. This process may be repeated until a desired number of build-up wiring layers are formed. At this stage, if necessary, solder resist, bumps for mounting such as pillars, and the like may be formed on the outer layer surface. Further, an outer layer wiring pattern may be formed on the outermost layer surface of the build-up wiring layer in a later outer layer processing step.

(3) Formation of printed wiring board including build-up wiring layer (i) Separation of laminate with build-up wiring layer After forming the laminate with build-up wiring layer, the laminate with build-up wiring layer is separated from the release layer 16. Etc. can be separated. When the carrier-attached copper foil comprises the carrier 15, the release layer 16, the first copper layer 11, the etching sacrificial layer 12, and the second copper layer 13 in this order, the method of the present invention is prior to removal with an etching solution described later, It is preferable to separate the laminated body with the buildup wiring layer by the release layer 16 to expose the first copper layer 11. As the separation method, physical peeling is preferable, and for this peeling method, a machine or jig, manual work, or a combination thereof may be employed.

On the other hand, when the carrier-attached copper foil comprises the carrier 15, the first copper layer 11, the etching sacrificial layer 12, and the second copper layer 13 in this order (that is, when the peeling layer 16 is not provided as a single layer), The method of the invention separates the laminate with a build-up wiring layer between the carrier 15 and the first copper layer 11 or inside the first copper layer 11 prior to the removal with an etching solution described later, and the first copper layer 11 Is preferably exposed.

(Ii) Etching of etching sacrificial layer and copper layer In the method of the present invention, the first copper layer 11, the etching sacrificial layer 12 and the second copper layer 13 are removed with an etching solution to expose the first wiring layer 26; Thereby, a printed wiring board 46 including the build-up wiring layer 42 is obtained. The printed wiring board 46 is preferably a multilayer printed wiring board. In any case, due to the presence of the etching sacrificial layer 12, it is possible to efficiently remove each layer uniformly by etching in the surface by Cu etching without the need for an additional etching step, and local circuit dents are generated. Can be suppressed. Therefore, according to the method of the present invention, the removal of the second copper layer 13, the etching sacrificial layer 12, and the first copper layer 11 with the etching solution can be performed in one step. The etching solution and etching method used at this time are as described above.

(Iii) Outer layer processing The printed wiring board 46 as shown in FIG. 8 can be processed into an outer layer by various methods. For example, an insulating layer and a wiring layer as build-up wiring layers may be further laminated on the first wiring layer 26 of the printed wiring board 46 as an arbitrary number of layers, or a solder resist layer is formed on the surface of the first wiring layer 26. And surface treatment as an outer layer pad such as Ni—Au plating, Ni—Pd—Au plating, or water-soluble preflux treatment may be performed. Furthermore, a columnar pillar or the like may be provided on the outer layer pad. At this time, the first wiring layer 26 formed using the etching sacrificial layer in the present invention can maintain the uniformity of the circuit thickness in the plane, and the surface of the first wiring layer 26 has a local circuit depression. Is less likely to occur. For this reason, there is a low incidence of defects such as local processing failures and solder-resist residue failures in the surface treatment process due to extremely thin parts of the circuit thickness, circuit recesses, etc., and mounting failures due to mounting pad irregularities. A printed wiring board having excellent mounting reliability can be obtained.

The printed wiring board manufacturing method described above is based on the coreless buildup method (ETS method), but the printed wiring board manufacturing method based on the MSAP method is based on the conventional MSAP method described with reference to FIGS. By using the copper foil 10 of the present invention instead of the ultrathin copper foil 110, a printed wiring board can be preferably manufactured.

The present invention will be described more specifically with reference to the following examples.

Examples 1-12
Preparation and various evaluations of the copper foil for manufacturing a printed wiring board of the present invention were performed as follows.

(1) Preparation of carrier A rotating electrode made of titanium whose surface was polished with a buff of # 2000 was prepared as a rotating cathode. Further, a DSA (dimensional stability anode) was prepared for the anode. Rotating cathode and anode are copper sulfate having a copper concentration of 80 g / L, a sulfuric acid concentration of 260 g / L, a bis (3-sulfopropyl) disulfide concentration of 30 mg / L, a diallyldimethylammonium chloride polymer concentration of 50 mg / L, and a chlorine concentration of 40 mg / L. It was immersed in a solution and electrolyzed at a solution temperature of 45 ° C. and a current density of 55 A / dm ² to obtain an electrolytic copper foil having a thickness of 18 μm as a carrier.

(2) Formation of Release Layer The electrode surface side of the pickled carrier is placed in a CBTA aqueous solution having a CBTA (carboxybenzotriazole) concentration of 1 g / L, a sulfuric acid concentration of 150 g / L, and a copper concentration of 10 g / L, at a liquid temperature of 30 ° C. So as to adsorb the CBTA component on the electrode surface of the carrier. Thus, a CBTA layer was formed as an organic release layer on the surface of the electrode surface of the carrier copper foil.

(3) Formation of Auxiliary Metal Layer The carrier on which the organic peeling layer is formed is immersed in a solution having a nickel concentration of 20 g / L prepared using nickel sulfate, and the liquid temperature is 45 ° C., the pH is 3, and the current density is 5 A / dm 2. Under the conditions, nickel having a thickness equivalent to 0.001 μm was deposited on the organic release layer. Thus, a nickel layer was formed as an auxiliary metal layer on the organic release layer.

(4) Formation of the first copper layer (ultra-thin copper foil) In Examples 1 to 9 and 12, the carrier on which the auxiliary metal layer was formed was changed to a copper sulfate solution having a copper concentration of 60 g / L and a sulfuric acid concentration of 200 g / L. Immersion was performed and electrolysis was performed at a solution temperature of 50 ° C. and a current density of 5 to 30 A / dm ² to form a first copper layer (ultra-thin copper foil) having a thickness of 0.3 μm on the auxiliary metal layer. On the other hand, in Examples 10 and 11, the first copper layer was not formed.

(5) Formation of etching sacrificial layer Table 1 shows carriers (Examples 1 to 9 and 12) on which the first copper layer (ultra-thin copper foil) is formed or carriers (Example 11) on which the auxiliary metal layer is formed. The film was immersed in a plating bath and electrolyzed under the plating conditions shown in Table 1, and an etching sacrificial layer having the composition and thickness shown in Table 2 was formed on the first copper layer or the auxiliary metal layer. On the other hand, in Example 10, the etching sacrificial layer was not formed.

(6) Formation of a second copper layer A carrier having an etching sacrificial layer (Examples 1 to 9, 11 and 12) or a carrier having an auxiliary metal layer formed (Example 10), having a copper concentration of 60 g / L and a sulfuric acid concentration It is immersed in a 145 g / L copper sulfate solution, electrolyzed at a solution temperature of 45 ° C. and a current density of 30 A / dm ² , and a second copper layer having a thickness shown in Table 2 is formed on the etching sacrificial layer or the auxiliary metal layer. Formed.

(7) Roughening process The surface of the copper foil with a carrier formed in this way was roughened. This roughening treatment includes a baking plating process in which fine copper grains are deposited on the copper foil, and a covering plating process for preventing the fine copper grains from falling off. In the baking plating step, a roughening treatment was performed at an acid density of 25 A / dm ² using an acidic copper sulfate solution containing a copper concentration of 10 g / L and a sulfuric acid concentration of 120 g / L. In the subsequent plating process, electrodeposition was performed using an acidic copper sulfate solution containing a copper concentration of 70 g / L and a sulfuric acid concentration of 120 g / L under smooth plating conditions of a liquid temperature of 40 ° C. and a current density of 15 A / dm ² .

(8) Rust prevention treatment The surface of the obtained copper foil with carrier was subjected to a rust prevention treatment comprising zinc-nickel alloy plating treatment and chromate treatment. First, a roughening treatment layer using an electrolytic solution having a zinc concentration of 0.2 g / L, a nickel concentration of 2 g / L, and a potassium pyrophosphate concentration of 300 g / L under the conditions of a liquid temperature of 40 ° C. and a current density of 0.5 A / dm ^2. And the surface of the carrier was subjected to a zinc-nickel alloy plating treatment. Next, a chromate treatment was performed on the surface on which the zinc-nickel alloy plating treatment was performed using a 3 g / L aqueous solution of chromic acid under the conditions of pH 10 and a current density of 5 A / dm ² .

(9) Silane coupling agent treatment Silane coupling is performed by adsorbing an aqueous solution containing 2 g / L of 3-glycidoxypropyltrimethoxysilane on the copper foil side surface of the copper foil with a carrier and evaporating water with an electric heater. Agent treatment was performed. At this time, the silane coupling agent treatment was not performed on the carrier side.

(10) Evaluation Various evaluation was performed as follows about the copper foil with a carrier obtained in this way, and its structural layer.

Evaluation 1 : Etching rate ratio r
In order to measure the etching rate ratio r of the etching sacrificial layer, in Examples 1 to 9, 11 and 12, the carrier whose outermost surface obtained in (5) is an etching sacrificial layer (that is, the etching sacrificial layer is formed). An intermediate product) in which the formation of the second copper layer and the subsequent treatment were not performed was prepared. Moreover, about Example 10, the copper foil with a carrier whose outermost surface obtained by said (6) is a 2nd copper layer (namely, intermediate product by which the 2nd copper layer is formed and the subsequent process is not performed) Prepared. On the other hand, commercially available 95 wt% concentrated sulfuric acid and 30 wt% hydrogen peroxide water were dissolved in water to produce an etching solution having a sulfuric acid concentration of 5.9 wt% and a hydrogen peroxide concentration of 2.1 wt%. Each copper foil sample with a carrier is masked so that the carrier side is not etched, and immersed in an etching solution at 25 ° C. for a certain period of time to dissolve, and the thickness change of the plating film before and after the dissolution is measured by a fluorescent X-ray film thickness meter (Fischer Instruments). (Fischerscope X-Ray XDAL-FD) manufactured by the same company. The etching rate of each target plating film was determined by dividing the obtained thickness change by the dissolution time. The etching rate of Example 10 thus obtained is the etching rate of Cu, and the etching rates of Examples 1 to 9, 11 and 12 are the etching rates of the respective etching sacrificial layers. Then, the etching rate ratio r was calculated by dividing the etching rate of the etching sacrificial layer by the etching rate of Cu. The results were as shown in Table 2.

Evaluation 2 : Number of pinholes per unit area In order to measure the number of pinholes per unit area of the first copper layer, the outermost surface obtained in (4) above is the first copper layer (ultra-thin copper foil) An ultra-thin copper foil with a carrier (that is, an intermediate product in which a copper layer having a thickness of 0.3 μm was formed and an etching sacrificial layer and subsequent processing were not performed) was prepared. This ultrathin copper foil with a carrier is laminated so that the first copper layer (ultrathin copper foil) side is in contact with an insulating resin base material (prepreg made by Panasonic Corporation, R-1661, thickness 0.1 mm), and pressure 4. Thermocompression bonding was performed at 0 MPa and a temperature of 190 ° C. for 90 minutes. Thereafter, the carrier was peeled off to obtain a laminate. This laminated plate was observed with an optical microscope while applying a backlight in a dark room, and the number of pinholes was counted. Thus, when the number of pinholes per 1 mm ² was measured, in all of Examples 1 to 9, 11 and 12, the number of pinholes per unit area of the first copper layer was 2 / mm ² or less.

Evaluation 3 : Defects The copper foil with a carrier obtained in (9) above was in contact with the insulating resin base material (prepreg made by Panasonic Corporation, R-1661, thickness 0.1 mm) on the second copper layer side. The laminate was laminated and thermocompression bonded at a pressure of 4.0 MPa and a temperature of 190 ° C. for 90 minutes. The carrier of the copper-clad laminate thus obtained was peeled off, cut into a size of 10 cm × 10 cm, and immersed in the etching solution prepared in Evaluation 1 until the etching sacrificial layer completely disappeared. The presence or absence was confirmed, and rating was evaluated according to the following criteria. In addition, the defect | deletion here refers to the state which can see the base material of a foundation | substrate. The results were as shown in Table 2.
-Evaluation A: No defect in the cupric layer-Evaluation B: One or more defects in the second copper layer are generated-Evaluation C: Four or more defects in the cupric layer What is happening

Evaluation 4 : Laser workability After the carrier was peeled from the copper clad laminate produced in Evaluation 3, the energy density was 6.5 MW / cm ² and the laser beam diameter was measured with a laser processing machine (Mitsubishi Electric, ML605GTWIII-H). Laser processing was performed at 20 points under the condition of 75.6 μm. The openings thus formed were observed with an optical microscope and rated according to the following criteria. The opening diameter was measured at the upper end. The results were as shown in Table 2.
・ Evaluation A: No opening, and the minimum value of 20 opening diameters is 40 μm or more ・ Evaluation B: No opening, but the minimum value of 20 opening diameters is less than 40 μm Items / Evaluation C: One with unopened items

Evaluation 5 : Circuit recess The carrier-side copper foil obtained in the above (9) was brought into contact with the first insulating resin base material (prepreg made by Panasonic Corporation, R-1661, thickness 0.1 mm). And thermocompression bonded at a pressure of 4.0 MPa and a temperature of 190 ° C. for 90 minutes. The copper-clad laminate thus obtained was washed with the etching solution prepared in Evaluation 1, and then a 19 μm thick dry film was laminated on the copper foil side. Line / space (L / S) = It exposed and developed using the 10/10 micrometer mask. The developed copper-clad laminate was subjected to pattern plating so that the plating height was 17 μm, and then the dry film was peeled off to form five linear circuits of L / S = 10/10. Next, a second insulating resin base material (prepreg made by Panasonic Corporation, R-1661, thickness 0.1 mm) was laminated on the surface of the laminated plate on which the five linear circuits were formed, and the pressure was 4.0 MPa, Thermocompression bonding was performed at a temperature of 190 ° C. for 90 minutes. Thereafter, the carrier and the first insulating resin substrate to which it was adhered were peeled off with the release layer as a boundary. Etching was performed on the side of the remaining second insulating resin base material where the copper foil was exposed, using the same etching solution prepared in Evaluation 1 until the copper foil disappeared. In this state, the cross section was observed at 2,000 times using an optical microscope, and the distance from the upper end of the second insulating resin substrate to the upper end of the circuit was measured as a circuit recess for five circuits, and the following criteria were used. Rating rating. The results were as shown in Table 2.
・ Evaluation A: The maximum value among 5 pieces is less than 2.0 μm ・ Evaluation B: The maximum value among 5 pieces is less than 2.0 μm and less than 2.5 μm ・ Evaluation C: Among 5 pieces With a maximum value of 2.5 μm or more (actually 3.0 μm or more)

Claims

A copper foil for producing a printed wiring board, comprising a first copper layer, an etching sacrificial layer, and a second copper layer in this order, wherein a ratio r of an etching rate of the etching sacrificial layer to an etching rate of Cu is higher than 1.0 .
The copper foil according to claim 1, wherein the ratio r is 1.2 or more.
The thickness of the first copper layer and d 1, if the thickness of the etching sacrificial layer was d 2, satisfying the d 2 / d 1 ≧ r, copper foil according to claim 1 or 2.
The etching sacrificial layer is made of Cu—Zn alloy, Cu—Sn alloy, Cu—Mn alloy, Cu—Al alloy, Cu—Mg alloy, Fe metal, Zn metal, Co metal, Mo metal and oxides thereof. The copper foil according to any one of claims 1 to 3, comprising at least one selected from the group consisting of:
The copper foil according to any one of claims 1 to 4, wherein the etching sacrificial layer is made of a Cu-Zn alloy containing Zn by 40 wt% or more.
The copper foil according to any one of claims 1 to 5, wherein the number of pinholes per unit area of the first copper layer is 2 / mm 2 or less.
The total thickness d 1 + d 2 + d 3 of the thickness d 1 of the first copper layer, the thickness d 2 of the etching sacrificial layer, and the thickness d 3 of the second copper layer is less than 3.0 μm, Item 7. The copper foil according to any one of Items 1 to 6.
A carrier-attached copper foil comprising the carrier, the release layer, and the copper foil according to any one of claims 1 to 7 in this order.
A copper-clad laminate comprising the copper foil according to any one of claims 1 to 7.
A method for producing a printed wiring board, comprising producing a printed wiring board using the copper foil according to any one of claims 1 to 7 or the copper foil with a carrier according to claim 8.