JP2002176242A - Copper foil for electronic circuit and method for forming electronic circuit - Google Patents

Copper foil for electronic circuit and method for forming electronic circuit

Info

Publication number
JP2002176242A
JP2002176242A JP2000369753A JP2000369753A JP2002176242A JP 2002176242 A JP2002176242 A JP 2002176242A JP 2000369753 A JP2000369753 A JP 2000369753A JP 2000369753 A JP2000369753 A JP 2000369753A JP 2002176242 A JP2002176242 A JP 2002176242A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
circuit
copper
electronic
etching
formed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000369753A
Other languages
Japanese (ja)
Other versions
JP4592936B2 (en )
JP2002176242A5 (en )
Inventor
Masaru Sakamoto
Kengo Yonezawa
勝 坂本
賢吾 米沢
Original Assignee
Nikko Materials Co Ltd
株式会社日鉱マテリアルズ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

PROBLEM TO BE SOLVED: To provide a copper foil of an electronic circuit, and a method for forming the electronic circuit, in which a uniform circuit having a target circuit width can be formed by preventing drooping due to etching at the time of forming a circuit by etching the copper foil of a copper clad laminate plate.
SOLUTION: In the copper foil 1 of an electronic circuit where a circuit is formed by etching, a metal or alloy layer 7 having an etching rate lower than that of copper is formed on the etching face side. Material of the metal or alloy layer 7 includes cobalt, nickel and alloys thereof and the layer is formed by plating to a thickness of 100-10000 μg/dm2.
COPYRIGHT: (C)2002,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、エッチングにより回路形成を行う電子回路用銅箔及び電子回路の形成方法に関する。 The present invention relates to the method for forming a copper foil and an electronic circuit for an electronic circuit, the circuit formed by etching.

【0002】 [0002]

【従来の技術】電子・電気機器に印刷回路用銅箔が広く使用されているが、この印刷回路用銅箔は、一般に合成樹脂ボードやフイルム等の基材に接着剤を介して、あるいは接着剤を用いずに高温高圧下で接着して銅張り積層板を製造し、その後、目的とする回路を形成するためにレジスト塗布及び露光工程により回路を印刷し、さらに銅箔の不要部分を除去するエッチング処理を経、またさらに各種の素子が半田付けされてエレクトロデバイス用の印刷回路が形成されている。 BACKGROUND ART Copper foil for printed circuit electrical and electronic equipment have been widely used, the printed circuit copper foil, through an adhesive to a substrate such as a general synthetic resin board or film, or an adhesive agent to produce a copper-clad laminate by bonding at high temperature and high pressure without using, then printed circuit by resist application and exposure steps to form a circuit of interest, further removing unnecessary portions of the copper foil etching a via, or even printed circuit for various elements soldered by electroporation devices are formed.

【0003】このような印刷回路に使用する銅箔は、その製造方法の種類の違いにより電解銅箔及び圧延銅箔に大別されるが、いずれも印刷回路板の種類や品質要求に応じて使用されている。 [0003] The copper foil for use in such printed circuit are roughly classified into electrolytic copper foil and rolled copper foil due to a difference in the type of manufacturing process, both depending on the type and quality requirements of the printed circuit board It is used. これらの銅箔は、樹脂基材と接着される面と非接着面があり、それぞれ特殊な表面処理(トリート処理)が施されている。 These copper foil has a surface and a non-adhesive surface which is adhered to the resin substrate, respectively special surface treatment (treat process) is performed. また、多層プリント配線板の内層に使用する銅箔のように両面に樹脂との接着機能をもつようにされる(ダブルトリート処理)場合もある。 Moreover, the the (double Treat process) to have an adhesive function between the resin on both surfaces such as copper foil used in the inner layer of the multilayer printed wiring board it may. 電解銅箔は一般に回転ドラムに銅を電着させ、 Electrolytic copper foil generally the copper is electrodeposited on a rotating drum,
それを連続的に剥がして銅箔を製造しているが、この製造時点で回転ドラムに接触する面は光沢面で、その反対側の面は多数の凹凸を有している(粗面)。 Although peeled it continuously manufactures copper foil, the surface in contact with the rotary drum at a glossy surface in the point of manufacture, the opposite surface has a number of irregularities (rough surface). しかし、このような粗面でも樹脂基板との接着性を一層向上させるために、0.2〜3μm程度の銅粒子を付着させるのが一般的である。 However, in order to further improve the adhesion between the resin substrate in such a rough surface, it is common to deposit copper particles of about 0.2 to 3 .mu.m. さらに、このような凹凸を増強した上に銅粒子の脱落を防止するために薄いめっき層を形成する場合もある。 Furthermore, there is also a case of forming a thin plating layer to prevent dropping of the copper particles on the enhanced such irregularities. これらの一連の工程を粗化処理と呼んでいる。 These series of steps is referred to as a roughening treatment. このような粗化処理は、電解銅箔に限らず圧延銅箔でも要求されることであり、同様な粗化処理が圧延銅箔においても実施されている。 Such roughening treatment is to be required in a rolled copper foil is not limited to the electrolytic copper foil, similar roughening treatment is implemented in the rolled copper foil.

【0004】以上のような銅箔を使用してホットプレス法や連続法により銅張り積層板が製造される。 [0004] or more by using the copper foil, such as copper-clad laminate by a hot press method or a continuous method is produced. この積層板は、例えばホットプレス法を例にとると、エポキシ樹脂の合成、紙基材へのフェノール樹脂の含浸、乾燥を行ってプリプレグを製造し、さらにこのプリプレグと銅箔を組合せプレス機により熱圧成形を行う等の工程を経て製造されている。 The laminate, for example, taking a hot press method in Examples, the synthesis of epoxy resin, impregnation of the phenol resin to the paper substrate, dried to produce a prepreg made by further combining press the prepreg and a copper foil It is manufactured through the steps for performing the thermal molding. このようにして製造された銅張り積層板は、目的とする回路を形成するためにレジスト塗布及び露光工程により回路を印刷し、さらに銅箔の不要部分を除去するエッチング処理を経るが、ここで大きな問題が発生した。 Thus copper-clad laminate manufactured by prints the circuit by resist application and exposure steps to form a circuit of interest, but further subjected to etching treatment for removing an unnecessary portion of the copper foil, wherein big problem has occurred.

【0005】それは、図2に示すようにエッチング後の銅箔回路の銅部分2が末広がりにエッチングされる(ダレを発生する)ことである。 [0005] It is to copper portion 2 of copper circuit after etching is etched flared as shown in FIG. 2 (for generating a sag). 図2において符号3はレジスト、符号4は樹脂基板を示す。 Reference numeral 3 in FIG. 2 is a resist, reference numeral 4 denotes a resin substrate. エッチングが十分でなく、このようなダレが発生した場合には、樹脂基板近傍で銅回路が短絡し不良品となる場合もある。 Etching is not sufficient, when such sagging occurs in some cases copper circuit is a defective short-circuit in the resin substrate neighborhood. このような末広がりのエッチング不良を防止するために、図3に示すようにエッチング時間を延長してエッチングをより高める方法を採用した。 In order to prevent such divergent etching defects, it was adopted a method of enhancing the etching by extending the etching time as shown in FIG. しかし、この場合は図3の符号5 However, reference numeral 5 in this case is 3
に示すように、銅回路の側面が極端に狭くなり、回路設計上目的とする均一な線幅(回路幅)が得られず、特にその部分(細線化された部分)で発熱し、場合によっては断線するという問題が発生した。 As shown in the side surface of the copper circuit is extremely narrow, not uniform line width (circuit width) is obtained for the circuit design purpose, and fever especially at that portion (thinned portion), optionally a problem that disconnection has occurred. 最近では電子回路のファインパターン化が要求されているが、このようなエッチング不良による問題がより強く現れ、回路形成上大きな問題となっている。 Although recent fine patterning of an electronic circuit is required, such appear problems stronger by defective etching, has become a major problem on the circuit formation.

【0006】 [0006]

【発明が解決しようとする課題】本発明は、銅張り積層板の銅箔をエッチングにより回路形成を行うに際し、エッチングによるダレを防止し、目的とする回路幅の均一な回路を形成できる電子回路用銅箔及びそのための電子回路の形成方法を課題とする。 [0008] The present invention, when a copper foil of a copper-clad laminate, a circuit formed by etching, to prevent sagging due to etching, an electronic circuit capable of forming a uniform circuit of the circuit width of interest forming method of use copper foil and electronic circuitry therefor an object.

【0007】 [0007]

【課題を解決するための手段】本発明者らは、銅箔の厚み方向のエッチング速度を制御することにより、ダレのない回路幅の均一な回路を形成できるとの知見を得た。 The present inventors have SUMMARY OF THE INVENTION, by controlling the etching rate in the thickness direction of the copper foil to obtain a knowledge that can form a uniform circuit sagging without circuit width.
本発明はこの知見に基づいて、 1 エッチングにより回路形成を行う電子回路用銅箔において、エッチング面側に銅よりエッチングレートの遅い金属又は合金層を形成したことを特徴とする電子回路用銅箔 2 銅張り積層板であることを特徴とする上記1記載の電子回路用銅箔 3 銅よりエッチングレートの遅い金属又は合金層がコバルト、ニッケル又はこれらの合金層であることを特徴とする上記1又は2記載の電子回路用銅箔 4 100〜10000μg/dm の金属又は合金層を形成することを特徴とする上記1〜3記載の電子回路用銅箔 5 銅箔のエッチング側面の傾斜角度が、80〜95度の範囲にあることを特徴とする上記1〜4のそれぞれに記載の電子回路用銅箔 6 銅箔のエッチング側面の傾斜角度が、85〜90度の範囲に The present invention is based on this finding, the copper foil for electronic circuit for performing a circuit formed by one etching, a copper foil for electronic circuit, characterized in that the formation of the slower metal or alloy layer etching rate of copper in the etching surface 1 above, the 1 slower than copper foil 3 copper electronics according etching rate metal or alloy layer, characterized in that 2 is a copper-clad laminate is cobalt, characterized in that nickel or an alloy thereof or the inclination angle of the copper foil 5 foil etched side surface of the electronic circuit of the 1-3, wherein the forming copper foil 4 100~10000μg / dm 2 of metal or alloy layer electronic circuit 2 described , the inclination angle of the electronic circuit for the copper foil 6 foil etched aspect of according to each of the 1 to 4, characterized in that in the range of 80 to 95 degrees, in the range of 85 to 90 degrees ることを特徴とする上記1〜4のそれぞれに記載の電子回路用銅箔を提供する。 Providing a copper foil for electronic circuit according to each of the above 1 to 4, wherein Rukoto.

【0008】さらに、また 7 銅張り積層板の銅箔をエッチングし電子回路を形成する方法において、銅箔のエッチング面側に銅よりエッチングレートの遅い金属又は合金層を形成した後、塩化第二銅水溶液を用いて該銅箔をエッチングし、回路を形成することを特徴とする電子回路の形成方法 8 銅よりエッチングレートの遅い金属又は合金層がコバルト、ニッケル又はこれらの合金層であることを特徴とする上記7記載の電子回路の形成方法 9 100〜10000μg/dm の金属又は合金層を形成することを特徴とする上記7又は8記載の電子回路の形成方法 10 銅箔のエッチング側面の傾斜角度が、80〜95 Furthermore, also in the method of forming the etched electronic circuits copper foil 7 copper-clad laminate, after forming a slower metal or alloy layer etching rate of copper to the etched surface side of the copper foil, the second chloride the copper foil with an aqueous solution of copper etched slower metal or alloy layer etching rate than forming method 8 copper of an electronic circuit and forming a circuit cobalt, that nickel or an alloy thereof characterized the etching side of the forming method 10 copper foil of the electronic circuit of claim 7 or 8, wherein the forming a metal or alloy layer forming method 9 100~10000μg / dm 2 of the electronic circuit of claim 7, wherein inclination angle, 80 to 95
度の範囲にあることを特徴とする上記7〜9のそれぞれに記載の電子回路の形成方法 11 銅箔のエッチング側面の傾斜角度が、85〜90 The inclination angle of the etched side surface of the forming method 11 copper foil of the electronic circuit according to each of the above 7-9, characterized in that the range of time is 85 to 90
度の範囲にあることを特徴とする上記7〜9のそれぞれに記載の電子回路の形成方法 を提供するものである。 There is provided a method of forming an electronic circuit according to each of the above 7-9, characterized in that the range of time.

【0009】 [0009]

【発明の実施の形態】本発明は、エッチングにより回路形成を行う電子回路用銅箔のエッチング面側に、銅よりエッチングレートの遅い金属又は合金層層を形成し、銅張り積層板とする。 DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the etching surface of the copper foil for electronic circuit for performing a circuit formed by etching, to form a slow metal or alloy layer layer etching rate of copper, and copper-clad laminate. この銅箔は、電解銅箔及び圧延銅箔のいずれにも適用できる。 This copper foil can be applied to any of the electrolytic copper foil and rolled copper foil. また、粗化面(M面)又は光沢面(S面)にも同様に適用できる。 Moreover, equally applicable to the roughened surface (M plane) or the glossy surface (S surface). 圧延銅箔の中には高純度銅箔又は強度を向上させた合金銅箔も存在するが、本件発明はこれらの銅箔の全てを包含する。 Alloys copper foil improves the high-purity copper or intensity in the rolled copper foil is also present, the present invention encompasses all these foils. 銅よりエッチングレートの遅い金属又は合金層を形成する材料としては、コバルト、ニッケル又はこれらの合金が使用できるが、特にコバルト、ニッケル又はこれらの合金が好適である。 As a material for forming a slow metal or alloy layer etching rate of copper, cobalt, and nickel, or alloys thereof can be used, in particular cobalt, nickel or alloys thereof are preferred. 合金層としては、Co−P、Ni−P、C The alloy layer, Co-P, Ni-P, C
o−Ni、Co−Zn、Ni−Znが使用できる。 o-Ni, Co-Zn, the Ni-Zn can be used.

【0010】コバルト又はニッケル等のエッチングを抑制する金属又は合金は、図1の符号1示すように銅箔1 [0010] etching suppressing metal or alloy such as cobalt or nickel, copper as shown reference numeral 1 in FIG. 1 1
上のレジスト部分3に近い位置にあり、レジスト3側の銅箔1のエッチング速度は、このコバルト、ニッケル等の層7により抑制され、逆にコバルト、ニッケル等の層から遠ざかるに従いエッチングは通常の速度で進行する。 In a position close to the resist portion 3 above, the etching rate of the copper foil 1 of the resist 3 side, cobalt, is suppressed by the layer 7 such as nickel, cobalt Conversely, as the distance from the layer of nickel such as etching normal proceeds at speed. これによって、銅回路の側面6のレジスト3側から樹脂基板4側に向かってほぼ垂直にエッチングが進行し、矩形の銅箔回路が形成される。 Thus, the resist 3 side surface 6 of the copper circuit toward the resin substrate 4 side etching proceeds substantially vertically, rectangular copper foil circuit is formed.

【0011】コバルト又はニッケル等の銅よりエッチングレートの遅い金属又は合金層の厚さは、100〜10 [0011] The thickness of the cobalt or slow metal or alloy layer etching rate of copper, such as nickel, 100-10
000μg/dm とするのが良い。 It is good for the 000μg / dm 2. 100μg/dm 100μg / dm
未満であると、銅箔の厚み方向のエッチング速度を効果的に制御することができず、ダレのない回路幅の均一な回路を形成することが難しくなる。 If it is less than 2, it is not possible to effectively control the etching rate in the thickness direction of the copper foil, to form a uniform circuit sagging without circuit width becomes difficult. また、10000 In addition, 10000
μg/dm を超えると、レジスト側のエッチングが抑制され過ぎて銅箔回路のエッチング部がいびつになるので好ましくない。 Beyond μg / dm 2, undesirable etching of the copper foil circuit resist side etching is excessively suppressed becomes distorted.

【0012】下記に好適なめっき条件の例を示す。 [0012] An example of a suitable plating conditions below. (コバルトめっき) Co:1〜20g/L pH:1〜4 温度:常温〜60°C 電流密度Dk:1〜15A/dm 時間:1〜10秒 (ニッケルめっき) Ni:1〜20g/L pH:1〜4 温度:常温〜60°C 電流密度Dk:1〜15A/dm 時間:1〜10秒 (Co−Ni合金めっき) Co:1〜20g/L Ni:1〜20g/L 温度:常温〜60°C 電流密度Dk:1〜15A/dm 時間:1〜10秒 (Cobalt Plating) Co: 1~20g / L pH: 1~4 Temperature: room temperature to 60 ° C Current density Dk: 1 through 15A / dm 2 Time: 1-10 seconds (nickel plated) Ni: from 1 to 20 g / L pH: 1 to 4 temperature: room temperature to 60 ° C current density Dk: 1 through 15A / dm 2 Time: 1-10 seconds (Co-Ni alloy plating) Co: 1~20g / L Ni: 1~20g / L temperature : room temperature to 60 ° C current density Dk: 1 through 15A / dm 2 Time: 1-10 seconds

【0013】銅張り積層板の銅箔のエッチングに際しては、銅箔のエッチング面側に銅よりエッチングレートの遅い金属又は合金層層を形成した後、塩化第二銅水溶液を用いて該銅箔をエッチングする。 [0013] In the etching of the copper foil of the copper-clad laminate is formed by forming a slow metal or alloy layer layer etching rate of copper to the etched surface side of the copper foil, a copper foil using a cupric chloride aqueous solution etching. 上記の条件でエッチングすることにより、銅箔回路のエッチング側面と樹脂基板との間の傾斜角度が80〜95度の範囲にすることができる。 By etching under the above conditions, the inclination angle between the etching side surface and the resin substrate of the copper foil circuit can be in the range of 80 to 95 degrees. 特に望ましい傾斜角度は85〜90度の範囲である。 Particularly preferred angle of inclination is in the range of 85 to 90 degrees. これによって、ダレのない矩形のエッチング回路が形成できる。 Thus, etching circuit rectangle without sagging can be formed.

【0014】 [0014]

【実施例及び比較例】次に、本発明の実施例について説明する。 [Examples and Comparative Examples will now be described embodiments of the present invention. なお、本実施例はあくまで1例であり、この例に制限されるものではない。 Note that this embodiment is only one example, but is not limited to this example. すなわち、本発明の技術思想の範囲内で、実施例以外の態様あるいは変形を全て包含するものである。 That is, within the technical scope of the present invention is intended to include the various modifications other than the Examples.

【0015】(実施例1)12μm電解銅箔の光沢(S)面に、コバルトめっきを施した。 [0015] Gloss (S) plane (Example 1) 12 [mu] m electrolytic copper foil was subjected to cobalt plating. めっき条件は次の通りである。 Plating conditions are as follows. Co:10g/L pH:2.5 温度:50°C 電流密度Dk:5A/dm 時間:2秒 このコバルトめっき層の厚さは2500μg/dm であった。 Co: 10g / L pH: 2.5 Temperature: 50 ° C Current density Dk: 5A / dm 2 Time: 2 seconds The thickness of the cobalt plated layer was 2500 g / dm 2. このコバルトめっき層を設けた銅箔をエッチング側とし、樹脂基板に接着して銅張り積層板とした。 The copper foil provided with the cobalt plated layer as an etching side, and adhered to the resin substrate and the copper-clad laminate. その後、レジスト塗布及び露光工程により10本の回路を印刷し、さらに銅箔の不要部分を除去するエッチング処理を実施した。 Thereafter, the resist coating and exposure process to print a circuit of ten was an etching process to further remove unwanted portions of the copper foil. エッチング液は塩化第二銅水溶液を用いた。 Etchant using an aqueous solution of cupric chloride. エッチング条件は次の通りである。 Etching conditions are as follows. 水溶液組成:CuCl 、CuO、HCl(3.5M/ Aqueous composition: CuCl 2, CuO, HCl ( 3.5M /
L) S. L) S. G. G. (比重):1.26 温度:50°C 搬送スピード:0.77m/min(槽長770mm) 上面回路幅:0.222mm これによって、図1に示すように銅回路の側面6のレジスト3側から樹脂基板4側に向かってほぼ垂直にエッチングが進行し、矩形の銅箔回路が形成された。 (Specific gravity): 1.26 Temperature: 50 ° C conveyance speed: 0.77 m / min (bath length 770 mm) top circuitry Width: 0.222Mm Thus, the resist 3 side surface 6 of the copper circuit as shown in FIG. 1 etching proceeds substantially vertically toward the resin substrate 4 side from a rectangular copper foil circuit was formed. 次に、エッチングした銅箔の傾斜角度を測定した(なお、この測定値は、エッチング回路10の平均値である)。 It was then measured inclination angle of the etched copper foil (Note that this measurement is an average value of the etching circuit 10). その結果左傾斜角91.8度であり、右傾斜角89.4°であり、ほぼ矩形の銅箔回路が形成され、極めて良好なエッチング回路が得られた。 As a result a left tilt angle 91.8 degrees, a right tilt angle 89.4 °, almost rectangular copper foil circuit is formed, very good etched circuit is obtained.

【0016】(実施例2)12μm電解銅箔の粗化(M)面に、ニッケルめっきを施した。 [0016] roughened (M) plane (Example 2) 12 [mu] m electrolytic copper foil, nickel-plated. めっき条件は次の通りである。 Plating conditions are as follows. Ni:10g/L pH:2.5 温度:50°C 電流密度Dk:5A/dm 時間:8秒 このコバルトめっき層の厚さは6600μg/dm であった。 Ni: 10g / L pH: 2.5 Temperature: 50 ° C Current density Dk: 5A / dm 2 Time: thickness of 8 seconds cobalt plating layer was 6600μg / dm 2. このコバルトめっき層を設けた銅箔をエッチング側として樹脂基板に接着し、銅張り積層板とした。 The copper foil provided with the cobalt plated layer is bonded to a resin substrate as an etching side, and the copper-clad laminate. その後、レジスト塗布及び露光工程により10本の回路を印刷し、さらに銅箔の不要部分を除去するエッチング処理を実施した。 Thereafter, the resist coating and exposure process to print a circuit of ten was an etching process to further remove unwanted portions of the copper foil. エッチング液は塩化第二銅水溶液を用いた。 Etchant using an aqueous solution of cupric chloride. エッチング条件は次の通りである。 Etching conditions are as follows. 水溶液組成:CuCl 、CuO、HCl(3.5M/ Aqueous composition: CuCl 2, CuO, HCl ( 3.5M /
L) S. L) S. G. G. (比重):1.26 温度:50°C 搬送スピード:0.77m/min(槽長770mm) 上面回路幅:0.232mm これによって、図1に示すように銅回路の側面6のレジスト3側から樹脂基板4側に向かってほぼ垂直にエッチングが進行し、矩形の銅箔回路が形成された。 (Specific gravity): 1.26 Temperature: 50 ° C conveyance speed: 0.77 m / min (bath length 770 mm) top circuitry Width: 0.232Mm Thus, the resist 3 side surface 6 of the copper circuit as shown in FIG. 1 etching proceeds substantially vertically toward the resin substrate 4 side from a rectangular copper foil circuit was formed. 次に、エッチングした銅箔の傾斜角度を測定した(なお、この測定値は、エッチング回路10の平均値である)。 It was then measured inclination angle of the etched copper foil (Note that this measurement is an average value of the etching circuit 10). その結果左傾斜角81.5度であり、右傾斜角82.5°であり、図1に示すような、ほぼ矩形の銅箔回路が形成され、良好なエッチング回路が得られた。 As a result a left tilt angle 81.5 degrees, a right tilt angle 82.5 °, as shown in FIG. 1, is generally rectangular copper foil circuit is formed, good etching circuit was obtained.

【0017】(比較例1)12μm電解銅箔の光沢(S)面に、コバルトめっきを施した。 [0017] Gloss (S) plane (Comparative Example 1) 12 [mu] m electrolytic copper foil was subjected to cobalt plating. めっき条件は次の通りである。 Plating conditions are as follows. Co:10g/L pH:2.5 温度:50°C 電流密度Dk:5A/dm 時間:14秒 このコバルトめっき層の厚さは13000μg/dm Co: 10g / L pH: 2.5 Temperature: 50 ° C Current density Dk: 5A / dm 2 Time: 14 seconds The thickness of the cobalt plated layer is 13000μg / dm 2
であった。 Met. このコバルトめっき層を設けた銅箔をエッチング面側として樹脂基板に接着し、エッチング側とし、 The copper foil provided with the cobalt plated layer is bonded to a resin substrate as an etching surface, an etching side,
銅張り積層板とした。 It was a copper-clad laminate. その後、レジスト塗布及び露光工程により10本の回路を印刷し、さらに銅箔の不要部分を除去するエッチング処理を実施した。 Thereafter, the resist coating and exposure process to print a circuit of ten was an etching process to further remove unwanted portions of the copper foil. エッチング液は塩化第二銅水溶液を用いた。 Etchant using an aqueous solution of cupric chloride. エッチング条件は次の通りである。 Etching conditions are as follows. 水溶液組成:CuCl 、CuO、HCl(3.5M/ Aqueous composition: CuCl 2, CuO, HCl ( 3.5M /
L) S. L) S. G. G. (比重):1.26 温度:50°C 搬送スピード:0.77m/min(槽長770mm) 上面回路幅:0.220mm 次に、エッチングした銅箔の傾斜角度を測定した(なお、この測定値は、エッチング回路10の平均値である)。 (Specific gravity): 1.26 Temperature: 50 ° C conveyance speed: 0.77 m / min (bath length 770 mm) top circuitry Width: 0.220 mm was then measured tilt angle of the etched copper foil (Note that this measurement values ​​are the average of etching circuit 10). その結果左傾斜角101.3度であり、右傾斜角108.0°であり、図3に示すような、レジスト側に比べて樹脂基板側が過度にエッチングされ、逆台形状の銅箔回路が形成され、エッチング不良の回路が形成された。 As a result a left tilt angle 101.3 degrees, a right tilt angle 108.0 °, as shown in FIG. 3, the resin substrate side as compared with the resist side is excessively etched, the copper foil circuits of inverted trapezoidal is formed, the circuit of etching defect is formed.

【0018】(比較例2)12μm電解銅箔を粗化(M)面側をエッチング面として、樹脂基板に接着して銅張り積層板とした後、レジスト塗布及び露光工程により10本の回路を印刷し、さらに銅箔の不要部分を除去するエッチング処理を実施した。 [0018] (Comparative Example 2) 12 [mu] m electrodeposited copper foil etched surface roughening (M) side and was adhered to the resin substrate and the copper-clad laminate, the circuit of ten by resist application and exposure steps printed, and an etching process to further remove unwanted portions of the copper foil. エッチング液は塩化第二銅水溶液を用いた。 Etchant using an aqueous solution of cupric chloride. エッチング条件は次の通りである。 Etching conditions are as follows. 水溶液組成:CuCl 、CuO、HCl(3.5M/ Aqueous composition: CuCl 2, CuO, HCl ( 3.5M /
L) S. L) S. G. G. (比重):1.26 温度:50°C 搬送スピード:0.77m/min(槽長770mm) 上面回路幅:0.233mm 次に、エッチングした銅箔の傾斜角度を測定した(なお、この測定値は、エッチング回路10の平均値である)。 (Specific gravity): 1.26 Temperature: 50 ° C conveyance speed: 0.77 m / min (bath length 770 mm) top circuitry Width: 0.233Mm was then measured inclination angle of the etched copper foil (Note that this measurement values ​​are the average of etching circuit 10). その結果、左傾斜角73.5度であり、右傾斜角76.3°であり、図2に示すような、ダレが大きく台形状の銅箔回路が形成され、エッチング不良であった。 As a result, a left tilt angle 73.5 degrees, a right tilt angle 76.3 °, as shown in FIG. 2, sagging is large trapezoidal copper foil circuit formed was poor etching.

【0019】以上の結果を表1に示す。 [0019] The above results are shown in Table 1. 表1から明らかなように、100〜10000μg/dm の範囲にあるコバルトめっき及びニッケルめっきは、ほぼ矩形の銅箔回路が形成され、極めて良好なエッチング回路が得られた。 As is evident from Table 1, cobalt plating and nickel plating in the range of 100~10000μg / dm 2 is substantially rectangular copper foil circuit is formed, very good etched circuit is obtained. 特にコバルトめっき層は少量でも優れたエッチング性が得られた。 In particular cobalt plating layer excellent etching resistance even in a small amount was obtained. これに対して、めっき層を設けていないものは、ダレが大きく台形状の銅箔回路が形成され、 In contrast, those not provided with the plating layer, sagging is large trapezoidal copper foil circuit formed,
エッチング不良であった。 It was defective etching. また、逆にめっき層が多すぎると、レジスト側に比べて樹脂基板側が過度にエッチングされ、逆台形状の銅箔回路が形成されて、エッチング不良の回路が形成された。 Further, when the reverse in the plating layer is too large, the resin substrate side as compared with the resist side is excessively etched, the copper foil circuits of inverted trapezoidal shape is formed, the circuit of etching defect is formed. 以上の実施例及び比較例以外に、多くの実験を繰り返し行ったところ、100〜10 Besides the above Examples and Comparative Examples, was repeated a number of experiments, 100 to 10
000μg/dm の金属又は合金層を形成することが望ましいことが分かった。 It was found that it is desirable to form a 000μg / dm 2 of metal or alloy layer. 実施例では、コバルト層及びニッケル層を形成した場合について説明したが、これらの合金層でも同様な効果があることを確認した。 In the embodiment has described the case of forming the cobalt layer and the nickel layer, it was confirmed that even in these alloy layers have the same effect. しかし、合金めっきに比べ,コバルトめっき及びニッケルめっきの単独層はめっき液及びめっき条件の管理が容易なので、めっき処理操作上より効果的である。 However, compared with the alloy plating, single layer of cobalt plating and nickel plating for their ease of management of the plating solution and the plating conditions, it is more effective than the plating operation.

【0020】 [0020]

【表1】 [Table 1]

【0021】 [0021]

【発明の効果】本発明は、銅張り積層板の銅箔をエッチングにより回路形成を行うに際し、銅箔の厚み方向のエッチング速度を制御することにより、ダレのない回路幅の均一な回路を形成できるという優れた効果を有する。 According to the present invention, formed when performing a copper foil of a copper-clad laminate circuit formed by etching, by controlling the etching rate in the thickness direction of the copper foil, uniform circuit sagging without circuit width It has an excellent effect that it can be.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の実施例で得られた良好な矩形の銅箔回路が形成された様子を示す説明図である。 FIG. 1 is an explanatory view showing a state in which good rectangular copper foil circuit obtained is formed in the embodiment of the present invention.

【図2】比較例2に示すようなダレが大きく、台形状の不良な銅箔回路が形成された様子を示す説明図である。 [Figure 2] large sag as shown in Comparative Example 2 is an explanatory view showing a state in which poor copper foil circuits of trapezoidal shape is formed.

【図3】エッチング速度を高めた例であり、エッチングが強すぎて銅箔回路が細くなり、不良な回路が形成された様子を示す説明図である。 [Figure 3] is an example of enhanced etching rate, etching is too strong narrows copper foil circuit is an explanatory view showing a state in which defective circuit is formed.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 銅箔 2 ダレが発生した銅箔エッチング面 3 レジスト 4 樹脂基板 5 過度にエッチングされた銅箔エッチング面 6 基板に対してほぼ垂直である銅箔エッチング面 7 コバルト又はニッケル等の金属又は合金層 Copper etched surface 7 cobalt or metal or alloy layer such as nickel is substantially perpendicular to the 1 copper foil 2 foil etched surface 3 resist 4 resin substrate 5 excessively etched copper foil etched surface 6 substrate sagging occurs

フロントページの続き Fターム(参考) 4K057 WA10 WB03 WB11 WB15 WE08 WE30 WG02 WG03 WN01 5E339 BC01 BC02 BD06 BD08 BD11 BE13 CE11 CE12 CE19 CF15 FF01 GG02 Front page of the continued F-term (reference) 4K057 WA10 WB03 WB11 WB15 WE08 WE30 WG02 WG03 WN01 5E339 BC01 BC02 BD06 BD08 BD11 BE13 CE11 CE12 CE19 CF15 FF01 GG02

Claims (11)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 エッチングにより回路形成を行う電子回路用銅箔において、エッチング面側に銅よりエッチングレートの遅い金属又は合金層を形成したことを特徴とする電子回路用銅箔。 1. A copper foil for electronic circuit for performing a circuit formed by etching a copper foil for electronic circuit, characterized in that the formation of the slower metal or alloy layer etching rate of copper in the etching surface.
  2. 【請求項2】 銅張り積層板であることを特徴とする請求項1記載の電子回路用銅箔。 2. A copper foil for electronic circuit according to claim 1, wherein the copper-clad laminate.
  3. 【請求項3】 銅よりエッチングレートの遅い金属又は合金層がコバルト、ニッケル又はこれらの合金層であることを特徴とする請求項1又は2記載の電子回路用銅箔。 Wherein cobalt slow metal or alloy layer etching rate than copper, nickel or copper foil for electronic circuit according to claim 1 or 2, wherein it is an alloy thereof.
  4. 【請求項4】 100〜10000μg/dm の金属又は合金層を形成することを特徴とする請求項1〜3のそれぞれに記載の電子回路用銅箔。 4. A copper foil for electronic circuit according to each of claims 1 to 3, characterized in that to form a 100~10000μg / dm 2 of metal or alloy layer.
  5. 【請求項5】 銅箔のエッチング側面の傾斜角度が、8 The inclination angle of 5. copper etching side of, 8
    0〜95度の範囲にあることを特徴とする請求項1〜4 Claims 1-4, characterized in that in the range of 0 to 95 degrees
    のそれぞれに記載の電子回路用銅箔。 Copper foil for electronic circuit according to each of.
  6. 【請求項6】 銅箔のエッチング側面の傾斜角度が、8 The inclination angle of 6. foil etching side of, 8
    5〜90度の範囲にあることを特徴とする請求項1〜4 Claims 1-4, characterized in that in the range of 5 to 90 degrees
    のそれぞれに記載の電子回路用銅箔。 Copper foil for electronic circuit according to each of.
  7. 【請求項7】 銅張り積層板の銅箔をエッチングし電子回路を形成する方法において、銅箔のエッチング面側に銅よりエッチングレートの遅い金属又は合金層を形成した後、塩化第二銅水溶液を用いて該銅箔をエッチングし、回路を形成することを特徴とする電子回路の形成方法。 7. A method for the copper foil of the copper-clad laminate is etched to form the electronic circuit, after forming a slower metal or alloy layer etching rate of copper to the etched surface side of the copper foil, an aqueous solution of cupric chloride method of forming an electronic circuit by etching the copper foil, and forming a circuit by using.
  8. 【請求項8】 銅よりエッチングレートの遅い金属又は合金層がコバルト、ニッケル又はこれらの合金層であることを特徴とする請求項7記載の電子回路の形成方法。 8. A cobalt slow metal or alloy layer etching rate than copper, nickel, or a method of forming the electronic circuit according to claim 7, wherein the alloys thereof layers.
  9. 【請求項9】 100〜10000μg/dm の金属又は合金層を形成することを特徴とする請求項7又は8 9. The method of claim 7 or 8, characterized in that to form a 100~10000μg / dm 2 of metal or alloy layer
    記載の電子回路の形成方法。 Method of forming an electronic circuit according.
  10. 【請求項10】 銅箔のエッチング側面の傾斜角度が、 10. A tilt angle of the etching side of the copper foil,
    80〜95度の範囲にあることを特徴とする請求項7〜 Claim, characterized in that in the range of 80 to 95 degrees 7
    9のそれぞれに記載の電子回路の形成方法。 Method of forming an electronic circuit according to each of 9.
  11. 【請求項11】 銅箔のエッチング側面の傾斜角度が、 The inclination angle of 11. copper etching side of,
    85〜90度の範囲にあることを特徴とする請求項7〜 Claim, characterized in that in the range of 85 to 90 degrees 7
    9のそれぞれに記載の電子回路の形成方法。 Method of forming an electronic circuit according to each of 9.
JP2000369753A 2000-12-05 2000-12-05 The method of forming the copper foil and electronic circuitry electronics Active JP4592936B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000369753A JP4592936B2 (en) 2000-12-05 2000-12-05 The method of forming the copper foil and electronic circuitry electronics

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000369753A JP4592936B2 (en) 2000-12-05 2000-12-05 The method of forming the copper foil and electronic circuitry electronics

Publications (3)

Publication Number Publication Date
JP2002176242A true true JP2002176242A (en) 2002-06-21
JP2002176242A5 true JP2002176242A5 (en) 2009-08-27
JP4592936B2 JP4592936B2 (en) 2010-12-08

Family

ID=18839747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000369753A Active JP4592936B2 (en) 2000-12-05 2000-12-05 The method of forming the copper foil and electronic circuitry electronics

Country Status (1)

Country Link
JP (1) JP4592936B2 (en)

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003015483A1 (en) * 2001-08-06 2003-02-20 Mitsui Mining & Smelting Co., Ltd. Printed wiring board-use copper foil and copper clad laminated sheet using the printed wiring board-use copper foil
JP2009081396A (en) * 2007-09-27 2009-04-16 Hitachi Cable Ltd Copper foil for printed wiring board, and processing method of surface thereof
WO2010074072A1 (en) 2008-12-26 2010-07-01 日鉱金属株式会社 Rolled copper foil or electrolytic copper foil for electronic circuit, and method for forming electronic circuit using the rolled copper foil or electrolytic copper foil
WO2010074053A1 (en) 2008-12-26 2010-07-01 日鉱金属株式会社 Rolled copper foil or electrolytic copper foil for electronic circuit and method of forming electronic circuit using same
WO2010074061A1 (en) 2008-12-26 2010-07-01 日鉱金属株式会社 Rolled copper foil or electrolytic copper foil for electronic circuit, and method for forming electronic circuit using the rolled copper foil or electrolytic copper foil
WO2010074054A1 (en) * 2008-12-26 2010-07-01 日鉱金属株式会社 Method for forming electronic circuit
WO2010087268A1 (en) 2009-01-29 2010-08-05 日鉱金属株式会社 Rolled copper foil or electrolytic copper foil for electronic circuit, and method for forming electronic circuit using same
WO2010147059A1 (en) * 2009-06-18 2010-12-23 Jx日鉱日石金属株式会社 Electronic circuit, method for forming same, and copper-clad laminate for electronic circuit formation
WO2011086972A1 (en) 2010-01-15 2011-07-21 Jx日鉱日石金属株式会社 Electronic circuit, method for forming same, and copper clad laminate for electronic circuit formation
JP2011166018A (en) * 2010-02-12 2011-08-25 Jx Nippon Mining & Metals Corp Copper foil for printed wiring board
WO2011122645A1 (en) * 2010-03-30 2011-10-06 Jx日鉱日石金属株式会社 Copper foil for printed wiring board with excellent etching properties and layered body using same
WO2011121803A1 (en) * 2010-03-30 2011-10-06 Jx日鉱日石金属株式会社 Copper foil for printed wiring board having excellent thermal discoloration resistance and etching properties, and laminate using same
JP2011210993A (en) * 2010-03-30 2011-10-20 Jx Nippon Mining & Metals Corp Copper foil for printed wiring board and layered body which have superior etching property
JP2011210988A (en) * 2010-03-30 2011-10-20 Jx Nippon Mining & Metals Corp Copper foil for printed wiring board and layered body which have superior etching property
WO2012017716A1 (en) 2010-08-06 2012-02-09 三洋電機株式会社 Content playback device for sequentially playing back multiple files
WO2012063805A1 (en) 2010-11-12 2012-05-18 Jx日鉱日石金属株式会社 Method for forming circuit on flexible laminate substrate
WO2013027444A1 (en) * 2011-08-24 2013-02-28 Jx日鉱日石金属株式会社 Copper foil for printed wiring board and laminated body using same
WO2013047847A1 (en) * 2011-09-30 2013-04-04 Jx日鉱日石金属株式会社 Copper foil for printed circuit board and laminated plate using same
WO2014136763A1 (en) * 2013-03-05 2014-09-12 三井金属鉱業株式会社 Copper foil for laser processing, carrier-foil-supported copper foil for laser processing, copper-clad laminate, and process for producing printed wiring board
KR20140119750A (en) 2012-02-03 2014-10-10 제이엑스 닛코 닛세키 킨조쿠 가부시키가이샤 Copper foil for printed wiring board, as well as laminate, printed wiring board, and electronic component using same
CN105018985A (en) * 2015-08-10 2015-11-04 灵宝华鑫铜箔有限责任公司 Surface treatment process for reducing electrolytic copper foil lateral erosion phenomenon
KR20160086287A (en) 2015-01-09 2016-07-19 제이엑스금속주식회사 Metal substrate with plating
JP2017505546A (en) * 2014-12-09 2017-02-16 インテル・コーポレーション Microelectronic substrate having a copper alloy conductive path structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04284690A (en) * 1991-03-13 1992-10-09 Furukawa Saakitsuto Foil Kk Copper foil for inner layer circuit of multilayer printed circuit board and manufacture thereof
JPH0681172A (en) * 1992-09-01 1994-03-22 Hitachi Cable Ltd Formation of fine pattern
JPH07297544A (en) * 1994-04-21 1995-11-10 Hitachi Chem Co Ltd Manufacture of printed wiring board
JP2000269619A (en) * 1999-03-16 2000-09-29 Reiko Co Ltd Data communication antenna circuit board and film for manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04284690A (en) * 1991-03-13 1992-10-09 Furukawa Saakitsuto Foil Kk Copper foil for inner layer circuit of multilayer printed circuit board and manufacture thereof
JPH0681172A (en) * 1992-09-01 1994-03-22 Hitachi Cable Ltd Formation of fine pattern
JPH07297544A (en) * 1994-04-21 1995-11-10 Hitachi Chem Co Ltd Manufacture of printed wiring board
JP2000269619A (en) * 1999-03-16 2000-09-29 Reiko Co Ltd Data communication antenna circuit board and film for manufacturing the same

Cited By (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003015483A1 (en) * 2001-08-06 2003-02-20 Mitsui Mining & Smelting Co., Ltd. Printed wiring board-use copper foil and copper clad laminated sheet using the printed wiring board-use copper foil
US6989199B2 (en) * 2001-08-06 2006-01-24 Mitsui Mining & Smelting Co., Ltd. Copper foil for printed-wiring board and copper-clad laminate using copper foil for printed-wiring board
JP2009081396A (en) * 2007-09-27 2009-04-16 Hitachi Cable Ltd Copper foil for printed wiring board, and processing method of surface thereof
US8668994B2 (en) 2008-12-26 2014-03-11 Jx Nippon Mining & Metals Corporation Rolled copper foil or electrolytic copper foil for electronic circuit, and method of forming electronic circuit using same
WO2010074053A1 (en) 2008-12-26 2010-07-01 日鉱金属株式会社 Rolled copper foil or electrolytic copper foil for electronic circuit and method of forming electronic circuit using same
WO2010074072A1 (en) 2008-12-26 2010-07-01 日鉱金属株式会社 Rolled copper foil or electrolytic copper foil for electronic circuit, and method for forming electronic circuit using the rolled copper foil or electrolytic copper foil
WO2010074054A1 (en) * 2008-12-26 2010-07-01 日鉱金属株式会社 Method for forming electronic circuit
US8580390B2 (en) 2008-12-26 2013-11-12 Jx Nippon Mining & Metals Corporation Rolled copper foil or electrolytic copper foil for electronic circuit, and method of forming electronic circuit using same
KR101295472B1 (en) * 2008-12-26 2013-08-09 제이엑스 닛코 닛세키 킨조쿠 가부시키가이샤 Rolled copper foil or electrolytic copper foil for electronic circuit and method of forming electronic circuit using same
KR101269745B1 (en) 2008-12-26 2013-05-30 제이엑스 닛코 닛세키 킨조쿠 가부시키가이샤 Rolled copper foil or electrolytic copper foil for electronic circuit, method for forming electronic circuit and printed substrate using the rolled copper foil or electrolytic copper foil
KR101269708B1 (en) 2008-12-26 2013-05-30 제이엑스 닛코 닛세키 킨조쿠 가부시키가이샤 Rolled copper foil or electrolytic copper foil for electronic circuit, method for forming electronic circuit and printed substrate using the rolled copper foil or electrolytic copper foil
CN102265710B (en) 2008-12-26 2014-04-30 吉坤日矿日石金属株式会社 Rolled copper foil or electrolytic copper foil for electronic circuit, and method for forming electronic circuit using rolled copper foil or electrolytic copper foil
CN105578776A (en) * 2008-12-26 2016-05-11 吉坤日矿日石金属株式会社 Rolled copper foil or electrolytic copper foil for electronic circuit and method of forming electronic circuit using same
WO2010074061A1 (en) 2008-12-26 2010-07-01 日鉱金属株式会社 Rolled copper foil or electrolytic copper foil for electronic circuit, and method for forming electronic circuit using the rolled copper foil or electrolytic copper foil
KR101229617B1 (en) 2008-12-26 2013-02-04 제이엑스 닛코 닛세키 킨조쿠 가부시키가이샤 Method for forming electronic circuit
US8357307B2 (en) 2008-12-26 2013-01-22 Jx Nippon Mining & Metals Corporation Method of forming electronic circuit
JP5358586B2 (en) * 2008-12-26 2013-12-04 Jx日鉱日石金属株式会社 Method of forming a rolled copper foil or an electrolytic copper foil and electronic circuit using these electronics
WO2010087268A1 (en) 2009-01-29 2010-08-05 日鉱金属株式会社 Rolled copper foil or electrolytic copper foil for electronic circuit, and method for forming electronic circuit using same
JP2014053636A (en) * 2009-06-18 2014-03-20 Jx Nippon Mining & Metals Corp Electronic circuit and formation method therefor, and copper-clad laminate for electronic circuit formation
WO2010147059A1 (en) * 2009-06-18 2010-12-23 Jx日鉱日石金属株式会社 Electronic circuit, method for forming same, and copper-clad laminate for electronic circuit formation
JP5676443B2 (en) * 2009-06-18 2015-02-25 Jx日鉱日石金属株式会社 Electronic circuit and forming method and an electronic circuit for forming a copper clad laminate
WO2011086972A1 (en) 2010-01-15 2011-07-21 Jx日鉱日石金属株式会社 Electronic circuit, method for forming same, and copper clad laminate for electronic circuit formation
EP2525633A1 (en) * 2010-01-15 2012-11-21 JX Nippon Mining & Metals Corporation Electronic circuit, method for forming same, and copper clad laminate for electronic circuit formation
EP2525633A4 (en) * 2010-01-15 2013-07-03 Jx Nippon Mining & Metals Corp Electronic circuit, method for forming same, and copper clad laminate for electronic circuit formation
JP2011166018A (en) * 2010-02-12 2011-08-25 Jx Nippon Mining & Metals Corp Copper foil for printed wiring board
WO2011122645A1 (en) * 2010-03-30 2011-10-06 Jx日鉱日石金属株式会社 Copper foil for printed wiring board with excellent etching properties and layered body using same
WO2011121803A1 (en) * 2010-03-30 2011-10-06 Jx日鉱日石金属株式会社 Copper foil for printed wiring board having excellent thermal discoloration resistance and etching properties, and laminate using same
JP2011210993A (en) * 2010-03-30 2011-10-20 Jx Nippon Mining & Metals Corp Copper foil for printed wiring board and layered body which have superior etching property
JP2011210988A (en) * 2010-03-30 2011-10-20 Jx Nippon Mining & Metals Corp Copper foil for printed wiring board and layered body which have superior etching property
JP2011211008A (en) * 2010-03-30 2011-10-20 Jx Nippon Mining & Metals Corp Copper foil for printed wiring board and layered body which have superior etching property
JP5079883B2 (en) * 2010-03-30 2012-11-21 Jx日鉱日石金属株式会社 Resistance to thermal discoloration and excellent copper foil for printed wiring boards in etching properties and laminate using the same
WO2012017716A1 (en) 2010-08-06 2012-02-09 三洋電機株式会社 Content playback device for sequentially playing back multiple files
WO2012063805A1 (en) 2010-11-12 2012-05-18 Jx日鉱日石金属株式会社 Method for forming circuit on flexible laminate substrate
CN103262665A (en) * 2011-08-24 2013-08-21 Jx日矿日石金属株式会社 Copper foil for printed wiring board and laminated body using same
JP2013045881A (en) * 2011-08-24 2013-03-04 Jx Nippon Mining & Metals Corp Copper foil for printed wiring board and laminate sheet using the same
WO2013027444A1 (en) * 2011-08-24 2013-02-28 Jx日鉱日石金属株式会社 Copper foil for printed wiring board and laminated body using same
CN103262665B (en) * 2011-08-24 2016-03-09 Jx日矿日石金属株式会社 The method of forming a copper foil laminate, the printed wiring board and electronic circuit
WO2013047847A1 (en) * 2011-09-30 2013-04-04 Jx日鉱日石金属株式会社 Copper foil for printed circuit board and laminated plate using same
KR20140119750A (en) 2012-02-03 2014-10-10 제이엑스 닛코 닛세키 킨조쿠 가부시키가이샤 Copper foil for printed wiring board, as well as laminate, printed wiring board, and electronic component using same
WO2014136763A1 (en) * 2013-03-05 2014-09-12 三井金属鉱業株式会社 Copper foil for laser processing, carrier-foil-supported copper foil for laser processing, copper-clad laminate, and process for producing printed wiring board
JPWO2014136763A1 (en) * 2013-03-05 2017-02-09 三井金属鉱業株式会社 For laser processing a copper foil, the carrier foil for laser processing a copper foil, a manufacturing method of the copper-clad laminate and a printed wiring board
US9758845B2 (en) 2014-12-09 2017-09-12 Intel Corporation Microelectronic substrates having copper alloy conductive route structures
JP2017505546A (en) * 2014-12-09 2017-02-16 インテル・コーポレーション Microelectronic substrate having a copper alloy conductive path structures
KR20160086287A (en) 2015-01-09 2016-07-19 제이엑스금속주식회사 Metal substrate with plating
CN105018985A (en) * 2015-08-10 2015-11-04 灵宝华鑫铜箔有限责任公司 Surface treatment process for reducing electrolytic copper foil lateral erosion phenomenon

Also Published As

Publication number Publication date Type
JP4592936B2 (en) 2010-12-08 grant

Similar Documents

Publication Publication Date Title
US4604160A (en) Method for manufacture of printed wiring board
US4394419A (en) Printed circuit material
US4503112A (en) Printed circuit material
US6779262B1 (en) Method for manufacturing a multilayer printed circuit board
US5545466A (en) Copper-clad laminate and printed wiring board
US5437914A (en) Copper-clad laminate and printed wiring board
US4889584A (en) Method of producing conductor circuit boards
US6117300A (en) Method for forming conductive traces and printed circuits made thereby
WO2010110092A1 (en) Copper foil for printed wiring board and method for producing same
WO2002024444A1 (en) Copper foil for high-density ultrafine wiring board
US20030145458A1 (en) Method for manufacturing multilayer wiring board, and multilayer wiring board manufactured thereby
JP2004169181A (en) Ultrathin copper foil with carrier and method for manufacturing the same, and printed wiring board using ultrathin copper foil with carrier
US7381475B2 (en) Treated copper foil and circuit board
JP2006103189A (en) Surface-treated copper foil and circuit board
JP2000269637A (en) Copper foil for high-density ultrafine wiring board
JPH11340595A (en) Copper foil for printed circuit board and copper foil attached with resin
JP2002280684A (en) Copper clad flexible circuit board and its manufacturing method
JPH10341066A (en) Copper foil for printed circuit and copper foil with resin adhesive for printed circuit and copper-clad lamination board for printed circuit using it
JP2003008199A (en) Method for roughening copper surface of printed wiring board and printed wiring board and its producing method
JP2011168887A (en) Roughened copper foil, method for producing the same, copper-clad laminate, and printed circuit board
JPH09143785A (en) Electrolytic copper foil for fine pattern and its production
JPH06318783A (en) Manufacturing method of multilayered circuit substrate
JP2004263296A (en) Copper foil for fine pattern printed circuit and manufacturing method therefor
US5504992A (en) Fabrication process of wiring board
JP2011166018A (en) Copper foil for printed wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071116

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090709

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20090709

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20090811

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090818

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091117

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100115

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100115

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100316

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100609

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20100628

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100727

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100804

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100804

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20100813

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100914

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100915

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130924

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130924

Year of fee payment: 3

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250