WO2010138204A1 - Method and apparatus for iterative timing recovery - Google Patents

Method and apparatus for iterative timing recovery Download PDF

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Publication number
WO2010138204A1
WO2010138204A1 PCT/US2010/001576 US2010001576W WO2010138204A1 WO 2010138204 A1 WO2010138204 A1 WO 2010138204A1 US 2010001576 W US2010001576 W US 2010001576W WO 2010138204 A1 WO2010138204 A1 WO 2010138204A1
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WO
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Prior art keywords
timing
signal
error
iterative
recovery
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English (en)
French (fr)
Inventor
Dirk Schmitt
Paul Gothard Knutson
Wen Gao
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Thomson Licensing SAS
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Thomson Licensing SAS
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Priority to US13/138,923 priority Critical patent/US20120039380A1/en
Priority to BRPI1011199A priority patent/BRPI1011199A2/pt
Priority to JP2012513059A priority patent/JP2012528523A/ja
Priority to CN2010800234822A priority patent/CN102449949A/zh
Priority to EP10727521A priority patent/EP2436138A1/en
Publication of WO2010138204A1 publication Critical patent/WO2010138204A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2656—Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2668—Details of algorithms
    • H04L27/2673—Details of algorithms characterised by synchronisation parameters
    • H04L27/2676—Blind, i.e. without using known symbols
    • H04L27/2678—Blind, i.e. without using known symbols using cyclostationarities, e.g. cyclic prefix or postfix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2668—Details of algorithms
    • H04L27/2673—Details of algorithms characterised by synchronisation parameters
    • H04L27/2676—Blind, i.e. without using known symbols
    • H04L27/2679—Decision-aided
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/004—Synchronisation arrangements compensating for timing error of reception due to propagation delay
    • H04W56/005—Synchronisation arrangements compensating for timing error of reception due to propagation delay compensating for timing error by adjustment in the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/90—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for satellite broadcast receiving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H04L2027/0044—Control loops for carrier regulation
    • H04L2027/0053—Closed loops
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H04L2027/0044—Control loops for carrier regulation
    • H04L2027/0063—Elements of loops
    • H04L2027/0067—Phase error detectors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation

Definitions

  • the present principles relate to iterative timing recovery in receivers systems.
  • Carrier recovery schemes can be classified into two structures: feed-forward structure and feedback structure.
  • the feedback carrier recovery uses a digital Phase Locked Loop (PLL) to track out the carrier phase and frequency offset.
  • PLL Phase Locked Loop
  • it relies on a decision directed or non-data-aided approach to estimate the phase error at each time instant.
  • decision-directed approach the decision errors will cause additional self noise while the non-data-aided approach can only apply to a limited number of multiple phase shift keying (MPSK) formats.
  • MPSK phase shift keying
  • the feedback carrier recovery scheme could be disturbed by cycle slips which may cause a large number of errors due to phase ambiguity.
  • Feed forward carrier recovery is used to reduce the probability of cycle slips.
  • the feed forward carrier recovery relies on pre-known data symbols (e.g. pilot or sync symbols) embedded in the data stream. This reduces the bandwidth efficiency since no data is transmitted during a pilot or sync interval.
  • the second disadvantage of the feed-forward carrier recovery is the inability to recover large frequency offsets or phase variations due to phase noise between the measurement blocks.
  • FTN Faster-than-Nyquist
  • an iterative timing recovery is suggested for FTN signaling using a feedback timing error signal from the forward error correction (FEC) block.
  • the FEC block could be realized by a so-called soft decoder like Low Density Parity Check (LDPC), a turbo decoder or a soft output Viterbi algorithm (SOVA).
  • LDPC Low Density Parity Check
  • SOVA soft output Viterbi algorithm
  • a MAP decoder is used to match the intersymbol interference (ISI) response of the FTN signal.
  • An additional equalizer is utilized in front of the maximum a posteriori (MAP) decoder which matches the equalized FTN signal to the truncated ISI target.
  • the timing error is then generated by using a modified Mueller and Muller (M&M) timing error detector (TED).
  • M&M Mueller and Muller
  • the iterative symbol timing recovery is used when ISI becomes a severe problem for FTN signaling.
  • the method comprises performing adaptive equalization and maximum likelihood sequence estimation in order to recover symbol timing.
  • an apparatus for iterative timing recovery comprising an comprising adaptive equalizer for performing adaptive equalization and a symbol detector for performing maximum likelihood sequence estimation in order to recover symbol timing.
  • a method for iterative timing recovery comprising filtering an interpolated first error signal using a matched filter, equalizing the filtered interpolated first error signal, detecting a timing error with an M&M timing error detector to produce a second error signal, and using said second error signal to recover the timing of a signal that uses faster-than-Nyquist signaling.
  • an apparatus for iterative timing recovery comprises a matched filter for filtering an interpolated first error signal using a matched filter, an equalizer for equalizing the filtered interpolated first error signal, a timing error detector for detecting a timing error with an M&M timing error detector to produce a second error signal, and a recovery circuit for using said second error signal to recover the timing of a signal that uses faster-than-Nyquist signaling.
  • Figure 1 shows an apparatus for least-mean-square error (LMSE) estimation with equalization for FTN signaling.
  • Figure 2 shows an apparatus for iterative timing recovery for FTN signaling.
  • LMSE least-mean-square error
  • Figure 3 shows a method for iterative timing recovery.
  • Figure 4 shows a method for iterative timing recovery for FTN signaling.
  • FTN signaling can be modeled as a channel response with memory.
  • AWGN Additive White Gaussian noise
  • the optimum symbol detector for FTN signaling relies not only on the current symbol but also the neighbor symbols.
  • the interference introduced by the neighbor symbols is called inter-symbol interference (ISI).
  • ISI inter-symbol interference
  • the ISI distorted signals are modeled with a trellis structure and its memory is often infinite. So infinite states in the trellis have to be considered for symbol detection.
  • One way to solve this problem is to reduce the number of states in the decoding process by using sub-optimum decoding structures.
  • the PU100126 is the maximum likelihood detector or maximum a posteriori detector if a priori information is available.
  • MLSE Maximum Likelihood Sequence Estimation
  • the Maximum Likelihood Sequence Estimation was first mentioned by Forney and Viterbi [Fo73] and an optimum detection was given by Viterbi [Vit67] with the Viterbi decoder, which estimates the maximum likelihood path (maximum likelihood sequence) through the trellis. Bahl, Cocke, Raviv and Jelinek further improve the maximum likelihood sequence estimation by the BCJR algorithm [BCJR74] which generates soft output values for each symbol decision.
  • BCJR74 Max-log-MAP decoder
  • the Max-log-MAP decoder relies on a backward and forward recursion through the trellis.
  • the most important step on the design of a Maximum Likelihood Sequence Estimation (MLSE) decoder is the definition of the state transition probabilities or so-called branch metrics. Therefore the Euclidian distance between the received symbol y and the ISI response targets t(s,s') is evaluated as it is shown in equation
  • s denotes the successor states and s' denotes the current state in the trellis.
  • the targets t(s,s') for each state transition are generated by folding the possible candidates in the channel memory with the truncated ISI response waveform hm with the trunctated ISI length L.
  • Max-log-MAP decoding process is then further divided into the forward, backward recursions and the a posteriori log likelihood ratios LLR computation [WHOO].
  • An example for BSPK modulation is provided as following: (1) Forward recursion
  • a k (s) msoL(A k _ ⁇ (s') + x k (s',s)) (3) s
  • k denotes the time index of the trellis.
  • the truncated ISI response has to be used to implement a realizable MLSE detector.
  • H ⁇ s ⁇ (j) the true ISI response H pos tG
  • an adaptive equalizer should be used before the MLSE detector.
  • the LMSE adaptation minimizes the least mean square error between the equalized symbol y ⁇ nT s ) and the desired symbol d ⁇ nT s ) given in following equation.
  • e(nT s ) y'(nT s ) -d(nT s ) (6)
  • the LMSE with equalization is shown in Figure 1.
  • the filter coefficient vector w(nT s ) can be expressed as following: PU100126
  • ⁇ (n + l)T s ) ⁇ nT s ) + a ⁇ L(y(nT s ) ⁇ a, ⁇ r ) (8) ⁇
  • ⁇ XnT s Re[(a ⁇ nT s ))* y'(nT s -T s + ⁇ )-(a"(nT s -T s )) * yXnT s + ⁇ )] , (9)
  • FIG. 1 shows an apparatus for iterative timing recovery.
  • An FIR filter is used to filter an input signal.
  • the input signal is also in signal communication with a first Max-log-Map and Equalizer block.
  • the FIR filter has coefficients under control by a Least Mean Squared (LMS) block.
  • LMS Least Mean Squared
  • the LMS block takes as input the output of the first Max-log-Map and Equalizer block, and the output of a summing circuit.
  • the summing circuit has a non-inverting input that is in signal communication with a second Max-log-Map circuit, and a second PU100126
  • the FIR filter output is in signal communication with the second Max-log-Map circuit and a third Max-log-Map circuit.
  • the output of the third Max-log-Map circuit is in signal communication with the input of the target pulse shaping block and is used as an output of the apparatus.
  • the output of the second Max-log-Map circuit is also an output of the apparatus that is representative of the equalized symbol.
  • FIG. 2 shows an apparatus for iterative timinig recovery for faster-than-Nyquist (FTN) signaling.
  • An interpolator output is in signal communication with the input of a matched filter, whose output is in signal communication with an equalizer.
  • the equalizer output is in signal communication with a Max-log-Map block, and in signal communication with a first input of an Mueller & Muller (M&M) timing error detector (TED) block.
  • M&M Mueller & Muller
  • TED timing error detector
  • the Max-log-Map block's output is in signal communication with the input of an inter-symbol interference (ISI) filter, whose output is in signal communication with a second input of the M&M TED.
  • ISI inter-symbol interference
  • the M&M TED's output is in signal communication with a first input of a multiplier circuit, whose second input is a variable.
  • the output of the multiplier circuit is in signal communication with a first non-inverting input of a summing circuit, whose second input is a delayed version of the summing circuit output, which is also in signal communication with the interpolator input.
  • Figure 3 shows a method for interative timing recovery. The method is comprised of an adaptive equalization step 310 and a Mean Least Squared estimation step 320.
  • Figure 4 shows a method for itnerative timing recovery for FTN signaling, comprising the steps of filtering 410, equalizing 420, detecting 430 and recovering timing 440.
  • processor or “controller” should not be construed to refer PU100126
  • DSP digital signal processor
  • ROM read-only memory
  • RAM random access memory
  • non-volatile storage non-volatile storage
  • any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.
  • a description will now be given of the many attendant advantages and features of the present principles, some of which have been mentioned above.
  • one advantage is a method for iterative timing recovery comprising performing adaptive equalization and maximum likelihood sequence estimation in order to recover symbol timing.
  • Another advantage is an apparatus for iterative timing recovery comprising an comprising adaptive equalizer for performing adaptive equalization and a symbol detector for performing maximum likelihood sequence estimation in order to recover symbol timing.
  • Another advantage is a method for iterative timing recovery comprising filtering an interpolated first error signal using a matched filter, equalizing the filtered interpolated first error signal, detecting a timing error with an M&M timing error detector to produce a second error signal, and using said second error signal to recover the timing of a signal that uses faster-than-Nyquist signaling.
  • Yet another advantage is an apparatus for iterative timing recovery comprising a matched filter for filtering an interpolated first error signal using a matched filter, an equalizer for equalizing the filtered interpolated first error signal, a timing error detector for detecting a timing error with an M&M timing error detector to produce a second error signal, and a recovery circuit for using said second error signal to recover the timing of a signal that uses faster-than-Nyquist signaling.
  • any element expressed as a means for performing a specified function is intended to encompass any way of performing that function including, for example, a) a combination of circuit elements that performs that function or b) software in any form, including, therefore, firmware, microcode or the like, combined with appropriate circuitry for executing that software to perform the function.
  • the present principles as defined by such claims reside in the fact that the functionalities provided by the various recited means are combined and brought together in the manner which the claims call for. It is thus regarded that any means that can provide those functionalities are equivalent to those shown herein.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Circuits Of Receivers In General (AREA)
  • Radio Relay Systems (AREA)
  • Error Detection And Correction (AREA)
PCT/US2010/001576 2009-05-29 2010-05-28 Method and apparatus for iterative timing recovery Ceased WO2010138204A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US13/138,923 US20120039380A1 (en) 2009-05-29 2010-05-28 Method and apparatus for iterative timing and carrier recovery
BRPI1011199A BRPI1011199A2 (pt) 2009-05-29 2010-05-28 método e equipamento para recuperação de sincronização iterativa
JP2012513059A JP2012528523A (ja) 2009-05-29 2010-05-28 反復タイミング再生に関する方法及び装置
CN2010800234822A CN102449949A (zh) 2009-05-29 2010-05-28 迭代定时恢复的方法和装置
EP10727521A EP2436138A1 (en) 2009-05-29 2010-05-28 Method and apparatus for iterative timing recovery

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US21733309P 2009-05-29 2009-05-29
US61/217,333 2009-05-29

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PCT/US2010/001576 Ceased WO2010138204A1 (en) 2009-05-29 2010-05-28 Method and apparatus for iterative timing recovery
PCT/US2010/001568 Ceased WO2010138198A1 (en) 2009-05-29 2010-05-28 Fast cycle slip detection and correction
PCT/US2010/001572 Ceased WO2010138201A2 (en) 2009-05-29 2010-05-28 Improved sync detection and frequency recovery for satellite systems
PCT/US2010/001577 Ceased WO2010138205A1 (en) 2009-05-29 2010-05-28 Improved feed-forward carrier recovery system and method
PCT/US2010/001578 Ceased WO2010138206A1 (en) 2009-05-29 2010-05-28 Method and apparatus for iterative timing and carrier phase recovery
PCT/US2010/001570 Ceased WO2010138199A2 (en) 2009-05-29 2010-05-28 Method and apparatus for symbol timing recovery

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PCT/US2010/001568 Ceased WO2010138198A1 (en) 2009-05-29 2010-05-28 Fast cycle slip detection and correction
PCT/US2010/001572 Ceased WO2010138201A2 (en) 2009-05-29 2010-05-28 Improved sync detection and frequency recovery for satellite systems
PCT/US2010/001577 Ceased WO2010138205A1 (en) 2009-05-29 2010-05-28 Improved feed-forward carrier recovery system and method
PCT/US2010/001578 Ceased WO2010138206A1 (en) 2009-05-29 2010-05-28 Method and apparatus for iterative timing and carrier phase recovery
PCT/US2010/001570 Ceased WO2010138199A2 (en) 2009-05-29 2010-05-28 Method and apparatus for symbol timing recovery

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US (5) US20120039380A1 (enExample)
EP (5) EP2436158B1 (enExample)
JP (5) JP2012528523A (enExample)
KR (2) KR20120028343A (enExample)
CN (5) CN102439928A (enExample)
BR (5) BRPI1011995A2 (enExample)
WO (6) WO2010138204A1 (enExample)

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