WO2010134276A1 - ゲート駆動回路 - Google Patents
ゲート駆動回路 Download PDFInfo
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- WO2010134276A1 WO2010134276A1 PCT/JP2010/003128 JP2010003128W WO2010134276A1 WO 2010134276 A1 WO2010134276 A1 WO 2010134276A1 JP 2010003128 W JP2010003128 W JP 2010003128W WO 2010134276 A1 WO2010134276 A1 WO 2010134276A1
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- bipolar transistor
- drive circuit
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- 230000000670 limiting effect Effects 0.000 claims abstract description 36
- 230000000694 effects Effects 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 230000000052 comparative effect Effects 0.000 description 14
- 230000007423 decrease Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/168—Modifications for eliminating interference voltages or currents in composite switches
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
- H03K17/163—Soft switching
Definitions
- the present invention relates to a gate drive circuit for driving a voltage-driven power semiconductor switching element.
- the conventional gate drive circuit is an IGBT (Insulated Gate Bipolar Transistor) switching circuit in which SiC diodes with a small recovery current are connected in parallel, reducing noise due to ringing while reducing element loss during turn-on and diode loss during recovery.
- IGBT Insulated Gate Bipolar Transistor
- the gate voltage and collector voltage of the IGBT are detected, and the gate drive voltage is varied in several steps based on the detected values (see, for example, Patent Document 1).
- the gate-emitter capacitance of the IGBT constituted by the capacitive component is charged with a constant voltage through the gate resistance when turned on. For this reason, the change of the gate voltage when exceeding the gate threshold voltage becomes steeper than the subsequent voltage change, and the change at the beginning of the collector current flow becomes steeper. As a result, the collector-emitter voltage, which decreases with the product of the change in collector current over time and the parasitic inductance, also changes sharply, resulting in large noise. Thus, it has been difficult to achieve both switching loss reduction and noise reduction by high-speed switching.
- the present invention has been made to solve the above-described problems, and is a gate that can realize low noise at turn-on while reducing switching loss due to high-speed switching of a power semiconductor switching element.
- a drive circuit is provided.
- the gate drive circuit according to the present invention is a gate drive circuit for driving a voltage-driven power semiconductor switching element, wherein the gate resistor has one end connected to the gate terminal of the power semiconductor switching element, and the gate terminal includes the gate.
- a DC voltage source for flowing a gate current through a resistor, a switch connected between the other end of the gate resistor and the DC voltage source, and controlling the turn-on of the power semiconductor switching element; and the gate current
- the current limiting circuit limits the gate current when the power semiconductor switching element is turned on by a predetermined upper limit value.
- the gate current at the turn-on time of the power semiconductor switching element is limited by the predetermined upper limit value, the change at the beginning of the collector current flow becomes gentle and the high frequency noise is reduced. Thereby, low noise can be realized in high-speed, low-loss switching of the power semiconductor switching element.
- FIG. 1A is a diagram showing a configuration of a gate drive circuit according to Embodiment 1 of the present invention
- FIG. 1B shows a basic form of a switching circuit using a power semiconductor switching element to which the gate drive circuit is applied.
- the structure of a half-bridge circuit is shown.
- the IGBT 1 made of Si semiconductor is used as the voltage-driven power semiconductor switching element driven by the gate drive circuit.
- the present invention is not limited to the IGBT 1, but other voltage-driven power semiconductor switching elements such as MOSFETs. But it ’s okay.
- a diode 2 is connected in reverse parallel to the IGBT 1.
- the half-bridge circuit 11 shown in FIG. 1B includes two combinations of the IGBT 1, the diode 2, and the gate drive circuit 10 and a DC voltage source 8, and illustrates the parasitic inductance Ls existing in the main circuit. ing.
- Such a half-bridge circuit 11 can be used for various power converters. For example, in the power conversion system shown in FIG. 2, after the AC power from the system power supply 13 is rectified by the rectifier circuit 14, the motor load 15 This constitutes one phase of the three-phase inverter circuit 12 that converts the AC power to be output to the AC power.
- the gate drive circuit 10 controls the gate resistors 3a and 3b, one end of which is connected to the gate terminal of the IGBT 1, the MOSFET 4a which is a switch for controlling the turn-on of the IGBT 1, and the turn-off of the IGBT 1.
- MOSFET 4b which is a switch for switching, a DC voltage source 5a for applying a positive gate bias voltage to the gate terminal, and a DC voltage source 5b for applying a negative gate bias voltage to the gate terminal.
- a control signal is output to the MOSFETs 4a and 4b and the current limiting circuit 6 based on a switching command signal input to the gate drive circuit 10, for example, a PWM signal, for limiting the gate current ig when the IGBT 1 is turned on.
- a control circuit 7 for performing the operation.
- MOSFET 4a and current limiting circuit 6 are connected in series between gate resistor 3a and DC voltage source 5a, and MOSFET 4b is connected in series between gate resistor 3b and DC voltage source 5b.
- the emitter terminal 1 a serving as the first main electrode of the IGBT 1 is connected to the reference potential terminal 9 of the gate drive circuit 10.
- the MOSFET 4a When the IGBT 1 is turned on in accordance with the PWM signal, the MOSFET 4a is turned on using the control signal from the control circuit 7 as an input signal, and the gate current ig limited by the current limiting circuit 6 is supplied from the DC voltage source 5a through the gate resistor 3a. Flows into the gate terminal of the IGBT 1 to charge the gate terminal, and further flows from the emitter terminal 1 a of the IGBT 1 to the ground of the gate drive circuit 10. When the IGBT 1 is turned off, the MOSFET 4b is turned on by a control signal from the control circuit 7, and the gate terminal of the IGBT 1 is discharged through the gate resistor 3b. In order to increase noise resistance of the IGBT 1, a negative gate bias voltage is applied to the gate terminal of the IGBT 1 by the DC voltage source 5b.
- the current limiting circuit 6 includes a first PNP bipolar transistor 20, a resistor 16 connected between the emitter and base of the first PNP bipolar transistor 20, and a diode 18 connected in reverse parallel. 2 PNP bipolar transistors 17 and a resistor 19.
- the emitter of the first PNP bipolar transistor 20 is connected to the DC voltage source 5 a, and the emitter, base, and collector of the second PNP bipolar transistor 17 are connected to the base of the first PNP bipolar transistor 20 and the resistor 16. This is connected to the collector of the first PNP bipolar transistor 20 and the gate resistor 3a (in this case, via the MOSFET 4a).
- a control signal (voltage signal) from the control circuit 7 is connected to the base of the second PNP bipolar transistor 17, and the current limiting circuit 6 limits the gate current ig at turn-on by a predetermined upper limit value.
- the predetermined upper limit value by the current limiting circuit 6 is a value obtained by dividing the base-emitter voltage of the first PNP bipolar transistor 20 by the resistor 16.
- the IGBT 1 When the IGBT 1 is turned on, when a control signal which is a low voltage signal is input from the control circuit 7 to the current limiting circuit 6, the base current of the second PNP bipolar transistor 17 flows through the resistor 19. As a result, the second PNP bipolar transistor 17 becomes conductive, and the gate current ig flowing to the gate terminal of the IGBT 1 flows through the resistor 16 and the second PNP bipolar transistor 17. When the gate current ig increases and the voltage drop across the resistor 16 exceeds the base-emitter voltage of the first PNP bipolar transistor 20, the first PNP bipolar transistor 20 becomes conductive. As a result, the base and emitter of the second PNP bipolar transistor 17 are short-circuited and the second PNP bipolar transistor 17 is cut off. Such an operation is repeated, and the gate current ig flowing through the current limiting circuit 6 is limited with an upper limit value obtained by dividing the base-emitter voltage of the first PNP bipolar transistor 20 by the resistor 16.
- FIG. 4 shows a turn-on switching waveform of the IGBT 1 using the gate drive circuit 10 according to this embodiment.
- FIG. 4A shows the gate voltage V GE which is the gate-emitter voltage
- FIG. 4B shows the gate current ig
- FIG. 4C shows the collector current ic which is the main current
- FIG. V CE is shown in FIG.
- the waveforms when the current limiting circuit 6 is not provided and the gate current ig is not limited (hereinafter referred to as comparative example 30) are indicated by broken lines 30a to 30d.
- the configuration other than the current limiting circuit 6 is the same as that of this embodiment.
- the switching operation in the comparative example 30 in which the gate current is not limited will be described below based on the waveforms of the gate voltage 30a, the gate current 30b, the collector current 30c, and the collector-emitter voltage 30d in FIG.
- a large gate current first flows and the gate voltage rises sharply.
- the gate voltage reaches the gate threshold voltage Vth at time t1
- the collector current starts to flow and the collector-emitter voltage starts to decrease.
- the gate voltage increases, the gate current decreases, and the gate voltage also increases gradually. Subsequently, the gate voltage becomes constant for a predetermined period due to the mirror effect.
- the change at the beginning of the collector current flow is steep, and the collector-emitter voltage, which decreases by the product of the change in the collector current with time and the parasitic inductance Ls, also changes steeply.
- the gate current value at this time is defined as a first gate current value I1.
- the moment when the IGBT 1 cannot hold the collector-emitter voltage overlaps with the peak of the recovery current of the diode 2 connected in reverse parallel to the IGBT 1, and the current value of the collector current also peaks.
- the gate current ig is limited by the current limit circuit 6 with a current limit value IL which is a predetermined upper limit value.
- the gate current ig is limited by the current limit value IL from the beginning of flow, and the gate current is a constant current of the current limit value IL. ig flows for a predetermined period.
- the gate voltage V GE increases in proportion to time. When the gate voltage V GE reaches the gate threshold voltage Vth at time T1, the collector current ic starts to flow and the collector-emitter voltage V CE starts to decrease.
- the collector current ic flowing through the IGBT 1 is determined by the gate voltage V GE and the transfer characteristic (gate voltage-collector current characteristic) shown in FIG. In this case, around the time T1, i.e., the change of the gate voltage V GE near the gate threshold voltage Vth, to become slower than Comparative Example 30, also becomes slow changes of the portion where the collector current ic starts flowing.
- the collector-emitter voltage V CE decreases with the product of the time change of the collector current ic and the parasitic inductance Ls . Changes slowly.
- FIG. 6 is a diagram illustrating a voltage waveform (solid line) using a trapezoidal wave and a voltage waveform (dotted line) that does not include a high frequency component.
- a voltage waveform composed of a trapezoidal wave in which the collector-emitter voltage rises in about 100 ns by switching of the IGBT and a voltage waveform composed only of a component of the trapezoidal wave of less than 10 MHz are shown.
- the rise of the voltage waveform for example, the waveform around the voltage of 300 V is hardly changed, but the difference between the rise start and the rise end is remarkable.
- the gate driving circuit 6 can achieve the above effect with a simple circuit configuration. For this reason, a faster switching operation becomes possible.
- the current change in the part where the collector current begins to flow (time t1, T1) is moderated so that the collector-emitter voltage is moderated. It can be changed.
- the change in the gate-emitter voltage in the vicinity of the peak of the collector current (time t2, T2) is larger than that in the comparative example 30 and the first embodiment.
- the noise component becomes steep, and the noise component in that portion increases, and the noise reduction effect as a whole cannot be obtained as in the first embodiment.
- the current limit value IL in the current limit circuit 6 is higher than the gate current value (second gate current value I2) in the mirror period 23 in which the mirror effect occurs at turn-on and is not limited by the current limit circuit 6 in the comparative example 30.
- the gate current value at which the collector current starts to flow (first gate current value I1) is set lower.
- the second gate current value I2 in the mirror period 23 is determined as follows. When the collector current of the IGBT 1 is determined, the gate voltage in the mirror periods 22 and 23 is determined by the transfer characteristics shown in FIG. A difference voltage between the DC voltage source 5a of the gate driving circuit 6 and the gate voltage during the mirror period is applied to the gate resistor 3a, and the gate current (second gate current value I2) in the mirror periods 22 and 23 is determined.
- the current limit value IL is higher than the first gate current value I1
- the change in the gate voltage when reaching the gate threshold voltage Vth is the same as in the comparative example 30, and the noise reduction effect cannot be obtained.
- the current limit value IL is lower than the second gate current value I2
- the switching time increases and the switching loss increases.
- the second gate current value I2 in the mirror periods 22 and 23 varies depending on the collector current, the second gate current value I2 at the collector current value at which high-frequency noise is desired to be reduced is set.
- the second gate current value I2 in the mirror period 23 may be determined as follows.
- the maximum value of the collector current flowing through the IGBT 1 determined by the specifications of the device using the IGBT 1 is Imax
- the gate voltage determined by the gate voltage-collector current characteristic (see FIG. 5) at that time is Vgem
- the voltage of the DC voltage source 5a When the value is Vcc and the resistance value of the resistor 3a is Rg, the gate current (second gate current value I2) in the mirror period 23 is (Vcc ⁇ Vgem) ⁇ Rg.
- the current limit value IL in the current limit circuit 6 is set higher than (Vcc ⁇ Vgem) ⁇ Rg and lower than the first gate current value I1.
- FIG. 7 a gate drive circuit 10a according to Embodiment 2 of the present invention will be described with reference to FIG.
- the current limiting circuit 6 is connected in series between the gate resistor 3a and the DC voltage source 5a.
- the current limiting circuit 6a is connected.
- the control signal from the control circuit 7 is inverted by the NOT circuit 24 and input to the current limiting circuit 6a.
- the portions other than the current limiting circuit 6a and the NOT circuit 24 are the same as those in the first embodiment.
- the gate current ig is supplied from the DC voltage source 5a to the MOSFET 4a, the gate resistor 3a, the gate terminal of the IGBT 1, the emitter terminal 1a of the IGBT 1, and the current limiting circuit 6a in order. And flows to the ground of the gate drive circuit 10a.
- the current limiting circuit 6a includes a first NPN bipolar transistor 20a, a resistor 16a connected between the emitter and base of the first NPN bipolar transistor 20a, and a diode 18a connected in reverse parallel. 2 NPN bipolar transistors 17a and a resistor 19a.
- the emitter of the first NPN bipolar transistor 20a is connected to the reference potential terminal 9 of the gate drive circuit 10a.
- the emitter, base and collector of the second NPN bipolar transistor 17a are connected to the base of the first NPN bipolar transistor 20a.
- the connection point to the resistor 16a, the collector of the first NPN bipolar transistor 20a, and the emitter terminal 1a of the IGBT 1 are connected to the connection point.
- the control signal (voltage signal) from the control circuit 7 is inverted by the NOT circuit 24 and connected to the base of the second NPN bipolar transistor 17a, and the current limiting circuit 6a sets the gate current ig at turn-on to a predetermined upper limit value.
- the current limit value IL is limited.
- the current limit value IL is a value obtained by dividing the base-emitter voltage of the first NPN bipolar transistor 20a by the resistor 16a.
- the current limit value IL in the current limit circuit 6a is higher than the gate current value (second gate current value I2) of the mirror period 23 in which the mirror effect occurs at the time of turn-on, and is limited by the current limit circuit 6a.
- second gate current value I2 the gate current value of the mirror period 23 in which the mirror effect occurs at the time of turn-on
- the same switching operation as in the first embodiment can be obtained, that is, the current change in the part where the collector current ic begins to flow is moderated and the collector-emitter voltage VCE is gradually changed.
- the high frequency noise component generated can be reduced, and the same effect as in the first embodiment can be obtained.
- the gate driving circuit of the power semiconductor switching element made of Si semiconductor has been shown.
- the power semiconductor switching element may be made of a non-Si semiconductor material having a wider band gap than the Si semiconductor. Good.
- the wide band gap semiconductor that is a non-Si semiconductor material include silicon carbide, a gallium nitride-based material, and diamond.
- Power semiconductor switching elements made of wide bandgap semiconductors can be used in high voltage regions where unipolar operation is difficult with Si semiconductors, greatly reducing switching losses that occur during switching, and greatly reducing power losses .
- the heat sink fins can be downsized and the water cooling unit can be air-cooled. Miniaturization is possible.
- a power semiconductor switching element made of a wide band gap semiconductor is suitable for a high frequency switching operation, and when applied to a DC / DC converter that requires a high frequency, the carrier frequency of the DC / DC converter operation is increased.
- a reactor, a capacitor, and the like connected to the DC / DC converter can be downsized.
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Abstract
Description
以下、この発明の実施の形態1によるゲート駆動回路を図に基づいて説明する。
図1(a)は、この発明の実施の形態1によるゲート駆動回路の構成を示す図であり、図1(b)は、ゲート駆動回路を適用した電力用半導体スイッチング素子によるスイッチング回路の基本形としてのハーフブリッジ回路の構成を示す。
ここでは、ゲート駆動回路が駆動する電圧駆動型の電力用半導体スイッチング素子としてSi半導体から成るIGBT1を用いているが、IGBT1に限るものではなく、MOSFETなど他の電圧駆動型の電力用半導体スイッチング素子でも良い。なお、IGBT1には、ダイオード2が逆並列に接続されている。
なお、IGBT1の第1の主電極となるエミッタ端子1aは、ゲート駆動回路10の基準電位端子9に接続される。
また、IGBT1をターンオフさせるときは、制御回路7からの制御信号によりMOSFET4bをオンさせ、ゲート抵抗3bを介してIGBT1のゲート端子を放電させる。IGBT1のノイズ耐性を上げるために、直流電圧源5bによってIGBT1のゲート端子に負のゲートバイアス電圧を与えている。
図に示すように、電流制限回路6は、第1のPNPバイポーラトランジスタ20と、第1のPNPバイポーラトランジスタ20のエミッタ・ベース間に接続された抵抗16と、ダイオード18が逆並列接続された第2のPNPバイポーラトランジスタ17と、抵抗19とを備える。そして、第1のPNPバイポーラトランジスタ20のエミッタは直流電圧源5aに接続され、第2のPNPバイポーラトランジスタ17のエミッタ、ベース、コレクタは、第1のPNPバイポーラトランジスタ20のベースと抵抗16との接続点、第1のPNPバイポーラトランジスタ20のコレクタ、ゲート抵抗3a(この場合、MOSFET4aを介して)にそれぞれ接続される。そして、制御回路7からの制御信号(電圧信号)が第2のPNPバイポーラトランジスタ17のベースに接続され、電流制限回路6はターンオン時のゲート電流igを所定の上限値で制限する。この電流制限回路6による所定の上限値は、この場合、第1のPNPバイポーラトランジスタ20のベース-エミッタ間電圧を抵抗16で割った値である。
ゲート電流igが増加し、抵抗16の電圧降下が第1のPNPバイポーラトランジスタ20のベース-エミッタ間電圧を超えると、第1のPNPバイポーラトランジスタ20は導通する。これにより、第2のPNPバイポーラトランジスタ17のベース-エミッタ間は短絡して第2のPNPバイポーラトランジスタ17は遮断される。このような動作を繰り返し、電流制限回路6を流れるゲート電流igは、第1のPNPバイポーラトランジスタ20のベース-エミッタ間電圧を抵抗16で割った値を上限値として制限される。
比較例30において、直流電圧源5aからゲート抵抗3aを介してIGBT1のゲート端子を充電するターンオン時には、最初に大きなゲート電流が流れてゲート電圧が急峻に上昇する。時刻t1において、ゲート電圧がゲート閾値電圧Vthに達すると、コレクタ電流が流れ始め、コレクタ-エミッタ間電圧が下降し始める。その後ゲート電圧の上昇と共にゲート電流が低下して行き、ゲート電圧の上昇も緩やかになる。続いてミラー効果により所定期間、ゲート電圧が一定となる。
直流電圧源5aからゲート抵抗3aを介してIGBT1のゲート端子を充電するターンオン時において、ゲート電流igは、流れ始めから電流制限値ILにて制限され、電流制限値ILの一定電流であるゲート電流igが所定期間流れる。ゲート電圧VGEは時間に比例して上昇し、時刻T1において、ゲート電圧VGEがゲート閾値電圧Vthに達すると、コレクタ電流icが流れ始め、コレクタ-エミッタ間電圧VCEが下降し始める。
IGBT1に流れるコレクタ電流icは、ゲート電圧VGEと、図5に示す伝達特性(ゲート電圧-コレクタ電流特性)から決まる。この場合、時刻T1付近、即ちゲート閾値電圧Vth付近のゲート電圧VGEの変化が、比較例30よりも緩やかになるため、コレクタ電流icが流れ始める部分の変化も緩やかになる。
図6は、台形波による電圧波形(実線)と高周波成分を含まない電圧波形(点線)とを示す図である。ここでは、IGBTのスイッチングにより、コレクタ-エミッタ間電圧が約100nsで立ち上がる台形波による電圧波形と、その台形波の10MHz未満の成分のみで構成された電圧波形を示す。電圧波形が立ち上がる途中、例えば電圧が300V付近の波形はほとんど変わらないが、立ち上がり始めと立ち上がり終わりの差が顕著である。このように、ノイズとなる高周波成分は、立ち上がり始めと立ち上がり終わりのような、波形が急に変化している部分に多く含まれる。また、台形波と10MHz未満の成分で構成された波形では、スイッチング損失はほぼ変わらない。このように立ち上がりや立下りの部分を緩やかにできれば、スイッチング損失はほぼ変わらずとも高周波のノイズを低減することができる事が判る。
なお、この場合、電圧が立ち上がる場合について示したが、数十MHz以上のノイズ成分は、電圧が上昇・下降し始める瞬間など、波形の時間変化が大きい部分に集中するものである。
また、コレクタ電圧やゲート電圧を監視してゲート電圧やゲート電流を切り替える必要が無く、ゲート駆動回路6は簡略な回路構成で、上記効果が達成できる。このため、より高速なスイッチング動作が可能になる。
電流制限値ILが、仮に第1のゲート電流値I1よりも高いと、ゲート閾値電圧Vthに達する時のゲート電圧の変化は、比較例30の場合と同様で、ノイズ低減効果が得られない。また、電流制限値ILが、仮に第2のゲート電流値I2よりも低いと、スイッチング時間が増大してスイッチング損失が大きくなる。ミラー期間22、23における第2のゲート電流値I2はコレクタ電流によって変化するが、高周波ノイズを低減したいコレクタ電流値での第2のゲート電流値I2を設定する。
次に、この発明の実施の形態2によるゲート駆動回路10aを図7に基づいて説明する。
上記実施の形態1では、電流制限回路6は、ゲート抵抗3aと直流電圧源5aとの間に直列に接続されたが、この実施の形態2では、図7に示すように、電流制限回路6aをIGBT1のエミッタ端子1aとゲート駆動回路10aの基準電位端子9との間に直列接続する。この場合、制御回路7からの制御信号はNOT回路24で反転されて電流制限回路6aに入力される。なお、電流制限回路6aおよびNOT回路24以外の部分は、上記実施の形態1と同様である。
この実施の形態では、ゲート駆動回路10aによりIGBT1をターンオンさせると、ゲート電流igは、直流電圧源5aからMOSFET4a、ゲート抵抗3a、IGBT1のゲート端子、IGBT1のエミッタ端子1a、電流制限回路6aを順に通ってゲート駆動回路10aのグランドに流れる。
図に示すように、電流制限回路6aは、第1のNPNバイポーラトランジスタ20aと、第1のNPNバイポーラトランジスタ20aのエミッタ・ベース間に接続された抵抗16aと、ダイオード18aが逆並列接続された第2のNPNバイポーラトランジスタ17aと、抵抗19aとを備える。そして、第1のNPNバイポーラトランジスタ20aのエミッタはゲート駆動回路10aの基準電位端子9に接続され、第2のNPNバイポーラトランジスタ17aのエミッタ、ベース、コレクタは、第1のNPNバイポーラトランジスタ20aのベースと抵抗16aとの接続点、第1のNPNバイポーラトランジスタ20aのコレクタ、IGBT1のエミッタ端子1aにそれぞれ接続される。
そして、制御回路7からの制御信号(電圧信号)がNOT回路24で反転されて第2のNPNバイポーラトランジスタ17aのベースに接続され、電流制限回路6aはターンオン時のゲート電流igを所定の上限値である電流制限値ILで制限する。この場合、電流制限値ILは、第1のNPNバイポーラトランジスタ20aのベース-エミッタ間電圧を抵抗16aで割った値である。
ワイドバンドギャップ半導体から成る電力用半導体スイッチング素子は、Si半導体ではユニポーラ動作が困難な高電圧領域で使用可能であり、スイッチング時に発生するスイッチング損失を大きく低減でき、電力損失の大きな低減が可能になる。また、電力損失が小さく、耐熱性も高いため、冷却部を備えてパワーモジュールを構成した場合、ヒートシンクの放熱フィンの小型化や、水冷部の空冷化が可能であるので、半導体モジュールの一層の小型化が可能になる。また、ワイドバンドギャップ半導体から成る電力用半導体スイッチング素子は、高周波スイッチング動作に適しており、高周波化の要求が大きいDC/DCコンバータに適用すると、DC/DCコンバータ動作のキャリア周波数の高周波化によって、DC/DCコンバータに接続されるリアクトルやコンデンサなどを小型化することもできる。
Claims (6)
- 電圧駆動型の電力用半導体スイッチング素子を駆動するゲート駆動回路において、
上記電力用半導体スイッチング素子のゲート端子に一端が接続されたゲート抵抗と、上記ゲート端子に上記ゲート抵抗を介してゲート電流を流し込むための直流電圧源と、上記ゲート抵抗の他端と上記直流電圧源との間に接続され、上記電力用半導体スイッチング素子のターンオンを制御するスイッチと、上記ゲート電流を制限する電流制限回路とを備え、
上記電流制限回路は、上記電力用半導体スイッチング素子のターンオン時の上記ゲート電流を所定の上限値で制限するものであるゲート駆動回路。 - 上記電流制限回路における上記所定の上限値は、上記電力用半導体スイッチング素子のターンオン時にミラー効果が生じる期間のゲート電流値より高く、該電流制限回路による制限がない場合のターンオン時に主電流が流れ始める時点のゲート電流値より低く設定されるものである請求項1に記載のゲート駆動回路。
- 上記電流制限回路は、
上記直流電圧源と上記ゲート抵抗との間に直列接続され、
上記直流電圧源がエミッタに接続された第1のPNPバイポーラトランジスタと、
該第1のPNPバイポーラトランジスタの上記エミッタとベースとの間に接続された抵抗と、
上記第1のPNPバイポーラトランジスタの上記ベースと上記抵抗との接続点がエミッタに、上記第1のPNPバイポーラトランジスタのコレクタがベースに、上記ゲート抵抗がコレクタにそれぞれ接続されると共に、上記スイッチへの制御信号に基づく電圧信号が該ベースに接続される第2のPNPバイポーラトランジスタとを備えるものである請求項1または2に記載のゲート駆動回路。 - 上記電流制限回路は、
上記電力用半導体スイッチング素子の第1の主電極と該ゲート駆動回路の基準電位端子との間に直列接続され、
上記基準電位端子がエミッタに接続された第1のNPNバイポーラトランジスタと、
該第1のNPNバイポーラトランジスタの上記エミッタとベースとの間に接続された抵抗と、
上記第1のNPNバイポーラトランジスタの上記ベースと上記抵抗との接続点がエミッタに、上記第1のNPNバイポーラトランジスタのコレクタがベースに、上記電力用半導体スイッチング素子の上記第1の主電極がコレクタにそれぞれ接続されると共に、上記スイッチへの制御信号に基づく電圧信号が該ベースに接続される第2のNPNバイポーラトランジスタとを備えるものである請求項1または2に記載のゲート駆動回路。 - 上記電力用半導体スイッチング素子は、シリコンよりもバンドギャップが広い非Si半導体材料から成るものである請求項1または2に記載のゲート駆動回路。
- 上記非Si半導体材料は、炭化珪素、窒化ガリウム系材料、又はダイヤモンドのいずれかである請求項5に記載のゲート駆動回路。
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US13/260,069 US8598920B2 (en) | 2009-05-19 | 2010-05-07 | Gate driving circuit |
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