WO2010099072A2 - Procédés de formation de circuits intégrés et structures résultantes - Google Patents

Procédés de formation de circuits intégrés et structures résultantes Download PDF

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WO2010099072A2
WO2010099072A2 PCT/US2010/024956 US2010024956W WO2010099072A2 WO 2010099072 A2 WO2010099072 A2 WO 2010099072A2 US 2010024956 W US2010024956 W US 2010024956W WO 2010099072 A2 WO2010099072 A2 WO 2010099072A2
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level
silicon
substrate
another
wafer
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PCT/US2010/024956
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WO2010099072A3 (fr
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Gurtej S. Sandhu
Krishna K. Parat
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Micron Technology, Inc.
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Priority to CN201080009005.0A priority Critical patent/CN102326230B/zh
Priority to KR1020117019648A priority patent/KR101372018B1/ko
Publication of WO2010099072A2 publication Critical patent/WO2010099072A2/fr
Publication of WO2010099072A3 publication Critical patent/WO2010099072A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/041—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00
    • H01L25/043—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Definitions

  • TECHNICAL FIELD relates generally to methods for fabricating integrated circuit devices, such as memory, logic or application specific integrated circuits (ASICs) without consuming an acceptor semiconductor substrate on which the integrated circuit devices are formed. More specifically, embodiments of the invention include integrated circuit fabrication methods in which semiconductor material is provided for fabrication of integrated circuits at one or more levels over an acceptor substrate having no circuitry thereon. In addition, embodiments of the present invention comprise multi-level integrated circuits.
  • 3D integrated circuit (IC) devices have been fabricated to improve chip density, by initially forming individual circuit devices and subsequently stacking and bonding the chips together to form a multi-level chip stack or assembly. Consequently, the time, materials and process acts expended in carrying out individual chip fabrication, forming an assembly and electrically connecting the chips results in undesirably high cost. Moreover, stacking and electrical connection of the individually fabricated chips may lead to increased resistance and signal delay in the overall circuit due to undesirably long signal paths. Further, transmission of signals through wiring of one layer of the assembly may electrically interfere with wiring on other layers, e.g., cross-talk.
  • bottom-up approach Another technique that has been suggested to increase chip density, for minimization of design dimension, is a so-called "bottom-up" approach.
  • circuits are fabricated conventionally on a base substrate, such as a silicon-on-insulator (SOI) wafer, followed by growth of successive layers of silicon on the wafer to provide an active surface and fabrication of additional circuit levels on each successive silicon layer prior to growth of the next-higher level. The process is repeated to create a device having a desired number of layers.
  • SOI silicon-on-insulator
  • this approach requires an excessive amount of time as a consequence of growing each new layer of silicon on the base substrate.
  • the foregoing approaches to multi-level circuit fabrication each require the use, and consumption, of a silicon wafer or other bulk substrate, which bulk substrate comprises a significant portion of the total cost of the fabrication process, on the order of twenty to thirty percent.
  • Embodiments of the present invention comprise methods of circuit fabrication on an acceptor substrate having no circuitry thereon.
  • One or more levels of circuitry may be respectively and sequentially formed on levels of foundation material severed from a donor substrate after bonding to the acceptor substrate.
  • the resulting integrated circuit, encapsulated in a passivation material is removed from the acceptor substrate.
  • a sacrificial material interposed between the circuitry and the acceptor substrate may be removed, as by etching with an etchant selective to the sacrificial material over the circuitry encapsulant and the acceptor substrate.
  • Embodiments of the invention comprise 3D integrated circuits, which may be singulated into individual semiconductor dice.
  • FIGS. IA through II comprise schematic representations of semiconductor structures formed during a process flow according to an embodiment of the present invention for fabrication of an integrated circuit;
  • FIG. 2 is a schematic side sectional illustration of a semiconductor die according to an embodiment of the invention
  • FIGS. 3 A-3C are partial, enlarged side cross-sectional representations of a multi-level circuit under fabrication in accordance with an embodiment of the present invention
  • FIG. 4 is a partial, enlarged side cross-sectional representation of the multi-level circuit of FIG. 3 C after performance of a spacer etch
  • FIG. 5 is a partial, enlarged side cross-sectional representation of another embodiment of a multi-level circuit under fabrication in accordance with an embodiment of the present invention.
  • the present invention comprises embodiments of methods of fabricating integrated circuit devices on an acceptor substrate without consumption thereof, as well as resulting integrated circuit devices, which may comprise multiple levels of integrated circuitry sequentially fabricated on superposed levels of semiconductor foundation material.
  • three-dimensional integrated circuit means and includes a plurality of integrated circuits arranged in planes or levels disposed vertically, one above another.
  • form and “forming” as used herein, encompass both disposition of a material as a final material or components thereof, and in situ formation of a material.
  • another as used herein, means and includes both a component or structure used a plurality of times, as well as an additional occurrence of fabrication of a type of component or structure.
  • a sacrificial material 102 is formed on base substrate, which may also be characterized as an acceptor substrate 100.
  • a passivation material 104 is then formed on sacrificial material 102, followed by another, dielectric material 106.
  • Acceptor substrate 100 may comprise, by way of non-limiting example, monocrystalline silicon, and may comprise a new wafer or a reject wafer on which defective semiconductor devices have been fabricated.
  • Acceptor substrate 100 may also comprise a substrate of another material, such as a ceramic, having a coefficient of thermal expansion (CTE) similar to that of a semiconductor material of a donor substrate to be bonded thereto as described below, to which sacrificial material 102 may bond, and highly resistant to an etchant for sacrificial material 102.
  • acceptor substrate 100 maybe of sufficient thickness and structural integrity to withstand mechanical stresses thereon without detectable deformation during handling and processing.
  • Sacrificial material 102 may comprise a material which may be etched selective to silicon such as, by way of example, a silicon oxide (SiO x , e.g., SiO or SiO 2 ), and may comprise a thickness of, for example, between about 2000 A and 2 ⁇ m.
  • Passivation material 104 may comprise, for example, silicon nitride (Si 3 N 4 ), and comprise a thickness of, for example, between about 1000 A and about 5000 A.
  • Dielectric material 106 may also comprise a silicon oxide (SiO x ) and comprise a thickness, for example, between about 2000 A and 2 ⁇ m.
  • the silicon oxide maybe formed, for example, by chemical vapor deposition (CVD), such as low pressure CVD or plasma enhanced CVD, spin-on deposition, thermal decomposition of tetraethyl orthosilicate (TEOS), or may be thermally grown.
  • CVD chemical vapor deposition
  • TEOS tetraethyl orthosilicate
  • the foundation semiconductor material may be placed on acceptor substrate 100 by a process described herein using a modification of so-called SMART-CUT® technology.
  • SMART-CUT® technology Such processes are described in detail in, for example, U.S. Patent No. RE 39,484 to Bruel, U.S. Patent No. 6,303,468 to Aspar et al., U.S. Patent No. 6,335,258 to Aspar et al., U.S. Patent No. 6,756,286 to Moriceau et al., U.S. Patent No. 6,809,044 to Aspar et al., U.S. Patent No. 6,946,365 to Aspar et al., and U.S. Patent Application Publication No. 2006/0099776 to Dupont.
  • acceptor substrate 100 may also be used, if sufficiently low processes temperatures are maintained.
  • donor and acceptor wafers are bonded together using a high temperature anneal, on the order of about 1000°C to about 1300°C.
  • Such temperatures are unacceptable for use when a substrate already bears circuitry fabricated thereon.
  • processing temperatures should not exceed about 800°C when flash memory is fabricated.
  • an additional plasma activation act may be integrated into a conventional SMART-CUT® technology fabrication process to lower a required substrate bonding temperature, as described in detail below.
  • a plurality of ions of rare gases e.g., neon, argon, krypton, or xenon
  • hydrogen, or helium may be implanted into the donor substrate 200 to form an implanted region 202.
  • a conventional ion source (not shown) may be used to implant the plurality of ions into the donor substrate 200 in a direction substantially perpendicular to a major surface 206 of the donor substrate 200 to create the implanted region 202, which may also be characterized as a transfer region, the inner boundary 208 of which is shown in the donor substrate 200 in broken lines.
  • the depth to which the ions are implanted into the donor substrate 200 is at least partially a function of the energy with which the ions are implanted. Generally, ions implanted with less energy will be implanted at relatively lesser depths, while ions implanted with higher energy will be implanted at relatively greater depths.
  • the inner boundary 208 of implanted region 202 lies substantially parallel to the major surface 206 of the donor substrate 200 and is at a preselected depth which is dependent on selected parameters of the atomic species implant process, as is well known to one of ordinary skill in the art.
  • hydrogen ions may be implanted into the donor substrate with an energy selected to form the inner boundary 208 at a depth D of between about eighty nanometers (80 nm) and about five hundred nanometers (500 nm) (about 800 A to about 5000 A), and more particularly, of about two hundred nanometers (200 nm) (about 2000 A) within the donor substrate 200.
  • the inner boundary 208 of implanted region 202 comprises a layer of microbubbles or microcavities (not shown) comprising the implanted ion species, and provides a weakened structure within donor substrate 200.
  • the donor substrate 200 may then be thermally treated at a temperature above that at which ion implantation is effected, in accordance with the disclosures of the patent documents in the preceding paragraph, to effect crystalline rearrangement in the semiconductor material of the donor substrate 200 and coalescence of the microbubbles or microcavities.
  • An attachment surface 210 to be bonded to dielectric material 106 on acceptor substrate 100 may be formed on donor substrate 200 by exposing the major surface 206 of the donor substrate 200 to a reactive ion etching (RIE) plasma including hydrogen or an inert gas (e.g., argon, oxygen, or nitrogen) to form a plasma-activated major surface 206'.
  • RIE reactive ion etching
  • the plasma-activated major surface 206' increases the kinetics of a subsequent bonding act in the form of an oxide reaction with an adjacent surface of the dielectric material 106 overlying the acceptor substrate 100 due to the increased mobility and reactivity of the ionic species (e.g., hydrogen) created on attachment surface 210.
  • the wafer bonding process may be performed at temperatures of less than about four hundred degrees Celsius (400 0 C).
  • Plasma-activated bonding is described in U.S. Patent 6,180,496 to Farrens et al., assigned to Silicon Genesis Corporation.
  • the donor substrate 200 is disposed on the dielectric material 106 carried by acceptor substrate 100 and maybe bonded to the dielectric material 106 using an annealing process.
  • the plasma-activated major surface 206' enables annealing at a substantially reduced temperature, as noted above, in comparison to those employed in conventional wafer bonding techniques.
  • the hydrogen or other ions implanted in ion implanted region 202 to the depth of inner boundary 208 makes the silicon in the thermally treated donor substrate 200 susceptible to breakage substantially along inner boundary 208 when a shear force is applied substantially parallel to the major plane of the donor substrate 200.
  • the portion of the donor substrate 200 on the side of the inner boundary 208 opposing the dielectric material 106 may be cleaved or fractured by applying a shearing force to the donor substrate 200.
  • the portion of the donor substrate 200 below the inner boundary 208 of a thickness, for example, of between about eighty nanometers (80 nm) (about 800 A) and about four hundred nanometers (400 nm) (about 4000 A), for example, about two hundred nanometers (200 nm) (about 2000 A), is detached from the remainder of donor substrate 200 and remains bonded to the acceptor substrate 100 through dielectric material 106, passivation material 104 and sacrificial material 102 to form a foundation material 212, as shown in FIG. ID.
  • Donor substrate 200 may then have its new major surface 206n, which is substantially at the location of former inner boundary 208 of implanted region 202, smoothed as desired, ion-implanted and plasma-activated in preparation for transfer of another thickness of semiconductor material for use as a foundation material 212. It is contemplated that each donor substrate 200, if comprising a silicon wafer of conventional initial thickness, may be used to donate foundation material 212 at least about ten times, if about a 2000 A thickness of silicon is transferred each time a layer of silicon is donated.
  • an exposed surface 214 of the foundation material 212 may be undesirably rough for fabrication of integrated circuitry thereon.
  • the exposed surface 214 of the foundation material 212 may be smoothed to a desired degree in order to facilitate further processing as described below, according to techniques known in the art such as, for example, one or more of grinding, wet etching, and chemical-mechanical polishing (CMP).
  • CMP chemical-mechanical polishing
  • the foundation material 212 may be used as a substrate on which to form a level of circuitry 216, as depicted in broken lines, which may, for example, include a plurality of memory devices such as two-dimensional arrays of NAND flash memory, in accordance with processes known to those of ordinary skill in the art. It is contemplated, however that, as previously mentioned, logic or ASIC circuitry may also be fabricated. In any case, conventional circuitry fabrication techniques may be employed to fabricate integrated circuitry on foundation material 212 in the same manner as employed on a conventional semiconductor substrate such as, for example, a monocrystalline silicon wafer.
  • an oxide material 218 (SiO x ) is formed or disposed thereover, as by a spin-on-glass technique, a chemical vapor deposition (CVD) technique, such as low pressure CVD or plasma-enhanced CVD, or a spin-on deposition technique.
  • a donor substrate 200 (not shown) (which may comprise the same or another donor substrate 200) which has been ion-implanted, annealed and plasma-treated to enhance bonding is then disposed over and bonded to oxide material 218, and sheared to leave another foundation material 212' bonded to oxide material 218.
  • Another level of circuitry 216' may then be formed over foundation material 212'.
  • Inter-level signal paths may be formed by techniques known to those of ordinary skill in the art, to each level of circuitry 216 through the underlying foundation material 212 and oxide material 218 of the next subsequent level.
  • the number of circuitry levels 216 which may be formed is largely dictated by the number and complexity of required inter-level signal paths.
  • a 3D circuit comprising three circuit levels 216, 216' and 216" maybe respectively fabricated on three levels of foundation material 212, 212' and 212", although such number of circuit levels is not limiting of the scope of the invention.
  • FIG. IG depicts three such circuit levels 216, 216' and 216".
  • the circuitry of 3D integrated circuit structure 300 may then be probe tested in a conventional manner from the top thereof and, as also depicted in FIG. 1 G in broken lines, silicon nitride 222 is formed over all of the circuit levels 216, 216' and 216" and the lateral peripheries thereof, to contact with passivation material 104 which, as noted above, also comprises silicon nitride.
  • passivation material 104 which, as noted above, also comprises silicon nitride.
  • the entire 3D integrated circuit structure 300 is encapsulated on its top, bottom and sides in silicon nitride passivation material 104 and silicon nitride 222.
  • a carrier substrate 400 may then be bonded to the 3D integrated circuit structure 300 opposite acceptor substrate 100. Such bonding may comprise adhesive bonding, and carrier substrate 400 may comprise, for example, a glass, silicon or a ceramic. It may be desirable to employ a material for carrier substrate 400, which is transparent to ultraviolet (UV) radiation, for reasons noted below.
  • acceptor substrate 100 may then be removed from 3D integrated circuit structure 300 by a wet chemical etch which is highly selective to silicon oxide over both the silicon of acceptor substrate 100 and silicon nitride passivation material 104 and silicon nitride 222, which encapsulates the levels of circuitry 216, 216' and 216".
  • the wet chemical etch may include, but is not limited to a hydrofluoric acid (HF)-based etchant, such as an etchant including water, HF, and ammonium fluoride or water, HF, ammonium fluoride, and isopropyl alcohol.
  • HF hydrofluoric acid
  • the acceptor substrate 100 may then be reused by formation of another sacrificial material 102 thereon, followed by another passivation material 104 and a dielectric material 106 (FIG. IA). Consequently, the acceptor substrate 100 maybe employed a large number of times, as little, if any, of the substrate material is consumed during each fabrication sequence.
  • the 3D integrated circuit structure 300 with optional carrier substrate 400 bonded thereto may then be inverted, as depicted in FIG. 11, individual, multi-level semiconductor dice 500 (FIG. 2) singulated therefrom as known in the art, and removed from carrier substrate 400 in a conventional pick-and-place sequence.
  • a UV-transparent material for carrier substrate 400 may be employed, enabling the use of an adhesive which is UV-sensitive and of the type conventionally employed to adhere a semiconductor wafer to a film for singulation to be used to bond carrier substrate 400 to 3D integrated circuit structure 300.
  • singulation may be effected using a conventional wafer saw and the UV-sensitive adhesive then exposed through the carrier substrate 400 to permit release of the singulated semiconductor dice 500 therefrom.
  • Semiconductor dice 500 to the extent circuit levels 216, 216' and 216" are not internally connected, maybe mutually electrically interconnected and connected to a permanent carrier substrate through edge-connect techniques well-known to those of ordinary skill in the art using conductive contacts 502 at one or more circuit levels exposed at their lateral peripheries by the singulation process.
  • conductive traces may be formed across streets between locations of individual semiconductor dice, to be severed during singulation and expose ends thereof.
  • Electrical connections may also be established between 3D integrated circuit structure 300 and an end-product or intermediate product carrier substrate such as a card or board bearing circuitry and, optionally, other semiconductor dice and other components thereon, through conductive vias on the bottom of the 3D integrated circuit structure 300 formed during circuit fabrication.
  • the vias may be exposed by masking and etching the overlying silicon nitride while 3D integrated circuit structure 300 is still secured to carrier substrate 400, a redistribution layer of circuit traces formed and discrete conductive elements (e.g., solder bumps, or conductive or conductor-filled polymer bumps, columns, studs, etc.) formed or disposed on terminal pads of the circuit traces.
  • discrete conductive elements e.g., solder bumps, or conductive or conductor-filled polymer bumps, columns, studs, etc.
  • lowermost foundation material 212 maybe set back from the periphery of acceptor substrate 100, while each of the levels of foundation material 212, 212' and 212" maybe peripherally coextensive.
  • each foundation material 212, 212' and 212" may comprise a periphery that is set back from the next lower foundation material, and the lowermost foundation material 212 set back from the periphery of acceptor substrate 100, as depicted in FIG. 5.
  • Either such architecture may be achieved by selectively treating the major surface 206 of a donor substrate 200 so that ion implantation is not effected to the outer lateral periphery thereof.
  • ion implantation is effected only within a selected boundary inward of the outer lateral periphery of a donor substrate 200.
  • acceptor substrate 100 having sacrificial material 102, passivation material 104 and dielectric material 106 disposed thereon is located in proximity to a donor substrate 200 which has been ion-implanted in a region of major surface 206 interior of the periphery.
  • donor wafer 200 is bonded by an anneal to dielectric material 106, a strong bond therebetween is formed only in the region of ion implantation.
  • donor substrate 200 is sheared to release a foundation material 212, as depicted in FIG.
  • the unimplanted peripheral region of donor substrate 200 adjacent to acceptor substrate 100 remains attached to donor wafer 200.
  • the dielectric layer 106 may, if desired, optionally be formed inwardly of the periphery of acceptor substrate 100 as shown in FIG. 3 A, by masking and etching dielectric layer 106 after formation of passivation layer 104.
  • a periphery of donor substrate 200 may be slightly beveled, as shown in broken lines in FIG. 3 A, to a depth less than that to which ions are implanted. Such beveling may be effected when major surface 206 of donor substrate 200 may be smoothed, as by polishing, prior to ion implantation after a transfer region thereof has been bonded to a acceptor substrate 100 or a prior foundation material 212.
  • the lowermost foundation material 212 may be set back from passivation layer 104 on acceptor substrate 100 to form a ledge 220. Then, as illustrated, each subsequent foundation material 212' and 212" is then sized and aligned over foundation material 212 to be peripherally coextensive therewith.
  • Silicon nitride 222 is then formed by, for example, CVD or atomic layer deposition (ALD) over the structure, covering the upper surface of foundation material 212" and, optionally, an oxide material 218 thereover, as well as the lateral periphery of the multi-level structure, extending down the vertical side of 3D integrated circuit structure 300 along the sides of foundation materials212, 212' and 212", to and over ledge 220 and in contact with passivation material 104.
  • Peripheral, exposed dielectric material 106 outside of the footprint of the stacked foundation materials 212, 212' and 212" may be removed using a spacer etch prior to deposition of silicon nitride 222. As depicted in FIG. 4, an optional spacer etch of the silicon nitride 222 maybe performed to expose a peripheral portion of passivation material 104.
  • each of the levels of foundation material 212, 212' and 212" maybe stepped back from the next lowermost foundation material 212, as depicted in FIG. 5, with silicon nitride 222 covering the sides of foundation materials 212, 212' and 212" of 3D integrated circuit structure 300 and extending over intervening ledges 220 to and over silicon nitride passivation material 104.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention porte sur des procédés de fabrication de dispositifs à circuit intégré sur un substrat accepteur dépourvu de circuiterie. Des dispositifs à circuit intégré sont formés par agencement séquentiel d'un ou plusieurs niveaux de matériau semi-conducteur sur un substrat accepteur, et fabrication de circuiterie sur chaque niveau de matériau semi-conducteur avant l'agencement d'un niveau supérieur suivant. Après l'encapsulation de la circuiterie, le substrat accepteur est retiré et des dés de semi-conducteur sont séparés. L'invention porte également sur des dispositifs à circuit intégré formés par les procédés.
PCT/US2010/024956 2009-02-25 2010-02-22 Procédés de formation de circuits intégrés et structures résultantes WO2010099072A2 (fr)

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CN102326230B (zh) 2014-07-16
US8816489B2 (en) 2014-08-26
TW201041092A (en) 2010-11-16
US20140203409A1 (en) 2014-07-24
TWI419260B (zh) 2013-12-11
US20100213578A1 (en) 2010-08-26
KR101372018B1 (ko) 2014-03-14
CN102326230A (zh) 2012-01-18
US20120223409A1 (en) 2012-09-06
KR20110110352A (ko) 2011-10-06
US8198172B2 (en) 2012-06-12
WO2010099072A3 (fr) 2011-02-17

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