CN115376931A - 三维系统单芯片的制造方法及三维系统单芯片 - Google Patents
三维系统单芯片的制造方法及三维系统单芯片 Download PDFInfo
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- CN115376931A CN115376931A CN202210468030.XA CN202210468030A CN115376931A CN 115376931 A CN115376931 A CN 115376931A CN 202210468030 A CN202210468030 A CN 202210468030A CN 115376931 A CN115376931 A CN 115376931A
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Abstract
一种三维系统单芯片的制造方法,包括提供存储器晶圆结构,具有第一重布线层;设置第一导电结构以及具有第二导电结构的核心晶粒结构及输入/输出晶粒结构于第一重布线层,输入/输出晶粒结构设置于核心晶粒结构的周边;形成介电层包覆核心晶粒结构、输入/输出晶粒结构以及第一导电结构;移除部分介电层且薄化核心晶粒结构及多个输入/输出晶粒结构,以显露第一、第二导电结构;形成第三重布线层于介电层上,且与第一、第二导电结构电性连接;形成多个焊球于该第三重布线层;进行切单。一种三维系统单芯片亦被提供。
Description
技术领域
本发明涉及一种半导体结构的制造方法,尤其涉及一种三维(3D)系统单芯片(system-on-chip;SoC)的制造方法及三维系统单芯片。
背景技术
随着电子产业的蓬勃发展,电子产品逐渐进入多功能、高性能的研发方向,其中半导体 科技已广泛地应用于制造存储器、中央处理单元等芯片组。为了达成高集成度(Integration)与 高速度等目的,半导体集成电路的尺寸持续地缩减,目前已发展出多种不同的材料与技术以 达成上述的集成度与速度要求。
一般来说,在集成电路(integrated circuit;IC)芯片中可设计并嵌入多个装置/元件(例如, 晶体管、二极管等),接着将该芯片置于封装件(例如,塑胶壳)中或用作裸芯片以置于电子装 置的印刷电路板(printed circuit board;PCB)上。除晶体管级的传统技术节点微缩以外,正越 来越多地利用三维(three-dimensional;3D)IC芯片堆叠以继续使用当前的半导体制造技术来创 建三维系统单芯片(3D SoC)装置并为满足各种电子装置的性能、功率及频宽要求提供解决方 案。3D SoC装置可包括不同技术节点的数个逻辑、存储器、类比或其它芯片,而如何将逻辑、 存储器、类比等芯片堆叠以构成3维系统单芯片,成为当前相关领域极需研究的目标。
发明内容
本发明提供了一种3D SoC的制造方法及3D SoC,使3D SoC可满足高集成度与速度要 求,而具有更佳的电气特性及效率。
本发明所提供的三维系统单芯片的制造方法包括:提供存储器晶圆结构,包括晶圆、第 一主动层及第一重布线层,第一主动层形成于晶圆,第一重布线层形成于第一主动层;设置 多个第一导电结构、核心晶粒结构、及多个输入/输出晶粒结构于第一重布线层,其中输入/ 输出晶粒结构设置于核心晶粒结构的周边,其中,每一核心晶粒结构及每一输入/输出晶粒结 构包括半导体基板、停止层结构、第二主动层、多个第二导电结构及第二重布线层,半导体 基板具有相对的主动面及背面,停止层结构形成于半导体基板内,将半导体基板分为基板第 一部分及基板第二部分,其中基板第一部分位于停止层结构及主动面之间,基板第二部分位 于停止层结构及背面之间,第二主动层形成于主动面,第二导电结构形成于基板第一部分以 连接第二主动层及停止层结构,第二重布线层形成于第二主动层,每一核心晶粒结构的第二 重布线层及每一输入/输出晶粒结构的第二重布线层接合于第一重布线层;进行背面研磨制 程,自半导体基板的背面进行研磨,以移除基板第二部分的一部分;进行介电填充制程,以 形成介电层包复核心晶粒结构、输入/输出晶粒结构、以及第一导电结构;进行薄化制程,移 除部分的介电层、剩余的基板第二部分及部分的停止层结构,以显露第一导电结构及第二导 电结构;形成第三重布线层于介电层上,且第三重布线层与显露的第一导电结构及第二导电 结构电性连接;形成多个焊球于第三重布线层;以及进行切单。
本发明所提供的三维系统单芯片的制造方法包括:提供多个存储器晶粒,每一存储器晶 粒包括晶粒基板、第一主动层及第一重布线层,第一主动层形成于晶粒基板,第一重布线层 形成于第一主动层;提供SoC晶圆结构,分隔成独立的核心晶粒区及多个输入/输出晶粒区, 输入/输出晶粒区设置于核心晶粒区的周边,SoC晶圆结构包括半导体晶圆、停止层结构、第 二主动层、多个导电结构及第二重布线层,半导体晶圆具有相对的主动面及背面,停止层结 构形成于半导体晶圆内,将半导体晶圆分为晶圆第一部分及晶圆第二部分,其中晶圆第一部 分位于停止层结构及主动面之间,晶圆第二部分位于停止层结构及背面之间,第二主动层形 成于主动面,导电结构形成于晶圆第一部分以连接第二主动层及停止层结构,第二重布线层 形成于第二主动层;将每一存储器晶粒的第一重布线层接合至SoC晶圆结构的核心晶粒区的 第二重布线层;进行介电填充制程,以形成介电层包覆存储器晶粒;进行背面研磨制程,自 半导体晶圆的背面进行研磨,以移除晶圆第二部分的一部分;进行薄化制程,移除剩余的晶 圆第二部分及部分的停止层结构,以显露导电结构;形成第三重布线层于残留的部分停止层 结构,且第三重布线层与显露的导电结构电性连接;形成多个焊球于第三重布线层;以及进 行切单。
本发明所提供的三维系统单芯片的制造方法包括:提供存储器晶圆结构,包括晶圆、第 一主动层及第一重布线层,第一主动层形成于晶圆,第一重布线层形成于第一主动层;提供 SoC晶圆结构,分隔成独立的核心晶粒区、及多个输入/输出晶粒区,输入/输出晶粒区设置于 核心晶粒区的周边,SoC晶圆结构包括半导体晶圆、停止层结构、第二主动层、多个导电结 构及第二重布线层,半导体晶圆具有相对的主动面及背面,停止层结构形成于半导体晶圆内, 将半导体晶圆分为晶圆第一部分及晶圆第二部分,其中晶圆第一部分位于停止层结构及主动 面之间,晶圆第二部分位于停止层结构及背面之间,第二主动层形成于主动面,导电结构形 成于晶圆第一部分以连接第二主动层及停止层结构,第二重布线层形成于第二主动层;将存 储器晶圆结构的第一重布线层接合至SoC晶圆结构的第二重布线层;进行背面研磨制程,自 半导体晶圆的背面进行研磨,以移除晶圆第二部分的一部分;进行薄化制程,移除剩余的晶 圆第二部分及部分的停止层结构,以显露导电结构;形成第三重布线层于晶圆第一部分,且 第三重布线层与显露的导电结构电性连接;形成焊球于第三重布线层;以及进行切单。
在本发明的一实施例中,上述的停止层结构包括相互堆叠的第一停止层及第二停止层, 第一停止层的材料不同于第二停止层的材料,第二停止层介于第一停止层及第二主动层之间, 在进行薄化制程中,移除部分的停止层结构的步骤包括先移除第一停止层,再移除部分第二 停止层。
在本发明的一实施例中,上述的第一停止层为氮化硅层,该第二停止层为二氧化硅层。
在本发明的一实施例中,上述的氮化硅层及二氧化硅层的形成步骤包括先于半导体基板 (半导体晶圆)的第一深度进行氮离子注入制程,再于半导体基板(半导体晶圆)的第二深度进行 氧离子注入制程,且第二深度小于第一深度,接着进行高温处理制程,使氮离子注入的区域 形成氮化硅层,氧离子注入的区域形成二氧化硅层。
在本发明的一实施例中,上述的氮化硅层及二氧化硅层的移除方法选自化学机械抛光及 等离子干式蚀刻其中的一种,其中氮化硅及二氧化硅的选择比介于10至20之间,二氧化硅 及硅的选择比约为5。
在本发明的一实施例中,上述的薄化制程包括:第一去除步骤,移除部分的介电层及剩 余的基板第二部分(晶圆第二部分);以及第二去除步骤,移除部分的停止层结构,以显露第 二导电结构(导电结构)。
在本发明的一实施例中,上述的第一去除步骤选自化学机械抛光、湿式蚀刻及等离子干 式蚀刻其中的一种,第二去除步骤选自化学机械抛光及等离子干式蚀刻其中的一种。
在本发明的一实施例中,上述的第二重布线层以混合键合技术接合于第一重布线层。
本发明所提供的三维系统单芯片包括存储器芯片结构、多个第一导电结构、核心晶粒、 多个输入/输出晶粒、介电层、第三重布线层及多个焊球。存储器芯片结构包括半导体基板、 第一主动层及第一重布线层,第一主动层形成于半导体基板,第一重布线层形成于第一主动 层;第一导电结构、核心晶粒及输入/输出晶粒设置于第一重布线层,其中输入/输出晶粒设置 于核心晶粒的周边,其中,核心晶粒及输入/输出晶粒包括基板、停止层结构、第二主动层、 多个第二导电结构及第二重布线层,第二主动层及停止层结构分别设置于基板的相对两侧, 第二导电结构形成于基板,每一第二导电结构的一端连接于第二主动层,每一第二导电结构 的另一端穿透且显露于停止层结构,第二重布线层形成于第二主动层,核心晶粒区的第二重 布线层及输入/输出晶粒区的第二重布线层接合于第一重布线层;介电层填充于核心晶粒、输 入/输出晶粒、以及第一导电结构之间,且显露停止层结构及第一导电结构的一端;第三重布 线层形成于介电层,且第三重布线层与显露的第一导电结构及显露的第二导电结构电性连接; 焊球形成于第三重布线层。
本发明所提供的三维系统单芯片包括多个存储器晶粒、介电层、SoC芯片、第三重布线 层及焊球。每一存储器晶粒包括晶粒基板、第一主动层及第一重布线层,第一主动层形成于 晶粒基板,第一重布线层形成于第一主动层;介电层包覆存储器晶粒,且显露每一存储器晶 粒的第一重布线层;SoC芯片分隔成独立的核心晶粒及多个输入/输出晶粒,输入/输出晶粒设 置于核心晶粒的周边,SoC芯片包括基板、停止层结构、第二主动层、多个导电结构及第二 重布线层,第二主动层及停止层结构分别设置于基板相对两侧,导电结构形成于基板,每一 导电结构的一端连接于第二主动层,每一导电结构的另一端穿透且显露于停止层结构,第二 重布线层形成于第二主动层,每一存储器晶粒的第一重布线层接合至核心晶粒的第二重布线 层;第三重布线层形成于停止层结构,且第三重布线层与显露的导电结构电性连接;焊球形 成于第三重布线层。
本发明所提供的三维系统单芯片包括存储器芯片结构、SoC芯片、第三重布线层及焊球。 存储器芯片结构包括半导体基板、第一主动层及第一重布线层,第一主动层形成于半导体基 板,第一重布线层形成于第一主动层;SoC芯片分隔成独立的核心晶粒及多个输入/输出晶粒, 输入/输出晶粒设置于核心晶粒的周边,SoC芯片包括基板、停止层结构、第二主动层、多个 导电结构及第二重布线层,第二主动层及停止层结构分别设置于基板的相对两侧,导电结构 形成于基板,每一导电结构的一端连接于第二主动层,每一导电结构的另一端穿透且显露于 停止层结构,第二重布线层形成于第二主动层,每一存储器晶粒的第一重布线层接合至核心 晶粒的第二重布线层;第三重布线层形成于停止层结构,且第三重布线层与显露的导电结构 电性连接;焊球形成于第三重布线层。
本发明三维系统单芯片中,存储器芯片可被接合至由介电层所包覆的核心晶粒及多个输 入/输出晶粒,或者SoC芯片可被接合至由介电层所包覆多个存储器晶粒,或者存储器芯片及 SoC芯片相互接合。其中核心晶粒、输入/输出晶粒、或者是SoC芯片,借由其中停止层结构 的设置,皆可薄化而具有非常薄的厚度,如此使得三维系统单芯片的整体厚度大幅减少,可 满足高集成度与速度要求,而具有更佳的电气特性及效率。
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,而可依 照说明书的内容予以实施,并且为了让本发明的上述和其他目的、特征和优点能够更明显易 懂,以下特举较佳实施例,并配合附图,详细说明如下。
附图说明
图1A至图1I所示是本发明第一实施例三维系统单芯片的制造方法的剖面示意图。
图2是本发明第一实施例三维系统单芯片的剖面结构示意图。
图3是本发明实施例三维系统单芯片的仰视示意图。
图4A至图4H所示是本发明第二实施例三维系统单芯片的制造方法的剖面示意图。
图5是本发明第二实施例三维系统单芯片的剖面结构示意图。
图6是本发明第二实施例三维系统单芯片的仰视示意图。
图7A至图7E是所示本发明第三实施例三维系统单芯片的制造方法的剖面示意图。
图8是本发明第三实施例三维系统单芯片的剖面结构示意图。
具体实施方式
图1A至图1I所示是本发明第一实施例三维系统单芯片的制造方法的剖面示意图。如图 1A所示,提供存储器晶圆结构10,包括晶圆12、第一主动层14及第一重布线层16,第一主动层14形成于晶圆12上,第一重布线层16形成于第一主动层14上。于一实施例中,晶 圆12例如为硅晶圆、磊晶硅晶圆、硅锗晶圆、碳化硅晶圆;第一主动层14上例如形成有晶 体管元件等存储器的基本元件;第一重布线层16上例如形成有金属布线、金属柱(VIA)及微 凸块。
如图1B所示,设置多个第一导电结构18于第一重布线层16上,第一导电结构18例如 为导电柱;如图1C所示,设置核心晶粒结构20及多个输入/输出晶粒结构22于第一重布线 层16,其中输入/输出晶粒结构22设置于核心晶粒结构20的周边,第一导电结构18介于输 入/输出晶粒结构22及核心晶粒结构20之间。每一核心晶粒结构20及每一输入/输出晶粒结 构22的结构及配置大致相同,两者的差异主要在于核心晶粒结构20及输入/输出晶粒结构22 中主动层内的不同电气元件配置,因此底下以相同的元件符号标示核心晶粒结构20及输入/ 输出晶粒结构22中对应或相同的结构。
请继续参阅图1C所示,核心晶粒结构20及输入/输出晶粒结构22包括半导体基板24、 停止层结构26、第二主动层28、多个第二导电结构30及第二重布线层32,半导体基板24具有相对的主动面241及背面242,停止层结构26形成于半导体基板24内,将半导体基板 24分为基板第一部分243及基板第二部分244,其中,将停止层结构26至主动面241之间的 半导体基板24称为基板第一部分243,将停止层结构26至背面242之间的半导体基板24称 为基板第二部分244,因此基板第一部分243位于停止层结构26及主动面241之间,基板第 二部分244位于停止层结构26及背面242之间。又第二主动层28形成于主动面241,于一 实施例中,第二主动层28上例如形成有金属氧化物半导体(MOS)等电气元件。多个第二导电 结构30形成于基板第一部分243以连接第二主动层28及停止层结构26,于一实施例中,第 二导电结构30例如为导电柱。第二重布线层32形成于第二主动层28,第二重布线层32上 例如形成有金属布线、金属柱(VIA)及微凸块。如图1C所示,于一实施例中,核心晶粒结构 20的第二重布线层32及输入/输出晶粒结构22的第二重布线层32以混合键合技术接合于第 一重布线层16。
于一实施例中,停止层结构26包括相互堆叠的第一停止层261及第二停止层262,第一 停止层261的材料不同于第二停止层262的材料,第二停止层262介于第一停止层261及第 二主动层28之间,其中第一停止层261例如为氮化硅(Si3N4)层,第二停止层262例如为二氧 化硅(SiO2)层。停止层结构26的制造包括进行离子注入制程及高温处理制程,其中,离子注 入制程包括先在半导体基板24的距离主动面241的第一深度D1进行氮离子注入制程,再于 半导体基板24的距离主动面241的第二深度D2进行氧离子注入制程,氧离子注入区的第二 深度D2较氮离子注入区的第一深度D1小,亦即氧离子注入区较为靠近主动面241。之后进 行高温处理,在氮离子注入区形成氮化硅层(即第一停止层261),在氧离子注入区形成二氧化 硅层(即第二停止层262),其中,第二停止层262较为邻近主动面241,第一停止层261较为 邻近背面242。
如图1D所示,进行背面研磨(Grind)制程,自半导体基板24的背面242进行研磨,以移 除基板第二部分244的一部分,如图1D所示,残留厚度极薄的基板第二部分244'。
如图1E所示,进行介电填充制程,以形成介电层34包覆核心晶粒结构20、输入/输出晶 粒结构22、以及第一导电结构18。接着,进行薄化制程,移除部分的介电层34、剩余的基 板第二部分244'及部分的停止层结构26,以显露第一导电结构18及第二导电结构30。于一 实施例中,薄化制程包括第一去除步骤及第二去除步骤,第一去除步骤用以去除残留的基板 第二部分244'以及部分的介电层34,如图1F所示,以显露出停止层结构26,例如为显露第 一停止层261,第一去除步骤例如为选自化学机械抛光、湿式蚀刻及等离子干式蚀刻其中一 种制程,于一实施例中,基板第二部分244'的材料为硅,第一停止层261的材料为氮化硅, 当第一去除步骤选用化学机械抛光制程时,硅及氮化硅的选择比例如为20,亦即Si/Si3N4为 20。
接续上述说明,第二去除步骤用以移除部分的停止层结构26,亦即依序移除第一停止层 261及部分第二停止层262,如图1G所示,以显露第一导电结构18及第二导电结构30,第 二去除步骤例如为选自化学机械抛光及等离子干式蚀刻其中一种制程。于一实施例中,第一 停止层261例如为氮化硅(Si3N4)层,第二停止层262例如为二氧化硅(SiO2)层,在第二去除步 骤中,先以化学机械抛光制程移除氮化硅层(第一停止层261),以显露二氧化硅层(第二停止 层262),其中氮化硅及二氧化硅的选择比例如介于10至20之间,亦即Si3N4/SiO2介于10至 20;再以另一化学机械抛光制程移除部分二氧化硅层(第二停止层262),以残留极薄的二氧化 硅层(第二停止层262')且显露第一导电结构18及第二导电结构30,其中二氧化硅及硅的选择 比约为5,亦即SiO2/Si为5。如此使得核心晶粒结构20(标示于图1E)及输入/输出晶粒结构 22(标示于图1E)皆被薄化,此薄化后的核心晶粒结构20及输入/输出晶粒结构22例如分别称 为核心晶粒20A及输入/输出晶粒22A。
具体而言,核心晶粒20A及输入/输出晶粒22A包括基板(即基板第一部分243)、停止层 结构26的残留的第二停止层262'、第二主动层28、第二导电结构30及第二重布线层32,第 二主动层28及第二停止层262'分别设置于基板(即基板第一部分243)的相对两侧,第二导电 结构30形成于基板(即基板第一部分243),第二导电结构30的一端连接于第二主动层28, 第二导电结构30的另一端穿透且显露于第二停止层262',第二重布线层32形成于第二主动 层28。
如图1H所示,形成第三重布线层36于介电层34及部分残留且极薄的第二停止层262' 上,第三重布线层36并与显露的第一导电结构18及第二导电结构30电性连接,其中第三重 布线层36与第二停止层262'之间具有较佳的粘着性,因此第三重布线层36不易剥离。如图 1I所示,于第三重布线层36上形成多个焊球38,于一实施例中,焊球38借由第三重布线层 36以分别与例如第一导电结构18及第二导电结构30电性连接;之后,并于进行晶圆针测(Chip Probing,CP),以进行电性功能上的测试(Test)后,进行切单(die saw),以完成三维系统单 芯片。
图2是本发明第一实施例三维系统单芯片的剖面结构示意图,在图2中,并进一步绘示 了将三维系统单芯片40设置于电路板42或软板上,以借由焊球38与电路板42或软板进行 电性连接。如图2所示,三维系统单芯片40包括存储器芯片结构10A、多个第一导电结构 18、核心晶粒20A、多个输入/输出晶粒22A、介电层34、第三重布线层36及多个焊球38。其中存储器芯片结构10A为上述存储器晶圆结构10(标示于图1A)进行切单后的型态,于一实 施例中,存储器芯片结构10A包括半导体基板44、第一主动层14及第一重布线层16,第一主动层14形成于半导体基板44,第一重布线层16形成于第一主动层14。第一导电结构18、核心晶粒20A、输入/输出晶粒22A设置于第一重布线层16,其中输入/输出晶粒22A设置于核心晶粒20A的周边,第一导电结构18介于输入/输出晶粒22A及核心晶粒20A之间。核心 晶粒20A及输入/输出晶粒22A的结构已叙述于上,于此不再赘述。核心晶粒结构20A及输 入/输出晶粒22A的第二重布线层32接合于第一重布线层16;介电层34填充于核心晶粒20A、 输入/输出晶粒22A、以及第一导电结构18之间,且显露停止层结构26的残留第二停止层262'及第二导电结构30的一端;第三重布线层36形成于介电层34及残留第二停止层262',且第三重布线层36与显露的第一导电结构18及显露的第二导电结构30电性连接;多个焊球38形成于第三重布线层36。
图3是本发明一实施例三维系统单芯片的仰视示意图,亦即由焊球侧观看,如图3所示, 多个焊球38排列于第三重布线层36上,图3中并以虚线标示核心晶粒20A及输入/输出晶粒 22A的位置配置,其中输入/输出晶粒22A位于核心晶粒20A的周边。于一实施例中,多个 焊球38可包括信号焊球381及电源/接地焊球382,其中部分的电源/接地焊球382可供提供 核心晶粒20A及输入/输出晶粒22A电源或接地,部分的电源/接地焊球382亦可供经由第三 重布线层36及第一导电结构18提供存储器芯片结构10A电源或接地,又部分的信号焊球381 可供作为输入/输出晶粒22A的信号传出入媒介,其中,输入/输出晶粒22A的信号可例如来 自核心晶粒20A及/或电路板42,又核心晶粒20A与存储器芯片结构10A之间具有例如三级 缓存(L3 cache)的存取机制。
图4A至图4H所示是本发明第二实施例三维系统单芯片的制造方法的剖面示意图。如图 4A所示,提供SoC晶圆结构50,分隔成独立的核心晶粒区501及多个输入/输出晶粒区502, 输入/输出晶粒区502设置于核心晶粒区501的周边,SoC晶圆结构50包括半导体晶圆52、 停止层结构54、第二主动层56、多个导电结构58及第二重布线层60。半导体晶圆52具有相对的主动面521及背面522,停止层结构54形成于半导体晶圆52内,将半导体晶圆52分 为晶圆第一部分523及晶圆第二部分524,其中晶圆第一部分523位于停止层结构54及主动 面521之间,晶圆第二部分524位于停止层结构54及背面522之间。于一实施例中,停止层 结构54包括相互堆叠的第一停止层541及第二停止层542,第一停止层541的材料不同于第 二停止层542的材料,第二停止层542介于第一停止层541及主动面521之间,其中第一停 止层541例如为氮化硅(Si3N4)层,第二停止层542例如为二氧化硅(SiO2)层。停止层结构54 的制造与第一实施例所揭示的停止层结构26的制造流程相同或相近,于此不再赘述。
接续上述说明,第二主动层56形成于半导体晶圆52的主动面521;导电结构58形成于 晶圆第一部分523以连接第二主动层56及停止层结构54,于一实施例中,导电结构58例如 为导电柱;又第二重布线层60形成于第二主动层56,第二重布线层60上例如形成有金属布 线、金属柱(VIA)及微凸块。
如图4B所示,提供多个存储器晶粒62,图4B中仅绘示三个存储器晶粒62,惟不限于此。每一存储器晶粒62包括晶粒基板64、第一主动层66及第一重布线层68。第一主动层66形成于晶粒基板64,第一主动层66上例如形成有晶体管元件等存储器的基本元件。第一重布线层68形成于第一主动层66,第一重布线层68上例如形成有金属布线、金属柱(VIA)及微凸块。如图4B所示,多个存储器晶粒62倒置,且每一存储器晶粒62的第一重布线层68接合至SoC晶圆结构50的核心晶粒区501的第二重布线层60,于一实施例中,第一重布线层68以混合键合技术接合于第二重布线层60。
如图4C所示,进行介电填充制程,以形成介电层70包覆存储器晶粒62,于一实施例中, 介电层70设置于SoC晶圆结构50上且填充于多个存储器晶粒62之间,介电层70的顶面与 存储器晶粒62的晶粒基板64平齐。
之后,进行背面研磨制程,自半导体晶圆52的背面522进行研磨,以移除晶圆第二部分 524的一部分,如图4D所示,残留厚度极薄的晶圆第二部分524'。接着进行薄化制程,移除 剩余的晶圆第二部分524'及部分的停止层结构54,以显露导电结构58。于一实施例中,薄化 制程包括第一去除步骤及第二去除步骤,第一去除步骤用以去除残留的晶圆第二部分524', 如图4E所示,以显露出停止层结构54,例如为显露第一停止层541;第二去除步骤用以移除 部分的停止层结构54,亦即依序移除第一停止层541及部分第二停止层542,如图4F所示, 以显露导电结构58且残留极薄的第二停止层542'。第一去除步骤及第二去除步骤所可选择的 制程及方法已揭示于第一实施例中,于此不再赘述。借由薄化制程使得SoC晶圆结构50(标 示于图4A)被薄化,形成薄化SoC晶圆结构50'。
如图4G所示,形成第三重布线层72于部分残留且极薄的第二停止层542'上,第三重布 线层72并与显露的导电结构58电性连接,其中第三重布线层72与第二停止层542'之间具有 较佳的粘着性,因此第三重布线层72不易与薄化SoC晶圆结构50'剥离。如图4H所示,于 第三重布线层72上形成多个焊球74,于一实施例中,焊球74借由第三重布线层72以分别 与例如导电结构58电性连接;之后,并于进行晶圆针测,以进行电性功能上的测试后,进行 切单,以完成三维系统单芯片。
图5是本发明第二实施例三维系统单芯片的剖面结构示意图,在图5中,并进一步绘示 了将三维系统单芯片80设置于电路板42或软板上,以借由焊球74与电路板42或软板进行 电性连接。如图5所示,三维系统单芯片80包括多个存储器晶粒62、介电层70、SoC芯片50A、第三重布线层72及多个焊球74。其中每一存储器晶粒62的结构已揭示于图4B的叙述中,于此不再赘述;介电层70填充于存储器晶粒62之间;SoC芯片50A为上述薄化SoC晶 圆结构50'(标示于图4F)进行切单后的型态,SoC芯片50A分隔成独立的核心晶粒501A及多 个输入/输出晶粒502A,输入/输出晶粒502A设置于核心晶粒501A的周边,SoC芯片50A 包括基板52A(即晶圆第一部分523经切单后)、停止层结构54的残留第二停止层542'、第二 主动层56、多个导电结构58及第二重布线层60,第二主动层56及残留第二停止层542'分别 设置于基板52A的相对两侧,导电结构58形成于基板52A,每一导电结构58的一端连接于 第二主动层56,每一导电结构58的另一端穿透且显露于残留第二停止层542'。多个被介电 层70所包覆的存储器晶粒62的第一重布线层68接合至核心晶粒502A的第二重布线层60; 第三重布线层72形成于残留第二停止层542',且第三重布线层72与显露的导电结构58电性 连接;多个焊球74形成于第三重布线层72。
图6是本发明第二实施例三维系统单芯片的仰视示意图,亦即由焊球74侧观看,如图6 所示,多个焊球74排列于第三重布线层72上,图6中以长虚线标示核心晶粒501A及输入/ 输出晶粒502A的位置配置,其中输入/输出晶粒502A位于核心晶粒501A的周边;图6中并 以点状虚线标示存储器晶粒62的配置位置,如图所示,存储器晶粒62主要对应核心晶粒501A 设置,图中虽绘示了6个存储器晶粒62,惟不限于此。
接续上述说明,于一实施例中,多个焊球74可包括信号焊球741及电源/接地焊球742, 其中电源/接地焊球742可供提供核心晶粒501A、输入/输出晶粒502A及存储器晶粒62电源 或接地;又部分的信号焊球741可供作为输入/输出晶粒502A的信号传出入媒介,其中,输 入/输出晶粒502A的信号可例如来自核心晶粒501A及/或电路板42,又核心晶粒501A与存 储器晶粒62之间具有例如三级缓存(L3 cache)的存取机制。
图7A至图7E是所示本发明第三实施例三维系统单芯片的制造方法的剖面示意图,如图 7A所示,提供存储器晶圆结构10及提供SoC晶圆结构50。存储器晶圆结构10包括晶圆12、 第一主动层14及第一重布线层16,第一主动层14形成于晶圆12上,第一重布线层16形成 于第一主动层14上,存储器晶圆结构10的进一步特征已揭示于第一实施例中,于此不再赘 述。SoC晶圆结构50分隔成独立核心晶粒区501及多个输入/输出晶粒区502,输入/输出晶 粒区502设置于核心晶粒区501的周边,SoC晶圆结构50包括半导体晶圆52、停止层结构54、第二主动层56、多个导电结构58及第二重布线层60,SoC晶圆结构50的结构及配置已 揭示于第二实施例中,于此不再赘述。
如图7B所示,将存储器晶圆结构10的第一重布线层16接合至SoC晶圆结构50的第二 重布线层60;之后对SoC晶圆结构50依序进行背面研磨制程及薄化制程,如图7C所示,以显露导电结构58的一端且残留极薄的第二停止层542',其中背面研磨制程及薄化制程已揭示 于第二实施例中,于此不再赘述。
如图7D所示,形成第三重布线层72于部分残留且极薄的第二停止层542'上,第三重布 线层72与显露的导电结构58电性连接;接着,如图7E所示,于第三重布线层72上形成多 个焊球74,于一实施例中,焊球74借由第三重布线层72以分别与例如导电结构58电性连接;之后,并于进行晶圆针测,以进行电性功能上的测试后,进行切单,以完成三维系统单芯片。
图8是本发明第三实施例三维系统单芯片的剖面结构示意图,在图8中,并进一步绘示 了将三维系统单芯片90设置于电路板42或软板上,以借由焊球74与电路板42或软板进行 电性连接。如图8所示,三维系统单芯片90包括存储器芯片结构10A、SoC芯片50A、第三重布线层72及多个焊球74。其中存储器芯片结构10A为存储器晶圆结构10(标示于图7A) 进行切单后的型态,SoC芯片50A为薄化SoC晶圆结构50'(标示于图7C)进行切单后的型态。 存储器芯片结构10A的第一重布线层16与SoC芯片50A的第二重布线层60以面对面的方 式接合在一起,于一实施例中,第一重布线层16以混合键合技术接合于第二重布线层60。 第三重布线层72形成于残留第二停止层542',且第三重布线层72与显露的导电结构58电性 连接;多个焊球74形成于第三重布线层72。
根据上述,在本发明一实施例中,三维系统单芯片包括存储器芯片以及被介电层所包覆 的核心晶粒及多个输入/输出晶粒,其中输入/输出晶粒位于核心晶粒周边,且存储器芯片与核 心晶粒接合;在本发明一实施例中,三维系统单芯片包括SoC芯片以及被介电层所包覆多个 存储器晶粒,SoC芯片包括独立的核心晶粒及多个位于核心晶粒周边的输入/输出晶粒,且核 心晶粒与多个存储器晶粒接合;在本发明一实施例中,三维系统单芯片包括存储器芯片与SoC 芯片,SoC芯片包括独立的核心晶粒及多个位于核心晶粒周边的输入/输出晶粒,且核心晶粒 与存储器芯片接合。在本发明实施例三维系统单芯片中,无论是核心晶粒、输入/输出晶粒, 或者是SoC芯片,借由其中停止层结构的设置,皆可薄化而具有非常薄的厚度,例如核心晶 粒、输入/输出晶粒,或者是SoC芯片的整体厚度不大于12微米,如此使得三维系统单芯片 的整体厚度大幅减少,可满足高集成度与速度要求,而具有更佳的电气特性及效率。
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,虽然本 发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱 离本发明技术方案范围内,当可利用上述揭示的方法及技术内容作出些许的更动或修饰为等 同变化的等效实施例,但凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上 实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。
Claims (27)
1.一种三维系统单芯片的制造方法,其特征在于,包括:
提供存储器晶圆结构,包括晶圆、第一主动层及第一重布线层,所述第一主动层形成于所述晶圆,所述第一重布线层形成于所述第一主动层;
设置多个第一导电结构、至少一核心晶粒结构、及多个输入/输出晶粒结构于所述第一重布线层,其中所述输入/输出晶粒结构设置于所述至少一核心晶粒结构的周边,其中,
每一所述至少一核心晶粒结构及每一所述输入/输出晶粒结构包括半导体基板、停止层结构、第二主动层、多个第二导电结构及第二重布线层,所述半导体基板具有相对的主动面及背面,所述停止层结构形成于所述半导体基板内,将所述半导体基板分为基板第一部分及基板第二部分,其中所述基板第一部分位于所述停止层结构及所述主动面之间,所述基板第二部分位于所述停止层结构及所述背面之间,所述第二主动层形成于所述主动面,所述第二导电结构形成于所述基板第一部分以连接所述第二主动层及所述停止层结构,所述第二重布线层形成于所述第二主动层,每一所述至少一核心晶粒结构的第二重布线层及每一所述输入/输出晶粒结构的第二重布线层接合于所述第一重布线层;
进行背面研磨制程,自所述半导体基板的背面进行研磨,以移除所述基板第二部分的一部分;
进行介电填充制程,以形成介电层包覆所述至少一核心晶粒结构、所述输入/输出晶粒结构、以及所述第一导电结构;
进行薄化制程,移除部分的所述介电层、剩余的所述基板第二部分及部分的所述停止层结构,以显露所述第一导电结构及所述第二导电结构;
形成第三重布线层于所述介电层上,且所述第三重布线层与显露的所述第一导电结构及所述第二导电结构电性连接;
形成多个焊球于所述第三重布线层;以及
进行切单。
2.如权利要求1所述的三维系统单芯片的制造方法,其特征在于,所述停止层结构包括相互堆叠的第一停止层及第二停止层,所述第一停止层的材料不同于所述第二停止层的材料,所述第二停止层介于所述第一停止层及所述第二主动层之间,在进行所述薄化制程中,移除部分的所述停止层结构的步骤包括先移除所述第一停止层,再移除部分所述第二停止层。
3.如权利要求2所述的三维系统单芯片的制造方法,其特征在于,所述第一停止层为氮化硅层,所述第二停止层为二氧化硅层。
4.如权利要求3所述的三维系统单芯片的制造方法,其特征在于,所述氮化硅层及所述二氧化硅层的形成步骤包括先于所述半导体基板的第一深度进行氮离子注入制程,再于所述半导体基板的第二深度进行氧离子注入制程,且所述第二深度小于所述第一深度,接着进行高温处理制程,使所述氮离子注入的区域形成所述氮化硅层,所述氧离子注入的区域形成所述二氧化硅层。
5.如权利要求3所述的三维系统单芯片的制造方法,其特征在于,所述氮化硅层及所述二氧化硅层的移除方法选自化学机械抛光及等离子干式蚀刻其中的一种,其中氮化硅及二氧化硅的选择比介于10至20之间,二氧化硅及硅的选择比约为5。
6.如权利要求1所述的三维系统单芯片的制造方法,其特征在于,所述薄化制程包括:
第一去除步骤,移除部分的所述介电层及剩余的所述基板第二部分;以及
第二去除步骤,移除部分的所述停止层结构,以显露所述第二导电结构。
7.如权利要求6所述的三维系统单芯片的制造方法,其特征在于,所述第一去除步骤选自化学机械抛光、湿式蚀刻及等离子干式蚀刻其中的一种,所述第二去除步骤选自化学机械抛光及等离子干式蚀刻其中的一种。
8.如权利要求1所述的三维系统单芯片的制造方法,其特征在于,所述第二重布线层以混合键合技术接合于所述第一重布线层。
9.一种三维系统单芯片的制造方法,其特征在于,包括:
提供多个存储器晶粒,每一所述存储器晶粒包括晶粒基板、第一主动层及第一重布线层,所述第一主动层形成于所述晶粒基板,所述第一重布线层形成于所述第一主动层;
提供SoC晶圆结构,分隔成独立的至少一核心晶粒区、及多个输入/输出晶粒区,所述输入/输出晶粒区设置于所述至少一核心晶粒区的周边,所述SoC晶圆结构包括半导体晶圆、停止层结构、第二主动层、多个导电结构及第二重布线层,所述半导体晶圆具有相对的主动面及背面,所述停止层结构形成于所述半导体晶圆内,将所述半导体晶圆分为晶圆第一部分及晶圆第二部分,其中所述晶圆第一部分位于所述停止层结构及所述主动面之间,所述晶圆第二部分位于所述停止层结构及所述背面之间,所述第二主动层形成于所述主动面,所述导电结构形成于所述晶圆第一部分以连接所述第二主动层及所述停止层结构,所述第二重布线层形成于所述第二主动层;
将每一所述存储器晶粒的第一重布线层接合至所述SoC晶圆结构的至少一核心晶粒区的第二重布线层;
进行介电填充制程,以形成介电层包覆所述存储器晶粒;
进行背面研磨制程,自所述半导体晶圆的背面进行研磨,以移除所述晶圆第二部分的一部分;
进行薄化制程,移除剩余的所述晶圆第二部分及部分的所述停止层结构,以显露所述导电结构;
形成第三重布线层于残留的部分所述停止层结构,且所述第三重布线层与显露的所述导电结构电性连接;
形成多个焊球于所述第三重布线层;以及
进行切单。
10.如权利要求9所述的三维系统单芯片的制造方法,其特征在于,所述停止层结构包括相互堆叠的第一停止层及第二停止层,所述第一停止层的材料不同于所述第二停止层的材料,所述第二停止层介于所述第一停止层及所述第二主动层之间,在进行所述薄化制程中,移除部分的所述停止层结构的步骤包括先移除所述第一停止层,再移除部分所述第二停止层。
11.如权利要求10所述的三维系统单芯片的制造方法,其特征在于,所述第一停止层为氮化硅层,所述第二停止层为二氧化硅层。
12.如权利要求11所述的三维系统单芯片的制造方法,其特征在于,所述氮化硅层及所述二氧化硅层的形成步骤包括先于所述半导体晶圆的第一深度进行氮离子注入制程,再于所述半导体晶圆的第二深度进行氧离子注入制程,且所述第二深度小于所述第一深度,接着进行高温处理制程,使所述氮离子注入的区域形成所述氮化硅层,所述氧离子注入的区域形成所述二氧化硅层。
13.如权利要求11所述的三维系统单芯片的制造方法,其特征在于,所述氮化硅层及所述二氧化硅层的移除方法选自化学机械抛光及等离子干式蚀刻其中的一种,其中氮化硅及二氧化硅的选择比介于10至20之间,二氧化硅及硅的选择比约为5。
14.如权利要求9所述的三维系统单芯片的制造方法,其特征在于,所述薄化制程包括:
第一去除步骤,移除剩余的所述晶圆第二部分;以及
第二去除步骤,移除部分的所述停止层结构,以显露所述导电结构。
15.如权利要求14所述的三维系统单芯片的制造方法,其特征在于,所述第一去除步骤选自化学机械抛光、湿式蚀刻及等离子干式蚀刻其中的一种,所述第二去除步骤选自化学机械抛光及等离子干式蚀刻其中的一种。
16.如权利要求9所述的三维系统单芯片的制造方法,其特征在于,所述第二重布线层以混合键合技术接合于所述第一重布线层。
17.一种三维系统单芯片的制造方法,其特征在于,包括:
提供存储器晶圆结构,包括晶圆、第一主动层及第一重布线层,所述第一主动层形成于所述晶圆,所述第一重布线层形成于所述第一主动层;
提供SoC晶圆结构,分隔成独立的至少一核心晶粒区、及多个输入/输出晶粒区,所述输入/输出晶粒区设置于所述至少一核心晶粒区的周边,所述SoC晶圆结构包括半导体晶圆、停止层结构、第二主动层、多个导电结构及第二重布线层,所述半导体晶圆具有相对的主动面及背面,所述停止层结构形成于所述半导体晶圆内,将所述半导体晶圆分为晶圆第一部分及晶圆第二部分,其中所述晶圆第一部分位于所述停止层结构及所述主动面之间,所述晶圆第二部分位于所述停止层结构及所述背面之间,所述第二主动层形成于所述主动面,所述导电结构形成于所述晶圆第一部分以连接所述第二主动层及所述停止层结构,所述第二重布线层形成于所述第二主动层;
将所述存储器晶圆结构的第一重布线层接合至所述SoC晶圆结构的第二重布线层;
进行背面研磨制程,自所述半导体晶圆的背面进行研磨,以移除所述晶圆第二部分的一部分;
进行薄化制程,移除剩余的所述晶圆第二部分及部分的所述停止层结构,以显露所述导电结构;
形成第三重布线层于所述晶圆第一部分,且所述第三重布线层与显露的所述导电结构电性连接;
形成多个焊球于所述第三重布线层;以及
进行切单。
18.如权利要求17所述的三维系统单芯片的制造方法,其特征在于,所述停止层结构包括相互堆叠的第一停止层及第二停止层,所述第一停止层的材料不同于所述第二停止层的材料,所述第二停止层介于所述第一停止层及所述第二主动层之间,在进行所述薄化制程中,移除部分的所述停止层结构的步骤包括先移除所述第一停止层,再移除部分所述第二停止层。
19.如权利要求18所述的三维系统单芯片的制造方法,其特征在于,所述第一停止层为氮化硅层,所述第二停止层为二氧化硅层。
20.如权利要求19所述的三维系统单芯片的制造方法,其特征在于,所述氮化硅层及所述二氧化硅层的形成步骤包括先于所述半导体晶圆的第一深度进行氮离子注入制程,再于所述半导体晶圆的第二深度进行氧离子注入制程,且所述第二深度小于所述第一深度,接着进行高温处理制程,使所述氮离子注入的区域形成所述氮化硅层,所述氧离子注入的区域形成所述二氧化硅层。
21.如权利要求19所述的三维系统单芯片的制造方法,其特征在于,所述氮化硅层及所述二氧化硅层的移除方法选自化学机械抛光及等离子干式蚀刻其中的一种,其中氮化硅及二氧化硅的选择比介于10至20之间,二氧化硅及硅的选择比约为5。
22.如权利要求17所述的三维系统单芯片的制造方法,其特征在于,所述薄化制程包括:
第一去除步骤,移除部分的所述介电层及剩余的所述晶圆第二部分;以及
第二去除步骤,移除部分的所述停止层结构,以显露所述导电结构。
23.如权利要求22所述的三维系统单芯片的制造方法,其特征在于,所述第一去除步骤选自化学机械抛光、湿式蚀刻及等离子干式蚀刻其中的一种,所述第二去除步骤选自化学机械抛光及等离子干式蚀刻其中的一种。
24.如权利要求17所述的三维系统单芯片的制造方法,其特征在于,所述第二重布线层以混合键合技术接合于所述第一重布线层。
25.一种三维系统单芯片,其特征在于,包括:
存储器芯片结构,包括半导体基板、第一主动层及第一重布线层,所述第一主动层形成于所述半导体基板,所述第一重布线层形成于所述第一主动层;
多个第一导电结构、至少一核心晶粒及多个输入/输出晶粒设置于所述第一重布线层,其中所述输入/输出晶粒设置于所述至少一核心晶粒的周边,其中,
每一所述至少一核心晶粒及每一所述输入/输出晶粒包括基板、停止层结构、第二主动层、多个第二导电结构及第二重布线层,所述第二主动层及所述停止层结构分别设置于所述基板的相对两侧,所述第二导电结构形成于所述基板,每一所述第二导电结构的一端连接于所述第二主动层,每一所述第二导电结构的另一端穿透且显露于所述停止层结构,所述第二重布线层形成于所述第二主动层,每一所述至少一核心晶粒区的第二重布线层及每一所述输入/输出晶粒区的第二重布线层接合于所述第一重布线层;
介电层,填充于所述至少一核心晶粒、所述输入/输出晶粒、以及所述第一导电结构之间,且显露所述停止层结构及所述第一导电结构的一端;
第三重布线层,形成于所述介电层,且所述第三重布线层与显露的所述第一导电结构及显露的所述第二导电结构电性连接;以及
多个焊球,形成于所述第三重布线层。
26.一种三维系统单芯片,其特征在于,包括:
多个存储器晶粒,每一所述存储器晶粒包括晶粒基板、第一主动层及第一重布线层,所述第一主动层形成于所述晶粒基板,所述第一重布线层形成于所述第一主动层;
介电层,包覆所述存储器晶粒,且显露每一所述存储器晶粒的所述第一重布线层;
SoC芯片,分隔成独立的至少一核心晶粒、及多个输入/输出晶粒,所述输入/输出晶粒设置于所述至少一核心晶粒的周边,所述SoC芯片包括基板、停止层结构、第二主动层、多个导电结构及第二重布线层,所述第二主动层及所述停止层结构分别设置于所述基板的相对两侧,所述导电结构形成于所述基板,每一所述导电结构的一端连接于所述第二主动层,每一第二导电结构的另一端穿透且显露于所述停止层结构,所述第二重布线层形成于所述第二主动层,每一所述存储器晶粒的所述第一重布线层接合至所述至少一核心晶粒的第二重布线层;
第三重布线层,形成于所述停止层结构,且所述第三重布线层与显露的所述导电结构电性连接;以及
多个焊球,形成于所述第三重布线层。
27.一种三维系统单芯片,其特征在于,包括:
存储器芯片结构,包括半导体基板、第一主动层及第一重布线层,所述第一主动层形成于所述半导体基板,所述第一重布线层形成于所述第一主动层;
SoC芯片,分隔成独立的至少一核心晶粒、及多个输入/输出晶粒,所述输入/输出晶粒设置于所述至少一核心晶粒的周边,所述SoC芯片包括基板、停止层结构、第二主动层、多个导电结构及第二重布线层,所述第二主动层及所述停止层结构分别设置于所述基板的相对两侧,所述导电结构形成于所述基板,每一所述导电结构的一端连接于所述第二主动层,每一第二导电结构的另一端穿透且显露于所述停止层结构,所述第二重布线层形成于所述第二主动层,每一所述存储器晶粒的第一重布线层接合至所述至少一核心晶粒的第二重布线层;
第三重布线层,形成于所述停止层结构,且所述第三重布线层与显露的所述导电结构电性连接;以及
多个焊球,形成于所述第三重布线层。
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