WO2022241662A1 - 半导体超薄堆叠结构的制造方法 - Google Patents

半导体超薄堆叠结构的制造方法 Download PDF

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WO2022241662A1
WO2022241662A1 PCT/CN2021/094503 CN2021094503W WO2022241662A1 WO 2022241662 A1 WO2022241662 A1 WO 2022241662A1 CN 2021094503 W CN2021094503 W CN 2021094503W WO 2022241662 A1 WO2022241662 A1 WO 2022241662A1
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semiconductor
substrate
layer
semiconductor wafer
batch
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PCT/CN2021/094503
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English (en)
French (fr)
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邱志威
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邱志威
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Priority to PCT/CN2021/094503 priority Critical patent/WO2022241662A1/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates

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  • the invention relates to a method for manufacturing a semiconductor structure, in particular to a method for manufacturing an ultra-thin semiconductor stack structure.
  • the invention provides a method for manufacturing a semiconductor ultra-thin stack structure, so that the semiconductor ultra-thin stack structure can meet the requirements of high accumulation degree and speed, and has better electrical characteristics and efficiency.
  • the method for manufacturing a semiconductor ultra-thin stack structure includes: manufacturing a plurality of semiconductor wafers, selecting one of the semiconductor wafers as the bottom first semiconductor wafer, and part of the semiconductor wafers as the second semiconductor wafer to be stacked.
  • a semiconductor wafer and a third semiconductor wafer the manufacturing steps of each semiconductor wafer include: providing a semiconductor substrate having an opposite active surface and a back surface; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first part of the substrate and The second part of the substrate, wherein the first part of the substrate is located between the stop layer structure and the active surface, the second part of the substrate is located between the stop layer structure and the back surface, the stop layer structure at least includes a silicon nitride layer, and the manufacture of the silicon nitride layer includes a prior A nitrogen ion implantation process is performed on the first depth of the semiconductor substrate, followed by a high temperature treatment process, so that a silicon nitride layer is formed in the area where the nitrogen ion is implanted; An interconnection point, and a plurality of conductive structures are arranged on the first part of the substrate to connect the interconnection layer and the stop layer structure.
  • the first thinning process and the second thinning process include a substrate removal step and a stop layer removal step, wherein the substrate removal step removes the remaining second part of the substrate to reveal the stop layer structure; the stop layer removal step removes the stop layer structure to expose the first portion of the substrate and the conductive structure.
  • a plurality of thinned third semiconductor wafers can be stacked sequentially on the thinned second semiconductor wafer, wherein each thinned
  • the stacking step of the third semiconductor wafer includes: flipping the third semiconductor wafer relative to the first semiconductor wafer, so that the interconnection layer of the third semiconductor wafer and the first part of the substrate of the thinned second semiconductor wafer are opposite and bonding together; performing a third backside grinding process, grinding from the backside of the third semiconductor wafer to remove a portion of the second portion of the substrate of the third semiconductor wafer; and performing a third thinning process, including a substrate removal step and stop layer removal steps.
  • the above stop layer structure further includes a silicon dioxide layer, and the silicon dioxide layer is disposed on the silicon nitride layer so as to be between the silicon nitride layer and the active surface.
  • the step of forming the silicon dioxide layer includes: after the nitrogen ion implantation process, performing an oxygen ion implantation process at a second depth of the semiconductor substrate, and the second depth is smaller than the first depth, Afterwards, a high-temperature treatment process is performed to form a silicon dioxide layer in the region implanted with oxygen ions.
  • the above-mentioned step of removing the stop layer includes: removing the silicon nitride layer first, and then removing the silicon dioxide layer.
  • the substrate removal step is selected from one of chemical mechanical polishing, wet etching and plasma dry etching, wherein the selectivity ratio of silicon and silicon nitride is between 20 and 80.
  • the removal method of the above-mentioned silicon nitride layer and silicon dioxide layer is selected from one of chemical mechanical polishing and plasma dry etching, wherein the selectivity ratio of silicon nitride and silicon dioxide is Between 10 and 20, the selectivity ratio of silica to silicon is about 5.
  • the distance between the stop layer structure and the active surface is between 1 micron and 5 microns, and the thickness of the thinned second semiconductor wafer is not greater than 12 microns.
  • the following steps are further included: on the side of the thinned first semiconductor wafer away from the thinned second semiconductor wafer, a plurality of Solder balls are used to electrically connect the conductive structures respectively; and electrical testing and singulation are performed.
  • the method for manufacturing a semiconductor ultra-thin stack structure includes manufacturing a plurality of semiconductor wafers, and the manufacturing steps of each semiconductor wafer include: providing a semiconductor substrate with a relative active surface and a back surface; forming a stop layer structure on the semiconductor In the substrate, the semiconductor substrate is divided into a first part of the substrate and a second part of the substrate, wherein the first part of the substrate is located between the stop layer structure and the active surface, and the second part of the substrate is located between the stop layer structure and the back surface, and the stop layer structure contains at least nitrogen
  • the manufacture of the silicon nitride layer and the silicon nitride layer includes a nitrogen ion implantation process at the first depth of the semiconductor substrate, followed by a high temperature treatment process, so that the nitrogen ion implanted area forms a silicon nitride layer; Electrical components and an interconnection layer, the interconnection layer includes multiple interconnection points, and a plurality of conductive structures are arranged on the first part of the substrate to connect the interconnection layer
  • One of the semiconductor wafers is selected as the first semiconductor wafer at the bottom, and part of the semiconductor wafers are then singulated as the first batch of semiconductor chips to be stacked and at least one second batch of semiconductor chips; Flip-chip on the first semiconductor wafer, make the interconnection layer of the first batch of semiconductor chips and the interconnection layer of the first semiconductor wafer face each other and bond them together by hybrid bonding technology; carry out the first molding process, in order to A first encapsulant is formed on a semiconductor wafer to cover the first batch of semiconductor chips; a first back grinding process is performed to remove part of the first encapsulant and the first encapsulant from the side of the first encapsulant away from the first semiconductor wafer.
  • Part of the second portion of the substrate of the batch of semiconductor chips performing a first thinning process to form a first semiconductor chip layer; performing a second back grinding process to grind from the back of the first semiconductor wafer to remove the first semiconductor a portion of the second portion of the substrate of the wafer; and performing a second thinning process to form a thinned first semiconductor wafer, wherein the first thinning process and the second thinning process include a substrate removal step and a stop layer removal step , wherein the substrate removing step removes the remaining second portion of the substrate to expose the stop layer structure, and the stop layer removing step removes the stop layer structure to expose the first portion of the substrate and the conductive structure.
  • At least one second semiconductor chip layer can be sequentially stacked on the first semiconductor chip layer, wherein each second semiconductor chip layer
  • the stacking step includes: flipping the second batch of semiconductor chips relative to the first semiconductor wafer, so that the interconnection layer of the second batch of semiconductor chips and the first part of the substrate of the first semiconductor chip layer are opposite and bonded together; A molding process to form a second encapsulant on the first semiconductor chip layer to cover the second batch of semiconductor chips; perform a third back grinding process to remove part of the second encapsulant from the side of the second encapsulant away from the first semiconductor chip layer. encapsulating colloid and removing a part of the second part of the substrate of the second batch of semiconductor chips; and performing a third thinning process, including a substrate removal step and a stopper layer removal step.
  • the manufacturing method of the semiconductor ultra-thin stack structure provided by the present invention includes: providing a carrier board, and forming a plurality of first conductive pillars on the carrier board.
  • a plurality of semiconductor chips are provided, and the manufacturing steps of each semiconductor chip include: providing a semiconductor substrate having an opposite active surface and a back surface; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first part of the substrate and a second part of the substrate, The first part of the substrate is located between the stop layer structure and the active surface, the second part of the substrate is located between the stop layer structure and the back surface, the stop layer structure includes at least a silicon nitride layer, and the manufacture of the silicon nitride layer includes the first step prior to the semiconductor substrate.
  • a deep nitrogen ion implantation process is performed, followed by a high-temperature treatment process, so that a silicon nitride layer is formed in the area of nitrogen ion implantation; multiple electrical components and interconnection layers are arranged on the active surface, and the interconnection layer includes multiple interconnection points, and A plurality of conductive structures are arranged on the first part of the substrate to connect the interconnection layer and the stop layer structure; and singulation is performed.
  • a first batch of semiconductor chips and at least one second batch of semiconductor chips are selected from the semiconductor chips, the first batch of semiconductor chips includes a plurality of first semiconductor chips, and the second batch of semiconductor chips includes a plurality of second semiconductor chips.
  • the first batch of semiconductor chips is flip-chip disposed on the carrier board, and the first conductive column is interposed between adjacent first semiconductor chips, wherein the interconnection layer of the first batch of semiconductor chips is adjacent to the carrier board and the semiconductor substrate is away from the carrier board.
  • a first molding process is performed to form a first encapsulant on the carrier board to cover the first batch of semiconductor chips and the first conductive pillars.
  • a first back grinding process is performed to remove a portion of the first encapsulant from a side of the first encapsulant away from the carrier board and remove a portion of the second portion of the substrate of the first batch of semiconductor chips.
  • the first thinning process includes sequentially removing the remaining second portion of the substrate and the stop layer structure of the first batch of semiconductor chips to expose the first portion of the substrate, the conductive structure and the first conductive column.
  • a plurality of second conductive pillars are provided to electrically connect part of the conductive structure of the first semiconductor chip layer.
  • the second batch of semiconductor chips is flip-chip arranged on the first semiconductor chip layer, wherein the second semiconductor chips are respectively connected between the adjacent first semiconductor chips, so that the interconnection layer of the second semiconductor chips is electrically connected to the exposed first semiconductor chip layer.
  • a conductive column and a part of the conductive structure of the first semiconductor chip layer, and a part of the second conductive column is interposed between adjacent second semiconductor chips.
  • a second molding process is performed to form a second encapsulant on the first semiconductor chip layer to cover the second batch of semiconductor chips and the second conductive pillars.
  • a second back grinding process is performed to remove part of the second encapsulant from the side of the second encapsulant away from the layer of the first semiconductor chip and remove a part of the second portion of the substrate of the second batch of semiconductor chips.
  • the second thinning process includes sequentially removing the remaining second portion of the substrate and the stop layer structure of the second batch of semiconductor chips to expose the first portion of the substrate, the conductive structure and the second conductive column.
  • the carrier board is removed to expose the interconnection layer of the first semiconductor chip layer and the first conductive column.
  • the following steps are further included: arranging a plurality of solder balls on the side of the first semiconductor chip layer away from the second semiconductor chip layer, so as to electrically connect them respectively the interconnection layer and the first conductive column; and performing singulation.
  • the plurality of first semiconductor chips of the above-mentioned first batch of semiconductor chips have different electrical functions.
  • the second semiconductor chips of the above-mentioned second batch of semiconductor chips have different electrical functions.
  • the stop layer structure is first formed in the semiconductor substrate by ion implantation process, and then the electrical components and the interconnection layer are arranged on the active surface of the semiconductor substrate; after that, the two semiconductor wafers are bonded up and down, or After the semiconductor wafer is diced to form a plurality of semiconductor chips, the batch of semiconductor chips is bonded to the lowest semiconductor wafer.
  • the backside grinding and thinning process is used to remove part of the semiconductor substrate and stop layer structure of the upper semiconductor wafer/chip from the back of the upper semiconductor wafer/chip , so that the upper semiconductor wafer/chip is formed into a thinned semiconductor wafer/semiconductor chip layer, and then the thinned semiconductor wafer/chip is bonded to another semiconductor wafer/chip (and molded encapsulant), back grinding and Thinning process, and another thinned semiconductor wafer/semiconductor chip layer is stacked on top, and finally the bottom semiconductor wafer is subjected to back grinding and thinning process.
  • each thinned semiconductor wafer/semiconductor chip layer is not greater than 12 microns, it can be stacked to 57 chip layers under the limit of the total chip thickness of 700 microns, thereby meeting the requirements of high integration and speed.
  • FIGS are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a first embodiment of the present invention.
  • FIGS. 2A to 2K are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a second embodiment of the present invention.
  • 3A to 3L are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a third embodiment of the present invention.
  • FIGS. 1A to 1S are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a first embodiment of the present invention.
  • manufacture a plurality of semiconductor wafers 10 (marked in FIG. 1E ), select one of the semiconductor wafers 10 as the first semiconductor wafer 10a (marked in FIG. 1F ) at the bottom of the stack, and the other semiconductor wafers 10 are used as the first semiconductor wafer 10a to be stacked.
  • the second semiconductor wafer 10b (indicated in FIG. 1F) and the third semiconductor wafer 10c (indicated in FIG. 1L ) the manufacturing process of a plurality of semiconductor wafers 10 is the same or similar, as shown in FIGS. 1A to 1E.
  • a semiconductor substrate 12 is provided.
  • the semiconductor substrate 12 is, for example, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or Silicon on insulation (silicon on insulation, SOI) substrate, in one embodiment, the thickness of the semiconductor substrate is, for example, 700 to 800 microns (um), preferably 775 microns, and the semiconductor substrate 12 has an active surface 121 and a back surface opposite 122.
  • a stop layer structure is formed in the semiconductor substrate 12 .
  • manufacturing the stop layer structure includes performing at least one ion implantation process and high temperature treatment process.
  • the ion implantation process includes performing nitrogen ion implantation first, and then performing oxygen ion implantation. As shown in FIG. 1B and FIG. 1C, a nitrogen ion implantation process 14 is first performed at the first depth D1 of the semiconductor substrate 12, and then an oxygen ion implantation process 16 is performed at the second depth D2 of the semiconductor substrate 12.
  • the first depth D1 of the ion implantation region 14' is, for example, a depth of about 1 to 5 microns from the active surface 121, and the second depth D2 of the oxygen ion implantation region 16' is smaller than the first depth D1 of the nitrogen ion implantation region 14, also That is, the oxygen ion implantation region 16 ′ is closer to the active surface 121 .
  • a high temperature treatment is performed, as shown in FIG. 1D, a silicon nitride (Si 3 N 4 ) layer 14a is formed in the nitrogen ion implantation region 14', and a silicon dioxide (SiO 2 ) layer 16a is formed in the oxygen ion implantation region 16', wherein The silicon dioxide layer 16a is relatively close to the active surface 121, and the silicon nitride layer 14a is relatively close to the back surface 122.
  • the silicon nitride layer 14a and the silicon dioxide layer 16a constitute the above-mentioned stop layer structure 18, wherein, The silicon dioxide layer 16 a is located on the silicon nitride layer 14 and between the silicon nitride layer 14 a and the active surface 121 .
  • the thickness of the silicon nitride layer 14 a and the silicon dioxide layer 16 a is, for example, 500 nanometers (nm).
  • the semiconductor substrate 12 between the silicon dioxide layer 16a of the stop layer structure 18 and the active surface 121 is called the first part 123 of the substrate, and the semiconductor substrate between the silicon nitride layer 14a of the stop layer structure 18 and the back surface 122 12 is referred to as the second substrate portion 124 .
  • the depth of the general N-type well (Nwell) is about 2 microns, so the first part of the substrate
  • the thickness of 123 should be kept at not less than 2 microns, that is, when the above-mentioned nitrogen ion implantation process 14 and oxygen ion implantation process 16 are performed, the first depth D1 of the nitrogen ion implantation region 14' and the first depth D1 of the oxygen ion implantation region 16 '
  • the second depth should be slightly greater than 2 microns.
  • a plurality of electrical components 20 and an interconnection layer 22 having interconnection points 221 are provided on the active surface 121.
  • the electrical components 20 include metal oxide semiconductor (MOS), for example, and are placed on the first substrate of the substrate.
  • MOS metal oxide semiconductor
  • a portion 123 is provided with a plurality of conductive structures.
  • the conductive structure includes, for example, through silicon vias (Through Silicon Via, TSV) 24, and the through silicon vias 24 vertically connect the interconnection layer 22 and the silicon dioxide layer 16a of the stop layer structure 18.
  • the manufacturing process of the electrical element 20, the interconnection layer 22 and the TSV 24 includes the front-end-of-line (FEOL) and the back-end-of-line (BEOL) of the general semiconductor manufacturing process,
  • FEOL front-end-of-line
  • BEOL back-end-of-line
  • components such as resistors, capacitors, diodes, and transistors are made on the semiconductor substrate 12 in the front-end process, and metal wiring and interconnection points 221 for connection between the various elements are made in the back-end process; in one embodiment, the interconnection point 221 is, for example, For copper contacts.
  • FIG. 1E is a schematic diagram of a semiconductor wafer 10 according to an embodiment of the present invention.
  • the first semiconductor wafer 10a, the second semiconductor wafer 10b, and the third semiconductor wafer 10c described below follow the semiconductor wafer 10 to describe the components used.
  • the position of the TSV 24 of the first semiconductor wafer 10a corresponds to, for example, the installation position of the solder ball in the subsequent manufacturing process
  • the position of the TSV 24 of the second semiconductor wafer 10b corresponds to the interconnection layer 22 of the third semiconductor wafer 10c.
  • the interconnection point 221 corresponds to.
  • the second semiconductor wafer 10b is flipped relative to the first semiconductor wafer 10a, so that the interconnection layers 22 of the first semiconductor wafer 10a and the second semiconductor wafer 10b are opposite and the interconnection points 221 are respectively Corresponding; then use hybrid bonding technology (Hybrid bonding), as shown in Figure 1G, make the first semiconductor wafer 10a and the second semiconductor wafer 10b stack together up and down, wherein the hybrid bonding technology includes copper-to-copper bonding and back Fire and other processes.
  • Hybrid bonding Hybrid bonding
  • the remaining substrate second portion 124 has a thickness of about 20 ⁇ .
  • a first thinning process is performed to form a thinned second semiconductor wafer.
  • the first thinning process includes a substrate removal step and a stopper layer removal step, as shown in FIGS. 1I to 1K. schematic diagram.
  • the substrate removal step is used to remove the remaining second portion 124 of the substrate, as shown in FIG. 1I, to reveal the stop layer structure 18, for example, to expose the silicon nitride layer 14a.
  • CMP Chemical mechanical polishing
  • a thinned second semiconductor wafer 10 b ′ is formed by exposing the first portion 123 of the substrate and the TSV 24 .
  • connection points 221 respectively correspond to the TSVs 24 of the thinned second semiconductor wafer 10 b ′.
  • the above-mentioned first back grinding process and first thinning process are repeated to complete stacking of the thinned third semiconductor wafer 10c' and the thinned second semiconductor wafer 10b'.
  • the thinned second semiconductor wafer 10c' is stacked.
  • the thickness of the semiconductor wafer 10b' or the thinned third semiconductor wafer 10c' is, for example, 12 micrometers.
  • a second backside grinding process is used to grind from the backside 122 of the first semiconductor wafer 10a, as shown in FIG. 1N, to remove the first semiconductor wafer. 10a, a part of the second substrate portion 124 is left, and the second substrate portion 124 with an extremely thin thickness remains; then, a second thinning process is performed, as shown in FIG. 1O to FIG. , to sequentially remove the remaining substrate second portion 124, silicon nitride layer 14a, and silicon dioxide layer 16a of the first semiconductor wafer 10a, thereby exposing the thinned first substrate portion 123 and silicon dioxide layer of the first semiconductor wafer 10a′.
  • Perforation 24 thus completing multiple thinned semiconductor wafers 10' such as thinning the first semiconductor wafer 10a', thinning the second semiconductor wafer 10b', thinning the third semiconductor wafer 10c'... of stacks.
  • each thinned semiconductor wafer 10' is singulated as a semiconductor chip layer 10" since the thickness of each thinned semiconductor wafer 10' can be, for example, 12 microns, the total thickness of the chip is limited to 700 microns
  • up to 57 thinned semiconductor chip layers 10" can be stacked in the ultra-thin semiconductor stack structure 28 of the embodiment of the present invention, which can meet the requirements of high density and speed, and have better electrical characteristics and efficiency.
  • the substrate removal step and the stop layer removal step include three chemical mechanical polishing processes as an example for illustration, but it is not limited thereto.
  • the first/second thinning process includes a wet etching process and two chemical mechanical polishing processes, that is, in the substrate removal step, the above first chemical mechanical polishing process is replaced by a wet etching process, and the cross-sectional schematic diagram of the thinning process can still be Referring to FIG. 1H to FIG. 1K or FIG. 1N to FIG. 1Q, the remaining second part 124 of the substrate is firstly removed by a wet etching process to reveal the silicon nitride layer 14a.
  • the selection of silicon and silicon nitride in the wet etching process The ratio is, for example, 40, that is, Si/Si 3 N 4 is 40; then the second chemical mechanical polishing process and the third chemical mechanical polishing process are sequentially performed to sequentially remove the silicon nitride layer 14a and the silicon dioxide layer 16a remove.
  • the first/second thinning process can also be replaced by three plasma dry etching (plasma dry etching) processes, and the cross-sectional schematic diagram of the thinning process can still be referred to FIG. 1H to FIG. 1K or FIG. 1N to FIG. 1Q, the remaining second portion 124 of the substrate is removed by a first plasma dry etching process to expose the silicon nitride layer 14a.
  • plasma dry etching plasma dry etching
  • the first The selection ratio of silicon and silicon nitride in plasma dry etching is, for example, 80, that is, Si/Si 3 N 4 is 80; then, the silicon nitride layer 14a is removed by a second plasma dry etching process to reveal
  • the selection ratio of silicon nitride and silicon dioxide in the second plasma dry etching process is, for example, 20, that is, Si 3 N 4 /SiO 2 is 20;
  • the third plasma dry etching process removes the silicon dioxide layer 16a to expose the substrate first portion 123 and the TSV 24.
  • the selective ratio of silicon dioxide and silicon in the third plasma dry etching process If it is 5, that is, SiO 2 /Si is 5.
  • FIG. 1A to FIG. 1A show a second embodiment of the present invention, semiconductor ultra-thin stacking Schematic cross-sectional illustration of the fabrication method of the structure.
  • a plurality of semiconductor wafers 10 are firstly provided, the manufacturing steps of which have been disclosed in the above-mentioned FIG. 1A to FIG.
  • the first semiconductor wafer 10a (marked in FIG. 2B ), another part of the semiconductor wafer 10 is subjected to an electrical function test, and the crystal grains with good electrical functions are selected for singulation, as shown in FIG.
  • Each semiconductor chip 30 still includes an electrical element 20, an interconnection layer 22, and a semiconductor substrate 12.
  • a stop layer structure 18 is formed in the semiconductor substrate 12.
  • the stop layer structure 18 divides the semiconductor substrate 12 into a first part 123 of the substrate and a second part of the substrate.
  • the second part 124 is the first part 123 of the substrate and the TSV 24 is formed to connect the stop layer structure 18 and the interconnection layer 22 .
  • the plurality of semiconductor chips 30 are divided into the first batch of semiconductor chips 30 a and the second batch of semiconductor chips 30 b according to the sequence of the subsequent manufacturing process, and each batch includes a plurality of semiconductor chips 30 .
  • the first batch of semiconductor chips 30a is flipped relative to the first semiconductor wafer 10a, so that the interconnection layer 22 of the first batch of semiconductor chips 30a and the interconnection layer 22 of the first semiconductor wafer 10a are opposite and The interconnection points 221 correspond to each other; then, the first semiconductor wafer 10 a and the first batch of semiconductor chips 30 a are bonded together up and down by hybrid bonding technology, as shown in FIG. 2C .
  • a first molding (molding) process is carried out, as shown in FIG. 2D, a first packaging compound (molding compound) 32a is formed on the first semiconductor wafer 10a to cover the first batch of semiconductor chips 30a; after that, use the first
  • the back grinding process removes part of the first encapsulant 32a and a part of the second portion 124 of the substrate of the first batch of semiconductor chips 30a from the side of the first encapsulant 32a away from the first semiconductor wafer 10a, as shown in FIG. 2E, the first In the batch of semiconductor chips 30a, the second substrate portion 124 with an extremely thin thickness and the first encapsulant 32a flush with the second substrate portion 124 remain.
  • a first thinning process is performed, including the substrate removal step and the stop layer removal step described in the first embodiment, so as to remove the remaining second substrate portion 124, stop layer structure 18 and part of the first batch of semiconductor chips 30a
  • the encapsulant 32 as shown in FIG. 2F, exposes the first part 123 of the substrate and the through-silicon vias 24 of the first batch of semiconductor chips 30a, so that a thinned first semiconductor chip layer 30a' is formed, and the first semiconductor chip layer 30a' is stacked. on the first semiconductor wafer 10a.
  • the second batch of semiconductor chips 30b is still flipped relative to the first semiconductor wafer 10a, so that the interconnection layers 22 of the second batch of semiconductor chips 30b correspond to the substrate first part 123 of the first semiconductor chip layer 30a' respectively, and Carrying out the bonding of the second batch of semiconductor chips 30b and the first semiconductor chip layer 30a'; performing a second molding process to form a second encapsulant 32b on the first semiconductor chip layer 30a' to cover the second batch of semiconductor chips 30b; Carry out the backside grinding process and the thinning process, so as to remove part of the second encapsulant 32b and the second part of the substrate of the second batch of semiconductor chips 30b from the side of the second encapsulant 32b away from the first semiconductor chip layer 30a' (not shown ) and a stop layer structure (not shown), as shown in FIG.
  • a second back grinding process and a second thinning process are used to sequentially start from the back surface 122 of the first semiconductor wafer 10a Remove the second substrate portion 124 and the stop layer structure 18 of the first semiconductor wafer 10a, as shown in FIG. A stack of semiconductor chips 30.
  • the above-mentioned first and second thinning processes include the substrate removal step and the stop layer removal step described in the first embodiment, wherein the process selection for the substrate removal step and the stop layer removal step is, for example, three chemical mechanical polishing processes, or Whether it is a wet etching process combined with a chemical mechanical polishing process, or both are plasma dry etching processes, and the selection ratio between materials such as silicon, silicon nitride, and silicon dioxide has been described in the first embodiment, here No longer
  • solder balls are placed on the exposed through-silicon vias 24 of the thinned first semiconductor wafer 10 a ′, and after performing an electrical function test, along the first encapsulant 32 a and the second The dicing lines 321 of the encapsulant 32 b are singulated to complete the semiconductor ultra-thin stack structure 34 as shown in FIG. 2K .
  • the semiconductor ultra-thin stack structure 34 of this embodiment since the semiconductor chips 30 to be stacked have been tested and sorted for electrical functions, the yield rate of the semiconductor ultra-thin stack structure 34 is relatively high.
  • FIG. 3A to 3L are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a third embodiment of the present invention.
  • a carrier board 40 is provided, and a plurality of first conductive pillars 42 are formed on the carrier board 40, as shown in FIG. ) glass, the first conductive pillar 42 is, for example, a copper pillar.
  • each semiconductor chip 44 still includes an electrical element 20, an interconnection layer 22 and a semiconductor substrate 12.
  • a stop layer structure 18 is formed in the semiconductor substrate 12.
  • the stop layer structure 18 divides the semiconductor substrate 12 into a first part 123 of the substrate and a second part of the substrate. 124 , the first portion 123 of the substrate is formed with TSVs 24 for connecting the stop layer structure 18 and the interconnection layer 22 .
  • the thickness of the semiconductor substrate 12 is, for example, 775 microns
  • the thickness of the interconnection layer 22 is, for example, 10 microns.
  • the first batch of semiconductor chips picked are flip-chip bonded on the carrier board 40, as shown in FIG. 3B, taking the first batch of semiconductor chips 44 including three first semiconductor chips 44a as an example. have the same or different electrical functions, and the first conductive pillars 42 are interposed between adjacent first semiconductor chips 44a. 22 is adjacent to the carrier board 40 and the semiconductor substrate 12 is away from the carrier board 10 for flip-chip bonding.
  • a first molding process is performed.
  • a first encapsulant 46 a is formed on the carrier board 40 to cover the three first semiconductor chips 44 a and the first conductive pillars 42 .
  • a part of the first encapsulant 46a and the second substrate portion 124 and stop layer of the first semiconductor chip 44a are removed from the side of the first encapsulant 46a away from the carrier plate 40 by using the first back grinding process and the first thinning process.
  • the structure 18, as shown in FIG. 3D exposes the substrate first portion 123, the TSV 24, and the first conductive pillar 44, thus forming a thinned first semiconductor chip layer 44a'.
  • the setting of the second conductive column 48 is carried out.
  • the second conductive column 48 is vertically arranged on part of the TSV 24.
  • the second conductive pillar 48 is, for example, a copper pillar.
  • flip-chip the second batch of selected semiconductor chips between two adjacent thinned first semiconductor chips 44a as shown in FIG. 3F, taking the second batch of semiconductor chips including two second semiconductor chips 44b as an example , the two semiconductor chips 44b may have the same or different electrical functions.
  • the interconnection layer 22 of the second semiconductor chip 44b is opposite to the first part 123 of the substrate of the first semiconductor chip layer 44a', and the second semiconductor chip
  • the interconnection point 221 of the chip 44b is electrically connected to a portion of the TSV 24 and the first conductive pillar 42, and a portion of the second conductive pillar 48 is interposed between adjacent second semiconductor chips 44b.
  • the second molding process, the second back grinding process and the second thinning process are performed in order to form a second encapsulant 46b on the first semiconductor chip layer 44a' to cover the second semiconductor chip 44b and the second conductive
  • the second substrate portion 124 of the second semiconductor chip 44b, the stop structure layer 18, and part of the second encapsulant 46b are removed by a second back grinding process and a second thinning process, as shown in FIG. 3G , exposing the first portion 123 of the substrate, the TSVs 124 , and the second conductive pillars 48 , thus forming a thinned second semiconductor chip layer 44 b ′.
  • the arrangement of the third conductive pillar 50, the flip-chip arrangement of the third semiconductor chip 44c on the second semiconductor chip layer 44b', the encapsulation molding process, the back grinding process and the thinning process are repeated to complete the third semiconductor chip.
  • the stacking of chip layers 44c' is shown in FIG. 3H, and the stacking of more semiconductor chip layers is shown in FIG. 3I.
  • the carrier board 40 is removed, as shown in FIG. 3J , to expose the interconnection layer 22 and the first conductive pillar 42 of the first semiconductor chip layer, and the preset circuit contacts (not shown) of the interconnection layer 22 Solder balls 26 are disposed on the first conductive pillars, as shown in FIG. 3K , and singulated to complete the semiconductor ultra-thin stack structure 52 as shown in FIG. 3L .
  • the manufacture of the stop layer structure is to perform nitrogen ion and oxygen ion implantation successively, and perform high temperature treatment to form the silicon nitride layer and the second layer.
  • the silicon oxide layer is described as an example, but it is not limited thereto.
  • the stop layer structure may only include a silicon nitride layer, that is, a high-temperature treatment process is performed after the nitrogen ion implantation process is performed in the semiconductor substrate, so that A silicon nitride layer is formed at a depth of 1 to 5 microns from the active surface; correspondingly, only the silicon nitride layer needs to be removed in the stop layer removal step of the subsequent first/second thinning process, and the other subsequent processes are the same, No more details here.
  • a silicon nitride layer that is, a high-temperature treatment process is performed after the nitrogen ion implantation process is performed in the semiconductor substrate, so that A silicon nitride layer is formed at a depth of 1 to 5 microns from the active surface; correspondingly, only the silicon nitride layer needs to be removed in the stop layer removal step of the subsequent first/second thinning process, and the other subsequent processes are the same, No more details here.
  • the semiconductor substrate can be polished or etched to only Retain the first part of the substrate, that is, only retain the substrate thickness of 1 to 5 microns, so that the overall thickness of each semiconductor chip layer is not greater than 12 microns.
  • the semiconductor superconductor of the embodiment of the present invention Up to 50 layers of thinned semiconductor chips can be stacked in the thin stack structure 28 , which can meet the requirements of high density and speed, and has better electrical characteristics and efficiency.

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Abstract

一种半导体超薄堆叠结构的制造方法，包含以离子注入形成停止层结构于半导体基板内，再于半导体基板的主动面设置电气元件及内连层，以形成半导体晶圆；将两半导体晶圆的内连层相对且上下接合在一起；以背面研磨及薄化制程自上方半导体晶圆的背面去除上方半导体晶圆的部分半导体基板及停止层结构，使上方半导体晶圆形成薄化半导体晶圆，之后逐一在薄化半导体晶圆进行另一半导体晶圆的接合、背面研磨及薄化制程，而逐一往上堆叠另一薄化半导体晶圆，最后对最下方半导体晶圆进行背面研磨及薄化制程。此制造方法可堆叠多层薄化半导体晶圆，满足高积集度要求。

Description

半导体超薄堆叠结构的制造方法 技术领域
本发明涉及一种半导体结构的制造方法，尤其涉及一种半导体超薄堆叠结构的制造方法。
背景技术
随着电子产业的蓬勃发展，电子产品逐渐进入多功能、高性能的研发方向，其中半导体科技已广泛地应用于制造记忆体、中央处理单元等芯片组。为了达成高积集度(Integration)与高速度等目的，半导体集成电路的尺寸持续地缩减，目前已发展出多种不同的材料与技术以达成上述的积集度与速度要求，亦已研发出了包括多层基板(multiple substrates)的堆叠结构，借以改善电路的操作速度。当半导体平面封装相关技术到达极限，可借由集成化满足微小化的需求，堆叠晶圆的技术对未来科技有很大的助力，亦成为当前相关领域极需改进的目标。
发明内容
本发明提供了一种半导体超薄堆叠结构的制造方法，使半导体超薄堆叠结构可满足高积集度与速度要求，而具有更佳的电气特性及效率。
本发明所提供的半导体超薄堆叠结构的制造方法，包含：制造多个半导体晶圆，选择其中一半导体晶圆作为底层的第一半导体晶圆，部分的半导体晶圆则作为待堆叠的第二半导体晶圆及第三半导体晶圆，每一半导体晶圆的制造步骤包含：提供半导体基板，具有相对的主动面及背面；形成停止层结构于半导体基板内，将半导体基板分为基板第一部分及基板第二部分，其中基板第一部分位于停止层结构及主动面之间，基板第二部分位于停止层结构及背面之间，停止层结构至少包含氮化硅层，氮化硅层的制造包含先于半导体基板的第一深度进行氮离子注入制程，接着进行高温处理制程，使氮离子注入的区域形成氮化硅层；以及于主动面设置多个电气元件及内连层，内连层包含多个互连接点，并于基板第一部分设置多个导电结构连接内连层及停止层结构。将第二半导体晶圆相对于第一半导体晶圆倒装，使第一半导体晶圆的内连层及第二半导体晶圆的内连层相对且以混合键合技术接合在一起；进行第一背面研磨制程，自第二半导体晶圆的背面进行研磨，以移除第二半导体晶圆的基板第二部分的一部分；进 行第一薄化制程，以形成薄化第二半导体晶圆；进行第二背面研磨制程，自第一半导体晶圆的背面进行研磨，以移除第一半导体晶圆的基板第二部分的一部分；以及进行第二薄化制程，以形成薄化第一半导体晶圆，其中，第一薄化制程及第二薄化制程包含基板去除步骤及停止层去除步骤，其中基板去除步骤移除剩余的基板第二部分，以显露停止层结构；停止层去除步骤移除停止层结构，以显露基板第一部分及导电结构。
在本发明的一实施例中，在进行上述第二背面研磨制程之前，更可于薄化第二半导体晶圆上依序进行多个薄化第三半导体晶圆的堆叠，其中每一薄化第三半导体晶圆的堆叠步骤包含：将第三半导体晶圆相对于第一半导体晶圆倒装，使第三半导体晶圆的内连层及薄化第二半导体晶圆的基板第一部分相对且接合在一起；进行第三背面研磨制程，自第三半导体晶圆的背面进行研磨，以移除第三半导体晶圆的基板第二部分的一部分；以及进行第三薄化制程，包含基板去除步骤及停止层去除步骤。
在本发明的一实施例中，上述的停止层结构更包含二氧化硅层，二氧化硅层设置氮化硅层上，以介于氮化硅层及主动面之间。
在本发明的一实施例中，形成上述的二氧化硅层的步骤包含：于氮离子注入制程后，先在半导体基板的第二深度进行氧离子注入制程，且第二深度小于第一深度，之后再进行高温处理制程，使氧离子注入的区域形成二氧化硅层。
在本发明的一实施例中，上述的停止层去除步骤包含：先移除氮化硅层，再移除二氧化硅层。
在本发明的一实施例中，上述的基板去除步骤选自化学机械研磨、湿式蚀刻及电浆干式蚀刻其中之一，其中硅及氮化硅的选择比介于20至80之间。
在本发明的一实施例中，上述的氮化硅层及二氧化硅层的移除方法选自化学机械研磨及电浆干式蚀刻其中之一，其中氮化硅及二氧化硅的选择比介于10至20之间，二氧化硅及硅的选择比约为5。
在本发明的一实施例中，上述的停止层结构与主动面的距离介于1微米至5微米之间，薄化第二半导体晶圆的厚度不大于12微米。
在本发明的一实施例中，于形成上述的薄化第一半导体晶圆之后，更包含以下步骤：于薄化第一半导体晶圆的远离薄化第二半导体晶圆的一侧设置多个焊球，以分别电性连接导电结构；以及进行电性测试与切单。
本发明所提供的半导体超薄堆叠结构的制造方法，包含制造多个半导体晶圆，每一半导体晶圆的制造步骤包含：提供半导体基板，具有相对的主动面及背面；形成停止层结构于半导体基板内，将半导体基板分为基板第一部分及基板第二部分，其中基板第一部分位于停止层结构及主动面之间，基板第二部分位于停止层结构及背面之间， 停止层结构至少包含氮化硅层，氮化硅层的制造包含先于半导体基板的第一深度进行氮离子注入制程，接着进行高温处理制程，使氮离子注入的区域形成氮化硅层；以及于主动面设置多个电气元件及内连层，内连层包含多个互连接点，并于基板第一部分设置多个导电结构连接内连层及停止层结构。选择其中一半导体晶圆作为底层的第一半导体晶圆，部分的半导体晶圆则进行切单而作为待堆叠的第一批半导体芯片及至少一第二批半导体芯片；将第一批半导体芯片相对于第一半导体晶圆倒装，使第一批半导体芯片的内连层及第一半导体晶圆的内连层相对且以混合键合技术接合在一起；进行第一模制制程，以在第一半导体晶圆上形成第一封装胶体包覆第一批半导体芯片；进行第一背面研磨制程，自第一封装胶体远离第一半导体晶圆的一侧除去部分第一封装胶体以及移除第一批半导体芯片的基板第二部分的一部分；进行第一薄化制程，以形成第一半导体芯片层；进行第二背面研磨制程，自第一半导体晶圆的背面进行研磨，以移除第一半导体晶圆的基板第二部分的一部分；以及进行第二薄化制程，以形成薄化第一半导体晶圆，其中，第一薄化制程及第二薄化制程包含基板去除步骤及停止层去除步骤，其中基板去除步骤移除剩余的基板第二部分，以显露停止层结构，停止层去除步骤移除停止层结构，以显露基板第一部分及导电结构。
在本发明的一实施例中，在进行上述的第二背面研磨制程之前，更可于第一半导体芯片层上依序进行至少一第二半导体芯片层的堆叠，其中每一第二半导体芯片层的堆叠步骤包含：将第二批半导体芯片相对于第一半导体晶圆倒装，使第二批半导体芯片的内连层及第一半导体芯片层的基板第一部分相对且接合在一起；进行第二模制制程，以在第一半导体芯片层上形成第二封装胶体包覆第二批半导体芯片；进行第三背面研磨制程，自第二封装胶体远离第一半导体芯片层的一侧除去部分第二封装胶体以及移除第二批半导体芯片的基板第二部分的一部分；以及进行第三薄化制程，包含基板去除步骤及停止层去除步骤。
本发明所提供的半导体超薄堆叠结构的制造方法，包含：提供承载板，并于承载板上形成多个第一导电柱。提供多个半导体芯片，每一半导体芯片的制造步骤包含：提供半导体基板，具有相对的主动面及背面；形成停止层结构于半导体基板内，将半导体基板分为基板第一部分及基板第二部分，其中基板第一部分位于停止层结构及主动面之间，基板第二部分位于停止层结构及背面之间，停止层结构至少包含氮化硅层，氮化硅层的制造包含先于半导体基板的第一深度进行氮离子注入制程，接着进行高温处理制程，使氮离子注入的区域形成氮化硅层；于主动面设置多个电气元件及内连层，内连层包含多个互连接点，并于基板第一部分设置多个导电结构连接内连层及停止层结构；以及进行切单。从半导体芯片拣选出第一批半导体芯片及至少一第二批半导体 芯片，第一批半导体芯片包含多个第一半导体芯片，第二批半导体芯片包含多个第二半导体芯片。倒装设置第一批半导体芯片于承载板上，且第一导电柱介于相邻的第一半导体芯片之间，其中第一批半导体芯片的内连层邻近承载板且半导体基板远离承载板。进行第一模制制程，以在承载板上形成第一封装胶体包覆第一批半导体芯片及第一导电柱。进行第一背面研磨制程，自第一封装胶体远离承载板的一侧除去部分第一封装胶体以及移除第一批半导体芯片的基板第二部分的一部分。进行第一薄化制程以形成第一半导体芯片层，第一薄化制程包含依序移除第一批半导体芯片的剩余的基板第二部分以及停止层结构，以显露基板第一部分、导电结构以及第一导电柱。设置多个第二导电柱，以电性连接第一半导体芯片层的部分导电结构。倒装设置第二批半导体芯片于第一半导体芯片层上，其中第二半导体芯片分别跨接在相邻的第一半导体芯片之间，使第二半导体芯片的内连层电性连接显露的第一导电柱及第一半导体芯片层的部分导电结构，且部分第二导电柱介于相邻的第二半导体芯片之间。进行第二模制制程，以在第一半导体芯片层上形成第二封装胶体包覆第二批半导体芯片及第二导电柱。进行第二背面研磨制程，自第二封装胶体远离第一半导体芯片层的一侧除去部分第二封装胶体以及移除第二批半导体芯片的基板第二部分的一部分。进行第二薄化制程以形成第二半导体芯片层，第二薄化制程包含依序移除第二批半导体芯片的剩余的基板第二部分以及停止层结构，以显露基板第一部分、导电结构以及第二导电柱。移除承载板，以显露第一半导体芯片层的内连层及第一导电柱。
在本发明的一实施例中，于移除上述的承载板之后，更包含以下步骤：于第一半导体芯片层的远离第二半导体芯片层的一侧设置多个焊球，以分别电性连接内连层及第一导电柱；以及进行切单。
在本发明的一实施例中，上述的第一批半导体芯片的多个第一半导体芯片具有不同的电性功能。
在本发明的一实施例中，上述的第二批半导体芯片的第二半导体芯片具有不同的电性功能。
本发明在制造半导体晶圆时，先以离子注入制程形成停止层结构于半导体基板内，再于半导体基板的主动面设置电气元件及内连层；之后将两半导体晶圆进行上下接合，亦或将半导体晶圆进行切单以形成多个半导体芯片后，使批次的半导体芯片与最底层的半导体晶圆进行结合。每进行一次半导体晶圆/芯片的接合(及模制封装胶体)后，以背面研磨及薄化制程自上方半导体晶圆/芯片的背面去除上方半导体晶圆/芯片的部分半导体基板及停止层结构，使上方半导体晶圆/芯片形成薄化半导体晶圆/半导体芯片层，之后逐一在薄化半导体晶圆/芯片进行另一半导体晶圆/芯片的接合(及模制封装胶 体)、背面研磨及薄化制程，而往上堆叠另一薄化半导体晶圆/半导体芯片层，最后对最下方半导体晶圆进行背面研磨及薄化制程。由于每一薄化半导体晶圆/半导体芯片层厚度不大于12微米，在芯片总厚度限制为700微米的限制下，可堆叠至57层芯片层，进而满足高积集度与速度要求。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图,详细说明如下。
附图说明
图1A至图1S所示是本发明一第一实施例半导体超薄堆叠结构的制造方法的剖面示意图。
图2A至图2K所示是本发明一第二实施例半导体超薄堆叠结构的制造方法的剖面示意图。
图3A至图3L所示是本发明一第三实施例半导体超薄堆叠结构的制造方法的剖面示意图。
具体实施方式
图1A至图1S所示是本发明一第一实施例半导体超薄堆叠结构的制造方法的剖面示意图。首先，制造多个半导体晶圆10(标示于图1E)，选择其中一个半导体晶圆10作为堆叠底层的第一半导体晶圆10a(标示于图1F)，其他的半导体晶圆10则作为待堆叠的第二半导体晶圆10b(标示于图1F)及第三半导体晶圆10c(标示于图1L)，多个半导体晶圆10的制造过程相同或相近，图1A至图1E所示即为制造半导体晶圆10的剖面示意图。如图1A所示，提供半导体基板12，半导体基板12例如硅基板(silicon substrate)、磊晶硅基板(epitaxial silicon substrate)、硅锗基板(silicon germanium substrate)、碳化硅基板(silicon carbide substrate)或硅覆绝缘(silicon on insulation，SOI)基板，于一实施例中，半导体基板的厚度例如为700至800微米(um)，较佳者为775微米，半导体基板12具有相对的主动面121及背面122。
接着，形成停止层结构于半导体基板12内。于一实施例中，停止层结构的制造包含进行至少一离子注入制程及高温处理制程。于一实施例中，离子注入制程包含先进行氮离子注入，再进行氧离子注入。如图1B及图1C所示，先在半导体基板12的第一深度D1进行氮离子注入制程14，再于半导体基板12的第二深度D2进行氧离子注入制程16，于一实施例中，氮离子注入区14’的第一深度D1为距离主动面121例如约1 至5微米的深度，氧离子注入区16’的第二深度D2则较氮离子注入区14的第一深度D1小，亦即氧离子注入区16’较为靠近主动面121。
之后进行高温处理，如图1D所示，在氮离子注入区14’形成氮化硅(Si 3N 4)层14a，在氧离子注入区16’形成二氧化硅(SiO 2)层16a，其中，二氧化硅层16a较为邻近主动面121，氮化硅层14a较为邻近背面122，于此实施例中，氮化硅层14a及二氧化硅层16a即构成上述的停止层结构18，其中，二氧化硅层16a位于氮化硅层14上且介于氮化硅层14a及主动面121之间。于一实施例中，氮化硅层14a及二氧化硅层16a的厚度例如为500纳米(nm)。又便于说明，将停止层结构18的二氧化硅层16a至主动面121之间的半导体基板12称为基板第一部分123，停止层结构18的氮化硅层14a至背面122之间的半导体基板12称为基板第二部分124。于一实施例中，当半导体晶圆10后续是应用在金属氧化物半导体场效晶体管(MOSFET)的制作时，则为配合一般N型井(Nwell)的深度约为2微米，因此基板第一部分123的厚度应保留在不低于2微米的前提下，亦即在进行上述氮离子注入制程14及氧离子注入制程16时，氮离子注入区14’的第一深度D1及氧离子注入区16’的第二深度皆应略大于2微米。
接续上述说明，如图1E所示，于主动面121设置有多个电气元件20及具有互连接点221的内连层22，电气元件20例如包含金属氧化物半导体(MOS)，并于基板第一部分123设置多个导电结构，于一实施例中，导电结构例如包含硅穿孔(Through Silicon Via，TSV)24，硅穿孔24垂直连接内连层22及停止层结构18的二氧化硅层16a。其中电气元件20、内连层22及硅穿孔24的制造流程包含一般半导体制程的前段制程(front-end-of-line，FEOL)及后段制程(back-end-of-line，BEOL)，前段制程例如在半导体基板12上作出电阻、电容、二极管、晶体管等元件，后段制程例如在各个元件之间做出连接用金属布线及互连接点221；于一实施例中互连接点221例如为铜接点。图1E所示即为本发明一实施例的半导体晶圆10示意图，以下说明的第一半导体晶圆10a、第二半导体晶圆10b及第三半导体晶圆10c沿用半导体晶圆10描述所用的元件符号。其中第一半导体晶圆10a的硅穿孔24的位置例如对应于后续制程中焊球的安装位置，第二半导体晶圆10b的硅穿孔24的位置例如与第三半导体晶圆10c的内连层22的互连接点221对应。
如图1F所示，将第二半导体晶圆10b相对于第一半导体晶圆10a倒装，使第一半导体晶圆10a及第二半导体晶圆10b的内连层22相对且互连接点221各自对应；接着以混合键合技术(Hybrid bonding)，如图1G所示，使第一半导体晶圆10a及第二半导体晶圆10b上下堆叠在一起，其中混合键合技术包含铜对铜接合及回火等制程。
接着，利用第一背面研磨(Grind)制程自第二半导体晶圆10b的背面122进行研磨， 以除去第二半导体晶圆10b的基板第二部分124的一部分，如图1H所示，残留厚度极薄的基板第二部分124，于一实施例中，残留的基板第二部分124得厚度约为20。
之后，进行第一薄化制程，以形成一薄化第二半导体晶圆，第一薄化制程包含基板去除步骤以及停止层去除步骤，图1I至图1K所示即为第一薄化制程的示意图。基板去除步骤用以移除残留的基板第二部分124，如图1I所示，以显露出停止层结构18，例如为显露氮化硅层14a，于一实施例中，基板去除步骤为第一化学机械研磨(CMP)制程，其中，硅及氮化硅的选择比例如为20，亦即Si/Si 3N 4为20；停止层去除步骤为用以移除停止层结构18，亦即依序移除氮化硅层14a以及二氧化硅层16a，以显露基板第一部分123及硅穿孔24；于一实施例中，先以第二化学机械研磨制程移除氮化硅层14a，如图1J所示，以显露二氧化硅层16a，其中氮化硅及二氧化硅的选择比例如为10，亦即Si 3N 4/SiO 2为10；再以第三化学机械研磨制程移除二氧化硅层16a，如图1K所示，以显露基板第一部分123及硅穿孔24，其中二氧化硅及硅的选择比例如为5，亦即SiO 2/Si为5。借由基板第一部分123及硅穿孔24的显露，而形成薄化的第二半导体晶圆10b’。
接续上述说明，上述已完成第一半导体晶圆10a及薄化第二半导体晶圆10b’的堆叠；接着，如图1L所示，将第三半导体晶圆10c相对于第一半导体晶圆10a倒装，使第三半导体晶圆10c的内连层22面对薄化第二半导体晶圆10b’的基板第一部分123，于一实施例中，第三半导体晶圆10c的内连层22的互连接点221分别对应于薄化第二半导体晶圆10b’的硅穿孔24。之后，重复上述第一背面研磨制程及第一薄化制程，以完成薄化第三半导体晶圆10c’及薄化第二半导体晶圆10b’的堆叠，于一实施例中，薄化第二半导体晶圆10b’或薄化第三半导体晶圆10c’的厚度例如为12微米。如此，在具有多个半导体晶圆10的前提下，逐个重复进行上述半导体晶圆10的接合制程、第一背面研磨制程及第一薄化制程，即可完成多层薄化半导体晶圆10’与第一半导体晶圆10a的堆叠，如图1M所示，于一实施例中，作为堆叠在最上方的薄化半导体晶圆10’，其基板第一部分123可不需形成有硅穿孔24。
在完成预定数目的多个薄化半导体晶圆10’的堆叠之后，利用第二背面研磨制程自第一半导体晶圆10a的背面122进行研磨，如图1N所示，以除去第一半导体晶圆10a的基板第二部分124的一部分，而残留厚度极薄的基板第二部分124；接着，进行第二薄化制程，如图1O至图1Q所示，利用上述基板去除步骤及停止层去除步骤，以依序移除第一半导体晶圆10a残留的基板第二部分124、氮化硅层14a及二氧化硅层16a，进而显露薄化第一半导体晶圆10a’的基板第一部分123及硅穿孔24，如此完成薄化第一半导体晶圆10a’、薄化第二半导体晶圆10b’、薄化第三半导体晶圆10c’...... 等多个薄化半导体晶圆10’的堆叠。
之后，如图1R所示，于薄化第一半导体晶圆10a’的远离薄化第二半导体晶圆10b’的一侧设置多个焊球26，以分别电性连接显露的硅穿孔24；并于进行晶圆针测(Chip Probing，CP)，以进行电性功能上的测试(Test)后，进行切单(die saw)，以完成如图1S所示的半导体超薄堆叠结构28，其中每一层薄化半导体晶圆10’切单后作为一半导体芯片层10”，由于每一薄化半导体晶圆10’的厚度可例如为12微米，在芯片总厚度限制为700微米的限制下，本发明实施例半导体超薄堆叠结构28中可堆叠至57层薄化半导体芯片层10”，可满足高积集度与速度要求，而具有更佳的电气特性及效率。
又在上述第一薄化制程及第二薄化制程中，是以基板去除步骤及停止层去除步骤共包含三道化学机械研磨制程为例进行说明，惟不限于此，于又一实施例中，第一/第二薄化制程包含一湿式蚀刻制程及二化学机械研磨制程，亦即在基板去除步骤中，以湿式蚀刻制程取代上述第一化学机械研磨制程，薄化制程的剖面示意图仍可参阅图1H至图1K或者图1N至图1Q所示，先以湿式蚀刻制程移除残留的基板第二部分124，以显露出氮化硅层14a，湿式蚀刻制程中硅及氮化硅的选择比例如为40，亦即Si/Si 3N 4为40；再依序进行第二化学机械研磨制程及第三化学机械研磨制程，以依序将氮化硅层14a及二氧化硅层16a移除。
又于另一实施例中，第一/第二薄化制程亦可以三道电浆干式蚀刻(plasma dry etching)制程取代上述三道化学机械研磨制程，薄化制程的剖面示意图仍可参阅图1H至图1K或者图1N至图1Q所示，先以第一电浆干式蚀刻制程移除残留的基板第二部分124，以显露出氮化硅层14a，于一实施例中，第一电浆干式蚀刻中硅及氮化硅的选择比例如为80，亦即Si/Si 3N 4为80；接着，以第二电浆干式蚀刻制程移除氮化硅层14a，以显露二氧化硅层16a，于一实施例中，第二电浆干式蚀刻制程中氮化硅及二氧化硅的选择比例如为20，亦即Si 3N 4/SiO 2为20；接着，以第三电浆干式蚀刻制程移除二氧化硅层16a，以显露基板第一部分123及硅穿孔24，于一实施例中，第三电浆干式蚀刻制程中二氧化硅及硅的选择比例如为5，亦即SiO 2/Si为5。
在上述第一实施例中，是以晶圆堆叠晶圆(Wafer on Wafer，WoW)的方式进行，惟不限于此，图2A至图2K所示是本发明一第二实施例半导体超薄堆叠结构的制造方法的剖面示意图。于此第二实施例中，先提供多个半导体晶圆10，其制造步骤已揭示于上述图1A至图1E所示，于此不再赘述；接着，选择其中一部分半导体晶圆10作为底层的第一半导体晶圆10a(标示于图2B)，另一部分半导体晶圆10则进行电性功能测试，拣选电性功能良好的晶粒进行切单，如图2A所示，以获得多个半导体芯片30，每 一半导体芯片30仍包含电气元件20、内连层22及半导体基板12，半导体基板12中形成有停止层结构18，停止层结构18将半导体基板12分为基板第一部分123及基板第二部分124，基板第一部分123并形成有硅穿孔24，以连接停止层结构18及内连层22。底下为便于说明，将多个半导体芯片30依后续制程的先后顺序区分为第一批半导体芯片30a及及第二批半导体芯片30b，每一批中包含多个半导体芯片30。
如图2B所示，将第一批半导体芯片30a相对于第一半导体晶圆10a倒装，使第一批半导体芯片30a的内连层22及第一半导体晶圆10a的内连层22相对且互连接点221各自对应；接着以混合键合技术，如图2C所示，使第一半导体晶圆10a及第一批半导体芯片30a上下接合在一起。
接着，进行第一模制(molding)制程，如图2D所示，在第一半导体晶圆10a上形成第一封装胶体(molding compound)32a包覆第一批半导体芯片30a；之后，利用第一背面研磨制程自第一封装胶体32a远离第一半导体晶圆10a的一侧除去部分第一封装胶体32a以及第一批半导体芯片30a的基板第二部分124的一部分，如图2E所示，第一批半导体芯片30a残留厚度极薄的基板第二部分124以及与基板第二部分124平齐的第一封装胶体32a。
之后，进行第一薄化制程，包含第一实施例所述的基板去除步骤以及停止层去除步骤，借以移除第一批半导体芯片30a的残留的基板第二部分124、停止层结构18及部分的封装胶体32，如图2F所示，显露第一批半导体芯片30a的基板第一部分123及硅穿孔24，如此即形成薄化的第一半导体芯片层30a’，第一半导体芯片层30a’堆叠于第一半导体晶圆10a上。
接着，将第二批半导体芯片30b仍然相对于第一半导体晶圆10a倒装，使第二批半导体芯片30b的内连层22分别对应于第一半导体芯片层30a’的基板第一部分123，并进行第二批半导体芯片30b与第一半导体芯片层30a’的接合；进行第二模制制程，以在第一半导体芯片层30a’上形成第二封装胶体32b包覆第二批半导体芯片30b；进行背面研磨制程及薄化制程，借以自第二封装胶体32b远离第一半导体芯片层30a’的一侧除去部分第二封装胶体32b、第二批半导体芯片30b的基板第二部分(未绘示)及停止层结构(未绘示)，如图2G所示，显露第二批半导体芯片30b的基板第一部分123及硅穿孔24，以形成薄化的第二半导体芯片层30b’。如此，逐批重复进行上述批次半导体芯片30的接合制程、模制制程、背面研磨制程及第一薄化制程，即可完成第一半导体芯片层30a’及多层第二半导体芯片层30b’与第一半导体晶圆10a的堆叠，如图2H所示，于一实施例中，作为堆叠在最上方的第二半导体芯片层30b’，其基板第一部分123可不需形成有硅穿孔24。
接着，与第一实施例相同地，在完成预定数目的第二半导体芯片层30b’的堆叠之后，利用第二背面研磨制程及第二薄化制程自第一半导体晶圆10a的背面122依序除去第一半导体晶圆10a的基板第二部分124及停止层结构18，如图2I所示，以显露基板第一部分123及硅穿孔24，如此完成薄化的第一半导体晶圆10a’及多个半导体芯片30的堆叠。
上述第一及第二薄化制程包含第一实施例所述的基板去除步骤以及停止层去除步骤，其中对于基板去除步骤以及停止层去除步骤的制程选择，例如是三道化学机械研磨制程、或是湿式蚀刻制程搭配化学机械研磨制程、或者皆为电浆干式蚀刻制程，以及对于硅、氮化硅及二氧化硅等材料之间选择比的采用已叙述于第一实施例中，于此不再赘述
之后，如图2J所示，于薄化第一半导体晶圆10a’的显露的硅穿孔24上设置焊球，并于进行电性功能上的测试后，沿着第一封装胶体32a及第二封装胶体32b的切割道321进行切单，以完成如图2K所示的半导体超薄堆叠结构34。在此实施例半导体超薄堆叠结构34中，由于进行堆叠的半导体芯片30已先进行电性功能的测试及拣选，因此半导体超薄堆叠结构34的良率较高。
图3A至图3L所示是本发明一第三实施例半导体超薄堆叠结构的制造方法的剖面示意图。于第三实施例中，首先，提供一承载板40，并于承载板40上形成多个第一导电柱42，如图3A所示，承载板40例如为厚度500微米且长度301毫米(mm)的玻璃，第一导电柱42例如为铜柱。
接着，拣选多个经电性功能测试的半导体芯片44(标示于图3B)，半导体芯片44可具有相同或不同的电性功能，多种半导体芯片44为经由分别对多种半导体晶圆10进行切单而来，而每一种半导体晶圆10的制造步骤已揭示于上述图1A至图1E所示，于此不再赘述。每一半导体芯片44仍包含电气元件20、内连层22及半导体基板12，半导体基板12中形成有停止层结构18，停止层结构18将半导体基板12分为基板第一部分123及基板第二部分124，基板第一部分123并形成有硅穿孔24，以连接停止层结构18及内连层22。于一实施例中，半导体基板12的厚度例如为775微米，内连层22的厚度例如为10微米。
将拣选的第一批半导体芯片倒装接合于承载板40上，如图3B所示，以第一批的半导体芯片44包含三个第一半导体芯片44a为例，三个第一半导体芯片44a可具有相同或不同的电性功能，且第一导电柱42介于相邻第一半导体芯片44a之间，于一实施例中，在进行第一半导体芯片44a的倒装接合时，是以内连层22邻近承载板40且半导体基板12远离承载板10的倒装方式进行接合。
之后，进行第一模制制程，如图3C所示，在承载板40上形成第一封装胶体46a包覆三个第一半导体芯片44a及第一导电柱42。接着，利用上述第一背面研磨制程及第一薄化制程自第一封装胶体46a远离承载板40的一侧除去部分第一封装胶体46a以及第一半导体芯片44a的基板第二部分124及停止层结构18，如图3D所示，显露基板第一部分123与硅穿孔24、以及第一导电柱44，如此即形成薄化的第一半导体芯片层44a’。
之后，进行第二导电柱48的设置，第二导电柱48例如为垂直设置在部分硅穿孔24上，如图3E所示，每一薄化的第一半导体芯片44a的至少一硅穿孔24上设置有第二导电柱48，第二导电柱48例如为铜柱。之后将拣选的第二批半导体芯片倒装跨接在相邻两薄化的第一半导体芯片44a之间，如图3F所示，以第二批半导体芯片包含两个第二半导体芯片44b为例，两个半导体芯片44b可具有相同或不同的电性功能，于一实施例中，第二半导体芯片44b的内连层22与第一半导体芯片层44a’的基板第一部分123相对，第二半导体芯片44b的互连接点221与部分硅穿孔24及第一导电柱42形成电性连接，且部分第二导电柱48介于相邻的第二半导体芯片44b之间。
接着，依序进行第二模制制程、第二背面研磨制程及第二薄化制程，以在第一半导体芯片层44a’上形成第二封装胶体46b包覆第二半导体芯片44b及第二导电柱48后，再以第二背面研磨制程及第二薄化制程移除第二半导体芯片44b的基板第二部分124、停止结构层18、以及部分的第二封装胶体46b，如图3G所示，显露基板第一部分123与硅穿孔124、以及第二导电柱48，如此即形成薄化的第二半导体芯片层44b’。
如此，重复地进行第三导电柱50的设置、第三半导体芯片44c倒装设置于第二半导体芯片层44b’上、封胶模制制程、背面研磨制程及薄化制程，以完成第三半导体芯片层44c’的堆叠，如图3H所示，以及陆续更多层半导体芯片层的堆叠，如图3I所示。
之后，移除承载板40，如图3J所示，以显露第一半导体芯片层的内连层22以及第一导电柱42，且在内连层22所预设的电路接点(未绘示)及第一导电柱上设置焊球26，如图3K所示，并进行切单，以完成如图3L所示的半导体超薄堆叠结构52。
在上述第一/第二/第三实施例半导体超薄堆叠结构的制造方法中，停止层结构的制造是以先后进行氮离子及氧离子注入，并进行高温处理以形成氮化硅层及二氧化硅层为例进行说明，惟不限于此，于一实施例中，停止层结构可仅包含氮化硅层，亦即在半导体基板内进行氮离子注入制程后即进行高温处理制程，以便在距离主动面1至5微米的深度形成氮化硅层；则对应地，后续第一/第二薄化制程的停止层去除步骤仅需对氮化硅层进行移除，其他后续制程则相同，于此不再赘述。
在本发明实施例中，借由停止层结构的形成于半导体基板的一深度，以及后续薄 化制程中基板移除步骤及停止层结构的逐步进行，使得半导体基板可确实被研磨或蚀刻至仅保留基板第一部分，亦即仅保留1至5微米的基板厚度，而使得每一半导体芯片层的整体厚度不大于12微米，在芯片总厚度限制为700微米的限制下，本发明实施例半导体超薄堆叠结构28中可堆叠至50多层薄化半导体芯片层，可满足高积集度与速度要求，而具有更佳的电气特性及效率。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内，当可利用上述揭示的方法及技术内容作出些许的更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (16)

  1. 一种半导体超薄堆叠结构的制造方法，其特征在于，包含：
    制造多个半导体晶圆，选择该些半导体晶圆其中之一作为底层的一第一半导体晶圆，其他部分的该些半导体晶圆则作为待堆叠的一第二半导体晶圆及至少一第三半导体晶圆，每一该些半导体晶圆的制造步骤包含：提供一半导体基板，具有相对的一主动面及一背面；形成一停止层结构于该半导体基板内，将该半导体基板分为一基板第一部分及一基板第二部分，其中该基板第一部分位于该停止层结构及该主动面之间，该基板第二部分位于该停止层结构及该背面之间，该停止层结构至少包含一氮化硅层，该氮化硅层的制造包含先于该半导体基板的一第一深度进行一氮离子注入制程，接着进行一高温处理制程，使该氮离子注入的区域形成该氮化硅层；以及于该主动面设置多个电气元件以一内连层，该内连层包含多个互连接点，并于该基板第一部分设置多个导电结构连接该内连层及该停止层结构；
    将该第二半导体晶圆相对于该第一半导体晶圆倒装，使该第一半导体晶圆的该内连层及该第二半导体晶圆的该内连层相对且以一混合键合技术接合在一起；
    进行一第一背面研磨制程，自该第二半导体晶圆的该背面进行研磨，以移除该第二半导体晶圆的该基板第二部分的一部分；
    进行一第一薄化制程，以形成一薄化第二半导体晶圆；
    进行一第二背面研磨制程，自该第一半导体晶圆的背面进行研磨，以移除该第一半导体晶圆的该基板第二部分的一部分；以及
    进行一第二薄化制程，以形成一薄化第一半导体晶圆，其中，该第一薄化制程及该第二薄化制程包含：一基板去除步骤，移除剩余的该基板第二部分，以显露该停止层结构；以及一停止层去除步骤，移除该停止层结构，以显露该基板第一部分及该些导电结构。
  2. 如权利要求1所述的半导体超薄堆叠结构的制造方法，其特征在于，在进行该第二背面研磨制程之前，更可于该薄化第二半导体晶圆上依序进行多个薄化第三半导体晶圆的堆叠，其中每一该些薄化第三半导体晶圆的堆叠步骤包含：
    将该第三半导体晶圆相对于该第一半导体晶圆倒装，使该第三半导体晶圆的该内连层及该薄化第二半导体晶圆的该基板第一部分相对且接合在一起；
    进行一第三背面研磨制程，自该第三半导体晶圆的该背面进行研磨，以移除该第三半导体晶圆的该基板第二部分的一部分；以及
    进行一第三薄化制程，包含该该基板去除步骤及该停止层去除步骤。
  3. 如权利要求1所述的半导体超薄堆叠结构的制造方法，其特征在于，该停止层结构更包含一二氧化硅层，该二氧化硅层设置在该氮化硅层上，以介于该氮化硅层及该主动面之间。
  4. 如权利要求3所述的半导体超薄堆叠结构的制造方法，其特征在于，形成该二氧化硅层的步骤包含：于该氮离子注入制程后，先在该半导体基板的一第二深度进行一氧离子注入制程，且该第二深度小于该第一深度，之后再进行该高温处理制程，使该氧离子注入的区域形成该二氧化硅层。
  5. 如权利要求4所述的半导体超薄堆叠结构的制造方法，其特征在于，该停止层去除步骤包含：先移除该氮化硅层，再移除该二氧化硅层。
  6. 如权利要求5所述的半导体超薄堆叠结构的制造方法，其特征在于，该基板去除步骤选自化学机械研磨、湿式蚀刻及电浆干式蚀刻其中之一，其中硅及氮化硅的选择比介于20至80之间。
  7. 如权利要求5所述的半导体超薄堆叠结构的制造方法，其特征在于，该氮化硅层及该二氧化硅层的移除方法选自化学机械研磨及电浆干式蚀刻其中之一，其中氮化硅及二氧化硅的选择比介于10至20之间，二氧化硅及硅的选择比为5。
  8. 如权利要求1所述的半导体超薄堆叠结构的制造方法，其特征在于，该停止层结构与该主动面的距离介于1微米至5微米之间，该薄化第二半导体晶圆的厚度不大于12微米。
  9. 如权利要求1所述的半导体超薄堆叠结构的制造方法，其特征在于，于形成该薄化第一半导体晶圆之后，更包含以下步骤：
    于该薄化第一半导体晶圆的远离该薄化第二半导体晶圆的一侧设置多个焊球，以分别电性连接该些导电结构；以及
    进行电性测试与切单。
  10. 一种半导体超薄堆叠结构的制造方法，其特征在于，包含：
    制造多个半导体晶圆，每一该些半导体晶圆的制造步骤包含：提供一半导体基板，具有相对的一主动面及一背面；形成一停止层结构于该半导体基板内，将该半导体基板分为一基板第一部分及一基板第二部分，其中该基板第一部分位于该停止层结构及该主动面之间，该基板第二部分位于该停止层结构及该背面之间，该停止层结构至少包含一氮化硅层，该氮化硅层的制造包含先于该半导体基板的一第一深度进行一氮离子注入制程，接着进行一高温处理制程，使该氮离子注入的区域形成该氮化硅层；以及于该主动面设置多个电气元件以一内连层，该内连层包含多个互连接点，并于该基板第一部分设置多个导电结构连接该内连层及该停止层结构；
    选择该些半导体晶圆其中之一作为底层的一第一半导体晶圆，其他部分的该些半导体晶圆则进行切单而作为待堆叠的一第一批半导体芯片及至少一第二批半导体芯片；
    将该第一批半导体芯片相对于该第一半导体晶圆倒装，使该第一批半导体芯片的该内连层及该第一半导体晶圆的该内连层相对且以一混合键合技术接合在一起；
    进行一第一模制制程，以在该第一半导体晶圆上形成一第一封装胶体包覆该第一批半导体芯片；
    进行一第一背面研磨制程，自该第一封装胶体远离该第一半导体晶圆的一侧除去部分该第一封装胶体以及移除该第一批半导体芯片的该基板第二部分的一部分；
    进行一第一薄化制程，以形成一第一半导体芯片层；
    进行一第二背面研磨制程，自该第一半导体晶圆的该背面进行研磨，以移除该第一半导体晶圆的该基板第二部分的一部分；以及
    进行一第二薄化制程，以形成一薄化第一半导体晶圆，其中，该第一薄化制程及该第二薄化制程包含：一基板去除步骤，移除剩余的该基板第二部分，以显露该停止层结构；以及一停止层去除步骤，移除该停止层结构，以显露该基板第一部分及该些导电结构。
  11. 如权利要求10所述的半导体超薄堆叠结构的制造方法，其特征在于，在进行该第二背面研磨制程之前，更可于该第一半导体芯片层上依序进行至少一第二半导体芯片层的堆叠，其中每一该些第二半导体芯片层的堆叠步骤包含：
    将该至少一该第二批半导体芯片相对于该第一半导体晶圆倒装，使该至少一第二批半导体芯片的该内连层及该第一半导体芯片层的该基板第一部分相对且接合在一起；
    进行一第二模制制程，以在该第一半导体芯片层上形成一第二封装胶体包覆该第二批半导体芯片；
    进行一第三背面研磨制程，自该第二封装胶体远离该第一半导体芯片层的一侧除去部分该第二封装胶体以及移除该第二批半导体芯片的该基板第二部分的一部分；以及
    进行一第三薄化制程，包含该基板去除步骤及该停止层去除步骤。
  12. 如权利要求10所述的半导体超薄堆叠结构的制造方法，其特征在于，于形成该薄化第一半导体晶圆之后，更包含以下步骤：
    于该薄化第一半导体晶圆的远离该第一半导体芯片层的一侧设置多个焊球，以分别电性连接该些导电结构；以及进行电性测试与切单。
  13. 一种半导体超薄堆叠结构的制造方法，其特征在于，包含：
    提供一承载板，并于该承载板上形成多个第一导电柱；
    提供多个半导体芯片，每一该些半导体芯片的制造步骤包含：提供一半导体基板，具有相对的一主动面及一背面；形成一停止层结构于该半导体基板内，将该半导体基板分为一基板第一部分及一基板第二部分，其中该基板第一部分位于该停止层结构及该主动面之间，该基板第二部分位于该停止层结构及该背面之间，该停止层结构至少包含一氮化硅层，该氮化硅层的制造包含先于该半导体基板的一第一深度进行一氮离子注入制程，接着进行一高温处理制程，使该氮离子注入的区域形成该氮化硅层；于该主动面设置多个电气元件以及一内连层，该内连层包含多个互连接点，并于该基板第一部分设置多个导电结构连接该内连层及该停止层结构；以及进行切单；
    从该些半导体芯片拣选出一第一批半导体芯片及至少一第二批半导体芯片，该第一批半导体芯片包含多个第一半导体芯片，该至少一第二批半导体芯片包含多个第二半导体芯片；
    倒装设置该第一批半导体芯片于该承载板上，且该些第一导电柱介于相邻的该些第一半导体芯片之间，其中该第一批半导体芯片的该内连层邻近该承载板且该半导体基板远离该承载板；
    进行一第一模制制程，以在该承载板上形成一第一封装胶体包覆该第一批半导体芯片及该些第一导电柱；
    进行一第一背面研磨制程，自该第一封装胶体远离该承载板的一侧除去部分该第一封装胶体以及移除该第一批半导体芯片的该基板第二部分的一部分；
    进行一第一薄化制程以形成一第一半导体芯片层，该第一薄化制程包含依序移除该第一批半导体芯片的剩余的该基板第二部分以及该停止层结构，以显露该基板第一部分、该些导电结构以及该些第一导电柱；
    设置多个第二导电柱，以电性连接该第一半导体芯片层的部分该些导电结构；
    倒装设置该第二批半导体芯片于该第一半导体芯片层上，其中该些第二半导体芯片分别跨接在相邻的该些第一半导体芯片之间，使该些第二半导体芯片的该些内连层电性连接显露的该些第一导电柱及该第一半导体芯片层的部分该些导电结构，且部分该些第二导电柱介于相邻的该些第二半导体芯片之间；
    进行一第二模制制程，以在该第一半导体芯片层上形成一第二封装胶体包覆该第二批半导体芯片及该些第二导电柱；
    进行一第二背面研磨制程，自该第二封装胶体远离该第一半导体芯片层的一侧除去部分该第二封装胶体以及移除该第二批半导体芯片的该基板第二部分的一部分；
    进行一第二薄化制程以形成一第二半导体芯片层，该第二薄化制程包含依序移除该第二批半导体芯片的剩余的该基板第二部分以及该停止层结构，以显露该基板第一部分、该些导电结构以及该些第二导电柱；以及
    移除该承载板，以显露该第一半导体芯片层的该内连层及该些第一导电柱。
  14. 如权利要求13所述的半导体超薄堆叠结构的制造方法，其特征在于，于移除该承载板之后，更包含以下步骤：
    于该第一半导体芯片层的远离该第二半导体芯片层的一侧设置多个焊球，以分别电性连接该内连层及该第一导电柱；以及进行切单。
  15. 如权利要求13所述的半导体超薄堆叠结构的制造方法，其特征在于，该第一批半导体芯片的该些第一半导体芯片具有不同的电性功能。
  16. 如权利要求13所述的半导体超薄堆叠结构的制造方法，其特征在于，该第二批半导体芯片的该些第二半导体芯片具有不同的电性功能。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101320684A (zh) * 2007-04-03 2008-12-10 胜高股份有限公司 半导体基板的制造方法
CN101853804A (zh) * 2009-04-03 2010-10-06 南茂科技股份有限公司 半导体装置的制造方法
CN101971328A (zh) * 2008-02-26 2011-02-09 财团法人首尔科技园区 晶圆堆叠制作方法
JP2011138825A (ja) * 2009-12-25 2011-07-14 Nitta Haas Inc 半導体デバイスの製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101320684A (zh) * 2007-04-03 2008-12-10 胜高股份有限公司 半导体基板的制造方法
CN101971328A (zh) * 2008-02-26 2011-02-09 财团法人首尔科技园区 晶圆堆叠制作方法
CN101853804A (zh) * 2009-04-03 2010-10-06 南茂科技股份有限公司 半导体装置的制造方法
JP2011138825A (ja) * 2009-12-25 2011-07-14 Nitta Haas Inc 半導体デバイスの製造方法

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