WO2010077037A3 - Ｃｏｇ 애플리케이션을 위한 인터페이스 시스템 - Google Patents

Ｃｏｇ 애플리케이션을 위한 인터페이스 시스템 Download PDF

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Publication number
WO2010077037A3
WO2010077037A3 PCT/KR2009/007828 KR2009007828W WO2010077037A3 WO 2010077037 A3 WO2010077037 A3 WO 2010077037A3 KR 2009007828 W KR2009007828 W KR 2009007828W WO 2010077037 A3 WO2010077037 A3 WO 2010077037A3
Authority
WO
WIPO (PCT)
Prior art keywords
current
interface system
receiving unit
data
transmission line
Prior art date
Application number
PCT/KR2009/007828
Other languages
English (en)
French (fr)
Other versions
WO2010077037A2 (ko
WO2010077037A4 (ko
Inventor
홍주표
최정환
김준호
Original Assignee
(주)실리콘웍스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by (주)실리콘웍스 filed Critical (주)실리콘웍스
Priority to CN200980153078.4A priority Critical patent/CN102265518B/zh
Priority to US13/142,413 priority patent/US8400194B2/en
Priority to JP2011544368A priority patent/JP5632390B2/ja
Publication of WO2010077037A2 publication Critical patent/WO2010077037A2/ko
Publication of WO2010077037A3 publication Critical patent/WO2010077037A3/ko
Publication of WO2010077037A4 publication Critical patent/WO2010077037A4/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)

Abstract

본 발명은 전송라인을 통하여 반도체 칩 간에 전류의 형태로 데이터를 전송하는 전류 구동방식의 송신기와 수신기 및 이를 적용한 COG 애플리케이션을 위한 인터페이스 시스템에 관한 것으로서, 보다 상세하게는 전송하고자 하는 데이터의 논리상태를 나타내는 차동전류를 외부 전류 없이 정데이터전류와 부데이터전류의 차이에 의해 독립적으로 생성하여 전송함으로써 전류원의 설계 및 공정상 원인에 영향 받지 않고 전송라인쌍에 인가되는 전류의 크기를 일정하게 유지할 수 있는 독립 전류신호를 이용한 전류 구동방식의 송신기와, 전송라인을 통해 수신한 전류의 레벨차이를 단일 IV 컨버터에서 동시에 전압레벨로 변환하여 트루라인과 바라인의 오차를 감소시킬 수 있는 독립 전류신호를 이용한 전류 구동방식의 수신기, 및 이러한 송신기와 수신기를 이용하여 전송신호의 왜곡을 줄일 수 있게 한 COG 애플리케이션을 위한 인터페이스 시스템에 관한 것이다.
PCT/KR2009/007828 2008-12-29 2009-12-28 Ｃｏｇ 애플리케이션을 위한 인터페이스 시스템 WO2010077037A2 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN200980153078.4A CN102265518B (zh) 2008-12-29 2009-12-28 用于cog应用的接口系统
US13/142,413 US8400194B2 (en) 2008-12-29 2009-12-28 Interface system for a cog application
JP2011544368A JP5632390B2 (ja) 2008-12-29 2009-12-28 Ｃｏｇアプリケーションのためのインターフェースシステム

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2008-0135783 2008-12-29
KR1020080135783A KR101030957B1 (ko) 2008-12-29 2008-12-29 차동전류 구동 방식의 인터페이스 시스템

Publications (3)

Publication Number Publication Date
WO2010077037A2 WO2010077037A2 (ko) 2010-07-08
WO2010077037A3 true WO2010077037A3 (ko) 2010-10-07
WO2010077037A4 WO2010077037A4 (ko) 2010-11-25

Family

ID=42310359

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2009/007828 WO2010077037A2 (ko) 2008-12-29 2009-12-28 Ｃｏｇ 애플리케이션을 위한 인터페이스 시스템

Country Status (6)

Country Link
US (1) US8400194B2 (ko)
JP (1) JP5632390B2 (ko)
KR (1) KR101030957B1 (ko)
CN (1) CN102265518B (ko)
TW (1) TWI416873B (ko)
WO (1) WO2010077037A2 (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007029526A1 (de) * 2007-06-25 2009-01-15 Sitronic Gesellschaft für elektrotechnische Ausrüstung mbH. & Co. KG Elektronisches Modul und Anordnung zur Signalübertragung damit
JP5838650B2 (ja) 2011-08-16 2016-01-06 株式会社ソシオネクスト 出力回路
JP2014039214A (ja) * 2012-08-20 2014-02-27 Lapis Semiconductor Co Ltd データ受信回路及び半導体装置
KR101588489B1 (ko) * 2012-10-29 2016-01-25 주식회사 엘지화학 차동 입력 방식 통신의 종단 저항 발생 장치 및 차동 입력 방식 통신 장치
KR20210156982A (ko) * 2020-06-19 2021-12-28 주식회사 엘엑스세미콘 디스플레이 구동 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977796A (en) * 1997-06-26 1999-11-02 Lucent Technologies, Inc. Low voltage differential swing interconnect buffer circuit
US6593801B1 (en) * 2002-06-07 2003-07-15 Pericom Semiconductor Corp. Power down mode signaled by differential transmitter's high-Z state detected by receiver sensing same voltage on differential lines
KR100420689B1 (ko) * 1999-12-01 2004-03-02 엔이씨 일렉트로닉스 코포레이션 버퍼회로
KR100588752B1 (ko) * 2005-04-26 2006-06-12 매그나칩 반도체 유한회사 차동 전류 구동 방식의 전송 시스템

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US6295323B1 (en) * 1998-12-28 2001-09-25 Agere Systems Guardian Corp. Method and system of data transmission using differential and common mode data signaling
DE10134874B4 (de) * 2001-07-18 2012-03-29 Lantiq Deutschland Gmbh Leitungstreiber
US20030085737A1 (en) * 2001-11-08 2003-05-08 Tinsley Steven J. Innovative high speed LVDS driver circuit
JP3916502B2 (ja) * 2002-04-26 2007-05-16 富士通株式会社 出力回路
JP3730607B2 (ja) * 2002-08-29 2006-01-05 株式会社東芝 差動データドライバー回路
JP4170972B2 (ja) * 2003-11-21 2008-10-22 松下電器産業株式会社 差動出力回路
JP4026593B2 (ja) * 2003-12-25 2007-12-26 セイコーエプソン株式会社 受信装置
US7119600B2 (en) * 2004-04-20 2006-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Wide common mode high-speed differential receiver using thin and thick gate oxide MOSFETS in deep-submicron technology
CA2601453A1 (en) * 2005-03-23 2006-09-28 Qualcomm Incorporated Current mode interface for off-chip high speed communication
JP4578316B2 (ja) * 2005-05-02 2010-11-10 ザインエレクトロニクス株式会社 送信装置
US7362146B2 (en) * 2005-07-25 2008-04-22 Steven Mark Macaluso Large supply range differential line driver
JP4685813B2 (ja) * 2007-02-19 2011-05-18 富士通株式会社 レシーバ
US8228096B2 (en) * 2007-03-02 2012-07-24 Kawasaki Microelectronics, Inc. Circuit and method for current-mode output driver with pre-emphasis
KR100913528B1 (ko) * 2008-08-26 2009-08-21 주식회사 실리콘웍스 차동전류구동방식의 송신부, 차동전류구동방식의 수신부 및상기 송신부와 상기 수신부를 구비하는 차동전류구동방식의 인터페이스 시스템

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977796A (en) * 1997-06-26 1999-11-02 Lucent Technologies, Inc. Low voltage differential swing interconnect buffer circuit
KR100420689B1 (ko) * 1999-12-01 2004-03-02 엔이씨 일렉트로닉스 코포레이션 버퍼회로
US6593801B1 (en) * 2002-06-07 2003-07-15 Pericom Semiconductor Corp. Power down mode signaled by differential transmitter's high-Z state detected by receiver sensing same voltage on differential lines
KR100588752B1 (ko) * 2005-04-26 2006-06-12 매그나칩 반도체 유한회사 차동 전류 구동 방식의 전송 시스템

Also Published As

Publication number Publication date
KR101030957B1 (ko) 2011-04-28
JP2012514413A (ja) 2012-06-21
CN102265518A (zh) 2011-11-30
JP5632390B2 (ja) 2014-11-26
TW201031115A (en) 2010-08-16
TWI416873B (zh) 2013-11-21
KR20100077750A (ko) 2010-07-08
WO2010077037A2 (ko) 2010-07-08
WO2010077037A4 (ko) 2010-11-25
US8400194B2 (en) 2013-03-19
US20110267022A1 (en) 2011-11-03
CN102265518B (zh) 2014-08-06

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