WO2010075125A1 - Fabricating a gallium nitride device with a diamond layer - Google Patents

Fabricating a gallium nitride device with a diamond layer Download PDF

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Publication number
WO2010075125A1
WO2010075125A1 PCT/US2009/068180 US2009068180W WO2010075125A1 WO 2010075125 A1 WO2010075125 A1 WO 2010075125A1 US 2009068180 W US2009068180 W US 2009068180W WO 2010075125 A1 WO2010075125 A1 WO 2010075125A1
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WO
WIPO (PCT)
Prior art keywords
gan
layer
diamond
diamond layer
disposed
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Ceased
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PCT/US2009/068180
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English (en)
French (fr)
Inventor
Ralph Korenstein
Steven D. Bernstein
Stephen J. Pereira
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Raytheon Co
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Raytheon Co
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Priority to JP2011542361A priority Critical patent/JP5486610B2/ja
Priority to KR1020117015678A priority patent/KR101227925B1/ko
Publication of WO2010075125A1 publication Critical patent/WO2010075125A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02389—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02527—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/8303—Diamond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

  • Gallium Nitride has electrical and physical properties that make it highly suitable for high frequency (HF) devices such as microwave devices.
  • HF devices produce a high amount of heat requiring a heat spreader to be attached to the HF devices to avoid device failure.
  • One such heat spreader is diamond.
  • a hot filament chemical vapor deposition (CVD) process has been used to form diamond that is used on GaN layers. Generally, these diamond layers are not deposited directly onto the GaN layers but onto some other material (e.g., silicon, silicon carbide, and so forth) that is eventually disposed with the GaN layer.
  • a method includes fabricating a device.
  • the device includes a gallium nitride (GaN) layer, a diamond layer disposed on the GaN layer and a gate structure disposed in contact with the GaN layer and the diamond layer.
  • GaN gallium nitride
  • a device in another aspect, includes a GaN layer, a diamond layer disposed on the GaN layer and a gate structure disposed in contact with the GaN layer and the diamond layer.
  • a method includes disposing a diamond layer onto a first surface of gallium nitride (GaN), removing a portion of the diamond layer exposing the first surface of the GaN and forming a gate structure in contact with the first surface of the GaN and the diamond layer.
  • FIG. IA is a diagram of an example of a Gallium Nitride (GaN) layer with a first diamond layer and a second diamond layer.
  • GaN Gallium Nitride
  • FIG. IB is a diagram of another example of the GaN layer with the first diamond layer and the second diamond layer.
  • FIG. 2 is a flowchart of an example of a process to fabricate the GaN layer with the first diamond layer and the second diamond layer.
  • FIGS. 3A to 3D are diagrams corresponding to the process of FIG. 2.
  • FIG. 4 is a flowchart of another example of a process to fabricate a GaN layer with the first diamond layer and the second diamond layer.
  • FIGS. 9A to 9D are diagrams corresponding to the process of FIG. 6.
  • FIG. 10 is an example of a device with diamond layers.
  • FIG. 1 1 is another example of a device with diamond layers.
  • FIG. 12 is a graph depicting thermal performance with diamond coatings.
  • Hot filament chemical vapor deposition (CVD) processes have been used to form diamond layers of less than 1 mil that are used on gallium nitride (GaN) layers. To be effective as a heat spreader, diamond layers must be greater than 2 mils. Moreover, the hot filament CVD process by its very nature produces a blackish-color diamond which is contaminated with material used in the hot filament CVD process such as tungsten, for example. In general, these "dirty" diamond layers that are produced have a lower thermal conductivity than pure diamond. In general, the thermal conductivity of diamond layers using the hot filament CVD process is about 800 to 1000 Watts/meter - Kelvin (W/m-K).
  • a microwave plasma CVD process has been known to produce much thicker diamond layers on the order of 4 mils or greater at a much faster rate than the hot filament CVD process. Moreover the diamond layers are purer than the hot filament
  • the thermal conductivity of diamond produced using the microwave plasma CVD process is twice the thermal conductivity of diamond produced using the hot filament process.
  • the CVD processes including the microwave plasma CVD process is relatively unknown with respect to direct deposition onto GaN.
  • the deposition of diamond using hot filament CVD is typically done onto some other material (e.g., silicon, silicon carbide, and so forth) that is eventually is disposed with the GaN layer. Since the deposition of diamond directly onto to GaN using the microwave plasma CVD process is relatively unknown, the costs of developing and testing a reliable and successful processes to deposit diamond directly onto the GaN is extremely expensive.
  • GaN layers may include pure GaN, doped GaN or GaN combined with other elements (e.g., AlGaN) or any combination thereof.
  • Silicon substrates may include pure silicon, doped silicon, silicon dioxide, silicon carbide or any combination of silicon with other elements or any combination thereof. Referring to FIGS.
  • a structure 10 for use in forming a device includes a second diamond layer 12, a first diamond layer 14 adjacent to the second diamond layer and a GaN layer 16 adjacent to the first diamond layer.
  • a structure 20 uses to form a device (e.g., a high frequency device, a HEMT transistor, a microwave device and so forth) is similar to the structure 10 but includes an interlayer 22 between the first diamond layer and the GaN layer 16.
  • the interlayer 22 is needed because the fabrication of diamond directly onto GaN is not easy process much less predictable or consistent.
  • the interlayer 22 may be simply an adhesive holding the first diamond layer 14 to the GaN 16 or a silicon-type structure onto which diamond may easily be disposed.
  • the interlayer 22 has a thermal conductivity less than that of the diamond layers 12, 14 so that it holds heat more; or put another way, the heat transference from the GaN layer 16 is impeded by the interlayer 22.
  • minimizing the interlayer 22 or not having the interlayer at all as in the structure 10 is preferred.
  • one process to fabricate a GaN layer with a first diamond layer and a second diamond layer is a process 100.
  • the hot filament CVD process is used to deposit a first diamond layer 14 (e.g., a layer of 5 to 20 microns thick) onto a silicon-on-insulator (SOI) substrate 122 (102) (FIG. 3A).
  • SOI silicon-on-insulator
  • the insulator (not shown) (e.g., silicon dioxide) is removed from the SOI substrate 122 leaving a silicon substrate 122', for example (104) (FIG. 3B).
  • the microwave plasma CVD is used to deposit a second diamond layer 12 onto the first diamond layer 14 (108) (FIG. 3C).
  • GaN is grown onto the remaining SOI substrate, the silicon substrate 122 (112) (FIG. 3D).
  • FIGS. 4 and 5 A to 5H another process to fabricate a GaN layer with a first diamond layer and a second diamond layer is a process 200.
  • GaN 16 is grown on a first substrate 230 (202) (FIG. 5A).
  • the first substrate may be silicon carbide, silicon or sapphire.
  • a silicon layer 232 (e.g., silicon, silicon carbide and so forth) is disposed onto the GaN (204) (FIG. 5B).
  • the silicon layer 232 is attached to the GaN 16 using an adhesive.
  • the silicon layer 232 is grown onto the GaN 16.
  • the first substrate 230 is removed (208), for example, through etching leaving a GaN/silicon structure 250 (FIG. 5C).
  • a hot filament CVD is used to deposit a first layer of diamond 14 onto a second substrate 234 (212) (FIG. 5D).
  • the second substrate 234 is a silicon substrate 500 microns thick.
  • a microwave plasma CVD process is used to deposit a second diamond layer 12 onto the first diamond layer 14 (218) (FIG. 5E).
  • the second substrate 234 is removed (218), for example, through etching (FIG. 5F).
  • the first and second diamond layers 12, 14 are attached to the GaN/silicon structure 250 (224) (FIG. 5G).
  • the first diamond layer 14 is attached to the GaN 16 using an adhesive.
  • the silicon layer 232 is removed (228), for example, through etching (FIG. 5H).
  • a further process to fabricate a GaN layer with diamond layers is a process 300.
  • Process 300 is similar to process 200 except a third diamond layer 316 is disposed on a first GaN surface 302 (e.g., a top surface) (FIG. 7F) opposite a second GaN surface 304 (e.g., a bottom surface) (FIG.7F) that has the first and second diamond layers 14, 12.
  • processing blocks 202, 204 and 208 are performed as in process 200.
  • the GaN 16 is grown on the first substrate 230 (202) (FIG. 7A)
  • the silicon layer 232 is disposed onto the GaN 16 (204) (FIG. 7B); and the first substrate 230 is removed (208), for example, through etching leaving the GaN/silicon structure 250 (FIG. 7C).
  • the silicon/GaN structure 250 is immersed in a solution and subjected to ultrasound (302). By treating the surface prior to deposition (e.g., a processing block 314), the diamond layer 316 has a better chance of forming on the GaN 16 during deposition.
  • the solution is an isopropyl alcohol solution that includes diamond particles (e.g., nano-diamond particles (10 " m)).
  • the third diamond layer 316 is disposed on the silicon/GaN structure 250 (314) (FIG. 7D).
  • the microwave plasma CVD process is used to deposit the third diamond layer 316 onto the GaN 250 at temperatures from about 600 0 C to about 650 °C.
  • the silicon layer 232 is removed (228), for example, through etching (FIG. 7E).
  • the first and second diamond layers 14, 12, formed using process blocks 212, 214 and 218, for example, are attached to the remaining GaN/diamond structure to form a diamond/GaN/diamond/diamond structure 360 (334) (FIG. 7F).
  • the first diamond layer 14 is attached to the GaN 16 using an adhesive.
  • the first diamond layer 14 is attached to the second surface 304 opposite to the first surface 302 disposed with the third diamond layer 316.
  • heat is more effectively pulled away from devices formed from the diamond/GaN/diamond/diamond structure 360. Referring to FIG.
  • the first and second diamond layers 14, 12 are formed using processing blocks 212, 214, and 218, for example.
  • the first and second diamond layers 14, 12 are attached to the GaN/diamond 350 to form the diamond/GaN/diamond/diamond structure 360 (334) (FIG. 9D).
  • a device 400 (e.g., a HEMT device) includes a source 404, a drain 406 and a gate 408 (e.g., a T-Gate) that are deposited in a metallization step onto to the surface 302 of the GaN layer 16.
  • the gate 408 is formed in the diamond layer 316 after removal of portions of the diamond layer thereby exposing the GaN.
  • the removal of portions of the diamond layer 316 splits the diamond layer into two diamond layers 316a, 316b each having a width W.
  • the diamond layers 316a, 316b may function as a dielectric layer and a heat spreader by removing the heat away from the gate 408.
  • the widths of the diamond layers 316a, 316b may not be equal.
  • portions of the gate 408 are adjacent to and in contact with the diamond layers 316a, 316b and other portions of the gate 408 form gaps 410a, 410b (e.g., air gaps) between the gate and the diamond layers 316a, 316b.
  • gate 408, the gaps 410a, 410b, the diamond layer 316a, 316b form capacitance structures.
  • a material e.g., photoresist
  • the .05 micron diamond coating reduces thermal resistance by 10% (>25°C at 5 W/mm) than not having a diamond layers 316a, 316b.
  • any of the processing steps of FIGS. 2, 4, 6 and 8 may be re-ordered, combined or removed, performed in parallel or in serial, as necessary, to achieve the results set forth above.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
PCT/US2009/068180 2008-12-22 2009-12-16 Fabricating a gallium nitride device with a diamond layer Ceased WO2010075125A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011542361A JP5486610B2 (ja) 2008-12-22 2009-12-16 ダイアモンド層を有する窒化ガリウム・デバイスの製造
KR1020117015678A KR101227925B1 (ko) 2008-12-22 2009-12-16 다이아몬드 층을 갖는 갈륨 질화물 장치 제조

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US12/341,115 2008-12-22
US12/341,115 US7989261B2 (en) 2008-12-22 2008-12-22 Fabricating a gallium nitride device with a diamond layer

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US (2) US7989261B2 (enExample)
JP (1) JP5486610B2 (enExample)
KR (1) KR101227925B1 (enExample)
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WO (1) WO2010075125A1 (enExample)

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CN117646275A (zh) * 2024-01-30 2024-03-05 北京大学 一种大尺寸高热导率iii族氮化物外延材料的制备方法

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