WO2010068699A3 - Interconnexion de puce semi-conductrice formée par application aérosol de matériau électriquement conducteur - Google Patents
Interconnexion de puce semi-conductrice formée par application aérosol de matériau électriquement conducteur Download PDFInfo
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- WO2010068699A3 WO2010068699A3 PCT/US2009/067386 US2009067386W WO2010068699A3 WO 2010068699 A3 WO2010068699 A3 WO 2010068699A3 US 2009067386 W US2009067386 W US 2009067386W WO 2010068699 A3 WO2010068699 A3 WO 2010068699A3
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- die
- conductive material
- electrically conductive
- semiconductor die
- die interconnect
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011540873A JP5631328B2 (ja) | 2008-12-09 | 2009-12-09 | 電気伝導材料のエアゾール・アプリケーションによって形成される半導体ダイ相互接続 |
CN2009801492852A CN102246298A (zh) | 2008-12-09 | 2009-12-09 | 通过电传导材料的喷雾施加形成的半导体裸片互连 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12113808P | 2008-12-09 | 2008-12-09 | |
US61/121,138 | 2008-12-09 | ||
US28058409P | 2009-11-04 | 2009-11-04 | |
US61/280,584 | 2009-11-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2010068699A2 WO2010068699A2 (fr) | 2010-06-17 |
WO2010068699A3 true WO2010068699A3 (fr) | 2010-08-26 |
Family
ID=42230183
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2009/067386 WO2010068699A2 (fr) | 2008-12-09 | 2009-12-09 | Interconnexion de puce semi-conductrice formée par application aérosol de matériau électriquement conducteur |
Country Status (5)
Country | Link |
---|---|
US (1) | US20100140811A1 (fr) |
JP (1) | JP5631328B2 (fr) |
KR (1) | KR101566573B1 (fr) |
CN (1) | CN102246298A (fr) |
WO (1) | WO2010068699A2 (fr) |
Families Citing this family (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8704379B2 (en) | 2007-09-10 | 2014-04-22 | Invensas Corporation | Semiconductor die mount by conformal die coating |
CN103325764B (zh) * | 2008-03-12 | 2016-09-07 | 伊文萨思公司 | 支撑安装的电互连管芯组件 |
US9153517B2 (en) | 2008-05-20 | 2015-10-06 | Invensas Corporation | Electrical connector between die pad and z-interconnect for stacked die assemblies |
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US9165907B2 (en) * | 2010-02-22 | 2015-10-20 | Interposers Gmbh | Method and a system for producing a semi-conductor module |
US8587088B2 (en) | 2011-02-17 | 2013-11-19 | Apple Inc. | Side-mounted controller and methods for making the same |
KR20120135626A (ko) * | 2011-06-07 | 2012-12-17 | 삼성전자주식회사 | 반도체 칩 패키지의 제조 방법 |
US10388584B2 (en) * | 2011-09-06 | 2019-08-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming Fo-WLCSP with recessed interconnect area in peripheral region of semiconductor die |
US9966319B1 (en) | 2011-10-27 | 2018-05-08 | Global Circuit Innovations Incorporated | Environmental hardening integrated circuit method and apparatus |
US10002846B2 (en) | 2011-10-27 | 2018-06-19 | Global Circuit Innovations Incorporated | Method for remapping a packaged extracted die with 3D printed bond connections |
US10177054B2 (en) | 2011-10-27 | 2019-01-08 | Global Circuit Innovations, Inc. | Method for remapping a packaged extracted die |
US10147660B2 (en) | 2011-10-27 | 2018-12-04 | Global Circuits Innovations, Inc. | Remapped packaged extracted die with 3D printed bond connections |
US10128161B2 (en) | 2011-10-27 | 2018-11-13 | Global Circuit Innovations, Inc. | 3D printed hermetic package assembly and method |
US9870968B2 (en) | 2011-10-27 | 2018-01-16 | Global Circuit Innovations Incorporated | Repackaged integrated circuit and assembly method |
US9935028B2 (en) | 2013-03-05 | 2018-04-03 | Global Circuit Innovations Incorporated | Method and apparatus for printing integrated circuit bond connections |
US10109606B2 (en) | 2011-10-27 | 2018-10-23 | Global Circuit Innovations, Inc. | Remapped packaged extracted die |
TWI467731B (zh) * | 2012-05-03 | 2015-01-01 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
US9064977B2 (en) | 2012-08-22 | 2015-06-23 | Freescale Semiconductor Inc. | Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof |
US9190390B2 (en) | 2012-08-22 | 2015-11-17 | Freescale Semiconductor Inc. | Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof |
US9093457B2 (en) | 2012-08-22 | 2015-07-28 | Freescale Semiconductor Inc. | Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof |
US9362244B2 (en) | 2012-10-22 | 2016-06-07 | Sandisk Information Technology (Shanghai) Co., Ltd. | Wire tail connector for a semiconductor device |
KR102190382B1 (ko) | 2012-12-20 | 2020-12-11 | 삼성전자주식회사 | 반도체 패키지 |
US9299670B2 (en) | 2013-03-14 | 2016-03-29 | Freescale Semiconductor, Inc. | Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof |
US9524950B2 (en) | 2013-05-31 | 2016-12-20 | Freescale Semiconductor, Inc. | Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof |
KR102001880B1 (ko) | 2013-06-11 | 2019-07-19 | 에스케이하이닉스 주식회사 | 적층 패키지 및 제조 방법 |
KR102099878B1 (ko) | 2013-07-11 | 2020-04-10 | 삼성전자 주식회사 | 반도체 패키지 |
US9025340B2 (en) | 2013-09-30 | 2015-05-05 | Freescale Semiconductor, Inc. | Devices and stacked microelectronic packages with in-trench package surface conductors and methods of their fabrication |
US9036363B2 (en) | 2013-09-30 | 2015-05-19 | Freescale Semiconductor, Inc. | Devices and stacked microelectronic packages with parallel conductors and intra-conductor isolator structures and methods of their fabrication |
US9263420B2 (en) | 2013-12-05 | 2016-02-16 | Freescale Semiconductor, Inc. | Devices and stacked microelectronic packages with package surface conductors and methods of their fabrication |
US9305911B2 (en) | 2013-12-05 | 2016-04-05 | Freescale Semiconductor, Inc. | Devices and stacked microelectronic packages with package surface conductors and adjacent trenches and methods of their fabrication |
US9876152B2 (en) | 2014-05-27 | 2018-01-23 | Epistar Corporation | Light emitting device with an adhered heat-dissipating structure |
US10388607B2 (en) | 2014-12-17 | 2019-08-20 | Nxp Usa, Inc. | Microelectronic devices with multi-layer package surface conductors and methods of their fabrication |
KR102444204B1 (ko) * | 2015-02-10 | 2022-09-19 | 옵토멕 인코포레이티드 | 에어로졸의 비행 중 경화에 의해 3차원 구조를 제조하는 방법 |
US20170348903A1 (en) * | 2015-02-10 | 2017-12-07 | Optomec, Inc. | Fabrication of Three-Dimensional Materials Gradient Structures by In-Flight Curing of Aerosols |
US9871019B2 (en) | 2015-07-17 | 2018-01-16 | Invensas Corporation | Flipped die stack assemblies with leadframe interconnects |
US9490195B1 (en) | 2015-07-17 | 2016-11-08 | Invensas Corporation | Wafer-level flipped die stacks with leadframes or metal foil interconnects |
US9825002B2 (en) | 2015-07-17 | 2017-11-21 | Invensas Corporation | Flipped die stack |
US9508691B1 (en) | 2015-12-16 | 2016-11-29 | Invensas Corporation | Flipped die stacks with multiple rows of leadframe interconnects |
US10636767B2 (en) * | 2016-02-29 | 2020-04-28 | Invensas Corporation | Correction die for wafer/die stack |
US10566310B2 (en) | 2016-04-11 | 2020-02-18 | Invensas Corporation | Microelectronic packages having stacked die and wire bond interconnects |
US9595511B1 (en) | 2016-05-12 | 2017-03-14 | Invensas Corporation | Microelectronic packages and assemblies with improved flyby signaling operation |
US9728524B1 (en) | 2016-06-30 | 2017-08-08 | Invensas Corporation | Enhanced density assembly having microelectronic packages mounted at substantial angle to board |
US10373932B2 (en) * | 2017-04-20 | 2019-08-06 | Nanya Technology Corporation | Stacked semiconductor structure |
US10632746B2 (en) | 2017-11-13 | 2020-04-28 | Optomec, Inc. | Shuttering of aerosol streams |
US10115645B1 (en) | 2018-01-09 | 2018-10-30 | Global Circuit Innovations, Inc. | Repackaged reconditioned die method and assembly |
JP7001482B2 (ja) | 2018-01-22 | 2022-01-19 | 日鉄建材株式会社 | 集水井における水位計測センサ取付構造、及び水位計測センサ取付方法 |
WO2019222410A1 (fr) | 2018-05-18 | 2019-11-21 | Board Of Trustees Of Michigan State University | Structure de conditionnement d'interconnexion fabriquée |
US10790172B2 (en) * | 2018-08-17 | 2020-09-29 | Jabil Inc. | Apparatus, system, and method of providing a ramped interconnect for semiconductor fabrication |
US10903153B2 (en) | 2018-11-18 | 2021-01-26 | International Business Machines Corporation | Thinned die stack |
US11742284B2 (en) * | 2018-12-12 | 2023-08-29 | Intel Corporation | Interconnect structure fabricated using lithographic and deposition processes |
KR102644598B1 (ko) * | 2019-03-25 | 2024-03-07 | 삼성전자주식회사 | 반도체 패키지 |
CN110349933A (zh) * | 2019-07-23 | 2019-10-18 | 上海先方半导体有限公司 | 一种晶圆键合堆叠芯片的封装结构及制备方法 |
US11171109B2 (en) * | 2019-09-23 | 2021-11-09 | Micron Technology, Inc. | Techniques for forming semiconductor device packages and related packages, intermediate products, and methods |
US11939905B2 (en) | 2020-05-20 | 2024-03-26 | Board Of Trustees Of Michigan State University | Internal combustion engine including multiple fuel injections external to a pre-chamber |
US12021060B2 (en) * | 2020-09-22 | 2024-06-25 | Western Digital Technologies, Inc. | Reducing keep-out-zone area for a semiconductor device |
US11508680B2 (en) | 2020-11-13 | 2022-11-22 | Global Circuit Innovations Inc. | Solder ball application for singular die |
KR20230023852A (ko) * | 2021-08-10 | 2023-02-20 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20050009036A (ko) * | 2003-07-15 | 2005-01-24 | 삼성전자주식회사 | 적층 패키지 및 그 제조 방법 |
US20070284716A1 (en) * | 2004-04-13 | 2007-12-13 | Vertical Circuits, Inc. | Assembly Having Stacked Die Mounted On Substrate |
KR100813624B1 (ko) * | 2006-10-25 | 2008-03-17 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
US20080112150A1 (en) * | 2006-11-13 | 2008-05-15 | Trident Space & Defense, Llc | Radiation-shielded semiconductor assembly |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5466634A (en) * | 1994-12-20 | 1995-11-14 | International Business Machines Corporation | Electronic modules with interconnected surface metallization layers and fabrication methods therefore |
US5880530A (en) * | 1996-03-29 | 1999-03-09 | Intel Corporation | Multiregion solder interconnection structure |
KR100533673B1 (ko) * | 1999-09-03 | 2005-12-05 | 세이코 엡슨 가부시키가이샤 | 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기 |
US20030006493A1 (en) * | 2001-07-04 | 2003-01-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and manufacturing method thereof |
US6747348B2 (en) * | 2001-10-16 | 2004-06-08 | Micron Technology, Inc. | Apparatus and method for leadless packaging of semiconductor devices |
US6750547B2 (en) * | 2001-12-26 | 2004-06-15 | Micron Technology, Inc. | Multi-substrate microelectronic packages and methods for manufacture |
US6756252B2 (en) * | 2002-07-17 | 2004-06-29 | Texas Instrument Incorporated | Multilayer laser trim interconnect method |
JP2004063569A (ja) * | 2002-07-25 | 2004-02-26 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP4081666B2 (ja) * | 2002-09-24 | 2008-04-30 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
KR100499289B1 (ko) * | 2003-02-07 | 2005-07-04 | 삼성전자주식회사 | 패턴 리드를 갖는 반도체 패키지 및 그 제조 방법 |
JP3772984B2 (ja) * | 2003-03-13 | 2006-05-10 | セイコーエプソン株式会社 | 電子装置及びその製造方法、回路基板並びに電子機器 |
JP2004281538A (ja) * | 2003-03-13 | 2004-10-07 | Seiko Epson Corp | 電子装置及びその製造方法、回路基板並びに電子機器 |
DE102004008135A1 (de) * | 2004-02-18 | 2005-09-22 | Infineon Technologies Ag | Halbleiterbauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben |
JP2005302763A (ja) * | 2004-04-06 | 2005-10-27 | Seiko Epson Corp | 半導体装置及びその製造方法並びに電子機器 |
JP2007073803A (ja) * | 2005-09-08 | 2007-03-22 | Toshiba Corp | 半導体装置及びその製造方法 |
JP5018024B2 (ja) * | 2006-11-08 | 2012-09-05 | セイコーエプソン株式会社 | 電子部品の実装方法、電子基板、及び電子機器 |
JP5080295B2 (ja) * | 2007-01-26 | 2012-11-21 | 帝人株式会社 | 放熱性実装基板およびその製造方法 |
JP5110995B2 (ja) * | 2007-07-20 | 2012-12-26 | 新光電気工業株式会社 | 積層型半導体装置及びその製造方法 |
-
2009
- 2009-12-09 JP JP2011540873A patent/JP5631328B2/ja not_active Expired - Fee Related
- 2009-12-09 CN CN2009801492852A patent/CN102246298A/zh active Pending
- 2009-12-09 US US12/634,598 patent/US20100140811A1/en not_active Abandoned
- 2009-12-09 WO PCT/US2009/067386 patent/WO2010068699A2/fr active Application Filing
- 2009-12-09 KR KR1020117015983A patent/KR101566573B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20050009036A (ko) * | 2003-07-15 | 2005-01-24 | 삼성전자주식회사 | 적층 패키지 및 그 제조 방법 |
US20070284716A1 (en) * | 2004-04-13 | 2007-12-13 | Vertical Circuits, Inc. | Assembly Having Stacked Die Mounted On Substrate |
KR100813624B1 (ko) * | 2006-10-25 | 2008-03-17 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
US20080112150A1 (en) * | 2006-11-13 | 2008-05-15 | Trident Space & Defense, Llc | Radiation-shielded semiconductor assembly |
Also Published As
Publication number | Publication date |
---|---|
US20100140811A1 (en) | 2010-06-10 |
JP2012511835A (ja) | 2012-05-24 |
JP5631328B2 (ja) | 2014-11-26 |
KR20110103413A (ko) | 2011-09-20 |
WO2010068699A2 (fr) | 2010-06-17 |
CN102246298A (zh) | 2011-11-16 |
KR101566573B1 (ko) | 2015-11-05 |
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