WO2010059367A2 - Procédés et appareils de production de semi-conducteurs sur des structures isolantes au moyen d’une exfoliation dirigée - Google Patents

Procédés et appareils de production de semi-conducteurs sur des structures isolantes au moyen d’une exfoliation dirigée Download PDF

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Publication number
WO2010059367A2
WO2010059367A2 PCT/US2009/062531 US2009062531W WO2010059367A2 WO 2010059367 A2 WO2010059367 A2 WO 2010059367A2 US 2009062531 W US2009062531 W US 2009062531W WO 2010059367 A2 WO2010059367 A2 WO 2010059367A2
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WIPO (PCT)
Prior art keywords
semiconductor wafer
weakened slice
donor semiconductor
ions
weakened
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PCT/US2009/062531
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English (en)
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WO2010059367A3 (fr
Inventor
Sarko Cherekdjian
Jeffrey S Cites
James G Couillard
Richard O Maschmeyer
Michael J. Moore
Alex Usenko
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Corning Incorporated
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Publication date
Priority claimed from US12/290,384 external-priority patent/US8003491B2/en
Priority claimed from US12/290,362 external-priority patent/US7816225B2/en
Application filed by Corning Incorporated filed Critical Corning Incorporated
Priority to EP09744304A priority Critical patent/EP2359400A2/fr
Priority to JP2011534755A priority patent/JP5650653B2/ja
Priority to CN200980143709.4A priority patent/CN102203933B/zh
Publication of WO2010059367A2 publication Critical patent/WO2010059367A2/fr
Publication of WO2010059367A3 publication Critical patent/WO2010059367A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/786—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being other than a semiconductor body, e.g. insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present invention relates to the manufacture of semiconductor-on- insulator (SOI) structures, such as those of non-circular cross section and/or those of relatively large cross sectional area.
  • SOI semiconductor-on- insulator
  • SOI structures may include a thin layer of semiconductor material, such as silicon, on an insulating material.
  • Various ways of obtaining SOI structures include epitaxial growth of silicon (Si) on lattice matched substrates, and bonding a single crystal silicon wafer to another silicon wafer.
  • Further methods include ion-implantation techniques in which either hydrogen or oxygen ions are implanted either to form a buried oxide layer in the silicon wafer topped by Si in the case of oxygen ion implantation or to separate (exfoliate) a thin Si layer to bond to another Si wafer with an oxide layer as in the case of hydrogen ion implantation.
  • U.S. Patent No.: 7,176,528 discloses a process that produces an SOG (semiconductor on glass) structure using an exfoliation technique.
  • the steps include: (i) exposing a silicon wafer surface to hydrogen ion implantation to create a bonding surface; (ii) bringing the bonding surface of the wafer into contact with a glass substrate; (iii) applying pressure, temperature and voltage to the wafer and the glass substrate to facilitate bonding therebetween; and (iv) separating the glass substrate and a thin layer of silicon from the silicon wafer.
  • the above approach is susceptible to an undesirable effect under some circumstance and/or when employed in certain applications.
  • a semiconductor wafer 20 is implanted with ions, e.g., hydrogen ions, through a surface 21, such that the implantation dose is uniform in terms of density and depth across the semiconductor wafer 20.
  • the platelets or bubbles grow in effective diameter until they get close enough to each other that the remaining silicon is too weak to resist the high pressure of the gas.
  • the multiple separating fronts are randomly created and the multiple cracks propagate through the semiconductor wafer 20.
  • the ions decelerate through the lattice structure of the semiconductor wafer 20 (e.g., silicon) and displace some silicon atoms from their lattice sites, creating the plane of defects.
  • the hydrogen ions lose their kinetic energy, they become atomic hydrogen and define a further, atomic hydrogen plane.
  • Both the defect plane and the atomic hydrogen plane are not stable in the silicon lattice at room temperature.
  • the defects (vacancies) and the atomic hydrogen move toward one another and form thermally stable vacancy-hydrogen species. Multiple species collectively create a hydrogen rich plane.
  • the silicon lattice cleaves generally along the hydrogen rich plane.
  • a tent-like structure 24 is created with edges that are not separated.
  • fracture of the remaining semiconductor material occurs along relatively weak planes, such as ⁇ 111 ⁇ planes (FIG. 1C) and the separation of the exfoliation layer 22 from the semiconductor wafer 20 is complete (FIG. ID).
  • the edges 22A, 22B are out of a major cleavage plane defined by the damage sites. This non-planar cleavage is not desirable.
  • Other characteristics of the separation include that the exfoliated layer 22 can be described as having "mesas", where the platelets or bubbles were, surrounded by "canyons", where the fracture occurred. It is noted that these mesas and canyons are not accurately shown in FIG.
  • U.S. 6,010,579 describes a technique of uniform ion implantation into a semiconductor substrate 10 to a uniform depth ZO, taking the wafer to a temperature below that which would initiate the onset of separation, and then introducing multiple impulses of energy to the edge of the substrate 10 in the vicinity of the implant depth ZO in order to achieve a "controlled cleave front".
  • U.S. 6,010,579 states that the above approach is an improvement over so-called "random" cleavage at least as to surface roughness.
  • the instant invention takes a directed separation approach that is significantly different from the "controlled cleave front" approach of U.S. 6,010,579 and different from the "random" cleaving approach.
  • SOI semiconductor-on-insulator structures in general, including, but not limited to, silicon-on-insulator structures.
  • SOG abbreviation is used to refer to semiconductor-on-glass structures in general, including, but not limited to, silicon-on- glass structures.
  • SOI encompasses SOG structures.
  • method and apparatus employed in forming a semiconductor-on-insulator (SOI) structure provide for: subjecting a implantation surface of a donor semiconductor wafer to an ion implantation step to create a weakened slice in cross-section defining an exfoliation layer of the donor semiconductor wafer; and subjecting the donor semiconductor wafer to a spatial variation step, either before, during or after the ion implantation step, such that one or more parameters of the weakened slice vary spatially across the wafer in at least one of X- and Y- axial directions.
  • SOI semiconductor-on-insulator
  • the spatial variation step facilitates characteristics of separation of the exfoliation layer from the donor semiconductor wafer such that such separation is directionally and/or temporally controllable.
  • the parameters may include one or more of the following, alone or in combination: (i) densities of nucleation sites resulting from the ion implantation step; (i ⁇ ) depths of the weakened slice from the implantation surface (or the reference plane); (iii) artificially created damage locations (e.g., blind holes) through the implantation surface at least to the weakened slice; and (iv) nucleation of defect sites and/or pressure increases throughout the weakened slice using temperature gradients.
  • the method and apparatus further provide for elevating the donor semiconductor wafer to a temperature sufficient to initiate separation at the weakened slice from a point, edge, and/or region of the weakened slice.
  • the donor semiconductor wafer may be subject to further temperatures sufficient to continue separation substantially along the weakened slice directionally as a function of the varying parameter(s).
  • FIGS. IA, IB, 1C, and ID are block diagrams illustrating an exfoliation process in accordance with the prior art
  • FIGS. 2A-2B are block diagrams illustrating an exfoliation process in accordance with one or more aspects of the present invention.
  • FIG. 3 A is a top view of a donor semiconductor wafer having a spatially varying parameter associated with a weakened layer or slice therein in accordance with one or more aspects of the present invention;
  • FIG. 3B is a plot that graphically illustrates the spatially varying parameter of
  • FIG. 3A [0026]
  • FIG. 3C is a plot that graphically illustrates that the spatially varying parameter of FIG. 3 A is the depth of the weakened slice;
  • FIGS. 4 A, 4B, and 4C are top views of respective donor semiconductor wafers having further spatially varying parameters in accordance with one or more further aspects of the present invention;
  • FIGS. 5A, 5B, and 5C are simplified diagrams of some ion implantation apparatus that may be adapted to achieve spatially varying parameters of the donor semiconductor wafer;
  • FIGS. 6A-6B illustrate an ion implantation technique that may be adapted to achieve a spatially varying density of nucleation sites in the donor semiconductor wafer;
  • FIGS. 7A-7B illustrate an ion implantation technique that may be adapted to achieve a spatially varying implantation depth in the donor semiconductor wafer;
  • FIGS. 7C-7D are graphs illustrating relationships between tilt angle of ion implant and implant depth;
  • FIGS. 8A-8B illustrate an ion implantation technique that may be adapted to achieve a spatially varying ion implantation distribution width in the donor semiconductor wafer;
  • FIG. 8C is a graph illustrating a relationship between ion implant tilt angle and straggle
  • FIGS. 9A-9D illustrate a further ion implantation technique that may be adapted to achieve a spatially varying ion implantation depth in the donor semiconductor wafer
  • FIGS. 10A- 1OD and 11 illustrate a further ion implantation technique that may be adapted to achieve a spatially varying distribution of defect sites in the donor semiconductor wafer.
  • FIGS. 12A- 12B illustrate a time-temperature profile technique that may be adapted to achieve a spatially varying parameter profile in the donor semiconductor wafer.
  • FIGS. 2A-2B an intermediate SOI structure (in particular, an SOG structure) in accordance with one or more embodiments of the present invention.
  • the intermediate SOG structure includes an insulator substrate, such as a glass or glass ceramic substrate 102, and a donor semiconductor wafer 120.
  • the glass or glass ceramic substrate 102 and the donor semiconductor wafer 120 have been coupled together using any of the art-recognized processes, such as bonding, fusion, adhesive, etc.
  • the donor semiconductor wafer 120 Prior to coupling the glass or glass ceramic substrate 102 and the donor semiconductor wafer 120 together, the donor semiconductor wafer 120 includes an exposed implantation surface 121.
  • the implantation surface 121 of the donor semiconductor wafer 120 is subjected to an ion implantation step to create a weakened slice 125 in cross-section defining an exfoliation layer 122.
  • the weakened slice 125 lies substantially parallel to a reference plane (which could be anywhere, and thus is not illustrated) defined by X-Y orthogonal axial directions.
  • the X-axial direction is shown left-to-right in FIG. 2A, while the Y-axial direction is orthogonal to the X-axial direction into the page (and thus is not shown).
  • the donor semiconductor wafer 120 is subject to a spatial variation step, either before, during or after the ion implantation step, such that the characteristics of separation of the exfoliation layer 122 from the donor semiconductor wafer 120 are directionally and/or temporally controllable. While not intending to limit the invention to any theory of operation, it is believed that such directional and/or temporal controllability may result in improved separation characteristics, such as smoother exposed surfaces on the exfoliation layer 122 and the donor semiconductor wafer 120 (post separation).
  • the directionally and/or temporally controllable characteristics of separation of the exfoliation layer 122 from the donor semiconductor wafer 120 may be achieved in a number of ways, such as by varying one or more parameters spatially across the weakened slice 125 in at least one of the X- and Y- axial directions.
  • the parameters may include one or more of the following, alone or in combination: (i) densities of nucleation sites resulting from the ion implantation step; (ii) depths of the weakened slice 125 from the implantation surface 121 (or the reference plane); (iii) artificially created damage locations (e.g., blind holes) through the implantation surface 121 at least to the weakened slice 125; and (iv) nucleation of defect sites and/or pressure increases throughout the weakened slice 125 using temperature gradients. [0041 ] As illustrated in FIGS .
  • the directionally and/or temporally controllable characteristics of separation of the exfoliation layer 122 from the donor semiconductor wafer 120 result in a propagating separation from one point, edge, and/or region to other points, edges, and/or regions of the weakened slice 125 as a function of time.
  • This is generally achieved as follows: first, varying the one or more parameters spatially across the weakened slice 125 as discussed above, and second, elevating the donor semiconductor wafer 120 to a temperature sufficient to initiate separation at the weakened slice 125 from such point, edge, and/or region.
  • FIG. 3 A is a top view of the donor semiconductor wafer 120 viewed through the implantation surface 121.
  • the variation in shading in the X-axial direction represents the spatial variation in the parameter (e.g., density of nucleation sites, pressure within the sites, degree of nucleation, distribution of artificially created damage sites (holes), implantation depth, etc.).
  • the one or more parameters vary from one edge 130A in the X-axial direction toward an opposite edge 130B of the donor semiconductor wafer 120 (and thus the weakened slice 125 thereof), or vice verse.
  • a graph of the separation parameter illustrates the cross-sectional profile of, for example, the density of nucleation sites within the weakened slice 125 as a function of the X-axial direction.
  • the separation parameter may represent one or more of the pressure within the nucleation sites, the degree of nucleation, the distribution of artificially created damage sites (holes), etc., each as a function of the X-axial, spatial metric.
  • a graph of the separation parameter illustrates the cross-sectional profile of, for example, the depth of the weakened slice 125 (e.g., corresponding to the ion implantation depth) as a function of the X-axial direction.
  • FIGS. 4A-4C illustrate further details associated with varying the one or more parameters spatially across the weakened slice 125.
  • the figures show top views of the donor semiconductor wafer 120 viewed through the implantation surface 121.
  • the variation in shading in the X-and Y- axial directions represent the spatial variation in the parameter, again density of nucleation sites, pressure within the sites, degree of nucleation, distribution of artificially created damage sites (holes), implantation depth, etc.
  • the parameter is varied spatially in both the X- and Y- axial directions.
  • the shading may represent that the parameter varies spatially starting from two edges 130A, 130D toward other edges 130B, 130C and varying at successively further distances in both the X- and Y- axial directions.
  • the propagation of separation illustrated by the broken arrow
  • the shading may represent that the parameter varies spatially starting from all edges 130 and varying toward the center of the donor semiconductor wafer 120, or vice verse.
  • a maximum density of nucleation sites exists at one or more edges, points, or regions of the weakened slice 125 of about 5x10 5 sites/cm 2 and a minimum density of nucleation sites exists spaced away therefrom in the weakened slice 125 of about 5x10 sites/cm .
  • a difference between the maximum density of nucleation sites and the minimum density of nucleation sites may be between about 10 fold.
  • the density of nucleation sites within the weakened slice 125 may be varied spatially by varying the dose of the ion implantation step.
  • the weakened slice 125 (and thus the exfoliation layer 122) is created by subjecting the implantation surface 121 to one or more ion implantation steps.
  • the implantation surface 121 of the donor semiconductor wafer 120 may be subject to a hydrogen ion implantation step to at least initiate the creation of the exfoliation layer 122 in the donor semiconductor wafer 120.
  • FIG. 5 A a simplified schematic of an Axcelis NV-10 type batch implanter is illustrated, which may be modified for use in spatially varying the density of nucleation sites within the weakened slice 125 by varying the dose of implanted ions.
  • Multiple donor semiconductor wafers 120 may be distributed azimuthally at a fixed radius on a platen 200 relative to the incident ion beam 202 (directed into the page).
  • Rotation of the platen 200 provides a pseudo-X-scan (dX/dt) while mechanical translation of the entire platen 200 provides the Y-scan (dY/dt).
  • pseudo-X-scan is used because for small radius platens 200, the X-scan is somewhat more curved as compared to larger radius platens 200, and thus, perfectly straight scans are not obtained on such rotating platens 200. Modulating the X-scan speed and/or the Y-scan speed will result in spatial variation in the dose.
  • a spatially varying dose may be achieved by not adhering to the conventional scan protocol, resulting in the patterns of, for example, FIGS. 3 A and 4A. For example, leaving the Y- scan speed uniform as the ion beam 202 travels radially toward the center of the platen 200.
  • Y-scan speed as the ion beam 202 travels radially toward the center of the platen 200.
  • An alternative approach is to vary the beam energy as a function of the scan rates and positions. These changes may be effected through modification to the control algorithm of the implanter in software, an electronic interface between the controlling software and the end station drive, or other mechanical modification.
  • FIG. 5B a simplified schematic of a single-substrate X-Y implanter is illustrated, which also may be modified for use in spatially varying the density of nucleation sites within the weakened slice 125 by varying the dose of implanted ions.
  • the electronic beam 202 is scanned much faster than the mechanical substrate scan (of FIG. 5A).
  • the conventional thinking in the art is to achieve a spatially uniform dose, and thus the X and Y scanning rates and beam energy are set such that the uniform dose is achieved.
  • spatially varying dosages may be achieved by not adhering to the conventional scanning protocol.
  • Significant spatial variation in implant dosage may be achieved through numerous combinations of variable X and Y scanning rates and/or beam energy.
  • One-dimensional or two-dimensional gradients may be produced, either vertical or horizontal, through such variation resulting in the patterns of, for example, FIGS. 3 A, 4A, 4B and 4C.
  • FIG. 5C a simplified schematic of an implanter is illustrated in accordance with ion shower techniques.
  • a ribbon beam 204 arises from an extended ion source.
  • a single uniform speed scan in proportion with a uniform beam energy in the orthogonal direction
  • a spatially uniform dose hi accordance with various aspects of the invention, however, a one-dimensional gradient (e.g., that of FIG. 3 A rotated 90 degrees) may be produced through variation in the mechanical scanning rate of the donor semiconductor wafers 120 through the ribbon beam 204.
  • Twisting the donor semiconductor wafers 120 by some angle relative to the ribbon beam 204 in combination with variation in the mechanical scanning rate may produce spatial variation in the dose in a manner similar to that of FIG. 4 A.
  • a spatially varying beam current along the beam source would provide an orthogonal gradient to the scan direction, providing additional degrees of freedom to produce the subject spatially varying dosages.
  • the substantially highest dose is within some desirable range in units of atoms/cm 2 and the lowest dose further therefrom in at least one of the X- and Y- axial directions is within some other desirable range in units of atoms/cm .
  • a difference between the maximum dose and the minimum dose may be between about 10-30 %, with a maximum variation of about a factor of three. In some applications, a difference of at least about 20% has been found to be important.
  • the density of nucleation sites within the weakened slice 125 may be varied spatially by implanting a first species of ions in a substantially uniform manner to establish the weakened slice 125 with a substantially uniform distribution. Thereafter, the donor semiconductor wafer 120 may be implanted with a second species of ions in a substantially non-uniform manner. The non-uniform implantation is established such that the second species of ions causes migration of atoms to the weakened slice 125 resulting in the spatially varying densities of nucleation sites across the weakened slice 125.
  • the first species of ions may be hydrogen ions and the second species of ions may be helium ions.
  • the non-uniform implantation may take place using the techniques described above, described later in this description, or gleaned from other sources.
  • the dose of the second species of ions may be spatially varied.
  • the variation in the dose of the second species of ions (such as He ions) will cause a subsequent non-uniform migration of the second species to the location of the first species, thereby establishing a non-uniform density of nucleation sites.
  • This variation will probably also vary the pressure in the platelets, which could also be beneficial.
  • the non-uniform implantation of the second species of ions may include implanting the second species of ions to varying depths spatially across the donor semiconductor wafer 120. Any of the known techniques for implanting ions to uniform depths may be modified by those skilled in the art in accordance with the teaching herein to achieve non-uniform depth profiles.
  • He ions can be implanted deeper than H, for example, as much as two times deeper or more. As the wafer temperature increases, much of the He ions will migrate to the site of shallower H ion implants and will provide the gas pressure for later separation.
  • the damage caused by more deeply buried He is located at a depth in the donor semiconductor wafer 120 far from the shallower H ion implant and fewer of such He ions will arrive there in a given time.
  • the opposite is true for the less deeply implanted He ions, thereby resulting in a spatially varying density of nucleation sites across the weakened slice 125.
  • the spatially varied density of nucleation sites may be achieved irrespective of the order of the first and second species of ions (e.g., He implanted first or H implanted first), the order of the multiple ion implantation steps may also contribute to the desired result. Indeed, the order of implantation, depending on ion species, may have an overall effect on the density even as the density also varies spatially. While counterintuitive and surprising to many skilled artisans, it has been found that H implanted first creates more nucleation sites. For a given dose, He is recognized by skilled artisans to produce about ten times the damage as H ions.
  • H ions a vacancy and interstitial semiconductor atom, or Frankel pair
  • Si atoms forming an Si — H bond
  • FIGS. 6A-6B where a further example is illustrated that may be suitable for achieving the spatial variation in the density of nucleation sites.
  • the spatial variation in the density of nucleation sites is achieved by adjusting the beam angle of the ion beam during the ion implantation step.
  • the beam angle may be adjusted in a number of ways, one such approach is to tilt the donor semiconductor wafer 120 with respect to the ion beam (e.g., a dot beam 202) as illustrated in FIG. 6A.
  • the donor semiconductor wafer 120 has a width (left-to- right as shown on the page), a depth (into the page) and a height (top-to-bottom as shown on the page).
  • the width and depth may define the X- and Y- axial directions, and the height may define a longitudinal axis, Lo, normal to the implantation surface 121.
  • the donor semiconductor wafer 120 is tilted such that the longitudinal axis Lo thereof is at an angle ⁇ with respect to a directional axis of an ion implantation beam (shown as a solid arrow) during the ion implantation step.
  • the angle ⁇ may be between about 1 to 45 degrees.
  • the width W of the beam 202 varies at the implantation surface 121 of the donor semiconductor wafer 120 from width Wa to width Wb, or vice verse.
  • the variation in width W contributes to a variation in the densities of nucleation sites resulting from the ion implantation in the scanning directions (which may be set up to vary along at least one of the X- and Y- axial directions).
  • the implant beam 202 may include hydrogen ions, which have the same (positive) electrical charge. As particles with the same charge repel each other, the beam 202 is wider at a longer distance from ion source (position A), and narrower at a shorter distance from ion source (position B).
  • the more focused (lower width Wb) ion beam at position B heats the local area of the donor semiconductor wafer 120 to a higher degree than the less focused (higher width Wa) ion beam at position A. Under higher temperature, more hydrogen ions diffuse out from such local area, and a lower share of hydrogen ions remain as compared to other areas. As illustrated in FIG. 6B, this results in laterally non-uniform distribution of hydrogen (and thus the density of nucleation sites) in the weakened slice 125 of the donor semiconductor wafer 120.
  • Similar spatial variation in the density of nucleation sites may be achieved by adjusting the angle of the beam source or incorporating some of the known mechanisms for adjusting the collimation of the ion beam 202.
  • a further technique that may be suitable for achieving the spatial variation in the density of nucleation sites is to employ a two-stage ion implantation step.
  • a first ion implantation is performed to implant ions that have the effect of attracting a second species of ions. Thereafter, the second species of ions are implanted.
  • the first species of ions are implanted in a spatially non-uniform manner, using any of the suitable techniques described above or later herein.
  • the resultant weakened slice 125 exhibits a non-uniform density of nucleation sites.
  • the first ion species may be based on the material of the donor semiconductor wafer 120, such as using silicon ions for implantation in a silicon donor semiconductor wafer 120.
  • Such Si ions may have the property of trapping a second species of ions, such as hydrogen ions.
  • H ions bond with some semiconductor atoms, such as Si atoms, forming an Si - H bond.
  • silicon- into-silicon implantation may be performed at doses and energies known in the art, such as is described in U.S. Patent No. 7,148,124, the entire disclosure of which is incorporated by reference.
  • a spatial density distribution of the trapping ion specie in this case Si is non-uniform (e.g., highest at one edge and lowest on an opposite edge of the donor semiconductor wafer 120, or other variations discussed herein).
  • a second species of ions such as hydrogen, is implanted, which may be a uniform distribution.
  • the amount of hydrogen remaining in the weakened slice 125 of the donor semiconductor wafer 120 will depend on two factors: (1) the concentrating distribution of sites that are able to trap the second species, hydrogen, and (2) the available hydrogen (the hydrogen implanted and remaining from the implant dose).
  • the non-uniform spatial distribution of the species may be reversed to achieve a similar result.
  • the first species may implanted uniformly, followed by a non-uniform implantation of the second species.
  • both implants may be spatially non-uniform.
  • the non-uniform distribution of the second species (e.g., hydrogen) within the weakened slice 125 results in a point, edge or region of highest concentration of hydrogen, which in turn is location of the lowest temperature for initiating cleavage.
  • the arrow A illustrates the directionally and/or temporally controllable characteristics of separation of the exfoliation layer 122 from the donor semiconductor wafer 120, where a propagating separation from one a point, edge, and/or region to other points, edges, and/or regions of the weakened slice 125 is achieved as a function of time.
  • the donor semiconductor wafer 120 is elevated to a temperature sufficient to initiate separation at the weakened slice 125 from a point, edge, and/or region of highest density.
  • the depth of the weakened slice 125 may be varied spatially by adjusting beam angle of the ion beam during the ion implantation step. Indeed, the process discussed with respect to FIGS.
  • the spatial variation in the depth of the weakened slice 125 may be achieved by varying at least one of: (1) the angle ⁇ of tilt (shown and described with reference to FIG. 6A); and (2) a twist of the donor semiconductor wafer 120 about the longitudinal axis Lo thereof with respect to the directional axis of the ion implantation beam 202.
  • Adjustments in the tilt and/or twist are made to adjust a degree of channeling through the lattice structure of the donor semiconductor wafer 120, where such channels tend to align and misalign with the ion beam 202 as the ion beam 202 scans across the implantation surface 121. As the degree of channeling varies spatially, so does the depth of the weakened slice 125.
  • the angle ⁇ may be between about 1-10 deg degrees and the angle of twist may be between about 1-45 degrees.
  • the spatial variation step may include varying an energy level of the ion beam 202 such that as the ion beam 202 scans across the implantation surface 121 of the donor semiconductor wafer 120, depths of the weakened slice 125 from the implantation surface 121 vary spatially across the donor semiconductor wafer 120.
  • the above techniques results in a laterally nonuniform depth of the weakened slice (or implant depth) of the donor semiconductor wafer 120.
  • a further parameter that may be exploited to achieve spatial variations is the width of the ion deposition distribution (or straggle).
  • the width of the ion distribution through the weakened slice 125 varies as a function of the angle of the tilt of the donor semiconductor wafer 120 (or more generally the beam angle).
  • a spatially varying distribution width may be achieved in the weakened slice 125 (as illustrated in FIG. 8B).
  • another technique for spatially varying the depth of the weakened slice 125 includes subjecting the donor semiconductor wafer 120 to a post implantation material removal process such that the depths of the weakened slice 125 from the implantation surface 121 vary spatially across the donor semiconductor wafer 120.
  • the donor semiconductor wafer 120 may be subject to some deterministic polishing process or plasma-assisted chemical etching (PACE). These techniques permit local control of the amount of material removed by the polishing step.
  • Other methods including Reactive Ion Etching (RIE), Chemical Mechanical Polishing (CMP), and wet chemical etching may also have non-uniform material removal across the exposed surface which is regular and reproducible.
  • One or more of these or other techniques may be used to introduce slight variation in the depth of the weakened slice 125 from the implantation surface 121, such as any of those illustrated in FIGS. 3 A, 4A, 4B, 4C, and others.
  • the ion implantation step prior to material removal may be spatially uniform or non-uniform.
  • the spatial variation step may include using a mask 220A or 220B on the implantation surface 121 of the donor semiconductor wafer 120 in a spatially non-uniform manner such that penetration of the ions is impeded to varying degrees as the ion beam 202 scans across the implantation surface 121.
  • the masking film 220 may include silicon dioxide, organic polymers such as photoresist, and others. Possible deposition techniques include plasma-enhanced chemical vapor deposition (PECVD), spin coating, Polydimethylsiloxane (PDMS) stamping, etc.
  • PECVD plasma-enhanced chemical vapor deposition
  • PDMS Polydimethylsiloxane
  • the masking film 220 thickness may be less than or comparable to the intended depth of the weakened slice 125.
  • the impeding action of the mask 220 will translate into spatial modulation in primarily the depth of the implanted species in the donor semiconductor wafer 120.
  • the desired characteristic may be achieved by adding length to the ion path, scattering the ions to alter the degree of channeling, or other phenomena.
  • the donor semiconductor wafer 120 is elevated to a temperature sufficient to initiate separation at the weakened slice 125 from a point, edge, and/or region of lowest depth.
  • the donor semiconductor wafer 120 is elevated to further temperatures sufficient to continue separation substantially along the weakened slice 125 directionally as a function of the spatial variation of the depth from lowest depth to highest depth.
  • the spatial variation step may include boring one or more blind holes 230 through the implantation surface 121 at least to the weakened slice 125, and preferably through the weakened slice 125 (FIG. 10B). While not intending to limit the invention to any theory of operation, it is believed that during or after bonding to the substrate 102 (FIG. 10C), elevating the donor semiconductor wafer 120 to higher temperature will initiate separation at the blind hole 230 (FIG. 10D) prior to separation at locations without such hole. As illustrated in FIG. 11, boring an array of blind holes 230 through the implantation surface 121 may create a non-uniform spatial distribution of such holes. Thus, elevating the donor semiconductor wafer 120 to temperatures sufficient to initiate and continue separation substantially along the weakened slice 125 may be achieved directionally as a function of the distribution of the array of blind holes 230, from highest to lowest concentration.
  • the spatial variation step may include subjecting the donor semiconductor wafer 120 to a non-uniform time-temperature profile such that the nucleation site density or pressure at respective spatial locations throughout the weakened slice 125 vary spatially across the donor semiconductor wafer 120.
  • the illustrated temperature gradient in FIG. 12A applies a higher temperature to the left side of the wafer 120 as compared to the right side. This temperature gradient may be applied either before bonding or in-situ during bonding to the substrate 102.
  • the separation threshold time for a given process temperature is expected to follow an Arrhenius relationship, where the separation threshold time is exponentially proportional to the inverse of the process temperature.
  • the parameter of interest is the ratio of the process time to the separation threshold time at the process temperature. Any of the aforementioned spatially varying parameter profiles discussed herein or otherwise desirable may be achieved by adjusting the process time-separation time ratio profile.
  • the donor semiconductor wafer 120 is elevated to a temperature sufficient to initiate separation at the weakened slice 125 from a point, edge, and/or region of maximum process time-separation time ratio.
  • the maximum process time-separation time ratio is on the left side of the wafer 120.
  • the donor semiconductor wafer 120 is then elevated to further temperatures sufficient to continue separation substantially along the weakened slice 125 directionally as a function of the varying time-temperature profile, from maximum process time-separation time ratio(s) to minimum process time-separation time ratio(s).
  • the substantially high process time-separation time ratio is between about 0.9 and 0.5 and a lowest process time-separation time ratio is between about 0 and 0.5.
  • Various mechanisms may be used pre-bonding or in-situ bonding to achieve the spatially varying time-temperature profile.
  • one or more spatially nonuniform conductive, convective, or radiating heating techniques may be employed to heat the donor semiconductor wafer 120.
  • Controlled time/temperature gradients may be achieved by direct or indirect thermal contact (conduction) to achieve any of the desirable profiles.
  • An addressable, two- dimensional array of hotplate elements may be used to achieve different profiles based on computer control or programming.
  • Localized infrared radiation employing, for example, a lamp as used in rapid thermal annealing (radiation) may be employed, and/or visible or near-infrared laser radiation may be used to provide localized and spatially non-uniform heating (radiation).
  • a uniform or non-uniform thermal profile through any means and application of a spatially non-uniform cooling mechanism, such as direct contact (conductive), or gas or fluid flow jets (conductive / convective), may be employed to achieve the desired time-temperature gradient.
  • heating/cooling techniques may be used pre-bonding or in-situ.
  • the bonding apparatus described in, for example, U.S. Patent Application No. 11/417,445, entitled HIGH TEMPERATURE ANODIC BONDING APPARATUS, the entire disclosure of which is hereby incorporated by reference, may be adapted for use in accordance with the present invention.
  • Management of thermal radiation loss in the bonding apparatus may be controlled, and thus exploited to achieve the time-temperature gradient, through the incorporation of infrared reflecting elements around the perimeter of the bonding apparatus to ⁇ iinimize radiation loss and maximize edge temperature.
  • management of thermal radiation loss in the bonding apparatus may be controlled through the incorporation of cooled infrared absorbers to maximize radiation loss and minimize edge temperature.
  • Many variations on the above themes may be used to achieve the desired time-temperature gradient.

Abstract

Les procédés et appareils selon l’invention servent à former une structure de semi-conducteur sur isolant (SOI), consistant à soumettre une surface d’implantation d’une plaquette semi-conductrice donneuse vers une étape d’implantation d’ions pour créer une tranche affaiblie dans la section transversale définissant une couche d’exfoliation de la plaquette semi-conductrice donneuse; et à soumettre la plaquette semi-conductrice donneuse à une étape de variation spatiale, avant, pendant ou après l’étape d’implantation d’ions, de sorte qu’au moins un paramètre de la tranche affaiblie varie spatialement à travers la tranche affaiblie dans au moins l’une des directions axiales X ou Y.
PCT/US2009/062531 2008-10-30 2009-10-29 Procédés et appareils de production de semi-conducteurs sur des structures isolantes au moyen d’une exfoliation dirigée WO2010059367A2 (fr)

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EP09744304A EP2359400A2 (fr) 2008-10-30 2009-10-29 Procédés et appareils de production de semi-conducteurs sur des structures isolantes au moyen d une exfoliation dirigée
JP2011534755A JP5650653B2 (ja) 2008-10-30 2009-10-29 有向性の剥離を利用する、半導体・オン・インシュレータ構造を生産するための方法および装置
CN200980143709.4A CN102203933B (zh) 2008-10-30 2009-10-29 使用定向剥落在绝缘体结构上形成半导体的方法和装置

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US12/290,384 2008-10-30
US12/290,384 US8003491B2 (en) 2008-10-30 2008-10-30 Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation
US12/290,362 US7816225B2 (en) 2008-10-30 2008-10-30 Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation
US12/290,362 2008-10-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012186292A (ja) * 2011-03-04 2012-09-27 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3055063B1 (fr) * 2016-08-11 2018-08-31 Soitec Procede de transfert d'une couche utile
CN111834205B (zh) * 2020-07-07 2021-12-28 中国科学院上海微系统与信息技术研究所 一种异质半导体薄膜及其制备方法
CN114975765A (zh) * 2022-07-19 2022-08-30 济南晶正电子科技有限公司 复合单晶压电薄膜及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003032384A1 (fr) 2001-10-11 2003-04-17 Commissariat A L'energie Atomique Procede de fabrication de couches minces contenant des microcomposants
US7176528B2 (en) 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
US20070117354A1 (en) 2005-11-22 2007-05-24 Gadkaree Kishor P Large area semiconductor on glass insulator

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2714524B1 (fr) * 1993-12-23 1996-01-26 Commissariat Energie Atomique Procede de realisation d'une structure en relief sur un support en materiau semiconducteur
US5985742A (en) * 1997-05-12 1999-11-16 Silicon Genesis Corporation Controlled cleavage process and device for patterned films
JP3031904B2 (ja) * 1998-02-18 2000-04-10 キヤノン株式会社 複合部材とその分離方法、及びそれを利用した半導体基体の製造方法
TW437078B (en) 1998-02-18 2001-05-28 Canon Kk Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof
US20010007790A1 (en) * 1998-06-23 2001-07-12 Henley Francois J. Pre-semiconductor process implant and post-process film separation
US6054370A (en) * 1998-06-30 2000-04-25 Intel Corporation Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer
FR2811807B1 (fr) * 2000-07-12 2003-07-04 Commissariat Energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince
JP2002124652A (ja) * 2000-10-16 2002-04-26 Seiko Epson Corp 半導体基板の製造方法、半導体基板、電気光学装置並びに電子機器
FR2847077B1 (fr) * 2002-11-12 2006-02-17 Soitec Silicon On Insulator Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation
EP1429381B1 (fr) * 2002-12-10 2011-07-06 S.O.I.Tec Silicon on Insulator Technologies Procédé de fabrication d'un matériau composé
DE10318283A1 (de) * 2003-04-22 2004-11-25 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
US7148124B1 (en) * 2004-11-18 2006-12-12 Alexander Yuri Usenko Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers
JP2006324051A (ja) * 2005-05-17 2006-11-30 Nissin Ion Equipment Co Ltd 荷電粒子ビーム照射方法および装置
JP4977999B2 (ja) * 2005-11-21 2012-07-18 株式会社Ｓｕｍｃｏ 貼合せ基板の製造方法及びその方法で製造された貼合せ基板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003032384A1 (fr) 2001-10-11 2003-04-17 Commissariat A L'energie Atomique Procede de fabrication de couches minces contenant des microcomposants
US7176528B2 (en) 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
US20070117354A1 (en) 2005-11-22 2007-05-24 Gadkaree Kishor P Large area semiconductor on glass insulator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012186292A (ja) * 2011-03-04 2012-09-27 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法

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CN102203933A (zh) 2011-09-28
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CN102203933B (zh) 2015-12-02
WO2010059361A3 (fr) 2010-08-12
KR20110081881A (ko) 2011-07-14
TWI451534B (zh) 2014-09-01
JP5650652B2 (ja) 2015-01-07
TWI430338B (zh) 2014-03-11
JP5650653B2 (ja) 2015-01-07
TW201036112A (en) 2010-10-01
EP2359400A2 (fr) 2011-08-24
EP2356676A2 (fr) 2011-08-17
CN102203934B (zh) 2014-02-12
KR20110081318A (ko) 2011-07-13
JP2012507868A (ja) 2012-03-29
WO2010059367A3 (fr) 2010-08-05
WO2010059361A2 (fr) 2010-05-27
TW201030815A (en) 2010-08-16

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