JP5650653B2 - 有向性の剥離を利用する、半導体・オン・インシュレータ構造を生産するための方法および装置 - Google Patents
有向性の剥離を利用する、半導体・オン・インシュレータ構造を生産するための方法および装置 Download PDFInfo
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- JP5650653B2 JP5650653B2 JP2011534755A JP2011534755A JP5650653B2 JP 5650653 B2 JP5650653 B2 JP 5650653B2 JP 2011534755 A JP2011534755 A JP 2011534755A JP 2011534755 A JP2011534755 A JP 2011534755A JP 5650653 B2 JP5650653 B2 JP 5650653B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
- H01L21/786—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being other than a semiconductor body, e.g. insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Physical Vapour Deposition (AREA)
- Recrystallisation Techniques (AREA)
Description
Claims (4)
- 半導体・オン・インシュレータ(SOI)構造の形成方法であって、
ドナー半導体ウエハの注入面をイオン注入工程に供し、断面に脆弱化薄片を生成してドナー半導体ウエハの剥離層を画成し、
前記イオン注入工程から得られた核生成部位の最高密度の点、エッジ、および/または領域が、前記ドナー半導体ウエハのエッジの全体にわたり、前記核生成部位の密度が、XおよびY軸方向のうち少なくとも一方向における前記脆弱化薄片にわたって空間的に変化するように、前記イオン注入工程の前、間、または後で、前記ドナー半導体ウエハを空間的変動工程に供する各工程を有し、
前記核生成部位の最高局所密度が、前記脆弱な薄片における5×10 5 部位/cm 2 となる第1の領域に存在し、
前記核生成部位の最低密度が、前記脆弱な薄片における5×10 4 部位/cm 2 となる第2の領域に存在し、
前記第2の領域が、XおよびY軸のうち少なくとも一方における前記第1の領域から間隔をあけ、
前記核生成部位の密度が、前記第1の領域から前記第2の領域へ向けて減少することを特徴とする方法。 - 前記脆弱化薄片の第1の領域における前記核生成部位の最高密度と、前記脆弱化薄片の第2の領域における前記核生成部位の最低密度との間に10倍の差があることを特徴とする請求項1記載の方法。
- 前記核生成部位の最高密度の点、エッジ、および/または領域から、前記脆弱化薄片の分離を開始するのに十分な温度まで、前記ドナー半導体ウエハを上昇させる工程をさらに有してなることを特徴とする請求項1または2記載の方法。
- 最高密度から最低密度まで、前記核生成部位の密度変化の関数として、実質的に、有向的に脆弱化薄片に沿って、分離を継続するのに十分なさらなる温度まで、前記ドナー半導体ウエハを上昇させる工程をさらに有してなることを特徴とする請求項3記載の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/290,384 US8003491B2 (en) | 2008-10-30 | 2008-10-30 | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation |
US12/290,362 | 2008-10-30 | ||
US12/290,362 US7816225B2 (en) | 2008-10-30 | 2008-10-30 | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation |
US12/290,384 | 2008-10-30 | ||
PCT/US2009/062531 WO2010059367A2 (en) | 2008-10-30 | 2009-10-29 | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2012507870A JP2012507870A (ja) | 2012-03-29 |
JP2012507870A5 JP2012507870A5 (ja) | 2012-12-20 |
JP5650653B2 true JP5650653B2 (ja) | 2015-01-07 |
Family
ID=41559616
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011534746A Expired - Fee Related JP5650652B2 (ja) | 2008-10-30 | 2009-10-29 | 有向表面剥離を用いる絶縁体上半導体構造作成方法及び装置 |
JP2011534755A Expired - Fee Related JP5650653B2 (ja) | 2008-10-30 | 2009-10-29 | 有向性の剥離を利用する、半導体・オン・インシュレータ構造を生産するための方法および装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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JP2011534746A Expired - Fee Related JP5650652B2 (ja) | 2008-10-30 | 2009-10-29 | 有向表面剥離を用いる絶縁体上半導体構造作成方法及び装置 |
Country Status (6)
Country | Link |
---|---|
EP (2) | EP2356676A2 (ja) |
JP (2) | JP5650652B2 (ja) |
KR (2) | KR101568898B1 (ja) |
CN (2) | CN102203934B (ja) |
TW (2) | TWI430338B (ja) |
WO (2) | WO2010059367A2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5703853B2 (ja) * | 2011-03-04 | 2015-04-22 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
FR3055063B1 (fr) * | 2016-08-11 | 2018-08-31 | Soitec | Procede de transfert d'une couche utile |
CN111834205B (zh) * | 2020-07-07 | 2021-12-28 | 中国科学院上海微系统与信息技术研究所 | 一种异质半导体薄膜及其制备方法 |
CN114975765A (zh) * | 2022-07-19 | 2022-08-30 | 济南晶正电子科技有限公司 | 复合单晶压电薄膜及其制备方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
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FR2714524B1 (fr) * | 1993-12-23 | 1996-01-26 | Commissariat Energie Atomique | Procede de realisation d'une structure en relief sur un support en materiau semiconducteur |
US6146979A (en) * | 1997-05-12 | 2000-11-14 | Silicon Genesis Corporation | Pressurized microbubble thin film separation process using a reusable substrate |
TW437078B (en) * | 1998-02-18 | 2001-05-28 | Canon Kk | Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof |
JP3031904B2 (ja) * | 1998-02-18 | 2000-04-10 | キヤノン株式会社 | 複合部材とその分離方法、及びそれを利用した半導体基体の製造方法 |
US20010007790A1 (en) * | 1998-06-23 | 2001-07-12 | Henley Francois J. | Pre-semiconductor process implant and post-process film separation |
US6054370A (en) * | 1998-06-30 | 2000-04-25 | Intel Corporation | Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer |
FR2811807B1 (fr) * | 2000-07-12 | 2003-07-04 | Commissariat Energie Atomique | Procede de decoupage d'un bloc de materiau et de formation d'un film mince |
JP2002124652A (ja) * | 2000-10-16 | 2002-04-26 | Seiko Epson Corp | 半導体基板の製造方法、半導体基板、電気光学装置並びに電子機器 |
FR2830983B1 (fr) * | 2001-10-11 | 2004-05-14 | Commissariat Energie Atomique | Procede de fabrication de couches minces contenant des microcomposants |
FR2847077B1 (fr) * | 2002-11-12 | 2006-02-17 | Soitec Silicon On Insulator | Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation |
EP1429381B1 (en) * | 2002-12-10 | 2011-07-06 | S.O.I.Tec Silicon on Insulator Technologies | A method for manufacturing a material compound |
US7176528B2 (en) | 2003-02-18 | 2007-02-13 | Corning Incorporated | Glass-based SOI structures |
DE10318283A1 (de) * | 2003-04-22 | 2004-11-25 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur |
US7148124B1 (en) * | 2004-11-18 | 2006-12-12 | Alexander Yuri Usenko | Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers |
JP2006324051A (ja) * | 2005-05-17 | 2006-11-30 | Nissin Ion Equipment Co Ltd | 荷電粒子ビーム照射方法および装置 |
JP4977999B2 (ja) * | 2005-11-21 | 2012-07-18 | 株式会社Sumco | 貼合せ基板の製造方法及びその方法で製造された貼合せ基板 |
US7691730B2 (en) * | 2005-11-22 | 2010-04-06 | Corning Incorporated | Large area semiconductor on glass insulator |
-
2009
- 2009-10-28 TW TW098136605A patent/TWI430338B/zh not_active IP Right Cessation
- 2009-10-28 TW TW098136607A patent/TWI451534B/zh not_active IP Right Cessation
- 2009-10-29 EP EP09744303A patent/EP2356676A2/en not_active Withdrawn
- 2009-10-29 JP JP2011534746A patent/JP5650652B2/ja not_active Expired - Fee Related
- 2009-10-29 EP EP09744304A patent/EP2359400A2/en not_active Withdrawn
- 2009-10-29 CN CN200980143710.7A patent/CN102203934B/zh not_active Expired - Fee Related
- 2009-10-29 JP JP2011534755A patent/JP5650653B2/ja not_active Expired - Fee Related
- 2009-10-29 WO PCT/US2009/062531 patent/WO2010059367A2/en active Application Filing
- 2009-10-29 CN CN200980143709.4A patent/CN102203933B/zh not_active Expired - Fee Related
- 2009-10-29 KR KR1020117012221A patent/KR101568898B1/ko not_active IP Right Cessation
- 2009-10-29 WO PCT/US2009/062504 patent/WO2010059361A2/en active Application Filing
- 2009-10-29 KR KR1020117012220A patent/KR20110081318A/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
CN102203934A (zh) | 2011-09-28 |
CN102203933B (zh) | 2015-12-02 |
WO2010059361A3 (en) | 2010-08-12 |
KR20110081881A (ko) | 2011-07-14 |
JP2012507870A (ja) | 2012-03-29 |
JP2012507868A (ja) | 2012-03-29 |
JP5650652B2 (ja) | 2015-01-07 |
CN102203934B (zh) | 2014-02-12 |
TWI451534B (zh) | 2014-09-01 |
TW201030815A (en) | 2010-08-16 |
WO2010059361A2 (en) | 2010-05-27 |
KR20110081318A (ko) | 2011-07-13 |
EP2356676A2 (en) | 2011-08-17 |
WO2010059367A3 (en) | 2010-08-05 |
TW201036112A (en) | 2010-10-01 |
TWI430338B (zh) | 2014-03-11 |
WO2010059367A2 (en) | 2010-05-27 |
CN102203933A (zh) | 2011-09-28 |
KR101568898B1 (ko) | 2015-11-12 |
EP2359400A2 (en) | 2011-08-24 |
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