WO2010059367A3 - Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation - Google Patents

Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation Download PDF

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Publication number
WO2010059367A3
WO2010059367A3 PCT/US2009/062531 US2009062531W WO2010059367A3 WO 2010059367 A3 WO2010059367 A3 WO 2010059367A3 US 2009062531 W US2009062531 W US 2009062531W WO 2010059367 A3 WO2010059367 A3 WO 2010059367A3
Authority
WO
WIPO (PCT)
Prior art keywords
methods
exfoliation
directed
semiconductor wafer
producing semiconductor
Prior art date
Application number
PCT/US2009/062531
Other languages
French (fr)
Other versions
WO2010059367A2 (en
Inventor
Sarko Cherekdjian
Jeffrey S Cites
James G Couillard
Richard O Maschmeyer
Michael J. Moore
Alex Usenko
Original Assignee
Corning Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/290,384 external-priority patent/US8003491B2/en
Priority claimed from US12/290,362 external-priority patent/US7816225B2/en
Application filed by Corning Incorporated filed Critical Corning Incorporated
Priority to CN200980143709.4A priority Critical patent/CN102203933B/en
Priority to EP09744304A priority patent/EP2359400A2/en
Priority to JP2011534755A priority patent/JP5650653B2/en
Publication of WO2010059367A2 publication Critical patent/WO2010059367A2/en
Publication of WO2010059367A3 publication Critical patent/WO2010059367A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/786—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being other than a semiconductor body, e.g. insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

Methods and apparatus provide for forming a semiconductor-on-insulator (SOI) structure, including subjecting a implantation surface of a donor semiconductor wafer to an ion implantation step to create a weakened slice in cross-section defining an exfoliation layer of the donor semiconductor wafer; and subjecting the donor semiconductor wafer to a spatial variation step, either before, during or after the ion implantation step, such that at least one parameter of the weakened slice varies spatially across the weakened slice in at least one of X- and Y- axial directions.
PCT/US2009/062531 2008-10-30 2009-10-29 Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation WO2010059367A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN200980143709.4A CN102203933B (en) 2008-10-30 2009-10-29 Use orientation to peel off and form method for semiconductor and device on insulator structure
EP09744304A EP2359400A2 (en) 2008-10-30 2009-10-29 Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation
JP2011534755A JP5650653B2 (en) 2008-10-30 2009-10-29 Method and apparatus for producing semiconductor-on-insulator structures utilizing directional debonding

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12/290,362 2008-10-30
US12/290,384 US8003491B2 (en) 2008-10-30 2008-10-30 Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation
US12/290,384 2008-10-30
US12/290,362 US7816225B2 (en) 2008-10-30 2008-10-30 Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation

Publications (2)

Publication Number Publication Date
WO2010059367A2 WO2010059367A2 (en) 2010-05-27
WO2010059367A3 true WO2010059367A3 (en) 2010-08-05

Family

ID=41559616

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2009/062504 WO2010059361A2 (en) 2008-10-30 2009-10-29 Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation
PCT/US2009/062531 WO2010059367A2 (en) 2008-10-30 2009-10-29 Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/US2009/062504 WO2010059361A2 (en) 2008-10-30 2009-10-29 Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation

Country Status (6)

Country Link
EP (2) EP2356676A2 (en)
JP (2) JP5650652B2 (en)
KR (2) KR20110081318A (en)
CN (2) CN102203934B (en)
TW (2) TWI451534B (en)
WO (2) WO2010059361A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5703853B2 (en) * 2011-03-04 2015-04-22 信越半導体株式会社 Manufacturing method of bonded wafer
FR3055063B1 (en) * 2016-08-11 2018-08-31 Soitec METHOD OF TRANSFERRING A USEFUL LAYER
CN111834205B (en) * 2020-07-07 2021-12-28 中国科学院上海微系统与信息技术研究所 Heterogeneous semiconductor film and preparation method thereof
CN114975765A (en) * 2022-07-19 2022-08-30 济南晶正电子科技有限公司 Composite single crystal piezoelectric film and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0660140A1 (en) * 1993-12-23 1995-06-28 Commissariat A L'energie Atomique Method for making a relief structure on a substrate from semiconductor material
US6054370A (en) * 1998-06-30 2000-04-25 Intel Corporation Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer
WO2003032384A1 (en) * 2001-10-11 2003-04-17 Commissariat A L'energie Atomique Method for making thin layers containing microcomponents
EP1788621A2 (en) * 2005-11-21 2007-05-23 Sumco Corporation Method for manufacturing bonded substrate and bonded substrate manufactured by the method

Family Cites Families (13)

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Publication number Priority date Publication date Assignee Title
US6155909A (en) * 1997-05-12 2000-12-05 Silicon Genesis Corporation Controlled cleavage system using pressurized fluid
MY118019A (en) * 1998-02-18 2004-08-30 Canon Kk Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof
JP3031904B2 (en) * 1998-02-18 2000-04-10 キヤノン株式会社 Composite member, method of separating the same, and method of manufacturing semiconductor substrate using the same
US20010007790A1 (en) * 1998-06-23 2001-07-12 Henley Francois J. Pre-semiconductor process implant and post-process film separation
FR2811807B1 (en) * 2000-07-12 2003-07-04 Commissariat Energie Atomique METHOD OF CUTTING A BLOCK OF MATERIAL AND FORMING A THIN FILM
JP2002124652A (en) * 2000-10-16 2002-04-26 Seiko Epson Corp Manufacturing method of semiconductor substrate, the semiconductor substrate, electro-optical device, and electronic appliance
FR2847077B1 (en) * 2002-11-12 2006-02-17 Soitec Silicon On Insulator SEMICONDUCTOR COMPONENTS, PARTICULARLY OF THE MIXED SOI TYPE, AND METHOD OF MAKING SAME
EP1429381B1 (en) * 2002-12-10 2011-07-06 S.O.I.Tec Silicon on Insulator Technologies A method for manufacturing a material compound
US7176528B2 (en) 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
DE10318283A1 (en) * 2003-04-22 2004-11-25 Forschungszentrum Jülich GmbH Process for producing a strained layer on a substrate and layer structure
US7148124B1 (en) * 2004-11-18 2006-12-12 Alexander Yuri Usenko Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers
JP2006324051A (en) * 2005-05-17 2006-11-30 Nissin Ion Equipment Co Ltd Charge particle beam irradiation method and device
US7691730B2 (en) * 2005-11-22 2010-04-06 Corning Incorporated Large area semiconductor on glass insulator

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0660140A1 (en) * 1993-12-23 1995-06-28 Commissariat A L'energie Atomique Method for making a relief structure on a substrate from semiconductor material
US6054370A (en) * 1998-06-30 2000-04-25 Intel Corporation Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer
WO2003032384A1 (en) * 2001-10-11 2003-04-17 Commissariat A L'energie Atomique Method for making thin layers containing microcomponents
EP1788621A2 (en) * 2005-11-21 2007-05-23 Sumco Corporation Method for manufacturing bonded substrate and bonded substrate manufactured by the method

Also Published As

Publication number Publication date
EP2359400A2 (en) 2011-08-24
CN102203934B (en) 2014-02-12
JP2012507870A (en) 2012-03-29
KR20110081318A (en) 2011-07-13
KR101568898B1 (en) 2015-11-12
TWI451534B (en) 2014-09-01
TW201036112A (en) 2010-10-01
WO2010059361A2 (en) 2010-05-27
WO2010059367A2 (en) 2010-05-27
CN102203934A (en) 2011-09-28
CN102203933B (en) 2015-12-02
KR20110081881A (en) 2011-07-14
TWI430338B (en) 2014-03-11
CN102203933A (en) 2011-09-28
TW201030815A (en) 2010-08-16
JP5650653B2 (en) 2015-01-07
JP2012507868A (en) 2012-03-29
WO2010059361A3 (en) 2010-08-12
JP5650652B2 (en) 2015-01-07
EP2356676A2 (en) 2011-08-17

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