TWI430338B - Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation - Google Patents

Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation Download PDF

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TWI430338B
TWI430338B TW098136605A TW98136605A TWI430338B TW I430338 B TWI430338 B TW I430338B TW 098136605 A TW098136605 A TW 098136605A TW 98136605 A TW98136605 A TW 98136605A TW I430338 B TWI430338 B TW I430338B
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semiconductor wafer
depth
donor semiconductor
weakened
weakened sheet
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TW201030815A (en
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Sarko Cherekdjian
Jeffrey Scott Cites
James Gregory Couillard
Richard Orr Maschmeyer
Michael John Moore
Alex Usenko
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Corning Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/786Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being other than a semiconductor body, e.g. insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Description

使用定向剝離作用製造絕緣體上半導體結構之方法及裝置Method and apparatus for fabricating a semiconductor-on-insulator structure using directional stripping

本申請案主張以2008年10月30日申請之美國專利申請案第12/290,384號及2008年10月30日申請之美國專利申請案第12/290,362號為優先權,兩者全文皆併入本文中作為參考。The present application claims priority to U.S. Patent Application Serial No. 12/290,384, filed on Oct. 30, 2008, and to This is used as a reference.

本發明係關於絕緣體上半導體(SOI)結構之製造,例如為非圓形斷面的SOI結構及/或相當大的斷面面積的SOI結構。This invention relates to the fabrication of semiconductor-on-insulator (SOI) structures, such as SOI structures having a non-circular cross section and/or SOI structures having a relatively large cross-sectional area.

隨著市場需求不斷持續地增加,絕緣體上半導體(SOI)裝置變得越來越重要。SOI技術對高效能薄膜電晶體(TFT)、太陽能電池、和顯示器而言也變得越來越重要,譬如 主動式矩陣顯示器、有機發光二極體(OLED)顯示器、液晶顯示器(LCD)、積體電路、光伏打裝置等等。SOI結構可包括絕緣材料上一薄層的半導體材料,譬如矽。As market demand continues to increase, semiconductor-on-insulator (SOI) devices are becoming more and more important. SOI technology is also becoming more and more important for high performance thin film transistors (TFTs), solar cells, and displays, such as Active matrix display, organic light emitting diode (OLED) display, liquid crystal display (LCD), integrated circuit, photovoltaic device, and the like. The SOI structure can include a thin layer of semiconductor material on the insulating material, such as germanium.

取得SOI結構的各種方式包括在晶格匹配基板上的矽(Si)磊晶成長,以及黏結單晶矽晶片到另一矽晶片。更進一步的方法包括植入氫或氧離子的離子植入技術,在氧離子植入的情況下於以Si覆蓋之矽晶片內形成埋藏的氧化物層,或者在氫離子植入的情況下分離(剝離)薄Si層以黏結到另一具有氧化層的Si晶片。Various ways of achieving the SOI structure include germanium (Si) epitaxial growth on a lattice matching substrate, and bonding of a single crystal germanium wafer to another germanium wafer. Further methods include ion implantation techniques in which hydrogen or oxygen ions are implanted, in the case of oxygen ion implantation, a buried oxide layer is formed in a Si-covered germanium wafer, or in the case of hydrogen ion implantation. The thin Si layer is (stripped) to be bonded to another Si wafer having an oxide layer.

美國專利第7,176,528號說明了一種利用剝離技術產生玻璃上半導體(SOG)結構的處理方式。這些步驟包括:(i)將矽晶片表面暴露至氫離子植入以產生黏結表面;(ii)將晶片的黏結表面和玻璃基板接觸;(iii)施加壓力、溫度和電壓到晶片和玻璃基板促進其間的黏結;和(iv)從矽晶片分離玻璃基板和矽薄膜層。U.S. Patent No. 7,176,528 describes a process for producing a semiconductor-on-glass (SOG) structure using a lift-off technique. These steps include: (i) exposing the surface of the germanium wafer to hydrogen ion implantation to create a bonding surface; (ii) contacting the bonding surface of the wafer with the glass substrate; (iii) applying pressure, temperature, and voltage to the wafer and glass substrate to facilitate Bonding therebetween; and (iv) separating the glass substrate and the tantalum film layer from the tantalum wafer.

上述的方法在一些情況下及/或使用在一些應用時,容易產生令人討厭的效果。請參考圖1A-1D,以譬如氫離子的離子經由表面21植入半導體晶片20,使得此種植入量在整個半導體晶片20的密度和深度是均勻的。The above methods are prone to annoying effects in some cases and/or in some applications. Referring to FIGS. 1A-1D, the semiconductor wafer 20 is implanted via the surface 21 with ions such as hydrogen ions such that the implantation amount is uniform throughout the density and depth of the semiconductor wafer 20.

參考圖1A,當譬如矽的半導體材料以譬如氫離子的離子植入時會產生傷害部位。傷害部位層界定出剝離層22。有些傷害部位以非常高的寬高比形成晶核於薄板內(它們有很大的有效直徑而幾乎沒有高度)。從植入離子產生的氣體,譬如H2 擴散至薄板,形成相當高寬高比的氣泡。這些氣泡中的 氣體壓力非常高,估計可達約10千巴。Referring to FIG. 1A, when a semiconductor material such as germanium is implanted with ions such as hydrogen ions, a damage site is generated. The injury site layer defines a release layer 22. Some lesions form nucleation in the lamella at very high aspect ratios (they have large effective diameters with little height). Implanting ions generated from the gas, such as H 2 diffusion sheet to form a relatively high aspect ratio of bubbles. The gas pressure in these bubbles is very high and is estimated to be up to about 10 kilobars.

如圖1B的雙向箭頭所示,薄板和氣泡在有效直徑內增長,直到它們互相很靠近,而使剩餘的矽太弱而無法抵抗氣體的高壓。由於沒有一個最佳的點開始分離,就會隨機產生多個分離前緣,因而多個裂隙傳播穿過半導體晶片20。As indicated by the double arrow in Figure 1B, the sheets and bubbles grow within the effective diameter until they are in close proximity to one another, leaving the remaining turns too weak to withstand the high pressure of the gas. Since no optimal point begins to separate, a plurality of discrete leading edges are randomly generated, and thus a plurality of cracks propagate through the semiconductor wafer 20.

靠近半導體晶片20的邊緣,有很多植入的氫可以從富含氫的平面跑出來。這是因為靠近漏口(即晶片20的側邊壁板)的關係。更特別的是,在植入期間離子(譬如氫質子)減速通過半導體晶片20(譬如矽)的結構,並從晶格部位取代一些矽原子而產生缺陷的平面。當氫離子失去動能時,會變成原子氫,並進一步界定出一個原子氫平面。在室溫下,矽晶格內的缺陷平面和原子氫平面都不穩定,因此,缺陷(空隙)和原子氫互相移動形成熱穩定的空隙-氫成分。多種成分集合在一起產生富含氫的平面。(加熱時,矽晶格通常會沿著富含氫的平面分裂)。Near the edge of the semiconductor wafer 20, a large amount of implanted hydrogen can escape from the hydrogen-rich plane. This is due to the relationship near the leak (i.e., the side panels of the wafer 20). More specifically, ions (such as hydrogen protons) decelerate through the structure of the semiconductor wafer 20 (e.g., helium) during implantation and replace some germanium atoms from the lattice sites to create a plane of defects. When a hydrogen ion loses kinetic energy, it becomes atomic hydrogen and further defines an atomic hydrogen plane. At room temperature, both the defect plane and the atomic hydrogen plane in the germanium lattice are unstable, and therefore, the defects (voids) and atomic hydrogen move to each other to form a thermally stable void-hydrogen component. The multiple components are brought together to create a hydrogen-rich plane. (When heating, the germanium lattice usually splits along the hydrogen-rich plane).

並不是所有的空隙和氫都會崩解成空隙-氫成分。有些原子氫成分會從空隙平面擴散,最後離開矽晶片20。因此有些原子氫不會造成剝離層22的分裂。靠近矽晶片20的邊緣,氫原子有另外從晶格跑出的路徑。因此,矽晶片20邊緣區域的氫濃度可能較低。較低的氫濃度會需要更高溫或更長的時間來發展足夠的力量以支援分離。Not all voids and hydrogen will disintegrate into void-hydrogen components. Some of the atomic hydrogen components will diffuse from the void plane and eventually exit the germanium wafer 20. Therefore, some atomic hydrogen does not cause splitting of the peeling layer 22. Near the edge of the germanium wafer 20, the hydrogen atoms have a path that is otherwise escaping from the crystal lattice. Therefore, the hydrogen concentration in the edge region of the germanium wafer 20 may be low. Lower hydrogen concentrations will require higher temperatures or longer to develop enough power to support separation.

因此,在分離處理期間以沒有分離的邊緣產生帳篷狀的結構24。在臨界壓力,沿著譬如{111}平面(圖1C)的相對弱平面會出現其餘半導體材料的裂痕,而完成剝離層22自矽 晶片20的分離(圖1D)。然而,邊緣22A、22B是來自傷害部位界定出的主要分裂平面。這種非平面的分裂是令人討厭的。分離的其它特徵包括剝離層22可以被描述成薄板或氣泡所在的「台地」,被出現裂隙的「峽谷」圍燒著。要注意的是,這些台地和峽谷無法在圖1D精確顯示,因為這些細節是超過所示的比例尺可描繪出的可能。Thus, the tent-like structure 24 is created with no separate edges during the separation process. At the critical pressure, cracks in the remaining semiconductor material appear along the relatively weak plane of the {111} plane (Fig. 1C), and the peeling layer 22 is self-twisted. The separation of the wafer 20 (Fig. 1D). However, the edges 22A, 22B are the major split planes defined from the injury site. This non-planar split is annoying. Other features of the separation include that the release layer 22 can be described as a "station" in which the sheet or bubble is located, surrounded by a "canyon" where cracks appear. It should be noted that these terraces and canyons cannot be accurately displayed in Figure 1D because these details are beyond the scale of the scale shown.

不想限制本發明在任何運作理論,本案發明人認為使用前述的技術,從開始發生分離到完成分離的時間大約是數十個微秒。換句話說,分離的隨機開始發生和傳播大約是3000公尺/秒。再者,不想限制本發明在任何運作理論,本案發明人認為這種分離速率是前述的剝離層22分裂表面令人討厭的特性所造成(圖1D)。Without wishing to limit the invention in any theory of operation, the inventors of the present invention believe that the time from the onset of separation to the completion of separation using the aforementioned techniques is on the order of tens of microseconds. In other words, the random beginning of the separation occurs and propagates at approximately 3000 meters per second. Further, without wishing to limit the invention in any theory of operation, the inventors of the present invention believe that this separation rate is caused by the annoying characteristics of the aforementioned split surface of the peeling layer 22 (Fig. 1D).

美國專利第6,010,579號說明了一種將離子均勻植入半導體基板10的技術,其均勻植入深度至Z0,該技術係將晶片的溫度降到起始分離開始發生的溫度以下,然後在植入深度Z0附近的基板10邊緣引進多個能量脈衝以達到「控制分裂前緣」。美國專利第6,010,579號宣稱,至少就表面粗度而言,前述方式是所謂「隨機」分裂的改良。本發明採取定向的分離方式,和美國專利第6,010,579號「控制分裂前緣」的方式有顯著的不同,也和「隨機的」分裂方式不同。U.S. Patent No. 6,010,579 describes a technique for uniformly implanting ions into a semiconductor substrate 10 which is uniformly implanted to a depth of Z0 which reduces the temperature of the wafer below the temperature at which the initial separation begins, and then at the depth of implantation. A plurality of energy pulses are introduced at the edge of the substrate 10 near Z0 to achieve "control splitting front". U.S. Patent No. 6,010,579 claims that the aforementioned mode is an improvement of the so-called "random" splitting, at least in terms of surface roughness. The present invention adopts a directional separation method which is significantly different from the "controlling the splitting leading edge" of U.S. Patent No. 6,010,579, and is also different from the "random" splitting mode.

當SOI結構的大小增加,尤其當半導體晶片的形狀是長方形時,先前討論的與剝離層22自半導體晶片20分離相關的挑戰加劇。這種長方形半導體晶片可使用在多個半導體鋪片耦合到絕緣體基板的應用上。更進一步有關鋪片式SOI 結構的製造細節可在美國第2007/0117354號專利公開案中找到,其完整的說明在本文也全部併入參考。The previously discussed challenges associated with the separation of the release layer 22 from the semiconductor wafer 20 are exacerbated as the size of the SOI structure increases, particularly when the shape of the semiconductor wafer is rectangular. Such rectangular semiconductor wafers can be used in applications where multiple semiconductor wafers are coupled to an insulator substrate. Further on the tiled SOI Details of the fabrication of the structure can be found in U.S. Patent Application Publication No. 2007/0117354, the entire disclosure of which is incorporated herein by reference.

為了方便說明,以下的討論有時將根據SOI結構而言。參考這種特定型態的SOI結構,使得本發明的說明更加容易,但不希望也不應該被解釋成以任何方式來限制本發明的範疇。本文所使用的SOI縮寫一般是指絕緣體上半導體結構,包括但不限定是絕緣體上矽結構。同樣地,所使用的SOG縮寫一般是指玻璃上半導體結構包括但不限定是玻璃上矽結構。SOI縮寫涵蓋了SOG結構。For ease of explanation, the following discussion will sometimes be based on the SOI structure. With reference to this particular type of SOI structure, the description of the present invention is made easier, but it is not intended or should be construed as limiting the scope of the invention in any way. As used herein, the acronym for SOI generally refers to a semiconductor-on-insulator structure, including but not limited to, an insulator-on-insulator structure. Likewise, the SOG abbreviation used generally refers to a semiconductor structure on glass including, but not limited to, a glass upper structure. The SOI abbreviation covers the SOG structure.

依據本發明的一個或多個實施範例,形成絕緣體上半導體(SOI)結構的方法和裝置提供:在施體半導體晶片的植入表面施以離子植入步驟,以在界定出施體半導體晶片剝離層的橫截面上產生一個弱化片層;以及將施體半導體晶片在離子植入步驟之前、期間或之後施以空間性變化步驟,以使弱化片層的一個或多個參數在X-和Y-軸的至少一個方向上,在整個所述晶片空間性地變化。In accordance with one or more embodiments of the present invention, a method and apparatus for forming a semiconductor-on-insulator (SOI) structure provides an ion implantation step on an implanted surface of a donor semiconductor wafer to define a stripping of a donor semiconductor wafer Forming a weakened sheet on the cross section of the layer; and applying a spatially varying step to the donor semiconductor wafer before, during or after the ion implantation step such that one or more parameters of the weakened sheet are at X- and Y - at least one direction of the axis, spatially varying throughout the wafer.

空間性變化步驟可促進剝離層自半導體晶片分離的特性,使得分離是可定向及/或時間性控制的。The step of spatially varying can promote the separation of the release layer from the semiconductor wafer such that the separation is directional and/or temporally controllable.

參數可包括一個或多個下列的單一項或組合:(i)由離子植入步驟產生的晶核形成部位密度;(ii)自植入表面(或參考平面)算起之弱化片層的深度;(iii)穿過植入表面至少到弱化片層之人工造成的傷害部位(譬如盲洞);和(iv)利用溫度梯 度在整個弱化片層增加缺陷部位的晶核形成及/或壓力。The parameter may comprise one or more of the following single items or combinations: (i) the density of nucleation sites produced by the ion implantation step; (ii) the depth of the weakened layer from the implanted surface (or reference plane) (iii) at least the artificially injured site (such as a blind hole) that passes through the implanted surface to weaken the slice; and (iv) utilizes a temperature ladder The degree of nucleation and/or pressure at the defect site is increased throughout the weakened sheet.

此方法和裝置更進一步提供將施體半導體晶片的溫度提升到足以從弱化片層的一點、邊緣、及/或區域,在弱化片層起始分離。可進一步使施體半導體晶片的溫度足以在實質上定向地沿著弱化片層繼續分離,作為變化參數的函數。The method and apparatus further provide for raising the temperature of the donor semiconductor wafer sufficiently to initiate separation of the weakened sheet from a point, edge, and/or region of the weakened sheet. The temperature of the donor semiconductor wafer can be further sufficient to continue to separate along the weakened sheet in a substantially oriented manner as a function of the varying parameters.

當本文的說明配合附圖一起參考時,對熟悉此項技術的人而言,其他態樣、特徵、優點等將會變得顯而易見。Other aspects, features, advantages, and the like will become apparent to those skilled in the art.

10‧‧‧基板10‧‧‧Substrate

20‧‧‧半導體晶片20‧‧‧Semiconductor wafer

21‧‧‧植入表面21‧‧‧ implanted surface

22‧‧‧剝離層22‧‧‧ peeling layer

22A、22B‧‧‧邊緣Edge of 22A, 22B‧‧

24‧‧‧結構24‧‧‧structure

102‧‧‧基板102‧‧‧Substrate

120‧‧‧施體半導體晶片120‧‧‧Sensor semiconductor wafer

121‧‧‧植入表面121‧‧‧ implant surface

122‧‧‧剝離層122‧‧‧ peeling layer

125‧‧‧弱化片層125‧‧‧Weakened slices

130A、130B、130C、130D‧‧‧邊緣Edges of 130A, 130B, 130C, 130D‧‧

200‧‧‧平台200‧‧‧ platform

202‧‧‧離子射束202‧‧‧ ion beam

204‧‧‧條帶射束204‧‧‧Band beam

220‧‧‧遮罩薄膜220‧‧‧ mask film

220A、220B‧‧‧遮罩220A, 220B‧‧‧ mask

230‧‧‧盲孔230‧‧ ‧ blind holes

所示較佳的圖式用於說明本發明之不同態樣,應可理解本發明並不限制於所繪示之精確配置及方法。The preferred embodiments are shown to illustrate various aspects of the invention, and it is understood that the invention is not limited to the precise arrangements and methods illustrated.

在所有附圖中,「X」表示X-軸方向,「Y」表示Y-軸方向。In all the drawings, "X" indicates the X-axis direction, and "Y" indicates the Y-axis direction.

圖1A、1B、1C及1D為方塊圖,顯示出依據先前技術之剝離處理過程。1A, 1B, 1C and 1D are block diagrams showing the stripping process in accordance with the prior art.

圖2A-2B為方塊圖,顯示出依據本發明一或多個態樣之剝離處理過程。2A-2B are block diagrams showing the stripping process in accordance with one or more aspects of the present invention.

圖3A為依據本發明一或多個態樣之施體半導體晶片的頂視圖,該晶片內具有與弱化層或弱化片層相關之空間性變化參數。3A is a top plan view of a donor semiconductor wafer having one or more aspects in accordance with the present invention having spatially varying parameters associated with a weakened layer or a weakened sheet.

圖3B為曲線圖,顯示出圖3A的空間性變化參數。Figure 3B is a graph showing the spatial variation parameters of Figure 3A.

圖3C為曲線圖,顯示出圖3A的空間性變化參數為弱化片層之深度。Figure 3C is a graph showing the spatial variation parameter of Figure 3A as the depth of the weakened sheet.

圖4A、4B及4C為依據本發明之一或多個進一步態 樣之各別施體半導體晶片之頂視圖,該些晶片具有進一步之空間性變化參數。4A, 4B and 4C are diagrams of one or more further aspects in accordance with the present invention A top view of the respective donor semiconductor wafers having further spatial variation parameters.

圖5A、5B及5C為一些離子植入裝置之簡圖,可使用來達成施體半導體晶片之空間性變化參數。在圖5A中,dX/dt表示dX/dt掃瞄;以及dY/Dt表示dY/dt掃瞄。5A, 5B, and 5C are simplified diagrams of some ion implantation devices that can be used to achieve spatial variation parameters of a donor semiconductor wafer. In FIG. 5A, dX/dt represents a dX/dt scan; and dY/Dt represents a dY/dt scan.

圖6A-6B顯示出離子植入技術,被使用在施體半導體晶片中以達成晶核形成部位之空間性變化密度。Figures 6A-6B show ion implantation techniques used in donor semiconductor wafers to achieve a spatially varying density of nucleation sites.

圖7A-7B顯示出離子植入技術,被使用在施體半導體晶片中以達成空間性變化之植入深度。Figures 7A-7B show ion implantation techniques used in donor semiconductor wafers to achieve spatially varying implant depths.

圖7C-7D為曲線圖,顯示出離子植入傾斜角度與植入深度間之關係。Figures 7C-7D are graphs showing the relationship between ion implantation tilt angle and implant depth.

圖8A-8B顯示出離子植入技術,被使用來在施體半導體晶片中達成空間性變化離子植入分佈寬度。Figures 8A-8B show ion implantation techniques used to achieve spatially varying ion implantation distribution widths in donor semiconductor wafers.

圖8C為曲線圖,顯示出離子植入傾斜角度與分散間之關係。Fig. 8C is a graph showing the relationship between the ion implantation tilt angle and the dispersion.

圖9A-9D顯示出進一步之離子植入技術,被使用在施體半導體晶片中以達成空間性變化離子植入深度。Figures 9A-9D show a further ion implantation technique used in a donor semiconductor wafer to achieve a spatially varying ion implantation depth.

圖10A-10D及11顯示出進一步之離子植入技術,被使用在施體半導體晶片中以達成缺陷部位之空間性變化分佈。Figures 10A-10D and 11 show further ion implantation techniques used in donor semiconductor wafers to achieve a spatially varying distribution of defect sites.

圖12A-12B顯示出時間-溫度量變曲線技術,被使用在施體半導體晶片中以達成空間性變化參數量變曲線。Figures 12A-12B show time-temperature variability curves techniques used in a donor semiconductor wafer to achieve a spatially varying parameter magnitude curve.

參考附圖,類似的編號代表類似的元件,依據本發明的一個或多個實施範例,圖2A-2B顯示的是中間SOI結構(尤其是SOG結構)。中間SOI結構包括譬如玻璃或玻璃陶瓷基板102的絕緣體基板,和施體半導體晶片120。玻璃或玻璃陶瓷基板102和施體半導體晶片120可使用此項技術任何已知的處理過程耦合在一起,譬如黏結、熔融、黏著等。Referring to the drawings, like numerals represent like elements, and in accordance with one or more embodiments of the present invention, Figures 2A-2B show intermediate SOI structures (especially SOG structures). The intermediate SOI structure includes an insulator substrate such as a glass or glass ceramic substrate 102, and a donor semiconductor wafer 120. The glass or glass ceramic substrate 102 and the donor semiconductor wafer 120 can be coupled together using any known process of the art, such as bonding, melting, adhering, and the like.

在玻璃或玻璃陶瓷基板102和施體半導體晶片120耦合在一起之前,施體半導體晶片120包括暴露的植入表面121。將施體半導體晶片120的植入表面121施以離子植入步驟,以在界定出剝離層122的橫截面上產生一個弱化片層125。弱化片層125實質上平行於X-Y正交軸方向界定出的參考平面(可能在任意處,因而未顯示)。X-軸方向在圖2A中是從左到右顯示,而Y-軸方向是正交於X-軸方向到頁內(因而未顯示)。The donor semiconductor wafer 120 includes an exposed implant surface 121 prior to coupling the glass or glass ceramic substrate 102 and the donor semiconductor wafer 120 together. The implanted surface 121 of the donor semiconductor wafer 120 is subjected to an ion implantation step to create a weakened sheet 125 on the cross-section defining the lift-off layer 122. The weakened sheet 125 is substantially parallel to the reference plane defined by the X-Y orthogonal axis direction (possibly anywhere, and thus not shown). The X-axis direction is shown from left to right in Fig. 2A, and the Y-axis direction is orthogonal to the X-axis direction to the page (and thus not shown).

將半導體晶片120在離子植入步驟之前、期間或之後,施以空間性變化步驟以使剝離層122自施體半導體晶片120分離的特性是可定向及/或時間性控制的。然而不想限制本發明在任何運作理論,我們相信這種可定向及/或時間性控制可能改善分離特性,譬如(分離後)剝離層122和施體半導體晶片120上較平滑的暴露表面。我們也相信這種可定向及/或時間性之控制可能改善邊緣特性,譬如在弱化片層125界定出的主要分裂平面中改善剝離層122和施體半導體晶片120上暴露表面的邊緣之良率。The feature of applying the spatially varying step to the semiconductor wafer 120 before, during, or after the ion implantation step to separate the release layer 122 from the donor semiconductor wafer 120 is directional and/or temporally controllable. While not intending to limit the invention in any theory of operation, it is believed that such orientation and/or temporal control may improve separation characteristics, such as (after separation) the smoother exposed surface of the release layer 122 and the donor semiconductor wafer 120. We also believe that such orientable and/or temporal control may improve edge characteristics, such as improving the yield of the exposed surface of the release layer 122 and the donor semiconductor wafer 120 in the primary split plane defined by the weakened sheet 125. .

剝離層122自施體半導體晶片120分離的可定向及/或時間性控制特性可以數種方式達到,譬如藉由在X-和Y-軸的至少一個方向上,在整個弱化片層125空間性地改變一個或多個參數。這些參數可包括一個或多個下列項目的單一項或組合:(i)由離子植入步驟產生的晶核形成部位密度;(ii)自植入表面121(或參考平面)算起的弱化片層125深度;(iii)穿過植入表面121至少到弱化片層125之人工造成的傷害部位(譬如盲洞);和(iv)利用溫度梯度,在整個弱化片層125增加缺陷部位的晶核形成及/或壓力。The directional and/or temporal control characteristics of the separation layer 122 from the donor semiconductor wafer 120 can be achieved in several ways, such as by spatially dissipating the entire weakened layer 125 in at least one of the X- and Y-axes. Change one or more parameters. These parameters may include a single item or combination of one or more of the following: (i) the density of nucleation sites produced by the ion implantation step; (ii) the weakened slices from the implanted surface 121 (or reference plane) The depth of layer 125; (iii) at least the artificially created injury site (such as a blind hole) through the implanted surface 121; and (iv) the use of a temperature gradient to increase the crystal of the defect at the entire weakened sheet 125 Nuclear formation and / or pressure.

如圖2A-2B的箭頭A所示,剝離層122自施體半導體晶片120可定向及/或時間性控制的分離特性,造成從弱化片層125的一點、邊緣及/或區域到其他點、邊緣及/或區域的傳播分離,作為時間的函數。這通常可從下列達成:首先,如以上所討論之空間性地改變整個弱化片層125的一個或多個參數,第二,提升施體半導體晶片120的溫度到足以在弱化片層125的一點、邊緣及/或區域起始分離。因此,進一步提升施體半導體晶片120的溫度,使其足以在實質上定向地沿著弱化片層125繼續分離,作為整個弱化片層125之參數的空間性變化函數。最好建立變化的參數,使得提升溫度的時間-溫度量變曲線圖是大約數秒,沿著弱化片層125的分離傳播發生歷經至少一秒。As shown by the arrow A of FIGS. 2A-2B, the release layer 122 can be oriented and/or temporally controlled from the donor semiconductor wafer 120, resulting in a point, edge and/or region from the weakened sheet 125 to other points, The separation of edges and/or regions is separated as a function of time. This can generally be achieved by first varying the one or more parameters of the entire weakened sheet 125 spatially as discussed above, and second, raising the temperature of the donor semiconductor wafer 120 to a point sufficient to weaken the sheet 125. , edge and / or area start separation. Thus, the temperature of the donor semiconductor wafer 120 is further increased to be sufficient to continue to separate substantially along the weakened sheet layer 125 as a spatially varying function of the parameters of the entire weakened sheet 125. Preferably, the varying parameters are established such that the time-temperature magnitude curve of the elevated temperature is about a few seconds and the separation propagation along the weakened sheet 125 occurs for at least one second.

現在請參考圖3A-3C,進一步顯示關於在空間上在整個弱化片層125改變一個或多個參數的細節。圖3A是經由植入表面121觀看施體半導體晶片120的頂視圖。X-軸方向 陰影的變化是代表參數的空間性變化(譬如晶核形成部位密度、部位內壓力、晶核形成的程度、人工產生傷害部位(洞)的分佈、植入深度等)。在所示的例子中,一個或多個的參數以X-軸方向從施體半導體晶片120(因而是其弱化片層125)一個邊緣130A變化朝向相反的一個邊緣130B,反之亦然。Referring now to Figures 3A-3C, details regarding the spatially changing one or more parameters throughout the weakened sheet 125 are shown. FIG. 3A is a top view of the donor semiconductor wafer 120 viewed through the implant surface 121. X-axis direction The change in shadow is representative of the spatial variation of the parameters (such as the density of nucleation sites, the pressure within the site, the degree of nucleation, the distribution of artificially created lesions (holes), the depth of implantation, etc.). In the illustrated example, one or more parameters change from one edge 130A of the donor semiconductor wafer 120 (and thus its weakened sheet 125) toward the opposite edge 130B in the X-axis direction, and vice versa.

參考圖3B,這是分離參數的圖,顯示的是例如弱化片層125內晶核形成部位密度的橫截面量變曲線圖,作為X-軸方向的函數。或者或此外,分離參數可表示為晶核形成部位內壓力、晶核形成的程度、人工產生傷害部位(洞)的分佈等中的一個或多個,前述參數每個都可作為X-軸空間性度量的函數。請參考圖3C,這是分離參數的圖,顯示例如弱化片層125深度(對應離子植入的深度)的橫截面量變曲線圖,作為X-軸方向的函數。Referring to Figure 3B, this is a plot of separation parameters showing, for example, a cross-sectional quantitative variation of the density of nucleation sites in the weakened sheet 125 as a function of the X-axis direction. Alternatively or in addition, the separation parameter may be expressed as one or more of pressure in the nucleation site, degree of nucleation formation, distribution of artificially generated damage sites (holes), etc., each of which may be used as an X-axis space. The function of the sex measure. Please refer to FIG. 3C, which is a plot of separation parameters showing, for example, a cross-sectional volume change plot of the depth of the weakened sheet 125 (corresponding to the depth of ion implantation) as a function of the X-axis direction.

不想限制本發明在任何運作理論,咸信當邊緣130A的晶核形成部位密度相當高以及朝向邊緣130B的空間位置處之晶核形成部位密度降至較低時,會發生從邊緣130A朝向邊緣130B的分離傳播(以虛線的箭頭表示)。這個理論也被認為是和其他參數保持關聯性,譬如晶核形成部位內的氣體壓力、分離之前晶核形成部位合併的程度、和人工產生傷害部位(洞)的分佈。至於和弱化片層125深度相關的參數,咸信當實質上較淺的深度出現在沿著弱化片層125的起始邊緣130B以及較深的深度出現在連續更遠的距離處朝向邊緣130A時,會發生從邊緣130B朝向邊緣130A的分離傳播(以實線的箭頭表示)。Without wishing to limit the invention in any theory of operation, it is believed that when the density of the nucleation sites of the edge 130A is relatively high and the density of the nucleation sites at the spatial position toward the edge 130B drops to a low level, it occurs from the edge 130A toward the edge 130B. Separation propagation (indicated by dashed arrows). This theory is also considered to be related to other parameters, such as the gas pressure in the nucleation site, the extent to which the nucleation sites are merged prior to separation, and the distribution of artificially created lesions (holes). As for the parameters related to the depth of the weakened sheet 125, it is believed that when the substantially shallow depth occurs along the starting edge 130B of the weakened sheet 125 and the deeper depth occurs at a continuously further distance toward the edge 130A Separate propagation from the edge 130B toward the edge 130A occurs (indicated by the solid arrows).

現在參考圖4A-4C,進一步顯示關於在空間上在整個弱化片層125改變一個或多個參數的細節。圖顯示的是經由植入表面121觀看施體半導體晶片120的頂視圖。X-軸和Y-軸方向陰影的變化是代表參數的空間性變化,即晶核形成部位密度、部位內壓力、晶核形成的程度、人工產生傷害部位(洞)的分佈、植入深度等。在每個所示的例子中,參數在X-軸和Y-軸兩個方向空間性變化。Referring now to Figures 4A-4C, details regarding the spatially changing one or more parameters throughout the weakened sheet 125 are shown. The figure shows a top view of the donor semiconductor wafer 120 viewed through the implant surface 121. The change of the shadows in the X-axis and Y-axis directions represents the spatial variation of the parameters, that is, the density of the nucleation sites, the pressure within the sites, the degree of nucleation, the distribution of artificially created lesions (holes), the depth of implantation, etc. . In each of the illustrated examples, the parameters vary spatially in both the X-axis and the Y-axis.

請特別參考圖4A,陰影是代表空間上從兩個邊緣130A、130D開始朝向其他邊緣130B、130C的參數變化,以及在連續更遠的距離處,於X-軸和Y-軸兩個方向上變化。為了跟上以上的討論,在考慮晶核形成部位密度的參數時,假使在邊緣130A、130D的起始邊緣有較高的密度,則認為分離的傳播(以虛線箭頭表示)會從邊緣130A、130D的角落輻射朝向晶片120的中央,並朝向其他邊緣130B、130C。這個理論也被認為是和其他參數保持關聯性,譬如晶核形成部位內的氣體壓力、分離之前晶核形成部位合併的程度、和人工產生傷害部位(洞)的分佈。至於和弱化片層125深度相關的參數,咸信當較低深度沿著邊緣130B、130C起始降低深度時,分離的傳播(以實線箭頭表示)從邊緣130B、130C的角落輻射朝向晶片120中央,並朝向其他邊緣130A、130D。Referring specifically to Figure 4A, the shading is representative of spatially varying parameter changes from the two edges 130A, 130D toward the other edges 130B, 130C, and at successively further distances, in both the X-axis and the Y-axis. Variety. In order to keep up with the above discussion, in considering the parameters of the nucleation site formation density, if there is a higher density at the beginning edge of the edges 130A, 130D, then the separation propagation (indicated by the dashed arrow) is considered to be from the edge 130A, The corners of 130D radiate toward the center of wafer 120 and toward the other edges 130B, 130C. This theory is also considered to be related to other parameters, such as the gas pressure in the nucleation site, the extent to which the nucleation sites are merged prior to separation, and the distribution of artificially created lesions (holes). As for the parameters related to the depth of the weakened sheet 125, when the lower depth begins to decrease depth along the edges 130B, 130C, the separated propagation (indicated by solid arrows) radiates from the corners of the edges 130B, 130C toward the wafer 120. Centered and facing the other edges 130A, 130D.

特別參考圖4B和4C,陰影代表空間上從所有邊緣130開始的參數變化,並朝向施體半導體晶片120中央的變化,反之亦然。With particular reference to Figures 4B and 4C, the shading represents a change in the parameters spatially from all edges 130 and toward the center of the donor semiconductor wafer 120, and vice versa.

現在提供進一步的細節,參考在整個弱化片層125 在X-軸和Y-軸的一個或兩個方向,由離子植入所產生的晶核形成部位密度空間性變化的特定參數。不管使用什麼技術達到這種空間性變化,晶核形成部位最大密度較佳存在弱化片層125的一點、邊緣或區域約5x105 部位/cm2 ,而晶核形成部位最小密度較佳存在於遠離弱化片層125中該點、邊緣或區域約5x104 部位/cm2 。以另一種方式看待這種變化,最大晶核形成部位密度和最小晶核形成部位密度之間的差異大約10倍。Further details are now provided, with reference to specific parameters of the spatial variation in density of nucleation sites created by ion implantation in the one or both directions of the X-axis and the Y-axis throughout the weakened sheet 125. Regardless of the technique used to achieve such a spatial change, the maximum density of the nucleation sites is preferably present at a point, edge or region of the weakened sheet 125 of about 5x10 5 parts/cm 2 , and the minimum density of the nucleation sites is preferably present in the distance. The point, edge or region in the weakened sheet 125 is about 5 x 10 4 parts/cm 2 . Looking at this change in another way, the difference between the maximum nucleation site density and the minimum nucleation site density is about 10 times.

依據本發明的一個或多個態樣,可藉著改變離子植入步驟的劑量,空間性變化弱化片層125內晶核形成部位密度。經由先前技術之方式,將植入表面121施以一個或多個離子植入步驟,產生弱化片層125(因而造成剝離層122)。雖然在這方面可使用很多種離子植入技術、機器等,但一種適合的方法指出施體半導體晶片120的植入表面121可施以氫離子植入步驟,以至少起始產生施體半導體晶片120的剝離層122。In accordance with one or more aspects of the present invention, the density of the nucleation sites in the sheet 125 can be weakened by varying the dose of the ion implantation step. The implanted surface 121 is subjected to one or more ion implantation steps by prior art techniques to produce a weakened sheet 125 (and thus a peeling layer 122). Although a wide variety of ion implantation techniques, machines, etc. can be used in this regard, a suitable method indicates that the implanted surface 121 of the donor semiconductor wafer 120 can be subjected to a hydrogen ion implantation step to at least initiate the generation of a donor semiconductor wafer. The peeling layer 122 of 120.

請參考圖5A,顯示的是Axcelis NV-10型態整批植入器的簡圖,藉著改變植入離子的劑量,可修改用於弱化片層125內晶核形成部位密度的空間性變化。Referring to FIG. 5A, a schematic diagram of the Axcelis NV-10 type bulk implanter is shown. By varying the dose of the implanted ions, the spatial variation of the density of the nucleation sites in the weakened sheet 125 can be modified. .

多個施體半導體晶片120,在這個例子是長方形鋪片,可在相對於入射離子射束202(定向到頁內)的平台200上以固定半徑呈方位角的分佈。平台200的旋轉提供擬-X-掃瞄(dX/dt),而整個平台200的機械式平移提供Y-掃瞄(dY/dt)。使用擬-X-掃瞄這個詞是因為較小的平台200半徑,和大型的 平台200半徑比起來,X-掃瞄比較彎曲,因此在這種平台200上不會得到完全筆直的掃瞄。調整X-掃瞄速度及/或Y-掃瞄速度會造成劑量中的空間性變化。在過去,當離子射束202徑向通過朝向平台200中央時,可使用增加的Y-掃瞄速度以確保均勻的劑量。的確,此項技術傳統的思考是達到空間上均勻的劑量,當相對於施體半導體晶片120的角度速度減少到接近平台200中央時,Y-掃瞄速度必須對應地增加。然而,依據本發明,可以不執著於傳統的掃瞄協定達到空間性變化的劑量,產生譬如圖3A和4A的圖案。例如,當離子射束202徑向通過朝向平台200中央時,可保持Y-掃瞄速度均勻。或者,當離子射束202徑向通過朝向平台200中央時,我們也可以減少Y-掃瞄速度。本領域中熟悉此項技術的人,可從本文的揭露得知其他的可能性。另一種方式是改變射束能量,作為掃瞄速率和位置的函數。這種改變可透過修改軟體中植入器的控制演算法、控制軟體和終端站驅動程式之間的電子介面、或其他機械式的修改。A plurality of donor semiconductor wafers 120, in this example rectangular patches, may be azimuthally distributed at a fixed radius on a platform 200 relative to the incident ion beam 202 (oriented into the page). The rotation of the platform 200 provides a pseudo-X-scan (dX/dt), while the mechanical translation of the entire platform 200 provides a Y-scan (dY/dt). The word quasi-X-scan is used because of the smaller platform 200 radius, and large The X-scan is relatively curved compared to the platform 200 radius, so a completely straight scan is not obtained on such a platform 200. Adjusting the X-scan speed and/or Y-scan speed can cause spatial variations in the dose. In the past, when the ion beam 202 was directed radially toward the center of the platform 200, an increased Y-scan speed could be used to ensure a uniform dose. Indeed, the conventional wisdom of the art is to achieve a spatially uniform dose that must be correspondingly increased as the angular velocity relative to the donor semiconductor wafer 120 is reduced to near the center of the platform 200. However, in accordance with the present invention, it is possible to achieve a spatially varying dose without adhering to conventional scanning protocols, resulting in a pattern as shown in Figures 3A and 4A. For example, the Y-scan speed can be kept uniform as the ion beam 202 passes radially toward the center of the platform 200. Alternatively, we can also reduce the Y-scan speed as the ion beam 202 passes radially toward the center of the platform 200. Other possibilities are known to those skilled in the art from this disclosure. Another way is to change the beam energy as a function of scan rate and position. This change can be made by modifying the control algorithm of the implanter in the software, the electronic interface between the control software and the end station driver, or other mechanical modifications.

參考圖5B,顯示的是單一基板X-Y植入器的簡圖,藉著改變植入離子的劑量可修改用於弱化片層125內晶核形成部位密度的空間性變化。在這個例子中,電子射束202掃瞄比機械式基板掃瞄更快(圖5A)。再者,此項技術傳統的思考是達到空間上均勻的劑量,因而設定X和Y掃瞄速率和射束能量以達到均勻的劑量。再者,可以不執著於傳統的掃瞄協定,達到空間性變化的劑量。藉由數種變化的X和Y掃瞄速率及/或射束能量組合,可在植入劑量內達到顯著的空間性 變化。可產生垂直或水平,一維或二維的梯度,經由這種變化產生譬如圖3A、4A、4B和4C的圖案。Referring to Figure 5B, a simplified diagram of a single substrate X-Y implanter is shown, which can be modified to mitigate the spatial variation in the density of nucleation sites in the sheet 125 by varying the dose of implanted ions. In this example, the electron beam 202 scan is faster than the mechanical substrate scan (Fig. 5A). Furthermore, the traditional thinking of this technology is to achieve a spatially uniform dose, thus setting the X and Y scan rates and beam energy to achieve a uniform dose. Furthermore, it is possible to achieve a dose of spatial variation without adhering to conventional scanning protocols. Significant spatiality within the implant dose with several varying X and Y scan rates and/or beam energy combinations Variety. A vertical or horizontal, one- or two-dimensional gradient can be produced, via which the pattern of Figures 3A, 4A, 4B and 4C is produced.

請參考圖5C,顯示的是依據離子浴技術的植入器簡圖。條帶射束204從延伸的離子來源產生。依據傳統的技術,單一均勻速度掃瞄(和正交方向的均勻射束能量成比例)可達到傳統的目標,即空間上均勻的劑量。然而,依據本發明的各種態樣,藉著改變施體半導體晶片120通過條帶射束204的機械式掃瞄速率可以產生一維的梯度(即圖3A旋轉90度)。以某個相對於條帶射束204的角度扭轉施體半導體晶片120,以及結合機械式掃瞄速率的改變,可以類似於圖4A的方式產生劑量內的空間性變化。或者或此外,沿著射束來源的空間性變化射束電流會在婦瞄方向提共正交的梯度,提供額外的自由度以產生受支配的空間性變化劑量。Referring to Figure 5C, a schematic of the implanter in accordance with the ion bath technique is shown. Strip beam 204 is produced from an extended source of ions. According to conventional techniques, a single uniform velocity scan (proportional to the uniform beam energy in the orthogonal direction) achieves the conventional goal of spatially uniform dose. However, in accordance with various aspects of the present invention, a one-dimensional gradient (i.e., rotated 90 degrees in FIG. 3A) can be produced by varying the mechanical scanning rate of the donor semiconductor wafer 120 through the strip beam 204. By twisting the donor semiconductor wafer 120 at an angle relative to the strip beam 204, and in conjunction with changes in the mechanical scan rate, spatial variations within the dose can be produced in a manner similar to that of Figure 4A. Alternatively or additionally, the spatially varying beam current along the beam source will provide a co-orthogonal gradient in the direction of the gaze, providing additional degrees of freedom to produce a dominant spatially varying dose.

不管用來達到劑量變化的特定植入技術,不管最高劑量的位置(沿著一個或多個起始邊緣、起始點、或起始區域),實質上最高劑量是在所要範圍內以原子/cm2 為單位,而最低劑量是在其他所要範圍內X-和Y-軸的至少一個方向以原子/cm2 為單位。最高劑量和最低劑量之間的差異可以在約10-30%之間,最大變化約3倍。在一些應用上,至少約20%的差異是很重要的。Regardless of the particular implantation technique used to achieve the dose change, regardless of the location of the highest dose (along one or more starting edges, starting points, or starting regions), the substantially highest dose is within the desired range as atoms/ The unit of cm 2 is the unit, and the lowest dose is in units of atoms/cm 2 in at least one of the X- and Y-axes in other desired ranges. The difference between the highest dose and the lowest dose can be between about 10-30% with a maximum change of about 3 fold. In some applications, at least about 20% of the difference is important.

依據本發明的一種或以上進一步之態樣,可藉由實質上均勻的方式植入第一離子成分,空間性變化弱化片層125內的晶核形成部位密度以建立實質上均勻分佈的弱化片層125。之後,可以實質上非均勻的方式植入第二離子成分到施 體半導體晶片120。建立非均勻的植入使得第二離子成分導致原子遷移到弱化片層125,產生整個弱化片層125上晶核形成部位空間性變化的密度。In accordance with one or more further aspects of the present invention, the first ionic component can be implanted in a substantially uniform manner, spatially varying to weaken the density of nucleation sites in the sheet 125 to create a substantially uniformly distributed weakened sheet. Layer 125. Thereafter, the second ionic component can be implanted in a substantially non-uniform manner Body semiconductor wafer 120. The non-uniform implantation is established such that the second ionic component causes the atoms to migrate to the weakened sheet 125, resulting in a spatially varying density of nucleation sites on the entire weakened sheet 125.

舉例而言,第一離子成分可以是氫離子,而第二離子成分可以是氦離子。For example, the first ionic component can be a hydrogen ion and the second ionic component can be a cerium ion.

非均勻的植入可以使用上述技術,此說明中稍後的描述,或從其他來源得知而產生。例如,可空間性地變化第二離子成分的劑量。第二離子成分(譬如He離子)的劑量變化會導致接下來第二成分非均勻的遷移到第一離子成分的位置,因而建立非均勻的晶核形成部位密度。這種變化可改變薄板內的壓力,這也是有幫助的。Non-uniform implantation can be performed using the techniques described above, as described later in this description, or from other sources. For example, the dose of the second ionic component can be varied spatially. A dose change of the second ionic component (e.g., He ion) results in a non-uniform migration of the second component to the location of the first ionic component, thereby establishing a non-uniform nucleation site density. This change can change the pressure inside the sheet, which is also helpful.

或者,第二離子成分非均勻的植入可包括植入第二離子成分到整個施體半導體晶片120的空間上不同深度。本領域中熟悉此項技術的人可依據本文的教示修改任何已知的植入離子到均勻深度的技術以達到非均勻深度的量變曲線圖。在先前技術中,我們知道He離子可以比氫離子植入的更深,譬如兩倍深度或以上。晶片溫度增加時,很多He離子會遷移到較淺氫離子植入的部位,提供稍後分離的氣體壓力。依據本發明的此態樣,植入較深的He導致的傷害是位在施體半導體晶片120遠離較淺氫離子植入的深度,而且很少這種He離子會在一定的時間內抵達。植入較不深的He離子的相反的情況也是如此,因而會造成整個弱化片層125空間性變化晶核形成部位的密度。Alternatively, non-uniform implantation of the second ionic component can include implanting the second ionic component to a spatially different depth of the entire donor semiconductor wafer 120. Those skilled in the art will be able to modify any known technique of implanting ions to a uniform depth to achieve a non-uniform depth quantitative curve in accordance with the teachings herein. In the prior art, we know that He ions can be implanted deeper than hydrogen ions, such as twice the depth or above. As the wafer temperature increases, many of the He ions migrate to the site where the shallower hydrogen ions are implanted, providing a gas pressure that is later separated. In accordance with this aspect of the invention, the damage caused by implanting a deeper He is at a depth away from the shallower hydrogen ion implantation of the donor semiconductor wafer 120, and very little such He ions will arrive in a certain amount of time. The same is true for the opposite case of implanting the lesser He ions, thus causing the density of the nucleation sites of the entire weakened sheet 125 to be spatially changed.

雖然理論上不管第一和第二離子成分的順序(譬如 先植入He或先植入H)都可達成晶核形成部位空間性變化的密度,但多個離子植入步驟的順序也可達成所需的結果。的確,根據離子成分,植入的順序可能在密度上有整體效果,甚至密度也會空間性變化。雖然有點反直覺並令很多熟悉此項技術的人很驚訝,我們發現先植入氫離子會產生較多的晶核形成部位。以一定的計量而官,He被熟悉此項技術的人認為會比氫離子產生10倍的傷害。然而,應該要注意的是He離子的傷害(空隙和有空隙的半導體原子,或Frankel對),甚至在室溫下會快速自行退火。因此,很多但不是全部的He傷害是可以修復的。換句話說,氫離子和譬如Si原子的半導體原子黏結(形成Si-H鏈)以穩定產生的傷害。如果H在He植入之前就存在會產生更多的晶核形成部位。Although theoretically regardless of the order of the first and second ionic components (such as The density of spatial variation of the nucleation sites can be achieved by first implanting He or implanting H) first, but the order of multiple ion implantation steps can also achieve the desired results. Indeed, depending on the ionic composition, the order of implantation may have an overall effect on density, and even the density will vary spatially. Although somewhat counter-intuitive and surprised by many people familiar with the technology, we found that the first implantation of hydrogen ions produced more nucleation sites. With a certain amount of measurement, He is known to be familiar with this technology and will cause 10 times more damage than hydrogen ions. However, it should be noted that He ion damage (voids and voided semiconductor atoms, or Frankel pairs) will quickly self-anneal even at room temperature. Therefore, many, but not all, He injuries can be repaired. In other words, hydrogen ions and semiconductor atoms such as Si atoms are bonded (forming a Si-H chain) to stabilize the damage generated. If H is present before He implantation, more nucleation sites will be produced.

現在參考圖6A-6B,顯示的是適合用來達到晶核形成部位密度空間性變化的更進一步範例。在這個範例中,如圖6A所示,可在離子植入步驟期間藉著調整離子射束的射束角度達到晶核形成部位密度空間性變化。雖然射束角度可藉著多種方式調整,其中一種方式是將施體半導體晶片120針對離子射束(如點射束202)傾斜,如圖6A所示。施體半導體晶片120有一個寬度(如頁面顯示從左到右),深度(深入頁內),和高度(如頁面顯示從上到下)。寬度和深度可界定出X-和Y-軸方向,而高度可界定出垂直於植入表面121的縱向軸Lo。傾斜施體半導體晶片120以使縱向軸Lo在離子植入步驟期間是成針對離子植入射束方向軸(以實心箭頭顯示)的角度Φ。角度Φ可以是在約1到45度之間。Referring now to Figures 6A-6B, there is shown a further example suitable for achieving spatial variations in the density of nucleation sites. In this example, as shown in FIG. 6A, a spatial variation in density of nucleation sites can be achieved by adjusting the beam angle of the ion beam during the ion implantation step. While the beam angle can be adjusted in a number of ways, one way is to tilt the donor semiconductor wafer 120 against an ion beam (e.g., spot beam 202), as shown in Figure 6A. The donor semiconductor wafer 120 has a width (such as a page display from left to right), a depth (inside the page), and a height (such as a page display from top to bottom). The width and depth may define the X- and Y-axis directions, while the height may define a longitudinal axis Lo that is perpendicular to the implant surface 121. The donor semiconductor wafer 120 is tilted such that the longitudinal axis Lo is at an angle Φ for the ion implantation beam direction axis (shown by solid arrows) during the ion implantation step. The angle Φ can be between about 1 and 45 degrees.

在傾斜的情況下,射束來源從位置A掃瞄到位置B,射束202的寬度W在施體半導體晶片120的植入表面121從寬度Wa變化到Wb,反之亦然。寬度W的變化會造成掃瞄方向(可設定成沿著X-和Y-軸的至少一個方向變化)上由離子植入產生的晶核形成部位密度改變。In the case of tilting, the beam source is scanned from position A to position B, and the width W of the beam 202 varies from width Wa to Wb at the implant surface 121 of the donor semiconductor wafer 120, and vice versa. A change in the width W causes a change in the density of the nucleation sites formed by ion implantation on the scanning direction (which can be set to vary in at least one direction along the X- and Y-axes).

植入射束202可包括具有相同(正)電荷的氫離子。當具有相同電荷的粒子互相驅離時,射束202在距離離子來源較遠的距離時較寬(位置A),在距離離子來源較近的距離時較窄(位置B)。位置B較聚集(較低的寬度Wb)的離子射束會比位置A較不聚集(較高的寬度Wa)的離子射束,加熱施體半導體晶片120的局部區域到較高的程度。在較高的溫度下,較多氫離子會從這個局部區域擴散,和其他區域比較,會剩下較少的氫離子。如圖6B所示,這會在施體半導體晶片120的弱化片層125內產生側向的氫非均勻分佈(因而是晶核形成部位的密度)。Implanted beam 202 can include hydrogen ions having the same (positive) charge. When particles of the same charge are driven away from each other, beam 202 is wider at a greater distance from the ion source (position A) and narrower at a closer distance from the ion source (position B). The ion beam of position B is more concentrated (lower width Wb) than the ion beam of position A (higher width Wa), and the local area of the donor semiconductor wafer 120 is heated to a higher degree. At higher temperatures, more hydrogen ions will diffuse from this localized area, leaving less hydrogen ions than other regions. As shown in FIG. 6B, this creates a lateral hydrogen non-uniform distribution (and thus a density of nucleation sites) within the weakened sheet 125 of the donor semiconductor wafer 120.

藉著調整射束來源的角度或併入一些已知的用來調整離子射束202準直的機制可達到類似的晶核形成部位密度空間性變化。Similar spatial variations in nucleation site density can be achieved by adjusting the angle of the beam source or by incorporating some known mechanisms for adjusting the alignment of ion beam 202.

適合用來達到晶核形成部位密度空間性變化的更進一步技術是使用二階段離子植入步驟。第一離子植入步驟是執行具有吸引第二離子成分效果的離子植入。之後,植入第二離子成分。第一離子成分是使用本文中任何適合的前述或稍後描述的技術以空間上非均勻的方式植入。因此,當第二離子成分植入時,會遷移到第一成分,產生的弱化片層125 會顯示非均勻的晶核形成部位密度。A further technique suitable for achieving spatial variations in the density of nucleation sites is to use a two-stage ion implantation step. The first ion implantation step is to perform ion implantation with the effect of attracting the second ion component. Thereafter, a second ionic component is implanted. The first ionic component is implanted in a spatially non-uniform manner using any suitable aforementioned or later described techniques herein. Therefore, when the second ion component is implanted, it migrates to the first component, and the resulting weakened sheet 125 It will show the density of non-uniform nucleation sites.

例如,第一離子成分可以根據施體半導體晶片120的材料,譬如使用矽離子植入在矽施體半導體晶片120內。這種Si離子的特性會捕捉第二離子成分譬如氫離子。如以上說明的,氫離子和譬如Si原子的一些半導體原子黏結,形成Si-H鏈。舉例而言,可在此項技術已知的劑量和能量下,執行矽到矽的植入,譬如美國專利第7,148,124號中所說明的,其完整的揭露在本文也全部併入參考。然而,不同於先前的技術,捕捉的離子成分(在這個例子是Si)空間上密度分佈是非均勻的(譬如在施體半導體晶片120的一邊是最高,而在相反一邊是最低,或本文討論的其他變化)。接著,植入譬如氫的第二離子成分,這可能是均勻的分佈。施體半導體晶片120的弱化片層125內剩餘的氫量取決於兩個因素:(1)可捕捉譬如氫的第二離子成分的集中分佈部位,和(2)可以使用的氫(植入的氫和植入劑量剩餘的氫)。For example, the first ionic component can be implanted within the donor semiconductor wafer 120 in accordance with the material of the donor semiconductor wafer 120, such as using erbium ions. This characteristic of Si ions captures a second ion component such as a hydrogen ion. As explained above, hydrogen ions and some semiconductor atoms such as Si atoms are bonded to form a Si-H chain. For example, implants of sputum can be performed at doses and energies known in the art, as described in U.S. Patent No. 7,148,124, the entire disclosure of which is incorporated herein by reference. However, unlike previous techniques, the captured ion composition (in this example is Si) spatially has a non-uniform density distribution (eg, the highest on one side of the donor semiconductor wafer 120 and the lowest on the opposite side, or discussed herein). Other changes). Next, a second ionic component such as hydrogen is implanted, which may be a uniform distribution. The amount of hydrogen remaining in the weakened sheet 125 of the donor semiconductor wafer 120 depends on two factors: (1) a concentrated distribution of the second ionic component that captures, for example, hydrogen, and (2) hydrogen that can be used (implanted Hydrogen and implanted dose of residual hydrogen).

要注意的是,可反轉成分的非均勻空間分佈以達到類似的結果。例如,可均勻植入第一成分,接著非均勻植入第二成分。或者,兩種植入都是空間上非均勻的。弱化片層125內第二成分(譬如氫)的非均勻分佈會產生最高氫濃度的一點、邊緣或區域,也就是起始分裂的最低溫度位置。It is to be noted that the non-uniform spatial distribution of the components can be reversed to achieve similar results. For example, the first component can be implanted uniformly, followed by non-uniform implantation of the second component. Alternatively, both implants are spatially non-uniform. The non-uniform distribution of the second component (e.g., hydrogen) within the weakened sheet 125 produces a point, edge or region of highest hydrogen concentration, i.e., the lowest temperature position at which the split begins.

再參考圖2A-2B,箭頭A顯示剝離層122自施體半導體晶片120可定向和/或時間性控制的分離特性以達到從弱化片層125的一點、邊緣及/或區域到其他一點、邊緣及/或區域的傳播分離,作為時間的函數。在晶核形成部位密度空間 性變化的情形中,提升施體半導體晶片120的溫度,使其足以從弱化片層125最高密度的一點、邊緣及/或區域起始分離。我們發現矽中氫的高濃度可在溫度350℃或以下分離,而較低濃度的氫要在較高溫例如450℃或更高分離。將施體半導體晶片120提升到進一步的溫度使其足以在實質上定向地沿著弱化片層125的方向繼續分離,作為整個弱化片層125密度空間性變化的函數。Referring again to Figures 2A-2B, arrow A shows the separation and/or temporally controlled separation characteristics of the release layer 122 from the donor semiconductor wafer 120 to achieve a point, edge and/or region from the weakened sheet 125 to other points, edges. And/or the separation of the regions as a function of time. Density space in the nucleation site In the case of a sexual change, the temperature of the donor semiconductor wafer 120 is raised enough to initiate separation from the point, edge and/or region of the highest density of the weakened sheet 125. We have found that high concentrations of hydrogen in helium can be separated at temperatures of 350 ° C or below, while lower concentrations of hydrogen are separated at higher temperatures, such as 450 ° C or higher. The donor semiconductor wafer 120 is lifted to a further temperature sufficient to continue to separate in a substantially oriented direction along the weakened sheet 125 as a function of the spatial variation of the density of the entire weakened sheet 125.

現在提供進一步的細節,參考在X-軸和Y-軸的一個或兩個方向上離子植入所產生的空間性變化弱化片層125深度的特定參數。不管使用什麼技術達到這種空間性變化,實質上低的深度最好在約200-380nm之間,而最高深度在約400-425nm之間。以另一種方式看待這種變化,最大和最小深度之間的差異可以是約5-200%之間。Further details are now provided, with reference to the spatial variation of ion implantation in one or both directions of the X-axis and the Y-axis to attenuate specific parameters of the depth of the sheet 125. Regardless of the technique used to achieve this spatial variation, the substantially low depth is preferably between about 200-380 nm and the highest depth is between about 400-425 nm. Looking at this change in another way, the difference between the maximum and minimum depths can be between about 5-200%.

依據本發明一或多個態樣,可藉著在離子植入步驟期間調整離子射束的射束角度,空間性變化弱化片層125的深度。的確,可應用針對圖6A-6B所討論的處理過程以調整弱化片層125的深度(要注意改變溫度作為射束寬度函數的機制,並不被認為是達到弱化片層125深度變化的理由)。In accordance with one or more aspects of the present invention, the spatial variation can weaken the depth of the sheet 125 by adjusting the beam angle of the ion beam during the ion implantation step. Indeed, the process discussed with respect to Figures 6A-6B can be applied to adjust the depth of the weakened sheet 125 (note the mechanism of changing the temperature as a function of beam width, and is not considered to be the reason for achieving the depth variation of the weakened sheet 125) .

參考圖6A以及7A-7B,可藉著改變至少下列一項,達到弱化片層125深度的空間性變化:(1)傾斜角度Φ(請參考圖6A的顯示和說明),(2)針對離子植入射束202的方向軸,施體半導體晶片120之縱向軸Lo的扭轉。調整傾斜及/或扭轉以調整導向通過施體半導體晶片120晶格結構的一個角度,使得當離子射束202掃瞄整個植入表面121時,通過施 體半導體晶片120晶格結構的導向有對齊和不對齊離子射束202的傾向。當導向的角度空間性變化時,弱化片層125的深度也會隨之改變。Referring to Figures 6A and 7A-7B, the spatial variation of the depth of the weakened sheet 125 can be achieved by changing at least one of the following: (1) tilt angle Φ (please refer to the display and illustration of Figure 6A), (2) for ions The direction axis of the implanted beam 202 is applied to the torsion of the longitudinal axis Lo of the semiconductor wafer 120. Adjusting the tilt and/or twist to adjust an angle directed through the donor semiconductor wafer 120 lattice structure such that when the ion beam 202 scans the entire implant surface 121, The orientation of the bulk crystal structure of the bulk semiconductor wafer 120 has a tendency to align and misalign the ion beam 202. When the angle of the orientation changes spatially, the depth of the weakened sheet 125 also changes.

角度Φ可以在約1-10度之間,而扭轉角度可以在約1-45度之間。The angle Φ can be between about 1-10 degrees and the twist angle can be between about 1-45 degrees.

如同以上的推論,請進一步參考圖7C和7D,植入深度會隨著傾斜變大而變小。對相對小的角度而言(譬如0-10度),植入深度和傾斜的關係是由導向來控制。對相對大的角度而官,是由餘弦效應控制。換句話說,所產生的剝離膜厚度是和入射角度的餘弦成正比。As with the above inference, with further reference to Figures 7C and 7D, the implant depth will become smaller as the tilt becomes larger. For relatively small angles (such as 0-10 degrees), the relationship between implant depth and tilt is controlled by steering. For a relatively large angle, the official is controlled by the cosine effect. In other words, the resulting peel film thickness is proportional to the cosine of the angle of incidence.

或者或此外,空間性變化步驟可包括改變離子射束202的能量水準,使得當離子射束202掃瞄施體半導體晶片120的整個植入表面121時,自植入表面121算起的弱化片層125深度也會在整個施體半導體晶片120空間性地變化。Alternatively or in addition, the spatially varying step can include varying the energy level of the ion beam 202 such that when the ion beam 202 scans the entire implant surface 121 of the donor semiconductor wafer 120, the weakened sheet from the implanted surface 121 The depth of layer 125 will also vary spatially throughout the donor semiconductor wafer 120.

如圖7B所示,以上的技術產生施體半導體晶片120的弱化片層(或植入深度)側向的非均勻深度。As shown in FIG. 7B, the above technique produces a laterally non-uniform depth of the weakened sheet (or implant depth) of the donor semiconductor wafer 120.

可以使用更進一步的參數和施體半導體晶片120的傾斜一起調整,達到離子沉積分佈寬度(或分散)的空間性變化。如圖8A所示,經過弱化片層125(從上到下)的離子分佈寬度改變是施體半導體晶片120傾斜角度(更概括而言是射束角度)的函數。因此,可藉著改變傾斜角度,達到弱化片層125內空間性變化的分佈寬度(如圖8B所示)。然而,不想被限定於任何運作理論,咸信與具有較寬分佈寬度的部分弱化片層125比較,具有較窄分佈寬度的部分弱化片層125會在較低的 溫度下分離。因此,咸信剝離層122自施體半導體晶片120可定向及/或時間性控制的分離特性可達到從弱化片層125的一點、邊緣及/或區域到其他一點、邊緣及/或區域的傳播分離,作為時間和溫度的函數。Further parameters can be adjusted along with the tilt of the donor semiconductor wafer 120 to achieve a spatial variation in the width (or dispersion) of the ion deposition distribution. As shown in FIG. 8A, the change in ion distribution width through the weakened sheet 125 (from top to bottom) is a function of the tilt angle (and more generally the beam angle) of the donor semiconductor wafer 120. Therefore, the distribution width of the spatial variation in the weakened sheet 125 can be achieved by changing the tilt angle (as shown in Fig. 8B). However, without wishing to be limited to any theory of operation, the partially weakened sheet 125 having a narrower distribution width will be lower in comparison with the partially weakened sheet 125 having a wider distribution width. Separated at temperature. Thus, the orientation and/or temporally controlled separation characteristics of the salt stripping layer 122 from the donor semiconductor wafer 120 can be propagated from a point, edge and/or region of the weakened sheet 125 to other points, edges and/or regions. Separation as a function of time and temperature.

請參考圖8C,有關傾斜在分散效應上的額外資料,又會衝擊植入劑之量變曲線的寬度。圖8C所示兩種植入劑的劑量是一樣的。雖然尖峰H濃度是不同的,但兩種植入劑都會分離。因此,±0.1度和±3度傾斜改變之間的差異,對分散而言是很明顯的。Referring to Figure 8C, additional information on the effect of the tilt on the dispersion effect will again impact the width of the dose curve of the implant. The doses of the two implants shown in Figure 8C are the same. Although the peak H concentration is different, both implants are separated. Therefore, the difference between the ±0.1 degree and ±3 degree tilt changes is apparent for dispersion.

參考圖9C-9D,另一種弱化片層125空間性變化深度的技術包括將施體半導體晶片120施以植入後的材料移除處理,使得自植入表面121算起的弱化片層125的深度在整個施體半導體晶片120是空間性變化的。如圖9A所示,可使施體半導體晶片120施以一些決定性的研磨處理過程或電漿輔助化學蝕刻(PACE)。這些技術可局部控制研磨步驟所移除的材料量。其他方法包括反應離子蝕刻(RIE)、化學機械式研磨(CMP)和溼化學蝕刻,也可以有規則且可再現性的在整個暴露表面非均勻的材料移除。可以使用一種或多種這些或其他技術,造成自植入表面121算起的的弱化片層125深度的些微變化,譬如圖3A、4A、4B、4C和其他圖所顯示的。在材料移除之前的離子植入步驟可以是空間上均勻或非均勻的。Referring to Figures 9C-9D, another technique for weakening the spatially varying depth of the sheet 125 includes applying the donor semiconductor wafer 120 to an implanted material removal process such that the depth of the weakened sheet 125 from the implanted surface 121 is The entire donor semiconductor wafer 120 is spatially variable. As shown in FIG. 9A, the donor semiconductor wafer 120 can be subjected to some decisive grinding process or plasma assisted chemical etching (PACE). These techniques can locally control the amount of material removed by the grinding step. Other methods include reactive ion etching (RIE), chemical mechanical polishing (CMP), and wet chemical etching, as well as regular and reproducible material removal across the exposed surface. One or more of these or other techniques may be used to cause slight variations in the depth of the weakened sheet 125 from the implanted surface 121, as shown in Figures 3A, 4A, 4B, 4C and other figures. The ion implantation step prior to material removal may be spatially uniform or non-uniform.

參考圖9B和9C,空間性變化的步驟可包括在施體半導體晶片120的植入表面121上以空間上非均勻的方式使用遮罩220A或220B,使得當離子射束202掃瞄整個植入表 面121時阻止離子的透至不同的程度。遮罩薄膜220可包括二氧化矽,譬如光阻的有機聚合物和其他。可能的沉積技術包括加強電漿的化學蒸氣沉積(PECVD)、旋轉塗膜、聚二甲基矽氧烷(PDMS)衝壓等。遮罩薄膜220的厚度可小於或比擬弱化片層125所需的深度。因為植入離子的深度是以入射離子的能量來決定,遮罩220的阻擋動作會轉變成施體半導體晶片120內主要植入成分深度的空間調變。根據沉積遮罩220的特性,可藉著增加離子路徑的長度、擴散離子以更改導向的度數、或其他現象達到所需的特性。Referring to Figures 9B and 9C, the step of spatially varying may include using the mask 220A or 220B in a spatially non-uniform manner on the implanted surface 121 of the donor semiconductor wafer 120 such that when the ion beam 202 scans the entire implant table When the face 121 is 121, the penetration of ions is prevented to a different extent. The mask film 220 may include ruthenium dioxide, such as a photoresist organic polymer and others. Possible deposition techniques include enhanced chemical vapor deposition of plasma (PECVD), spin coating, polydimethylsiloxane (PDMS) stamping, and the like. The thickness of the mask film 220 can be less than or less than the desired depth of the sheet 125. Because the depth of the implanted ions is determined by the energy of the incident ions, the blocking action of the mask 220 translates into a spatial modulation of the depth of the primary implant component within the donor semiconductor wafer 120. Depending on the nature of the deposition mask 220, the desired characteristics can be achieved by increasing the length of the ion path, diffusing ions to change the degree of orientation, or other phenomena.

如圖9D所示(顯示弱化片層125所有邊緣的較低深度和朝向中央的較高深度),施體半導體晶片120在黏結到基板102之後和期間,提升溫度到足以在弱化片層125較低深度的一點、邊緣及/或區域起始分離。進一步提升施體半導體晶片120的溫度,使其足以在實質上定向沿著弱化片層125繼續分離,作為從最低深度到最高深度空間性變化的函數。As shown in FIG. 9D (showing the lower depth of all edges of the weakened sheet 125 and the higher depth toward the center), the donor semiconductor wafer 120 is elevated to a temperature sufficient to weaken the sheet 125 after and during bonding to the substrate 102. A point, edge and/or area of low depth begins to separate. The temperature of the donor semiconductor wafer 120 is further increased to be sufficient to continue to separate along the weakened sheet 125 substantially as a function of spatial variation from the lowest depth to the highest depth.

參考圖10A-10D及11,空間性變化的步驟可包括鑽一個或多個的盲孔230穿過植入表面121至少到弱化片層125,最好是穿過弱化片層125(圖10B)。不想限制本發明在任何運作理論,咸信在黏結到基板102(圖10C)期間或之後,提升施體半導體晶片120到較高的溫度,在不具有盲孔230的位置分離之前,在盲孔230處(圖10D)起始分離。如圖11所示,穿過植入表面121鑽一個盲孔230的陣列可以產生這些孔非均勻的空間性分佈。因此,可定向達成提升施體半導體晶片120的溫度,使其足以在實質上沿著弱化片層125起始 並繼續分離,從最高到最低濃度,作為盲孔230陣列分佈的函數。Referring to Figures 10A-10D and 11, the step of spatially varying may include drilling one or more blind holes 230 through the implant surface 121 at least to the weakened sheet 125, preferably through the weakened sheet 125 (Figure 10B). . Without wishing to limit the invention in any theory of operation, the donor semiconductor wafer 120 is lifted to a higher temperature during or after bonding to the substrate 102 (Fig. 10C), before being separated at a location without the blind via 230, in a blind via. The separation was initiated at 230 (Fig. 10D). As shown in Figure 11, drilling an array of blind holes 230 through the implant surface 121 can create a non-uniform spatial distribution of the holes. Thus, the temperature of the donor semiconductor wafer 120 can be oriented to be sufficient to initiate substantially along the weakened sheet 125. And continue to separate, from highest to lowest concentration, as a function of the distribution of the blind holes 230 array.

參考圖12A-12B,空間性變化的步驟可包括將施體半導體晶片120施以非均勻的時間-溫度量變曲線,使得穿過弱化片層125的各個空間位置的晶核形成部位密度或壓力在整個施體半導體晶片120空間性地變化。例如,圖12A所示的溫度梯度施加比右邊較高的溫度到晶片120的左邊。這種溫度梯度可以在黏結之前,或黏結到基板102期間在原地施加。經過一段時間,假使處理時間維持在低於特定處理溫度的分離門檻,晶核形成的缺陷部位和其中的氣體壓力的至少一者在整個弱化片層125會以不同的程度增加,在空間上遍及晶片120作為溫度梯度的函數(請見圖12B)。預期特定處理溫度的分離門檻時間是遵循著Arrhenius關係,分離門檻時間是和處理溫度的倒數成指數比例。重要的參數是在處理溫度的處理時間和分離門檻時間的比例。本文討論的或需要的任何前述空間性變化參數量變曲線可藉著調整處理時間-分離時間比的量變曲線而達成。接著,施體半導體晶片120的溫度提升到足以在弱化片層125處,從最大處理時間-分離時間比的一點、邊緣及/或區域起始分離。在所示的例子中,最大處理時間-分離時間比是在晶片120的左邊。接著,更進一步提升施體半導體晶片120的溫度,使其足以在實質上定向地沿著弱化片層125繼續分離,從最大處理時間-分離時間比到最小處理時間-分離時間比,作為變化時間-溫度量變曲線的函數。根據材料特徵和其他因素,包括離子成分、劑量和植入 深度,實質上高的處理時間-分離時間比是在約0.9和0.5之間,而最低的處理時間-分離時間比是在約0和0.5之間。Referring to Figures 12A-12B, the step of spatially varying may include applying a non-uniform time-temperature variability curve to the donor semiconductor wafer 120 such that the nucleation site density or pressure across the various spatial locations of the weakened sheet 125 is The entire donor semiconductor wafer 120 varies spatially. For example, the temperature gradient shown in FIG. 12A applies a higher temperature than the right to the left of the wafer 120. This temperature gradient can be applied in situ prior to bonding, or during bonding to the substrate 102. After a period of time, if the processing time is maintained at a separation threshold below a certain processing temperature, at least one of the defect portion formed by the nucleus and the gas pressure therein may increase to a different extent throughout the weakened sheet layer 125, spatially throughout Wafer 120 acts as a function of temperature gradient (see Figure 12B). It is expected that the separation threshold time for a particular treatment temperature follows the Arrhenius relationship, and the separation threshold time is exponentially proportional to the reciprocal of the treatment temperature. The important parameters are the ratio of processing time at the processing temperature to the separation threshold time. Any of the aforementioned spatially varying parameter magnitude curves discussed or required herein can be achieved by adjusting the process time-separation time ratio. Next, the temperature of the donor semiconductor wafer 120 is raised sufficiently to initiate separation at a point, edge and/or region of the maximum processing time-separation time ratio at the weakened sheet layer 125. In the example shown, the maximum processing time-to-separation time ratio is on the left side of the wafer 120. Next, the temperature of the donor semiconductor wafer 120 is further increased to be sufficient to continue to separate along the weakened sheet layer 125 substantially in a direction, from a maximum processing time-separation time ratio to a minimum processing time-separation time ratio as a change time. - A function of the temperature variation curve. Based on material characteristics and other factors, including ionic composition, dose, and implant The depth, substantially high processing time-to-separation time ratio is between about 0.9 and 0.5, and the lowest processing time-separation time ratio is between about 0 and 0.5.

可以使用各種預先黏結或在原地黏結的機制,達到空間性變化之時間-溫度量變曲線。例如,可以使用一個或多個空間上非均勻的傳導、對流或輻射加熱技術(加熱板、雷射幅照、可見的/紅外燈或其他),來加熱施體半導體晶片120。可藉由直接或間接的熱接觸(傳導)達到控制的時間/溫度梯度,以達成任何所需的量變曲線。可根據電腦控制或程式設計,使用加熱板元件的可定址二維陣列,以達到不同的量變曲線。例如,使用快速熱退火的(輻射的)燈局部紅外線輻射,及/或使用可見的或近紅外線雷射幅射來提供局部和空間上非均勻的加熱(輻射)。或者,可透過任何方式使用空間上非均勻的冷卻機制,譬如直接接觸(傳導)、或氣體或流體流噴射(傳導/對流)及使用均勻或非均勻的熱量變曲線,以達到所需的時間-溫度梯度。A time-temperature variability curve for spatial variation can be achieved using a variety of pre-bonded or in-situ bonding mechanisms. For example, the donor semiconductor wafer 120 can be heated using one or more spatially non-uniform conductive, convective or radiant heating techniques (heating plates, laser radiation, visible/infrared lamps, or the like). The controlled time/temperature gradient can be achieved by direct or indirect thermal contact (conduction) to achieve any desired quantitative curve. Depending on the computer control or programming, an addressable two-dimensional array of heating plate elements can be used to achieve different quantitative curves. For example, rapid thermal annealing (radiation) lamps are used for local infrared radiation, and/or visible or near-infrared laser radiation is used to provide localized and spatially non-uniform heating (radiation). Alternatively, spatially non-uniform cooling mechanisms such as direct contact (conduction), or gas or fluid jet (conduction/convection) and uniform or non-uniform thermal curves can be used in any way to achieve the desired time. -Temperature gradient.

再者,可以在預先黏結或在原地使用這些加熱/冷卻技術。關於原地黏結技術,黏結裝置說明於例如美國第11/417,445號發明名稱為「HIGH TEMPERATURE ANODIC BONDING APPARATUS」的專利中“,該專利揭露之全文加入於本文中作為參考,該黏結裝置能夠經修改以使用於本發明。可控制及利用黏結裝置的熱輻射耗損管理達成時間-溫度梯度,經由合併圍繞黏結裝置周圍的紅外線反射元件,以最小化輻射耗損並最大化邊緣溫度。相反地,可控制黏結裝置的熱輻射耗損管理,經由合併冷卻的紅外線吸收器,以最大 化輻射耗損並最小化邊緣溫度。可使用上述主題的多種變化達到所需的時間-溫度梯度。Furthermore, these heating/cooling techniques can be used in advance bonding or in situ. With regard to the in-situ bonding technique, the bonding device is described, for example, in the patent entitled "HIGH TEMPERATURE ANODIC BONDING APPARATUS", US Patent No. 11/417,445, the entire disclosure of which is incorporated herein by reference, For use in the present invention, the thermal radiation loss management of the bonding device can be controlled and utilized to achieve a time-temperature gradient by combining the infrared reflecting elements around the bonding device to minimize radiation loss and maximize edge temperature. Conversely, controllable Heat radiation loss management of the bonding device, through the combined cooling of the infrared absorber, to the maximum Radiation loss and minimize edge temperature. A variety of variations of the above subject matter can be used to achieve the desired time-temperature gradient.

雖然本發明在此已對特定實施例作說明,人們瞭解這些實施例只作為說明本發明原理以及應用。因而人們瞭解數種修飾可做為說明性的實施例,且可在不背離下列申請專利範圍限定之本發明的精神及範疇的情形下設計出其他配置。While the invention has been described herein with respect to the specific embodiments, these embodiments Thus, it is to be understood that various modifications may be made in the exemplified embodiments, and other configurations may be devised without departing from the spirit and scope of the invention as defined by the following claims.

102‧‧‧基板102‧‧‧Substrate

120‧‧‧施體半導體晶片120‧‧‧Sensor semiconductor wafer

121‧‧‧植入表面121‧‧‧ implant surface

122‧‧‧剝離層122‧‧‧ peeling layer

125‧‧‧弱化片層125‧‧‧Weakened slices

Claims (23)

一種形成一絕緣體上半導體(SOI)結構之方法,其包含:提供一施體半導體晶片,該施體半導體晶片具有一寬度、一深度以及一高度,該寬度及該深度界定出X-及Y-軸方向,以及該高度界定出一縱向軸;將該施體半導體晶片的一植入表面施以一離子植入步驟,以在界定出該施體半導體晶片的一剝離層的橫截面上產生一弱化片層;以及在該離子植入步驟之前、期間或之後,將該施體半導體晶片施以一空間性變化步驟,以使自該植入表面算起的該弱化片層深度在針對垂直於該縱向軸而在該X-和Y-軸方向延伸的一參考平面而言的整個該施體半導體晶片上空間性地變化,使得一實質上較低的深度出現在沿著該弱化片層的一起始邊緣、一起始點或一起始區域,以及連續較高的深度出現在該X-及Y-軸的至少一個方向上自該起始邊緣、該起始點或該起始區域算起之連續更遠的距離處。 A method of forming a semiconductor-on-insulator (SOI) structure, comprising: providing a donor semiconductor wafer having a width, a depth, and a height, the width and the depth defining an X- and Y-axis And a height defining a longitudinal axis; applying an ion implantation step to an implant surface of the donor semiconductor wafer to create a weakened layer on a cross section defining a release layer of the donor semiconductor wafer And applying a spatially varying step to the donor semiconductor wafer before, during or after the ion implantation step such that the depth of the weakened layer from the implanted surface is perpendicular to the longitudinal axis Spatially varying across the donor semiconductor wafer in a reference plane extending in the X- and Y-axis directions such that a substantially lower depth occurs along a starting edge of the weakened sheet layer, together a starting point or a starting area, and a continuous higher depth appearing in the at least one direction of the X- and Y-axis from the starting edge, the starting point, or the starting region Distance away. 依據請求項1所述之方法,其中該弱化片層的一最大深度出現在一第一區域中約400-425nm處,以及一最小深度出現在該弱化片層的一第二區域中約200-380nm處,其中該第二區域在該X-和Y-軸方向之至少一個方向上與該第一區域分隔。 The method of claim 1, wherein a maximum depth of the weakened sheet layer occurs at about 400-425 nm in a first region, and a minimum depth occurs in a second region of the weakened sheet layer about 200- At 380 nm, the second region is separated from the first region in at least one of the X- and Y-axis directions. 依據請求項1或2所述之方法,其中在一第一區域中該弱 化片層之該最大深度約為在一第二區域中該弱化片層之該最小深度的1.05至2.00倍。 The method of claim 1 or 2, wherein the weakening in a first region The maximum depth of the layer is about 1.05 to 2.00 times the minimum depth of the weakened sheet in a second region. 依據請求項1或2所述之方法,更進一步包含提昇該施體半導體晶片至一溫度,該溫度足以在該弱化片層處由針對該參考平面而言的該弱化片層最小深度的一點、邊緣及/或區域起始分離。 The method of claim 1 or 2, further comprising elevating the donor semiconductor wafer to a temperature sufficient to be at the weakened sheet layer by a point, edge of the minimum depth of the weakened sheet for the reference plane And / or the area begins to separate. 依據請求項4所述之方法,更進一步包含提昇該施體半導體晶片至進一步的溫度,該溫度足以在實質上定向地沿著該弱化片層連續分離,作為該弱化片層由最小深度至最大深度之不同深度的一函數。 The method of claim 4, further comprising: elevating the donor semiconductor wafer to a further temperature sufficient to continuously separate substantially vertically along the weakened sheet layer as the weakened sheet layer from a minimum depth to a maximum depth A function of different depths. 依據請求項5所述之方法,其中該提升溫度的一時間-溫度量變曲線之規模為數秒,使得沿著該弱化片層由最小深度至最大深度的一分離傳播發生歷經至少一秒。 The method of claim 5, wherein the time-temperature variability curve of the elevated temperature is a few seconds such that a separate propagation from the minimum depth to the maximum depth along the weakened sheet occurs for at least one second. 依據請求項1或2所述之方法,其中該空間性變化步驟包含傾斜該施體半導體晶片,使得在該離子植入步驟過程中,該施體半導體晶片的縱向軸針對一離子植入射束的一方向軸而言為一非零的角度Φ,並使自該植入表面算起的該弱化片層深度於整個該施體半導體晶片空間性地變化。 The method of claim 1 or 2, wherein the spatially varying step comprises tilting the donor semiconductor wafer such that during the ion implantation step, the longitudinal axis of the donor semiconductor wafer is directed to one of the ion implanted beams The direction axis is a non-zero angle Φ and the depth of the weakened sheet from the implant surface varies spatially throughout the donor semiconductor wafer. 依據請求項7所述之方法,其中該角度Φ在約1至45度 之範圍內。 The method of claim 7, wherein the angle Φ is between about 1 and 45 degrees. Within the scope. 依據請求項7所述之方法,其中該空間性變化步驟更進一步包含變化下列至少一項:傾斜的該角度Φ;以及該施體半導體晶片的縱向軸針對該離子植入射束之方向軸而言的一扭轉,使得當該離子植入射束掃瞄整個該施體半導體晶片之該植入表面時,導向通過該施體半導體晶片的晶格結構有對齊以及不對齊該離子植入射束的傾向。 The method of claim 7, wherein the spatially varying step further comprises varying at least one of: an angle Φ of the tilt; and a longitudinal axis of the donor semiconductor wafer for a direction axis of the ion implant beam A twist such that when the ion implant beam scans the implant surface of the donor semiconductor wafer, the lattice structure directed through the donor semiconductor wafer has a tendency to align and misalign the ion implanted beam. 依據請求項9所述之方法,其中當該離子植入射束掃瞄整個該施體半導體晶片之該植入表面時,該空間性變化步驟更進一步包含變化該離子植入射束的一能量值,使得自該植入表面算起的該弱化片層深度於整個該施體半導體晶片空間性地變化。 The method of claim 9, wherein the spatially varying step further comprises varying an energy value of the ion implanted beam when the ion implant beam scans the implant surface of the donor semiconductor wafer. The depth of the weakened sheet from the implanted surface is spatially varied throughout the donor semiconductor wafer. 依據請求項7所述之方法,其中該空間性變化步驟包含以一空間上非均勻的方式遮罩該施體半導體晶片之該植入表面,使得當該離子植入射束掃瞄整個該植入表面時,阻止該離子的穿透至不同的程度。 The method of claim 7, wherein the step of spatially varying comprises masking the implanted surface of the donor semiconductor wafer in a spatially non-uniform manner such that when the ion implanted beam scans the implant At the surface, the penetration of the ions is prevented to a different extent. 依據請求項1或2所述之方法,其中該空間性變化步驟包含: 將該植入表面施以實質上均勻的離子植入步驟,以在針對該參考平面而言的一實質上均勻的深度產生該弱化片層;以及將該施體半導體晶片施以一植入後之材料去除處理過程,使得自該植入表面算起的該弱化片層深度於整個該施體半導體晶片空間性地變化。 The method of claim 1 or 2, wherein the spatially varying step comprises: Applying the implanted surface to a substantially uniform ion implantation step to produce the weakened sheet at a substantially uniform depth for the reference plane; and applying the donor semiconductor wafer to an implanted surface The material removal process causes the weakened sheet depth from the implanted surface to vary spatially throughout the donor semiconductor wafer. 依據請求項1所述之方法,其中該實質上較低的深度在約200-380nm的範圍內,以及一最高深度在約400-425nm的範圍內。 The method of claim 1 wherein the substantially lower depth is in the range of about 200-380 nm and the highest depth is in the range of about 400-425 nm. 依據請求項1所述之方法,其中:該施體半導體晶片為長方形;以及該空間性變化步驟包含空間性地變化深度,使得一實質上較低的深度出現在該弱化片層的至少兩個邊緣之每一邊緣處,以及相對較高的深度出現在該弱化片層的至少兩個邊緣朝向該弱化片層中心之連續更遠的距離處。 The method of claim 1, wherein: the donor semiconductor wafer is rectangular; and the spatially varying step comprises spatially varying depth such that a substantially lower depth occurs at at least two edges of the weakened sheet At each of the edges, and at a relatively high depth, at least two of the edges of the weakened sheet layer are at a greater distance from the center of the weakened sheet. 依據請求項1所述之方法,其中該空間性變化步驟包含空間性地變化該深度,使得一實質上較低的深度出現在該弱化片層的所有邊緣處,以及相對較高的深度出現在朝向該弱化片層中心於連續更遠的距離處。 The method of claim 1, wherein the step of spatially varying comprises spatially varying the depth such that a substantially lower depth occurs at all edges of the weakened sheet and a relatively higher depth occurs Towards the center of the weakened sheet at a continuously further distance. 一種形成一絕緣體上半導體(SOI)結構之方法,其包含: 將一施體半導體晶片的一植入表面施以一離子植入步驟,以在界定出該施體半導體晶片的一剝離層的橫截面上產生一弱化片層;以及將該施體半導體晶片施以一非均勻的時間-溫度量變曲線處理,因而調整一處理過程時間-分離時間之比值量變曲線,使得缺陷部位晶核形成以及壓力增加的至少一者在整個弱化片層的各別空間位置處遍及該X-及Y-軸的至少一個方向空間性地變化。 A method of forming a semiconductor-on-insulator (SOI) structure comprising: Applying an ion implantation step to an implant surface of a donor semiconductor wafer to create a weakened layer on a cross section defining a release layer of the donor semiconductor wafer; and applying the donor semiconductor wafer to Non-uniform time-temperature variability curve processing, thereby adjusting a process time-separation time ratio variability curve such that at least one of defect site nucleation and pressure increase is present throughout the weakened slab at respective spatial locations At least one direction of the X- and Y-axis changes spatially. 依據請求項16所述之方法,其中該時間-溫度量變曲線並不足以自該施體半導體晶片起始分離該剝離層。 The method of claim 16, wherein the time-temperature variability curve is not sufficient to separate the release layer from the donor semiconductor wafer. 依據請求項16或17所述之方法,其中包含下列一項:在將該植入表面黏接至一絕緣基板之前,施以該非均勻的時間-溫度量變曲線處理之步驟;以及在將該植入表面黏接至一絕緣基板之過程中,在原處施以該非均勻的時間-溫度量變曲線處理之步驟。 The method of claim 16 or 17, comprising the step of: applying the non-uniform time-temperature amount curve processing step before bonding the implant surface to an insulating substrate; In the process of bonding the surface to an insulating substrate, the non-uniform time-temperature variable curve processing step is applied in situ. 依據請求項17所述之方法,更進一步包含提高該施體半導體晶片的一溫度,該溫度足以在該弱化片層處由該弱化片層之處理時間-分離時間之最大比值的一點、邊緣及/或區域起始分離。 The method of claim 17, further comprising increasing a temperature of the donor semiconductor wafer at a point, edge and/or at a maximum ratio of the processing time-separation time of the weakened sheet at the weakened sheet layer. Or the area begins to separate. 依據請求項19所述之方法,更進一步包含提高該施體半 導體晶片至進一步的溫度,該溫度足以在實質上定向地沿著該弱化片層連續分離,作為該弱化片層變化時間-溫度量變曲線的一函數,該函數之範圍由處理時間-分離時間之最大比值至處理時間-分離時間之最小比值。 According to the method of claim 19, further comprising increasing the donor half The conductor wafer is further heated to a temperature that is substantially continuously separated along the weakened sheet layer as a function of the time-temperature variation curve of the weakened sheet, the function being ranged by the processing time-separation time The ratio of the maximum ratio to the processing time - the minimum ratio of the separation time. 依據請求項16或17所述之方法,其中該非均勻的時間-溫度量變曲線使得一實質上高的處理時間-分離時間之比值出現在沿著該弱化片層之一起始邊緣、一起始點或一起始區域,以及相對較低的處理時間-分離時間之比值出現在該X-及Y-軸的至少一個方向上自該起始邊緣、該起始點或該起始區域算起之連續更遠的距離處。 The method of claim 16 or 17, wherein the non-uniform time-temperature variability curve causes a substantially high processing time-to-separation time ratio to occur along a starting edge, a starting point of the weakened sheet or a starting region, and a relatively low processing time-separation time ratio appearing in at least one direction of the X- and Y-axis from the starting edge, the starting point, or the starting region Far away. 依據請求項21所述之方法,其中該實質上高的處理時間-分離時間之比值在約0.5至0.9之範圍內,以及一最低處理時間-分離時間之比值在約0至0.5之範圍內。 The method of claim 21, wherein the substantially high processing time-to-separation time ratio is in the range of about 0.5 to 0.9, and the minimum processing time-separation time ratio is in the range of about 0 to 0.5. 依據請求項16或17所述之方法,其中一實質上高的處理時間-分離時間之比值出現在沿著該弱化片層之一個或多個邊緣的一起始點或區域處,以及相對較低的處理時間-分離時間之比值出現在該X-及Y-軸之兩個方向上自該起始點或區域算起之連續更遠的距離處。 According to the method of claim 16 or 17, wherein a substantially high processing time-to-separation time ratio occurs at a starting point or region along one or more edges of the weakened sheet layer, and relatively low The processing time-to-separation time ratio occurs at successively longer distances from the starting point or region in both the X- and Y-axis directions.
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