Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/32—Timing circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
  • G11C7/1066—Output synchronization
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
  • G11C7/1069—I/O lines read out arrangements
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
  • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Definitions

• the invention relates generally to solid state memory systems featuring a set of serial-connected memory devices.
• NAND flash memory systems use a large number of parallel signals for the commanding, addressing, and data transferring operations. This was a very popular way of configuring memory systems and results in very fast system operation. This is particularly true for random access memory devices like DRAM (dynamic random access memory), SRAM (static random access memory), etc.
• DRAM dynamic random access memory
• SRAM static random access memory
• the conventional NAND flash memory communicates with other components using a set of parallel input/output (I/O) pins, numbering 8 or 16 depending on the desired word configuration, which receive command instructions, receive input data and provide output data.
• I/O input/output
• This is commonly known as a parallel interface. High speed operation will cause well known 76181-75
• Such parallel interfaces use a large number of pins to read and write data. As the number of input pins and wires increases, so do a number of undesired effects. These effects include inter-symbol interference, signal skew and cross talk.
• serial in/out data pins typically have serial in/out data pins along with two control signals for the enabling and disabling of a serial input port and serial output port respectively in order to provide a memory controller with the maximum flexibility of serial data communication.
• Some of these memory system configurations employ a shared bus topology for the system clock distribution, which is referred to as a 'common clock system' or 'multi-drop clocking system'.
• Some of these architectures use a point-to-point serial- connected clocking architecture featuring a DLL (delay locked loop) or PLL (phase locked loop) in every memory chip in order to synchronize two clock signals in each memory device, one being an input clock received from a preceding device or controller and the other being an output clock transmitted to the next device.
• the invention provides a method in a slave device of a plurality of serial-connected slave devices, the method comprising: receiving a command from a master device specifying an adjustment to a clock duty cycle; 76181-75
• the slave device is a memory device and the master device is a memory controller.
• the method further comprises: receiving a command from a master device specifying how the slave device is to adjust a delay to be applied to at least one signal output by the slave device; receiving at least one input signal, the at least one input signal comprising at least the input clock signal; for each of the at least one input signal: generating a delayed version of the input signal in accordance with the command; outputting the delayed version of the input signal, the delayed version of the input clock signal comprising a delayed version of the duty cycle corrected clock signal.
• receiving a command from a master device specifying an adjustment to a clock duty cycle comprises receiving a command containing a command identifier that identifies the command as a duty cycle correction command, the command further containing data indicating how to adjust the duty cycle.
• receiving a command further comprises receiving a device address indicating which device(s) acting as slave devices is to execute the command.
• the method further comprises: performing the step of generating the duty cycle corrected clock signal in accordance with the command if the command has a device address that matches a device address of the slave device; performing the step of generating the duty cycle corrected clock signal in accordance with the command if the command has a device address that is a broadcast device address. 76181-75
• generating a duty cycle corrected clock signal comprises: a) generating a half rate clock signal from the input clock signal; b) delaying the half rate clock signal by a selected one of a plurality of delays to produce a delayed half rate clock signal; c) combining the half rate clock signal with the delayed half rate clock signal to produce the duty cycle corrected clock signal.
• the data indicating how to adjust the duty cycle correction comprises an indication of the selected one of the plurality of delays.
• the invention provides a method in a memory system comprising a master device and a plurality of serial-connected slave devices comprising at least a first slave device and a last slave device, the method comprising: in the master device: a) outputting a first clock signal that functions as an input clock signal of the first slave device; b) receiving a second clock signal that is an output clock signal of the last slave device; c) generating a duty cycle correction command as a function of a duty cycle of the second clock signal and outputting the duty cycle correction command; in the first slave device of the plurality of serial-connected slave devices: a) receiving the first clock signal from the master device as the input clock signal of the first slave device; b) generating an output clock signal from the input signal; in each other slave device of the plurality of serial-connected slave devices: a) receiving the output clock signal of a preceding slave device as an input clock signal of the slave device; b) generating an output clock signal from the input clock signal; in each of at least one of the
• each slave device is a memory device and the master device is a memory controller. 76181-75
• the method further comprises: in the master device: a) outputting at least one output signal, the at least one output signal comprising the first clock signal to function as an input clock signal of the first slave device; b) receiving a second clock signal that is an output clock signal of the last slave device; c) determining an amount of phase offset between the first clock signal and the second clock signal; d) generating an output delay adjustment command as a function of the phase offset between the first clock signal and the second clock signal and outputting the output delay adjustment command.
• generating a duty cycle correction command as a function of a duty cycle of the second clock signal and outputting the duty cycle correction command comprises generating a duty cycle correction command for execution by any specified one of the plurality of serial-connected slave devices.
• generating a duty cycle correction command as a function of a duty cycle of the second clock signal and outputting the duty cycle correction command comprises generating a duty cycle correction command for execution by all of the plurality of serial-connected slave devices.
• receiving the duty cycle correction command comprises receiving a command containing a command identifier that identifies the command as a duty cycle correction command, and containing data indicating how to adjust the duty cycle.
• generating a duty cycle corrected clock signal comprises: a) generating a half rate clock signal from the input clock signal; b) delaying the half rate clock signal by a selected one of a plurality of delays to produce a delayed half rate clock signal; c) combining the half rate clock signal with the delayed half rate clock signal to produce the duty cycle corrected clock signal.
• the data indicating how to adjust the duty cycle correction comprises an indication of the selected one of the plurality of delays. 76181-75
• the invention provides a slave device for use in an arrangement comprising a plurality of serial-connected slave devices, the slave device comprising: a command input for receiving a command from a master device specifying an adjustment to a duty cycle; a clock input for receiving an input clock signal; a duty cycle correction circuit for generating a duty cycle corrected clock signal from the clock input in accordance with the control command; a clock output for outputting the duty cycle corrected clock signal.
• the slave device is a memory device.
• the command input is also for receiving a command from the master device specifying an adjustment to output delay; an output delay adjustment circuit for generating a delayed clock signal from the duty cycle corrected clock signal in accordance with the command; wherein the clock output for outputting the duty cycle corrected clock signal outputs the delayed clock signal.
• the slave device further comprises: a command processing circuit that processes the command, wherein the command comprises: a command identifier that identifies the command as a duty cycle correction command; and data indicating how to adjust the duty cycle.
• the slave device further comprises: a device address register; wherein the command further comprises a device address indicating which slave device is to execute the command, the slave device configured to execute the command if the device address matches contents of the device address register.
• the duty cycle correction circuit comprises: a) a clock divider circuit that generates a half rate clock signal from the input clock signal; b) a delay circuit that delays the half rate clock signal by a selected one of a plurality of delays to produce a delayed half rate clock signal; c) a combiner that 76181-75
• the invention provides a system comprising: a plurality of serial-connected device acting as slave devices according to claim 13 comprising at least a first slave device and a last slave device; a master device connected to the first slave device and to the last slave device; the master device configured to output a first clock signal that functions as an input clock signal of the first slave device; a clock input for receiving a second clock signal that is an output clock signal of the last slave device; a duty detector that determines a duty cycle of the second clock signal; a command generator that generates a duty cycle correction command specifying an adjustment to a clock duty cycle as a function of the duty cycle of the second clock signal; wherein, the first slave device of the plurality of serial-connected device acting as slave devices: a) receives the first clock signal from the master device as the input clock signal of the first slave device; b) generates an output clock signal from the input clock signal; wherein each other slave device of the plurality of serial- connected device acting as slave devices: a) receives the output clock signal
• the system is a memory system
• each slave device is a memory device
• the master device is a memory controller
• the memory system further comprises: a phase detector that determines an amount of phase offset between the first clock signal and the second clock signal; wherein the command generator also generates an output delay adjustment command as a function of the amount of phase offset; wherein, the first slave device of the plurality of serial-connected slave devices: a) receives the first clock signal from the master device as the input clock signal of the first slave device; b) generates an output clock signal from the input clock signal; wherein each other slave device of the plurality of serial-connected slave devices: a) receives the output clock signal of a preceding slave device as an input clock signal of the slave device; b) generates an output clock signal from the input clock signal; wherein at least one of the plurality of serial-connected slave devices: a) receives the output delay adjustment command; b) generates the output clock signal of the device by delaying the input clock signal of the device in accordance with the control command.
• a phase detector that determines an amount of phase offset between the first clock signal and the second clock signal
• the command generator
• the command generator is configured to generate a duty cycle correction command as a function of a duty cycle of the second clock signal and output the duty cycle correction command by generating a duty cycle correction command for execution by a specified one of the plurality of serial- connected device acting as slave devices.
• the command generator is configured to generate a duty cycle correction command as a function of a duty cycle of the second clock signal and output the duty cycle correction command by generating a duty cycle correction command for execution by all of the plurality of serial-connected device acting as slave devices.
• receiving the duty cycle correction command comprises receiving a command containing a command identifier that identifies the 76181-75
• the invention provides a method in a slave device of a plurality of serial-connected slave devices, the method comprising: receiving a command from a master device specifying how the slave device is to adjust a delay to be applied to at least one signal output by the slave device; receiving at least one input signal, the at least one input signal comprising at least an input clock signal; for each of the at least one input signal: generating a delayed version of the input signal in accordance with the command; outputting the delayed version of the input signal.
• the slave device is a memory device and the master device is a memory controller.
• the method comprises: outputting a data output signal; wherein at least one of the input signals comprises a data input signal and wherein outputting the delayed version of the data input signal is performed as part of outputting the data output signal such that: a) some of the time the data output signal is said delayed version of the data input signal; b) some of the time the data output signal is a delayed version of a signal produced locally to the slave device, after applying the delay to the signal produced locally to the slave device in accordance with the command.
• receiving a command from a master device specifying an adjustment to a delay to be applied to at least one signal output by the slave device comprises receiving a command containing a command identifier that identifies the command as an output delay adjustment command, the command further containing data indicating how to adjust the delay.
• receiving a command further comprises receiving a device address indicating which device(s) acting as slave devices is to execute the command. 76181-75
• the method further comprises: performing the step of, for each of the at least one input signal, generating a delayed version of the input signal in accordance with the command if the command has a device address that matches a device address of the slave device; performing the step of, for each of the at least one input signal, generating a delayed version of the input signal in accordance with the command if the command has a device address that is a broadcast device address.
• generating a delayed version of the input signal comprises: a) delaying the input signal by a selected one of a plurality of delays to produce the delayed version of the input signal.
• the data indicating how to adjust the delay comprises an indication of the selected one of the plurality of delays.
• the plurality of input signals comprise: a clock signal; a command strobe signal; a data strobe signal; a data signal containing commands and data.
• the invention provides a method in a memory system comprising a master device and a plurality of serial-connected device acting as slave devices comprising at least a first slave device and a last slave device, the method comprising: in the master device: a) outputting at least one output signal, the at least one output signal comprising a first clock signal to function as an input clock signal of the first slave device; b) receiving a second clock signal that is an output clock signal of the last slave device; c) determining an amount of phase offset between the first clock signal and the second clock signal; d) generating an output delay adjustment command as a function of the phase offset between the first clock signal and the second clock signal and outputting the output delay adjustment command.
• each slave device is a memory device and the master device is a memory controller. 76181-75
• the method further comprises: in the first slave device of the plurality of serial-connected device acting as slave devices: a) receiving the at least one output signal from the master device as corresponding at least one input signal of the first slave device; b) for each input signal, generating an output signal based on the input signal; in each other slave device of the plurality of serial-connected device acting as slave devices: a) receiving output signal(s) of a preceding slave device corresponding to at least one input signal of the slave device; b) for each input signal, generating an output signal based on the input signal; in at least one of the slave devices, a) receiving the output delay adjustment command; and b) generating the output signal(s) by generating a delayed version of the input signal(s) in accordance with the output delay adjustment command.
• the method further comprises: wherein the at least one output signal of the master device comprises a plurality of output signal(s).
• generating a delay adjustment command comprises generating a delay adjustment command for execution by a specified one of the plurality of serial-connected slave devices.
• generating a delay adjustment command comprises generating a delay adjustment command for execution by all of the plurality of serial-connected slave devices.
• generating a delayed version of the input signal(s) in accordance with the output delay adjustment command comprises generating a delayed version of the input signals(s) delayed by a selected one of a plurality of delays.
• generating a delay adjustment command comprises generating a command containing a command identifier that identifies the command as an output delay adjustment command, and containing data indicating how to adjust the delay.
• the data indicating how to adjust the delay comprises an indication of the selected one of the plurality of delays.
• the method further comprises: the master device outputting output delay adjustment commands that adjust delay by adding a delay one unit delay element in one slave device at a time until the phase offset is acceptable.
• the plurality of input signals comprise: a clock signal; a command strobe signal; a data strobe signal; a data signal containing commands and data.
• the invention provides a slave device for use in an arrangement comprising a plurality of serial-connected slave devices, the slave device comprising: a command input for receiving a command from a master device specifying how to perform output delay adjustment; a clock input for receiving an input clock signal; an output delay adjustment circuit for generating a delayed clock signal from the clock input in accordance with the command; a clock output for outputting the delayed clock signal.
• the slave device is a memory device.
• the slave device comprises: a command processing circuit that processes the command, wherein the command contains a command identifier that identifies the command as an output delay adjustment command, and contains data indicating how to adjust the output delay.
• the slave device further comprises: a device address register; wherein the command further comprises a device address indicating which slave device is to execute the command, the slave device configured to execute the command if the device identifier matches contents of the device address register. 76181-75
• the output delay adjustment circuit comprises: for each of a plurality of input signals, inclusive of the input clock signal, a delay circuit that delays the input signal by a selected one of a plurality of delays to produce a delayed version of the input signal.
• the invention provides a memory system comprising: a plurality of serial-connected slave devices comprising at least a first slave device and a last slave device; a master device connected to the first slave device and to the last slave device; the master device configured to output a first clock signal that functions as an input clock signal of the first slave device; a clock input for receiving a second clock signal that is an output clock signal of the last slave device; a phase detector that determines an amount of phase offset between the first clock signal and the second clock signal; a command generator that generates an output delay adjustment command as a function of the amount of phase offset; wherein, the first slave device of the plurality of serial-connected slave devices: a) receives the first clock signal from the master device as the input clock signal of the first slave device; b) generates an output clock signal from the input clock signal; wherein each other slave device of the plurality of serial-connected slave devices: a) receives the output clock signal of a preceding slave device as an input clock signal of the slave device; b)
• the system is a memory system
• each slave device is a memory device
• the master device is a memory controller
• the command generator is configured to generate the output delay adjustment command for execution by a specified one of the plurality of serial-connected slave devices.
• the command generator is configured to generate the output delay adjustment for execution by all of the plurality of serial-connected slave devices.
• generating an output delay adjustment command comprises generating a command containing a command identifier that identifies the command as an output delay adjustment command, and containing data indicating how to adjust the output delay.
• Methods and apparatus of clock duty cycle correction and/or phase synchronization are provided that do not require DLL or PLL, for a serial- connected memory system, typically including a memory controller and a plurality of memory chips connected in a ring configuration.
• the memory controller has a phase/duty cycle detector for detecting phase and duty cycle of a clock signal after having travelled around the ring, and each memory device has one or more controller programmable delay lines that are used to adjust the phase and/or duty cycle of the clock. These are adjusted by commands sent from the memory controller until the phase and duty cycle detected by the memory controller is acceptable.
• the methods and apparatus described herein can be applied to any kind of semiconductor integrated circuit system having any kind of semiconductor integrated circuit devices as slave devices in a serial-connected configuration with a common interface between adjacent devices.
• integrated circuit types include central processing units, graphics processing units, display controller IC, disk drive IC, memory devices like NAND Flash EEPROM, NOR 76181-75
• Flash EEPROM AND Flash EEPROM, DiNOR Flash EEPROM, Serial Flash EEPROM, DRAM, SRAM, ROM, EPROM, FRAM, MRAM, PCRAM etc.
• Figure 1 is a system block diagram of serial-connected memory system having a controller programmable duty cycle correction scheme
• Figure 2 is a block diagram of a memory device having controller programmable duty cycle correction scheme
• Figure 3 is a block diagram of a programmable delay line for duty cycle correction
• Figure 4 is a timing diagram of controller programmable duty cycle correction
• Figure 5 is a flowchart of a method of duty cycle correction
• Figure 6 is a timing diagram for a write duty cycle register command
• Figure 7 is a block diagram of a programmable delay line for output delay adjustment
• Figure 8 is a timing diagram of controller programmable output delay adjustment
• Figure 9 is a flowchart of a method of performing output delay adjustment.
• Figure 10 is a timing diagram for a write output delay register command.
• Some of the memory system configurations referred to in the background employ a shared bus topology for the system clock distribution, which is referenced to as a 'common clock system' or 'multi-drop clocking system'. If the system clock is applied to too many memory devices in parallel and the clock signal travels too far from the clock source, typically a memory controller, the maximum operating clock frequency may be limited by the total loading of the clock signal and the distance that the clock travels in the memory system's physical layout.
• Some of the memory system configurations referred to in the background use a point-to-point serial-connected clocking architecture featuring a DLL or PLL in each memory device in order to synchronize two clock signals in the memory device, one being an input clock received from a preceding device or controller and the other being an output clock transmitted to the next device.
• a DLL or PLL in each memory device can cause a significant amount of power consumption.
• various chip-to-chip clock delays (caused by various interconnect loadings and different wire bonding loadings such as multi-chip stacking or package) accumulate through a large number of serial-connected devices and may be unacceptable for system operation.
• FIG. 1 shown is a system block diagram of a serial- connected memory system generally indicated at 101 employing a controller programmable duty cycle correction scheme.
• the memory system 101 includes a memory controller 10 as a master device connected to a first memory device 100-1.
• Memory device 100-1 is the first of a series of slave devices including devices 100-1 through 100-8 that are connected in a ring configuration, with the 76181-75
• a highly multiplexed unidirectional point-to-point bus architecture is provided to transfer information such as commands, addresses and data from the memory controller 10 to the memory devices 100-1 to 100-8.
• This bus architecture includes a link 90 from the memory controller 10 to the first memory device 100-1 , and a respective link between each pair of adjacent memory devices, these including links 90-1 through 90-7, and a link 90-8 between the last memory device 100-8 and the memory controller 10.
• each link includes a set of signals output by a preceding device (the memory controller 10 or a memory device) for receipt by a succeeding device.
• Each link includes a set of output ports of a preceding device, a set of input ports of a succeeding device, and a set of physical interconnections between the output ports and the input ports.
• the output ports will be given the same name as the signals they output and the input ports will be given the same name as the signals they receive.
• the signals (and output ports) of a preceding device are referred to as CSO (Command Strobe Output), DSO (Data Strobe Output), Qn (Data Output), CKO/CKO# (differential clock output signals).
• the corresponding signals (and input ports) of a succeeding device are referred to as CSI (Command Strobe Input), DSI (Data Strobe Input), Dn (Data Input), CKI/CKI# (differential clock input signals).
• CSI Common Strobe Input
• DSI Data Strobe Input
• Dn Data Input
• CKI/CKI# differential clock input signals
• CE# chip enable
• RST# reset
• the physical interconnections include differential clock buses S111 , S111 -1 to S111 -8 for differential clock signals, S112, S112-1 to S112-8 for command strobe, S113, S113-1 to S113-8 for data strobe, S114, S114-1 to S114-8 for data.
• the width of the link may be programmed through a link configuration register to utilize 1 , 2, 4, or 8 of a device package's available data input and output pins. This feature allows these memory devices to operate in a ring configuration together with devices that have smaller or larger maximum link widths provided they are all programmed to use the same link width. See for example 'Switching Method of Link and Bit Width' (WO 2008/070978), hereby incorporated by reference in its entirety.
• CKI/CKI# are input clocks.
• a Command/Address Packet on the Dn port delineated by CSI is latched on the rising edges of CKI or the falling edges of CKI#.
• a Write Data Packet on Dn delineated by DSI is latched on the rising edges of CKl or the falling edges of CKI#.
• CKO/CKO# are output clocks which are delayed version of CKI/CKI#.
• CSO, DSO and Qn signals are referenced to the rising edges of CKO or to the falling edges of CKO#; for example, a Read Data Packet on Qn delineated by DSO is referenced at the rising edges of CKO or the falling edges of CKO#.
• Command Strobe Output is an echo signal of CSI. It echoes CSI transitions with a latency tlOL that in a particular implementation is a two clock cycle latency referenced to the rising edges of CKO or to the falling edges of CKO#. Two clock cycle latency is an implementation detail; more generally it could be any number of clock cycles appropriate for a given design.
• DSI Data Strobe Input
• Qn buffer When Data Strobe Input (DSI) is HIGH while the memory device is in 'Read- Mode', it enables the read data output path and Qn buffer (not shown). If DSI is LOW, the Qn buffer holds the previous data accessed. If DSI is HIGH while the memory device is in 'Write-Mode', it enables a Dn buffer and receives Write Data Packet on the rising edges of CKI or falling edges of CKI#. 76181-75
• Data Strobe Output is an echo signal of DSI. It echoes DSI transitions with latency tIOL referenced to the rising edges of CKO or to the falling edges of CKO#. As indicated above, tIOL is two clock cycles in a particular implementation.
• QO is the only valid signal and transmits one byte of a packet in eight clock cycles.
• QO & Q1 are valid signals and transmit one byte of a packet in four clock cycles.
• QO, Q1 , Q2 & Q3 are valid signals and transmit one byte of a packet in two clock cycles.
• QO, Q1 , Q2, Q3, Q4, Q5, Q6 & Q7 are all valid signals and transmit one byte of a packet in one clock cycle.
• serial-connected in this context is referring to the serial arrangement of memory devices, one after the other and not to the nature of the link between each pair of adjacent devices which may be serial or parallel in nature.
• the memory controller 10 contains a phase detector 11 , a duty detector 13 and a command generator 12. In some embodiments, the memory controller 10 only includes the phase detector 11 in which case only output delay adjustment is performed. In some embodiments, the memory controller 10 includes only the duty detector 13 in which case only duty cycle correction is performed. In some embodiments, both the phase detector 11 and the duty detector 13 are included in which case both output delay adjustment and duty cycle correction may be performed. This last case is assumed in the detailed description which follows.
• the phase detector 11 and the duty detector 13 are connected to the command generator 12 through signal buses S11 and S12 respectively.
• the command generator 12 has an output signal bus S13 connected to CSO and Qn ports through which it can output commands.
• the memory controller 10 drives the differential clock buses, S111 , from its port CKO/CKO#, and all eight memory devices 100-1 ⁇ 100-8 receive the differential clock buses through their own clock ports, CKI/CKI#, from the previous device's CKO/CKO# ports in a series flow-through manner.
• the memory controller 10 drives three different buses, S112, S113 and S114 through its ports, CSO, DSO and Qn, respectively.
• the second memory device 100-2 receives the three buses, S112-1 , S113-1 and S114-1, through its input ports, CSI, DSI and Dn, respectively. This approach applies to all of the eight memory 76181-75
• the duty detector 13 monitors a duty ratio of CKI/CKI# which is the clock input after it has been passed between all of the devices 100-1 to 100-8 in the ring. If the duty detector 13 detects a duty error from CKI/CKI#, namely a deviation in the duty cycle from a desired duty cycle, it asserts through signal bus S12 either a 'Duty_Add' to indicate the duty cycle is shorter than the desired duty cycle and should be lengthened or 'Duty_Sub' to indicate the duty cycle is longer than the desired duty cycle and should be shortened. In response, the command generator 12 generates an appropriate "Write Duty Cycle Register" command packet.
• the phase detector 11 monitors the phase of CKI/CKI#. If the phase detector 11 detects a phase error (PE) between CKI/CKI# and CKO/CKO#, it asserts a 'PE' signal through the signal bus S11. In response, the command generator 12 generates an appropriate "Write Output Delay Register" command packet.
• PE phase error
• the command generator 12 issues the appropriate command packet according to the received signals on S11 and S12, and sends the command information through signal bus, S13, and CSO, Qn ports.
• the device includes a memory core 150, command/address packet logic 130, data packet logic 140, and duty cycle correction logic 120.
• Memory core 150 may be a single bank of memory cell arrays or it could be multiple banks of memory cell arrays, depending on design variations.
• Data packet logic 140 processes and stores all necessary data transferring information.
• Command/address packet logic 130 processes all command instructions and/or 76181-75
• the device 100 includes clock input receiver 102D for CKI/CKI# which may for example be a differential type input buffer to handle the differential clock inputs, CKI & CKI#.
• the clock input receiver 102D translates the external interface levels of CKI/CKI# signals to the internal logic levels of an internal clock signal 'cki_i'.
• the internal clock signal, cki_i may be used in other internal logic blocks for various operations.
• the duty cycle correction logic 120 takes the internal clock signal, cki_i, and produces a duty cycle corrected clock signal clk_dcc.
• the duty cycle corrected clock signal, 'clk_dcc' is delayed by a controller programmable delay line, PDL2, 105D, and its delayed signal, 'clk_dcc_d', is finally driven to the input port of an output driver block 108D, which outputs the external clock output signals, CKO/CKO#.
• the device 100 includes command strobe receiver 102A which generates a buffered signal 'csi_i' from a CSI input signal.
• the buffered signal, csij is connected to the D port of a D-type flip-flop 103A.
• the flip-flop 103A is driven by the clock signal, 'cki_i', and latches the status of the 'csij' signal at every rising edge of 'cki_i'.
• the latched signal 'csijat' is provided to the command/address packet logic 130, and also is provided to the D port of another flip-flop 103E, whose clock input port is driven by the duty corrected clock signal, clk_dcc.
• the flip-flop 103E's output signal, 'cso_i', is delayed by a controller programmable delay line, PDL2, 105A, and its delayed signal, 'cso_d', is finally driven to the input port of an output driver block 108A, which then outputs the external signal, CSO.
• the device 100 includes data strobe input receiver 102C which generates a buffered signal 'dsi i' from a DSI input signal.
• the buffered signal, dsij is connected to D port of D-type flip-flop 103C.
• the flip-flop 103C is driven by the clock signal, 'cki_i', and latches the status of the 'dsij' signal at every rising edge of 'cki_i'.
• the latched signal 'dsijat' is provided to the command/address packet logic 130 and data packet logic 140, and also is provided to D port of another flip-flop 103G, whose clock input port is driven by the duty corrected clock signal, clk_dcc.
• the flip-flop 103G's output signal, 'dso_i' is delayed by a controller programmable delay line, PDL2, 105C, and its delayed signal, 'dso_d', is finally driven to the input port of an output driver block 108C, which outputs the external signal, DSO.
• PDL2, 105C controller programmable delay line
• 'dso_d' delayed signal
• DSO external signal
• the device 100 includes a data receiver, 102B, for receiving an external signal Dn.
• the number of receivers 102B can be one or more than one according to the bit width of Dn ports. For example, if Dn ports are designated in DO, D1 , ⁇ D7, for an 8 bit wide data input/output implementation, the receiver 102B will be repeated eight times.
• the output of the receiver 102B, 'dn_i' is provided to the D port of a D-type flip-flop 103B.
• the flip-flop 103B is driven by the clock signal, 'cki_i', and latches the status of the 'dn_i' signal at every rising edge of 'cki_i'.
• the latched signal 'dnjat' is provided to the command/address packet logic 130 and also is provided to data packet logic 140.
• the latched signal, 'dnjat' is also provided to one input port of a multiplexer 104.
• the other port of the multiplexer 104 is driven by a signal, 'core_data' from the data packet logic 140.
• the output of the multiplexer 104 is connected to the D input port of a flip- flop 103F, whose clock input port is driven by the duty corrected clock signal, clk_dcc, and latches the status of the output of the multiplexer 104 at every rising 76181-75
• the internal signal dn_i includes both command content (as delineated by the command strobe input) and data input (as delineated by the data strobe input) when present.
• Each device has a device address, in some embodiments stored in a device address register 131.
• Each command includes a Device Address portion that contains the device address of one of the memory devices to which the command is addressed. There may also be a broadcast address that requires the command to be processed by all devices.
• the memory device 100 processes each command by examining the Device Address portion. If the Device Address information in the received command/address packet matches the memory device 100's own stored device address, the command/address packet logic 130 processes the command, and also issues an "id_match" signal to signify that the command is for that memory device.
• the id_match signal is used to steer the data flow path of the multiplexer 104. If “id_match” is in a HIGH logic state (more generally in a “match state” however that is defined) as a result of device address matching process, the multiplexer 104 selects "core_data" to be outputted, so that the data from the memory core 150 can be transferred to the flip-flop 103F.
• the multiplexer 104 selects "dnjat" to be outputted, so that the data received from the data input Dn can be transferred to the flip-flop 103F to be echoed at the output Qn.
• the multiplexer 104 allows for the selection between a) bypassing data received from the data input Dn by selecting the dnjat input of the multiplexer 104, and b) outputting the core_data by selecting the core_data input of the 76181-75
• the signal 'core_data' is usually transferred from the memory core 150 to the data packet logic 140, for example as part of a 'PAGE READ' operation upon request from the memory controller 10. Then after the 'PAGE READ' operation is done, the memory controller 10 can request a 'BURST READ' operation to the memory device with a command addressed to that memory device. In that case, the memory device processes the 'BURST READ' command and the corresponding address information including Device Address portion. If the Device Address information in the received command/address packet matches the memory device 100's own stored device address, the command/address packet logic 130 issues "id_match" signal in order to steer the data flow path of the multiplexer 104.
• the multiplexer 104 selects "core_data" to be outputted, so that the data previously transferred from the memory core 150 to the data packet logic 140 can be transferred to the flip-flop 103F.
• the core_data input of the multiplexer 104 is still selected even though there is no data to output.
• the core_data signal may be a static signal in such a case. This results in the data input Dn not being echoed to the next device. This can have the effect of reducing power consumption in the subsequent devices by eliminating the need for them to process data associated with commands that are not addressed to them. This is described in further detail in US Application serial no. 12/018,272 filed 01/23/2008 entitled "Semiconductor Device and Method for Reducing Power Consumption in a System Having Interconnected Devices".
• a delayed version of the data input signal Dn is produced as one component of a data output signal (Qn). Some of the time the data output signal is the delayed version of the data input signal. For the implementation described, this will be the case when there is content on the data 76181-75
• the data output signal comprises a delayed version of a signal produced locally to the memory device, after applying the delay to the signal produced locally to the memory device in accordance with the command.
• the signal produced locally to the memory device is the so-called core_data output from the data packet logic 140 but other scenarios are possible.
• the command/address packet logic 130 has a DCR (duty cycle correction register) 132 that produces an output DCR ⁇ 0:3> to the duty cycle correction circuit 120 to control the amount of duty cycle correction performed as detailed below and has an ODR (output delay register) 134 that produces an output ODR ⁇ 0:1 > to the packet delay lines 105A, 105B, 105C, 105D to control the amount of output delay applied as detailed below.
• DCR duty cycle correction register
• ODR output delay register
• a "Write Duty Cycle Correction Register” command assumes an implementation, as described herein, in which an amount of delay to be applied in performing duty cycle correction is controlled by writing a value to a duty cycle correction register. More generally, any command, referred to herein as a duty cycle correction command, may be employed that has the effect of causing a device to set how duty cycle correction is to be performed. Thus, the described "Write Duty Cycle Correction Register” command is to be considered a specific example of a duty cycle correction command.
• any command referred to herein as an output delay adjustment command, may be employed that has the effect of causing a device to set the amount of delay to be applied.
• the described "Write Output Delay Register" command is to be considered a specific example of an output delay adjustment command.
• the duty cycle correction circuit 120 includes a clock divider 123, and a controller programmable delay line 121 that includes a '4-to-16 Decoder' block and 'Programmable Delay Line (PDL1 )'. Respective outputs clk_ref, clk_del of the clock divider 123 and the controller programmable delay line 121 are input to an XOR gate 122 the output of which is the duty cycle corrected clock clk_dcc.
• the clock divider 123 derives an output signal 'clk_ref which has a frequency that is one half that of the input 'cki_i' signal.
• Clock divider circuits are well known in the art.
• the clock divider 123 includes a D-type flip-flop 103D that is driven by the internal clock signal, cki_i, through its clock input port.
• the output port Q of the D-type Flip-Flop 103D is connected to the input port D though inverter logic 124 in order to obtain a half frequency output signal.
• the controller programmable delay line 121 produces an output signal, elk del, which is a delayed version of clk_ref.
• the amount of delay is determined by the '4-to-16 Decoder' logic block's select signals, which are controlled by DCR ⁇ 0:3> signal information received from command/address packet logic 130.
• the XOR logic gate 122 receives the two half clock signals, clk_ref and elk del, and outputs a duty cycle adjusted full clock signal, clk_dcc.
• Figure 3 is a block diagram of an example implementation of a programmable delay line 121 for duty cycle correction that may, for example, be used in the duty cycle correction circuit 120 of Figure 2.
• the unit delay block is composed of two NAND logic gates 1211 and 1212 and one inverter logic gate 1213.
• the first NAND logic gate 1211 receives the clk_ref input at its first input, and receives an output from a 4-to-16 decoder 1210 at its second input.
• the output of the first NAND logic gate 1211 is input to a first input of the second logic NAND gate 1212.
• the second input of the second logic NAND gate 1212 is connected to Vdd.
• the 4-to-16 Decoder block 1210 has a 4-bits wide input bus, DCR ⁇ 0:3> as its input.
• the decoder block 1210 decodes the input and outputs a 16-bit wide bus, SEI_ ⁇ 15:0>, with one line of the bus connected to each of the 16 unit delay blocks.
• the unit delay logic shown is an example of a known circuit technique has been used to to produce a register controlled delay-locked-loop. Other unit delay logics can alternatively be employed.
• the '4-to-16 Decoder' logic 1210 produces the 16 SEL ⁇ 15:0> output such that only one of the 16 select signals is in a HIGH logic state and all the other 15 select signals are in LOW logic states. Therefore, only one unit delay block is selected to transfer the 'clk_ref signal through the unit delay blocks that are to the right of the selected unit delay block.
• the control input DCR ⁇ 0:3> is used to select which of the unit delay blocks will process the clk_ref input. The minimum delay is selected by selecting the right most unit delay block 76181-75
• the unit delay amount of the illustrated unit delay block is around 100ps ⁇ 150ps. However, in some embodiments, a finer unit delay circuit block is employed for much higher operating frequency with finer delay tuning capability.
• the unit delay time is denoted as “tUD” in Figure 3 and the total delay time for the whole programmable delay line is denoted as “tPDL1" which is 16 times "tUD”.
• a default setting for the power-on initialization is that having a logic HIGH state on the SEI_ ⁇ 7> bit, as it is in the middle position of the delay line.
• the default settings can be different, and it may be recommended to have minimum delay setting in order to be ready for operating at the maximum frequency.
• FIG 4 is an example of a timing diagram of the controller programmable duty cycle correction procedure, where all of the signals are as shown in Figure 3 except CKI which is the raw input clock signal that is to be duty corrected.
• the timing diagram is showing one extremely distorted clock input signal, CKI at the top, for the sake of example only.
• the half clock signal, clk_ref is derived from the 'clock divider' block 123 of Figure 2 and its rising and falling edges are aligned with two rising edges of CKI.
• the clock signal, clk_dcc would have a distorted duty ratio, such as 45% on, 55% off, for example, in the absence of any change to the DCR ⁇ 0:3> values which are shown to initially be set to "01 11 b".
• the duty cycle of the clock signal, clk_dcc is corrected to be 50% on and 50% off as the result of a shift in the selection of the controller programmable delay line 121 from SEL (7) being enabled to SEL (8) being enabled. 76181-75
• the contents of the DCR 132 are used to control the amount of delay introduced by the controller programmable delay line 121 in the duty cycle correction circuit 120, thereby controlling the duty cycle correction.
• the contents of the DCR 132 can be written with a 'Write Duty Cycle Register' command.
• FIG. 5 is a flow chart for the duty cycle correction procedure from the perspective of the controller.
• the method begins at block 5-1 with power on of the devices. At this point, all of the delay lines are initialized and device addresses for all devices are assigned.
• the memory controller 10 monitors the duty ratio of CKI/CKI# using the duty detector 13. If there is a duty cycle error, yes path block 5-3, then in block 5-4 the duty detector 13 asserts the "Duty_Add" or the "Duty_Sub” signal S12. After this, the command generator 12 issues the 'Write Duty Cycle Register' command with "DCR+1 " or "DCR-1" values.
• step 5-6 If there is still a duty cycle error, yes path block 5-6, then the method continues back at step 5-4 with the further adjustment to the duty cycle register. If there is no longer a duty cycle error, no path block 5-6, then duty cycle correction is completed at 5-7. Similarly, if no duty cycle error was detected in block 5-3, then at that point the method also is completed at 5-7.
• Table 1 below is an example command packet definition for writing to the Duty Cycle Register (DCR).
• a broadcast address is provided, for example FFh. If DA is set to the broadcast address, it means that the command is a broadcasting command, so that every memory device is expected to execute the command. Otherwise, only a specific memory device that is matching the DA will execute the command.
• a 'Read Duty Cycle Register' command is also implemented in order to give more flexibility to the controller 10. 76181-75
• FIG. 6 is an example of a timing diagram of a 'Write Duty Cycle Register' command packet sequence based on SDR (Single Data Rate) operation.
• SDR Single Data Rate
• this means that the 'Write Duty Cycle Register' command is a broadcasting command, so that every memory device is expected to execute the command.
• the broadcasting command is used for Duty Cycle Correction operation.
• the circuit disclosed also allows for the more flexible 76181-75
• tWDCR Write Duty Cycle Register Latency
• tWDCR value is set as 4 clock cycles as shown in Figure 6.
• the described programmable delay lines 105A, 105B, 105C, 105D are provided to allow programmably delaying the output signals CSO, Qn, DSO and CKO/CKO# in order to allow phase correction.
• Figure 1 also shows output delay register signal buses ODR ⁇ 0:1 > connected to a 2-to-4 Decoder logic block 106.
• the 2-to-4 Decoder logic 106 outputs four select signal buses, SEL2 ⁇ 0:3>. Those SEL2 ⁇ 0:3> select signals are all connected to the four controller programmable delay lines 105A, 105B, 105C and 105D.
• Figure 7 is showing an exemplary circuit block implementation for the output delay adjustment.
• programmable delay lines 105A, 105B, 105C and 105D are composed of four unit delay elements that are the same as those used in Figure 3. This means that the range of delay adjustment for the output is only 4/16 that of the range of delay of adjustment of the duty 76181-75
• Each programmable delay line 105A, 105B, 105C, 105D receives a respective signal cso_i, q_i, dso_i and clk_dcc, as the input of the delay line and produces a respective delayed output cso_d, q_d, dso_d and clk_dcc_d.
• signals will be increased correspondingly, for example to be 8 in number, and the number of delay line blocks for q_i and q_d, will be increased correspondingly, for example to be 8 in number.
• the '2-to-4 Decoder' logic 106 produces the SEL2 ⁇ 0:3> output such that only one of the 4 select signals is in a HIGH logic state and all the other 3 select signals are to be logic LOW states. Only the selected unit delay block transfers the respective input signal through the remaining unit delay blocks to the right of the selected unit delay block.
• the control input ODR ⁇ 0:1 > is used to select which of the unit delay blocks will process the respective inputs. The minimum delay is selected by selecting the right most unit delay block UNIT_0 in which case each output signal is the respective input signal delayed by one unit delay block, whereas the maximum delay is selected by selecting the left most unit delay block UNIT_3 in which case each output signal is the respective input signal delayed by four delay unit blocks.
• the '2-to-4 decoder' logic 106 with four unit delay blocks is implemented in this example circuit design. However more generally, any required number of delay units and the corresponding decoder logic may be used.
• a default delay setting may be used during the power-on initialization period. In this example, the default selection might for example be set to SEL2 ⁇ 0>, and the memory device will have the least amount of delay for each output path after power-on or hard reset in some other design variations.
• the use of 4 unit delay blocks is implementation specific. For example, more generally, an N-to-M decoder might 76181-75
• the contents of the ODR 134 are used to control the amount of delay introduced by the delay lines 105A,105B,105C,105D thereby controlling the amount of output delay adjustment.
• the contents of the ODR 134 can be written with a 'Write Output Delay Register' command.
• the controller 10 When the phase detector 11 in the memory controller 10 detects an unacceptable phase difference between its CKI/CKI# and CKO/CKO# signals, the controller 10 will issue one "Write Output Delay Register" command packet with one added unit delay amount to allow the very first memory device 100-1 of Figure 1. After enough clock cycles for a first memory device, for example for the tWODR (Write Output Delay Register latency) and total tIOL latencies described below with respect to Figure 10, if there is still unacceptable phase difference, the controller 10 can issue another 'Write Output Delay Register" command packet to a second memory device, for example the second memory device 100- 2 of Figure 1. This sequence of operations can be continued until the memory 76181-75
• controller 10 gets the acceptable phase difference. After the last memory device is instructed to adjust its output delays, then the memory controller 10 points to the very first memory device with one more added unit delay value within the command packet, and continues for the rest of the memory devices until the phase difference reaches an acceptable range.
• the above procedure is shown in the flowchart of Figure 9.
• the method begins at block 9-1 with power on. At this point, all the delay lines and device addresses are initialized.
• the memory controller 10 monitors the phase error between CK!/CK!# and CKO/CKO# using the phase detector 11. If there is a phase error, yes path 9-3, then the phase detector 11 asserts the "PE" signal S11 in block 9-4. After that, the command generator 12 issues a 'write output delay register' command with "ODR+1 " value to each memory device from the first to the last, one at a time while monitoring the phase error.
• block 9-6 if there is still a phase error, yes path, then the method continues back at block 9-4. If there is no phase error, no path block 9-6, then the phase correction is completed at block 9-7. Similarly, if no phase error was detected in block 9-3, then the method ends, phase correction having been completed at block 9-7.
• Table 3 is an example command packet definition for the Write Output Delay Register command.
• a broadcast address is provided, for example FFh. If DA is set to the broadcast address, it means that the command is a broadcasting command, so that every memory device is expected to execute the command. Otherwise, only a specific memory device that is matching with DA will execute the command.
• a 'Read Output Delay Register' is implemented in order to give more flexibility to the controller 10. For example, this can be used by the controller to read the values from all of the memory devices and then rearrange the settings among the devices appropriately, if necessary. 76181-75
• FIG 10 is an example of a timing diagram of a 'Write Output Delay Register' command packet sequence based on SDR (Single Data Rate) operation.
• SDR Single Data Rate
• tWODR Write Output Delay Register Latency
• 76181 -75 76181 -75
• 37 tWODR value is set as 4 clock cycles as shown in Figure 10. After tWODR (for example, at T8), the memory controller 10 can issue any other command packets to the memory device.
• an embodiment of the application provides for methods and circuits performing output delay adjustment embodiments in which, a delayed version of at least one input signal is produced, the at least one input signal includes at least the clock signal.
• generating a delayed version of an input signal for output involves conditionally generating a delayed version of the input signal for output. That is to say, some of the signals may be conditionally conveyed between adjacent devices.
• a specific example is detailed below in which the input data signal of a memory device is conveyed to the next memory device some of the time.
• the embodiments described above have assumed the use of programmable delay lines that are composed of identical unit delay blocks.
• the programmable delay lines are divided into two or more sections, such as "Coarse” and “Fine” delay lines to allow further programmability of the delay adjustment for duty cycle correction and/or output delay adjustment.
• the output delay lines are located after the last Flip-Flop that is located near an output for each signal. In some embodiments, the output delay line is located before the last flip-flop.
• the devices that are connected in the serial-connected manner are assumed to be substantially identical. In some embodiments, these are substantially identical memory devices. In other embodiments, different 76181-75
• differential clock signals are employed. More generally, single ended or differential clock signals may be used. Similarly, any other input/output signals can be single ended or differential.
• a single MCP (multi-chip package) is provided that includes the plurality of memory devices and a controller, operable as described.
• the methods and apparatus described herein have assumed a serial-connected architecture featuring a controller and a set of memory devices connected in a ring.
• the memory devices are slave devices
• the memory controller is a master device.
• the methods and apparatus described herein can be applied to any kind of semiconductor integrated circuit system having any kind of semiconductor integrated circuit devices that are configured as slave devices in the serial-connected configuration with a common interface between adjacent devices, with a device that is configured to act as a master device that controls the duty cycle correction and/or phase correction performed by the slave devices .
• Examples of integrated circuit types include central processing units, graphics processing units, display controller IC, disk drive IC, memory devices like NAND Flash EEPROM, NOR Flash EEPROM, AND Flash EEPROM, DiNOR Flash EEPROM, Serial Flash EEPROM, DRAM, SRAM, ROM, EPROM, FRAM, MRAM, PCRAM etc.

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• 2009
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