EP2329496A4 - Serial-connected memory system with output delay adjustment - Google Patents

Serial-connected memory system with output delay adjustment

Info

Publication number
EP2329496A4
EP2329496A4 EP09817125A EP09817125A EP2329496A4 EP 2329496 A4 EP2329496 A4 EP 2329496A4 EP 09817125 A EP09817125 A EP 09817125A EP 09817125 A EP09817125 A EP 09817125A EP 2329496 A4 EP2329496 A4 EP 2329496A4
Authority
EP
European Patent Office
Prior art keywords
serial
memory system
delay adjustment
output delay
connected memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09817125A
Other languages
German (de)
French (fr)
Other versions
EP2329496A1 (en
Inventor
Hakjune Oh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Novachips Canada Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/241,832 external-priority patent/US8181056B2/en
Priority claimed from US12/241,960 external-priority patent/US8161313B2/en
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of EP2329496A1 publication Critical patent/EP2329496A1/en
Publication of EP2329496A4 publication Critical patent/EP2329496A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
EP09817125A 2008-09-30 2009-09-17 Serial-connected memory system with output delay adjustment Withdrawn EP2329496A4 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/241,832 US8181056B2 (en) 2008-09-30 2008-09-30 Serial-connected memory system with output delay adjustment
US12/241,960 US8161313B2 (en) 2008-09-30 2008-09-30 Serial-connected memory system with duty cycle correction
PCT/CA2009/001271 WO2010037205A1 (en) 2008-09-30 2009-09-17 Serial-connected memory system with output delay adjustment

Publications (2)

Publication Number Publication Date
EP2329496A1 EP2329496A1 (en) 2011-06-08
EP2329496A4 true EP2329496A4 (en) 2012-06-13

Family

ID=42072981

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09817125A Withdrawn EP2329496A4 (en) 2008-09-30 2009-09-17 Serial-connected memory system with output delay adjustment

Country Status (6)

Country Link
EP (1) EP2329496A4 (en)
JP (2) JP2012504263A (en)
KR (1) KR20110081958A (en)
CN (1) CN102165529B (en)
TW (1) TW201027556A (en)
WO (1) WO2010037205A1 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8665665B2 (en) * 2011-03-30 2014-03-04 Mediatek Inc. Apparatus and method to adjust clock duty cycle of memory
US9257164B2 (en) * 2013-03-14 2016-02-09 Altera Corporation Circuits and methods for DQS autogating
JP6232313B2 (en) * 2014-02-25 2017-11-15 新日本無線株式会社 Synchronous serial communication method and slave device
KR20180033368A (en) * 2016-09-23 2018-04-03 삼성전자주식회사 Electronic device comprising storage devices transmitting reference clock via cascade coupling structure
KR20190009534A (en) * 2017-07-19 2019-01-29 에스케이하이닉스 주식회사 Semiconductor device
KR101999125B1 (en) * 2017-11-24 2019-07-11 파밀넷 주식회사 Output signal automatic controller for RS-422 and RS-485 serial communication
KR102679157B1 (en) 2018-10-30 2024-06-27 삼성전자주식회사 System on chip performing training of duty cycle of write clock using mode register write command, operating method of system on chip, electronic device including system on chip
JP2020155841A (en) * 2019-03-18 2020-09-24 キオクシア株式会社 Semiconductor integrated circuit and transmitting device
US10937468B2 (en) * 2019-07-03 2021-03-02 Micron Technology, Inc. Memory with configurable die powerup delay
CN112332881B (en) * 2020-10-19 2022-04-26 深圳市信锐网科技术有限公司 Enabling circuit and communication device
CN112698683A (en) * 2020-12-28 2021-04-23 深圳市合信自动化技术有限公司 Method and device for solving error of transmission delay data by configurable bus and PLC

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040148482A1 (en) * 2003-01-13 2004-07-29 Grundy Kevin P. Memory chain
US20050058233A1 (en) * 2003-09-12 2005-03-17 Huy Nguyen System and method for adaptive duty cycle optimization
US6950956B2 (en) * 1999-10-19 2005-09-27 Rambus Inc. Integrated circuit with timing adjustment mechanism and method
US20060136618A1 (en) * 2004-07-30 2006-06-22 International Business Machines Corporation System, method and storage medium for a multi-mode memory buffer device
WO2007106766A2 (en) * 2006-03-16 2007-09-20 Rambus Inc. Signaling system with adaptive timing calibration
US20080028123A1 (en) * 2006-07-26 2008-01-31 Gerald Keith Bartley Computer System Having Daisy Chained Memory Chips

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000148674A (en) * 1998-11-09 2000-05-30 Sharp Corp Method for transmitting serial data
US6839393B1 (en) * 1999-07-14 2005-01-04 Rambus Inc. Apparatus and method for controlling a master/slave system via master device synchronization
JP2003140962A (en) * 2001-10-30 2003-05-16 Mitsubishi Electric Corp Signal transmit/receive system
JP3843002B2 (en) * 2001-11-26 2006-11-08 株式会社ルネサステクノロジ Variable delay circuit and system LSI using the variable delay circuit
US7533218B2 (en) * 2003-11-17 2009-05-12 Sun Microsystems, Inc. Memory system topology
US6980042B2 (en) * 2004-04-05 2005-12-27 Micron Technology, Inc. Delay line synchronizer apparatus and method
US7352219B2 (en) * 2005-08-30 2008-04-01 Infineon Technologies Ag Duty cycle corrector
TWI543185B (en) 2005-09-30 2016-07-21 考文森智財管理公司 Memory with output control and system thereof
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US7747833B2 (en) 2005-09-30 2010-06-29 Mosaid Technologies Incorporated Independent link and bank selection
US20070076502A1 (en) 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
US8069328B2 (en) 2006-03-28 2011-11-29 Mosaid Technologies Incorporated Daisy chain cascade configuration recognition technique
CA2659828A1 (en) * 2006-08-22 2008-02-28 Mosaid Technologies Incorporated Scalable memory system
JP4952177B2 (en) * 2006-10-02 2012-06-13 富士通株式会社 Storage device
US8140803B2 (en) * 2007-01-09 2012-03-20 International Business Machines Corporation Structure for reducing latency associated with read operations in a memory system
CN101617371B (en) * 2007-02-16 2014-03-26 莫塞德技术公司 Non-volatile semiconductor memory having multiple external power supplies

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6950956B2 (en) * 1999-10-19 2005-09-27 Rambus Inc. Integrated circuit with timing adjustment mechanism and method
US20040148482A1 (en) * 2003-01-13 2004-07-29 Grundy Kevin P. Memory chain
US20050058233A1 (en) * 2003-09-12 2005-03-17 Huy Nguyen System and method for adaptive duty cycle optimization
US20060136618A1 (en) * 2004-07-30 2006-06-22 International Business Machines Corporation System, method and storage medium for a multi-mode memory buffer device
WO2007106766A2 (en) * 2006-03-16 2007-09-20 Rambus Inc. Signaling system with adaptive timing calibration
US20080028123A1 (en) * 2006-07-26 2008-01-31 Gerald Keith Bartley Computer System Having Daisy Chained Memory Chips

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2010037205A1 *

Also Published As

Publication number Publication date
WO2010037205A1 (en) 2010-04-08
CN102165529B (en) 2014-12-31
TW201027556A (en) 2010-07-16
JP2013008386A (en) 2013-01-10
EP2329496A1 (en) 2011-06-08
KR20110081958A (en) 2011-07-15
JP2012504263A (en) 2012-02-16
JP5599852B2 (en) 2014-10-01
CN102165529A (en) 2011-08-24

Similar Documents

Publication Publication Date Title
EP2329496A4 (en) Serial-connected memory system with output delay adjustment
EP2115594A4 (en) Memory system
EP2250564A4 (en) Memory system
EP2250567A4 (en) Memory system
EP2269139A4 (en) Memory system
EP2250565A4 (en) Memory system
EP2248024A4 (en) Memory system
EP2248027A4 (en) Memory system
EP2260391A4 (en) Memory system
EP2260390A4 (en) Memory system
EP2250566A4 (en) Memory system
EP2248022A4 (en) Memory system
EP2248026A4 (en) Memory system
EP2225649A4 (en) Memory system
EP2294579A4 (en) Nand memory
EP2271988A4 (en) Memory system
ZA201202376B (en) Photovoltaic system with managed output
EP2118756A4 (en) Memory system
EP2389631A4 (en) Solid state memory formatting
EP2111583A4 (en) Memory system
ZA201100306B (en) Photovoltaic system
EP2260389A4 (en) Memory system
EP2480973A4 (en) Memory system
EP2382666A4 (en) Reflector channel
EP2179362A4 (en) Memory system

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20110208

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

AX Request for extension of the european patent

Extension state: AL BA RS

DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20120516

RIC1 Information provided on ipc code assigned before grant

Ipc: G11C 7/22 20060101AFI20120510BHEP

Ipc: G11C 16/32 20060101ALI20120510BHEP

Ipc: G06F 13/42 20060101ALI20120510BHEP

17Q First examination report despatched

Effective date: 20130917

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: NOVACHIPS CANADA INC.

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20150512