CN112698683A - Method and device for solving error of transmission delay data by configurable bus and PLC - Google Patents
Method and device for solving error of transmission delay data by configurable bus and PLC Download PDFInfo
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- CN112698683A CN112698683A CN202011586795.0A CN202011586795A CN112698683A CN 112698683 A CN112698683 A CN 112698683A CN 202011586795 A CN202011586795 A CN 202011586795A CN 112698683 A CN112698683 A CN 112698683A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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Abstract
The invention provides a device capable of configuring a bus to solve errors of transmission delay data, which comprises a synchronous clock generator and a bus synchronous clock duty ratio regulator; the synchronous clock generator generates clock signals, and in combination with configuration parameters, the clock signals are subjected to time reduction on the preset bus clock period, so that clock step lengths with the same number as the configuration parameters are formed in the bus clock period of the clock signals; the bus synchronous clock duty ratio regulator receives a clock signal output by the synchronous clock generator, and updates the clock step length in the bus clock period of the received clock signal after deleting the clock step length in combination with the step length adjustment parameter to obtain a clock signal after updating the bus clock period and load the clock signal on a bus; and the step length adjusting parameter is smaller than the configuration parameter. By implementing the invention, on the premise of not reducing the bus frequency, the module with longer transmission delay can be found by adjusting the duty ratio of the bus frequency, thereby solving the problem of data error caused by the transmission delay.
Description
Technical Field
The invention relates to the technical field of PLC (programmable logic controller), in particular to a method and a device for solving error of transmission delay data by a configurable bus and a PLC.
Background
At present, after some modules in the PLC are hung on a CPU, the modules can not be found or can be found from time to time, and the hidden danger that a system is unstable and key parameters are lost in practical application is easily caused. However, the main reason for the above hidden trouble is that the bus needs to be level-shifted when passing through each cascade module, and each level-shifted device has a transmission delay of a certain time. For example, the transmission delay range of the market universal bus driver 4AHCT125 is between 6ns and 10ns, and once the 8-stage cascade is performed, the total transmission delay reaches about 125ns and exceeds the half-wave time of the bus (for example, the bus frequency is 4 MHZ).
In order to solve the above hidden trouble, the most direct method is to reduce the bus frequency, but the system processing speed is slow. Therefore, it is necessary to provide a method for solving error of transmission delay data on PLC, which can avoid the problem of data error caused by transmission delay and ensure correct data transmission without reducing bus frequency.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide a method, an apparatus, and a PLC capable of configuring a bus to solve a transmission delay data error, which can ensure that a module with a longer transmission delay is found by adjusting a duty ratio of a bus frequency on the premise of not reducing the bus frequency, thereby solving a data error problem caused by a transmission delay and ensuring a correct data transmission.
In order to solve the above technical problem, an embodiment of the present invention provides a device for solving error of transmission delay data for a configurable bus, which is used for the bus and includes a synchronous clock generator and a bus synchronous clock duty ratio adjuster that are connected to each other; wherein the content of the first and second substances,
the synchronous clock generator is used for generating a clock signal and further multiplying a preset bus clock period of the clock signal by combining configuration parameters input by a user, so that the clock signal forms a clock step length with the same number as the configuration parameters in each preset bus clock period;
the bus synchronous clock duty ratio regulator is connected with the bus and used for receiving the clock signal output by the synchronous clock generator and further combining a step length adjustment parameter input by a user to delete and update the clock step length formed in each preset bus clock period on the received clock signal so as to obtain the clock signal with the updated bus clock period and load the clock signal on the bus; wherein the step size adjustment parameter is smaller than the configuration parameter.
Wherein the preset bus clock period is 250 ns.
Wherein the step size adjustment parameter is less than or equal to the configuration parameter/2.
When the configuration parameter is 10 and the step size adjustment parameter is 6, the duty ratio of the clock signal after the bus clock cycle is updated is 4: 6; or
When the configuration parameter is 10 and the step length adjustment parameter is 7, the duty ratio of the clock signal after the bus clock period is updated is 3: 7.
the embodiment of the invention also provides a method for solving errors of transmission delay data by using the configurable bus, which is realized on the device for solving errors of transmission delay data by using the configurable bus, and the method comprises the following steps:
the synchronous clock generator generates a clock signal, and further combines a configuration parameter input by a user to perform time-scaling on a bus clock period preset by the clock signal, so that the clock signal forms a clock step length with the same number as the configuration parameter in each preset bus clock period;
the bus synchronous clock duty ratio regulator receives the clock signal output by the synchronous clock generator, and further combines a step length adjustment parameter input by a user to delete and update the clock step length formed in each preset bus clock period on the received clock signal, so as to obtain the clock signal with the updated bus clock period and load the clock signal on a bus; wherein the step size adjustment parameter is smaller than the configuration parameter.
Wherein the preset bus clock period is 250 ns.
Wherein the step size adjustment parameter is less than or equal to the configuration parameter/2.
When the configuration parameter is 10 and the step size adjustment parameter is 6, the duty ratio of the clock signal after the bus clock cycle is updated is 4: 6; or
When the configuration parameter is 10 and the step length adjustment parameter is 7, the duty ratio of the clock signal after the bus clock period is updated is 3: 7.
the embodiment of the invention also provides a PLC, which comprises the device for solving the error of the transmission delay data by the configurable bus.
The embodiment of the invention has the following beneficial effects:
1. the invention generates clock signals based on a synchronous clock generator, doubles the bus clock period of the clock signals to form a plurality of clock step lengths, and further utilizes a bus synchronous clock duty ratio regulator to delete and update the clock step length in each bus clock period of the clock signals, so that the clock signals loaded on the bus finally have different duty ratios, thereby ensuring that a module with longer transmission delay is found on the premise of not reducing the bus frequency, solving the problem of data errors caused by the transmission delay and ensuring the correct data transmission;
2. the invention not only can solve the communication problem caused by time delay of the single main clock transmission bus, but also can reduce the compatibility problem of different products in different batches, and reduce the market repair rate, thereby achieving the purposes of reducing the maintenance amount and improving the product quality and reliability.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is within the scope of the present invention for those skilled in the art to obtain other drawings based on the drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of an apparatus for resolving errors in data transmission delay through a configurable bus according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating clock signal variations in an apparatus for resolving errors in data transmission delay according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for solving errors in transmission delay data by using a configurable bus according to a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
As shown in fig. 1, in a first embodiment of the present invention, an apparatus for solving error of transmission delay data for a configurable bus is provided, which is used on a bus (not shown), and includes a synchronous clock generator 1 and a bus synchronous clock duty cycle adjuster 2 that are connected to each other; wherein the content of the first and second substances,
the synchronous clock generator 1 is used for generating a clock signal, and further multiplying a preset bus clock period (such as 250ns, namely, the frequency is 4MHz) of the clock signal by combining a configuration parameter n (input is realized by presetting a register) input by a user, so that the clock signal forms clock step lengths with the same number as the configuration parameter in each preset bus clock period;
the bus synchronous clock duty ratio regulator 2 is connected with the bus, and is used for receiving the clock signal output by the synchronous clock generator 1, and further combining a step length adjustment parameter m input by a user (input is realized by presetting a register), deleting and updating the clock step length formed in each preset bus clock period on the received clock signal, obtaining the clock signal after updating the bus clock period, and loading the clock signal on the bus; and the step length adjusting parameter is smaller than the configuration parameter.
It should be noted that the step size adjustment parameter m is preferably less than or equal to the configuration parameter n/2.
It can be understood that, the synchronous clock generator 1 generates a clock signal (i.e. a bus signal), and multiplies a bus clock cycle of the clock signal to form a plurality of clock steps (as shown in a in fig. 2), and further uses the bus synchronous clock duty ratio adjuster 2 to delete and update the clock steps in each bus clock cycle of the clock signal (as shown in b in fig. 2), so that the clock signal finally loaded on the bus has different duty ratios, thereby ensuring that a module with longer transmission delay is found on the premise of not reducing the bus frequency, solving the problem of data error caused by transmission delay, and ensuring correct data transmission.
In the first embodiment of the present invention, the duty ratio of the bus frequency may be configured according to the specific maximum delay of the cascade module. For example, if the configuration parameter is 10 and the step size adjustment parameter is 6, the duty ratio of the clock signal after the bus clock cycle update is 4: 6, i.e. the duty cycle of the adjusted bus frequency is 4: 6; for another example, when the configuration parameter is 10 and the step size adjustment parameter is 7, the duty ratio of the clock signal after the bus clock cycle update is 3: 7, i.e. the duty cycle of the adjusted bus frequency is 3: 7.
it should be noted that the bus synchronous clock duty ratio adjuster 2 is not limited to input the step size adjustment parameter, but may also input the duty ratio, and automatically calculates the step size adjustment parameter through a built-in algorithm to delete the clock step size of the clock signal, which is not described herein again.
As shown in fig. 2, a method for solving errors in transmission delay data by using a configurable bus according to a second embodiment of the present invention is implemented on a device (as shown in fig. 1) for solving errors in transmission delay data by using a configurable bus according to a first embodiment of the present invention, and the method includes the following steps:
step S1, the synchronous clock generator generates clock signals, and further combines the configuration parameters input by the user to perform the time reduction on the preset bus clock period of the clock signals, so that the clock signals form the clock step length with the same number as the configuration parameters in each preset bus clock period;
step S2, the bus synchronous clock duty ratio adjuster receives the clock signal output by the synchronous clock generator, and further, in combination with the step size adjustment parameter input by the user, deletes and updates the clock step size formed in each preset bus clock period on the received clock signal, so as to obtain the updated clock signal of the bus clock period and load the updated clock signal on the bus; wherein the step size adjustment parameter is smaller than the configuration parameter.
Wherein the preset bus clock period is 250 ns.
Wherein the step size adjustment parameter is less than or equal to the configuration parameter/2.
When the configuration parameter is 10 and the step size adjustment parameter is 6, the duty ratio of the clock signal after the bus clock cycle is updated is 4: 6; or
When the configuration parameter is 10 and the step length adjustment parameter is 7, the duty ratio of the clock signal after the bus clock period is updated is 3: 7.
corresponding to the device capable of configuring the bus to solve the error of the transmission delay data in the first embodiment of the invention, a third embodiment of the invention also provides a PLC which comprises the device capable of configuring the bus to solve the error of the transmission delay data in the first embodiment of the invention. Since the device for solving error of transmission delay data by using the configurable bus in the third embodiment of the present invention has the same structure and connection relationship as the device for solving error of transmission delay data by using the configurable bus in the first embodiment of the present invention, please refer to the foregoing contents specifically, and thus, the details are not repeated herein.
The embodiment of the invention has the following beneficial effects:
1. the invention generates clock signals based on a synchronous clock generator, doubles the bus clock period of the clock signals to form a plurality of clock step lengths, and further utilizes a bus synchronous clock duty ratio regulator to delete and update the clock step length in each bus clock period of the clock signals, so that the clock signals loaded on the bus finally have different duty ratios, thereby ensuring that a module with longer transmission delay is found on the premise of not reducing the bus frequency, solving the problem of data errors caused by the transmission delay and ensuring the correct data transmission;
2. the invention not only can solve the communication problem caused by time delay of the single main clock transmission bus, but also can reduce the compatibility problem of different products in different batches, and reduce the market repair rate, thereby achieving the purposes of reducing the maintenance amount and improving the product quality and reliability.
It will be understood by those skilled in the art that all or part of the steps in the method for implementing the above embodiments may be implemented by relevant hardware instructed by a program, and the program may be stored in a computer-readable storage medium, such as ROM/RAM, magnetic disk, optical disk, etc.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.
Claims (9)
1. A device for solving error of transmission delay data by a configurable bus is used on the bus and is characterized by comprising a synchronous clock generator and a bus synchronous clock duty ratio adjuster which are connected with each other; wherein the content of the first and second substances,
the synchronous clock generator is used for generating a clock signal and further multiplying a preset bus clock period of the clock signal by combining configuration parameters input by a user, so that the clock signal forms a clock step length with the same number as the configuration parameters in each preset bus clock period;
the bus synchronous clock duty ratio regulator is connected with the bus and used for receiving the clock signal output by the synchronous clock generator and further combining a step length adjustment parameter input by a user to delete and update the clock step length formed in each preset bus clock period on the received clock signal so as to obtain the clock signal with the updated bus clock period and load the clock signal on the bus; wherein the step size adjustment parameter is smaller than the configuration parameter.
2. The apparatus of claim 1, wherein the predetermined bus clock period is 250 ns.
3. The apparatus for resolving errors in transmission delay data according to claim 2, wherein said step size adjustment parameter is less than or equal to said configuration parameter/2.
4. The apparatus for resolving error in data transmission delay according to claim 3, wherein when the configuration parameter is 10 and the step size adjustment parameter is 6, the duty cycle of the clock signal after updating the bus clock period is 4: 6; or
When the configuration parameter is 10 and the step length adjustment parameter is 7, the duty ratio of the clock signal after the bus clock period is updated is 3: 7.
5. a method for a configurable bus to resolve errors in transmission-delayed data, the method being implemented on an apparatus for resolving errors in transmission-delayed data according to claim 4, the method comprising the steps of:
the synchronous clock generator generates a clock signal, and further combines a configuration parameter input by a user to perform time-scaling on a bus clock period preset by the clock signal, so that the clock signal forms a clock step length with the same number as the configuration parameter in each preset bus clock period;
the bus synchronous clock duty ratio regulator receives the clock signal output by the synchronous clock generator, and further combines a step length adjustment parameter input by a user to delete and update the clock step length formed in each preset bus clock period on the received clock signal, so as to obtain the clock signal with the updated bus clock period and load the clock signal on a bus; wherein the step size adjustment parameter is smaller than the configuration parameter.
6. The method of claim 5, wherein the predetermined bus clock period is 250 ns.
7. The method of claim 6, wherein the step size adjustment parameter is less than or equal to the configuration parameter/2.
8. The method as claimed in claim 7, wherein when the configuration parameter is 10 and the step size adjustment parameter is 6, the duty cycle of the updated clock signal of the bus clock cycle is 4: 6; or
When the configuration parameter is 10 and the step length adjustment parameter is 7, the duty ratio of the clock signal after the bus clock period is updated is 3: 7.
9. a PLC comprising means for resolving transmission delay data errors in a configurable bus as claimed in any one of claims 1 to 4.
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| CN202011586795.0A CN112698683A (en) | 2020-12-28 | 2020-12-28 | Method and device for solving error of transmission delay data by configurable bus and PLC |
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| CN202011586795.0A CN112698683A (en) | 2020-12-28 | 2020-12-28 | Method and device for solving error of transmission delay data by configurable bus and PLC |
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