CN208890769U - Clock duty cycle calibration circuit - Google Patents
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- CN208890769U CN208890769U CN201821876357.6U CN201821876357U CN208890769U CN 208890769 U CN208890769 U CN 208890769U CN 201821876357 U CN201821876357 U CN 201821876357U CN 208890769 U CN208890769 U CN 208890769U
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Abstract
The utility model embodiment provides a kind of clock duty cycle calibration circuit, and circuit includes the delay chain group at least three concatenated time delay chains, and delay chain group clock signal based on the received passes through each time delay chain and generates the time delayed signal for adjusting clock signal duty cycle；The delay precision of the time delayed signal exported positioned at the time delay chain of head end can make the duty ratio of input clock signal roughly close to 50%, and the delay precision of the time delayed signal exported positioned at the time delay chain of tail end can make the duty ratio of input clock signal reach 50% ± 1%；Clock generator be used for receive input clock signal and positioned at tail end time delay chain export time delayed signal and issue output clock signal；Duty cycle detector is used to detect the duty ratio of output clock signal, and the length of each time delay chain is adjusted according to duty ratio.The utility model embodiment can be realized in any clock signal frequency, the duty ratio of the adjusting clock signal of fast accurate to 50% ± 1% by the way that multiple time delay chains for adjusting different accuracies are arranged.
Description
Technical field
The utility model relates to semiconductor integrated circuit fields, and in particular to a kind of clock duty cycle calibration circuit.
Background technique
This part intends to provides background or context for the utility model embodiment stated in claims.Herein
Description recognizes it is the prior art not because not being included in this section.
In DRAM (Dynamic Random Access Memory, dynamic random access memory) field, DDR
(Double Data Rate SDRAM, Double Data Rate synchronous DRAM) technology in clock lower edges due to all can
Data are read in triggering, therefore the clock of good duty ratio is also even more important in the field DRAM.Due to the work of DDR4 memory chip
Clock signal frequency can change in a bigger range, for example, may within the scope of 666.5MHz~1600MHz,
Under test pattern, in some instances it may even be possible to 666.5MHz can be lower than.No matter the height of DRAM clock signal frequency, internal DRAM requires
The duty ratio of its internal clock signal is adjusted in time as quickly as possible to guarantee that entire DRAM reads the correctness of data.
However existing clock duty cycle calibration circuit due to the delay precision that time delay chain designs all be it is fixed, be directed to not
With frequency clock signal, in duty ratio precision 50% ± 1% required by SPEC (Specification, specification) 1%
The size of a clock cycle, being can be as operating clock signals frequency be in variation.Therefore, frequency range span is larger
When, whole duty ratio calibration cycle will be very long.
Utility model content
The utility model embodiment provides a kind of clock duty cycle calibration circuit, at least to alleviate or solve the prior art
In one or more technical problems.
In a first aspect, the utility model embodiment provides a kind of clock duty cycle calibration circuit, comprising:
Be delayed chain group, including at least three concatenated time delay chains, and delay chain group input clock signal based on the received passes through
Each time delay chain generates the time delayed signal for adjusting input clock signal duty ratio；Wherein, the delay exported positioned at the time delay chain of head end
The delay precision of signal can make the duty ratio of input clock signal roughly close to 50%, prolong positioned at what the time delay chain of tail end exported
When signal delay precision the duty ratio of input clock signal can be made to reach 50% ± 1%；
Clock generator, for receiving the time delayed signal of input clock signal and the time delay chain output positioned at tail end, concurrently
Clock signal is exported out；
Duty cycle detector is connect with clock generator, for detecting the duty ratio of output clock signal, and according to output
The duty ratio of clock signal adjusts the length of each time delay chain.
In some embodiments, further includes:
Decoder, for being connected to register, it is current to obtain clock signal according to the encoded radio in register for decoder
Clock signal frequency；
Control unit is connected between decoder and delay chain group, for adjusting the initial length for being located at the time delay chain of head end
Degree is to roughly close to the extension position of current clock signal frequency half；It is also used to adjust the initial length of remaining time delay chain
To intermediate length position.
In some embodiments, control unit is also connect with duty cycle detector, for defeated according to duty cycle detector
Signal out adjusts the length of each time delay chain.
In some embodiments, control unit includes multiple counters, the quantity and the quantity phase of time delay chain of counter
It is corresponding；Counter is used to count the current length of corresponding time delay chain, and the signal exported according to duty cycle detector, adjusting pair
The length for the time delay chain answered.
In some embodiments, the signal of duty cycle detector output includes increasing signal and reduction signal；
When counter, which receives, increases signal, increase the length of time delay chain；When counter, which receives, reduces signal, subtract
The length of few time delay chain.
In some embodiments, clock signal frequency includes 1600MHz to the frequency between 666.5MHz.
In some embodiments, delay chain group includes three concatenated time delay chains, and being used for positioned at the time delay chain of head end will
Time delayed signal is adjusted to the first precision, is located in the middle time delay chain for the time delayed signal for being adjusted to the first precision to be adjusted to the
Two precision are used to the time delayed signal for being adjusted to the second precision being adjusted to third precision positioned at the time delay chain of tail end.
It in some embodiments, is 200ps-3200ps positioned at the adjustable range of the time delay chain of head end, the first precision is
187.5ps；The adjustable range for being located in the middle time delay chain is 0ps-200ps, and the second precision is 12.5ps；Positioned at the delay of tail end
The adjustable range of chain is 0ps-16ps, and third precision is 1ps.
Second aspect, the utility model embodiment provide a kind of semiconductor memory, including such as above-mentioned first aspect
Clock duty cycle calibration circuit.
The utility model embodiment by adopting the above technical scheme, has the advantages that by adjusting multiple and different precision
The delay length of time delay chain can be realized in any clock signal frequency, be capable of fast accurate to input clock signal
Duty ratio calibrated, guarantee final output clock signal duty ratio 50% ± 1%.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the utility model is into one
Aspect, embodiment and the feature of step, which will be, to be readily apparent that.
Detailed description of the invention
In the accompanying drawings, unless specified otherwise herein, otherwise indicate the same or similar through the identical appended drawing reference of multiple attached drawings
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to originally practical
Novel disclosed some embodiments, and should not be taken as the limitation to the scope of the utility model.
Fig. 1 is the schematic diagram of the clock duty cycle calibration circuit of the utility model embodiment.
Fig. 2 is the flow chart of the calibration method of the clock duty cycle calibration circuit of the utility model embodiment.
Fig. 3 is the flow chart of the calibration method of the clock duty cycle calibration circuit of another embodiment of the utility model.
Appended drawing reference:
100- delay chain group；101- time delay chain；200- clock generator；
300- duty cycle detector；400- decoder；500- register；
600- control unit；601- counter.
Specific embodiment
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present utility model, it can be modified by various different modes described real
Apply example.Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
The utility model embodiment provides a kind of clock duty cycle calibration circuit, as shown in Figure 1, comprising:
Be delayed chain group 100, including at least three concatenated time delay chains 101.The chain group 100 that is delayed is raw by each time delay chain 101
At the time delayed signal for adjusting clock signal duty cycle.Wherein, input clock signal is received positioned at the time delay chain of head end 101, be located at
The time delay chain 101 of tail end exports final delay clock signal.Latter time delay chain 101 is used for the delay exported to previous time delay chain
The precision of signal is adjusted again.Wherein, the degree of regulation of each time delay chain 101 is different.Prolong positioned at what the time delay chain 101 of head end exported
When signal delay precision the duty ratio of input clock signal can be made roughly close to 50%, the time delay chain 101 positioned at tail end is defeated
The delay precision of time delayed signal out can make the duty ratio of input clock signal reach 50% ± 1%.Due to memory chip
During the work time, clock signal frequency can be switched.For example, DDR chip can be in the operation at frequencies of 1600MHz, it can also be with
In the operation at frequencies of 666.5MHz.Therefore, if memory chip switch operating clock signal frequency, need according to it is current when
The operating clock signals frequency of clock signal fast and accurately adjusts the length of each time delay chain 101, to guarantee that circuit can normal work
Make.
Clock generator 200 is connect with the time delay chain 101 for being located at tail end, and clock generator 200 is located at tail end for receiving
Time delay chain 101 time delayed signal and input clock signal that export, and issue output clock signal.
Duty cycle detector 300 is arranged between control unit 600 and clock generator 200, duty cycle detector 300
For adjusting the length of each time delay chain 101 according to output clock signal.Duty cycle detector 300 adjusts the length of each time delay chain 101
The mode of degree includes increasing, reduce or keeping three kinds of modes.The length of time delay chain 101 increases when increasing operation, when reducing operation
The length of time delay chain 101 is reduced.
In one embodiment, the precision of each time delay chain 101 is successively improved by head end to tail end, to realize by multiple
Concatenated time delay chain 101 is solved when the clock signal frequency of chip makes any variation, still be able to fast accurate to clock
Duty ratio calibrated, guarantee the duty ratio of the clock signal of final output 50% ± 1%.
In one embodiment, as shown in Figure 1, further includes:
Decoder 400, for connecting register 500, to obtain clock signal and work as according to the encoded radio in register 500
Preceding clock signal frequency.Register 500 needs to be arranged under different clock signal frequencies the different tCCD_L (low-frequency cycles
Number) and tCWL (high frequency period number), tCCD_L and tCWL parameter (encoded radio) key reaction memory chip work at present
Clock signal frequency, and all operating clock signals frequencies of memory chip, i.e. frequency range under broadband can be included.
Control unit 600 is connected between decoder 400 and delay chain group 100.Control unit 600 is located at for adjusting
The initial length of the time delay chain 101 of head end is to roughly close to the extension position of current clock signal frequency half.It is also used to adjust
The initial length of remaining whole time delay chain 101 is to intermediate length position the half position of chain length (be delayed).Prolong to realize
When 101 length of chain quick adjusting, after obtaining clock signal frequency (T), first by the initial length of time delay chain 101 be adjusted to
At position corresponding to clock signal frequency half (T/2) or at the half position of 101 length of time delay chain, so as to more
Add the signal quickly exported according to duty cycle detector 300, so that time delay chain 101 is rapidly completed in a relatively short period of time and prolong
When 101 length of chain adjusting.
In an application example, since the clock signal frequency of DDR chip reaches as high as 1600MHz, but may also
Lower than 666.5MHz, when clock signal frequency is lower, the time delay chain precision for being directed to high-frequency circuit needs to make tune appropriate
It is whole.When clock signal frequency becomes less than 666.5MHz from 1600MHz, when being typically in test pattern, clock at this time is believed
Number frequency may only have 200MHz.As example, the delay time of delay unit in 6.25ps, the clock cycle be then from
625ps becomes greater than or is equal to 5ns, and the period elongated delay unit number meaned in a time delay chain will be from original 50
At least 400 are increased to, the time delay chain at this moment accessing circuit obviously has more than originally very much.Therefore, clock signal is known in advance
The approximate range of frequency can choose time delay chain precision appropriate and play a very important role for improving calibration speed.
Preferably, register 500 can be using MRS (Mode Register Setting, mode register setting) electricity
Road.The setting of tCCD_L mainly reflects clock low speed frequency (f≤1200MHz) range in MRS circuit, and CWL in MRS circuit
Main reflection clock fast frequency (800MHz~1600MHz) of setting, accesses after the coding circuit output signal of the two is integrated
The clock duty cycle calibration circuit of the utility model embodiment, so that being in the frequency for arbitrarily meeting SPEC requirement in chip clock
When duty-ratio calibrating circuit still be able to work normally to guaranteeing the clock signal duty cycle of final output 50% ± 1%.
In DRAM, the data of tCCD_L then can directly reflect the low-frequency range (as shown in table 1) of chip operation, this just makes
Information can be obtained in time at frequency conversion initial stage to be adjusted to the capacitor in delay chain length and duty detection circuit by obtaining
To guarantee testing result duty ratio 50% ± 1%.The data of CWL (CAS Write Latency) then can directly reflect core
The high-frequency range of piece work, this allows for that information can be obtained in time at frequency conversion initial stage to examine delay chain length and duty ratio
Capacitor in slowdown monitoring circuit is adjusted to guarantee testing result duty ratio 50% ± 1%.It can be mentioned by tCCD_L and CWL
The probable ranges of preceding precognition clock signal frequency variation, as long as adjusting delay chain length appropriate for different frequency ranges
The prover time of clock duty cycle can be reduced.
Table 1
Such as: there is setting different clocks signal frequency in DDR4JEDEC SPEC in Mode Register Setting, MR6
The periodicity for needing to be arranged to conform to spec requirement of tCCD_L under rate (for example, f≤1200MHz).Therefore from different tCCD_
The clock signal frequency range of available current chip in the setting coding of L, so as to accelerate the calibration matter of DCC in terms of two
Amount: 1, to time delay chain 101 the initial regulated value that is comparatively close to T/2 be set, it is possible to reduce prover time.2, duty is determined
Than lowest charge amount needed for identifying clock duty cycle in detector 300 so that it is determined that accessing the variable capacitance number in circuit,
To improve the accuracy of duty detection circuit.
In one embodiment, control unit 600 is also connect with duty cycle detector 300, for being detected according to duty ratio
The signal that device 300 exports, adjusts the length of each time delay chain 101.
In one embodiment, control unit 600 includes multiple counters 601, the quantity and time delay chain of counter 601
101 quantity is corresponding.Counter 601 is used to count the current length of corresponding time delay chain 101, and according to duty cycle detector
The signal of 300 outputs, adjusts the length of corresponding time delay chain 101.
In a specific embodiment, the signal that duty cycle detector 300 exports includes increasing signal and reduction signal；
When counter 601, which receives, increases signal, increase the length of corresponding time delay chain 101.When the reception of counter 601 subtracts
When few signal, the length of corresponding time delay chain 101 is reduced.
In a transformable embodiment, the tool of counter 601 there are two input terminal, respectively with duty cycle detector 300
Two output ends connection, be respectively used to receive increase signal and reduce signal, thus realize by two input terminals to delay
The length of chain 101 is adjusted.Each counter 601 is also connect with decoder 400, the deposit for being obtained according to decoder 400
The encoded radio of device 500 adjusts the initial length of corresponding time delay chain 101.
In one embodiment, clock signal frequency includes 1600MHz to the frequency between 666.5MHz.
In one embodiment, delay chain group 100 includes three concatenated time delay chains 101, positioned at the time delay chain 101 of head end
For time delayed signal to be adjusted to the first precision, it is located in the middle time delay chain 101 and believes for the delay of the first precision will to be adjusted to
Number it is adjusted to the second precision, is used to the time delayed signal for being adjusted to the second precision being adjusted to third positioned at the time delay chain 101 of tail end
Precision.Preferably, the first precision is at least 187.5ps, and the second precision is at least 12.5ps, and third precision is at least 1ps.
In an application example, duty cycle detector 300 receives the output clock signal of clock generator 200, if inspection
The precision for surveying the duty ratio of output clock signal is unsatisfactory for 50% ± 1%, then controls each adjustment of counter 601 delay chain group 100
In each time delay chain 101 length, and then adjust time delayed signal, and by time delayed signal again to the duty ratio of input clock signal
It is adjusted, until when the precision of the duty ratio of the detection output clock signal of duty cycle detector 300 meets 50% ± 1%, it will
The output clock signal is as the clock signal output after final calibration.
In an application example, the first time delay chain 101 is low frequency time delay chain, the corresponding delay length tune of low frequency time delay chain
Adjusting range is 200-3200ps, degree of regulation 187.5ps.Second time delay chain 101 is intermediate frequency time delay chain, and intermediate frequency time delay chain is corresponding
Delay length adjustable range be 0-200ps, degree of regulation 12.5ps.Third time delay chain 101 is high frequency time delay chain, and high frequency prolongs
When the corresponding delay length adjustable range of chain be 0-16ps, degree of regulation 1ps.Wherein, the first time delay chain 101 is accounted for for adjusting
Sky to generally proximal to 50%, second time delay chain 101 and third time delay chain 101 than being used for further by duty cycle adjustment to 50%
± 1%.According to the difference of degree of regulation, can also lead to only by the second time delay chain 101 by duty cycle adjustment to 50% ± 1%
The second time delay chain 101 and third time delay chain 101 are crossed jointly for duty cycle adjustment to 50% ± 1%.
According to the difference of the clock signal frequency of memory chip, degree of regulation selection as shown in Table 2 can be used and use
Time delay chain 101 number.
Table 2
For example, when the clock signal frequency that decoder 400 is read from register 500 is 5000ps, clock signal frequency
The 50% of rate is 2500ps, the adjustable range of corresponding first time delay chain 101, therefore passes through the first time delay chain 101 for duty ratio tune
Section is to roughly close to 50% or so.The 1% of clock signal frequency is 50ps, the adjustable range of corresponding second time delay chain 101, therefore
By the second time delay chain 101 further by duty cycle adjustment to 50% ± 1%, to realize using 101 He of the first time delay chain
The precision of time delayed signal is adjusted to 12.5ps by the second time delay chain 101.The duty cycle adjustment of clock signal after will calibrating is extremely
50% ± 1%, the precision of duty cycle detector is adjusted to 12.5ps.
When the clock signal frequency that decoder 400 is read from register 500 is 625ps, clock signal frequency
50% is 312.5ps, the adjustable range of corresponding first time delay chain 101, thus by the first time delay chain 101 by duty cycle adjustment extremely
Roughly close to 50%.The 1% of clock signal frequency is 6.25ps, the adjusting of corresponding second time delay chain 101 and third time delay chain 101
Range, therefore by the second time delay chain 101 and third time delay chain 101 further by duty cycle adjustment to 50% ± 1%, thus
It realizes and is jointly adjusted the precision of time delayed signal using the first time delay chain 101, the second time delay chain 101 and third time delay chain 101
To 1ps.The precision of duty cycle detector is adjusted to by the duty cycle adjustment of the clock signal after will calibrating to 50% ± 1%
1ps。
In an application example, 6bit data relevant to clock signal frequency are sent to decoder by register 500
400, decoder 400 obtains the 4bit data for being sent respectively to each counter 601 after handling data, for each counter
The 601 corresponding time delay chains 101 of adjustment, time delay chain 101 adjust the delay chain length of itself according to the 4bit data of acquisition.
The utility model embodiment provides a kind of calibration method of clock duty cycle calibration circuit, as shown in Fig. 2, packet
It includes:
S100: input clock signal is input in delay chain group, is generated by each concatenated time delay chain in delay chain group
Adjust the time delayed signal of clock signal duty cycle；Wherein, the delay precision energy of the time delayed signal exported positioned at the time delay chain of head end
Enough make the duty ratio of input clock signal roughly close to 50%, the delay precision of the time delayed signal exported positioned at the time delay chain of tail end
The duty ratio of input clock signal can be made to reach 50% ± 1%.
S200: the time delayed signal exported by clock signal and positioned at the time delay chain of tail end is input in clock generator, and
Output clock signal is issued by clock generator.
S300: by output clock signal input into duty cycle detector, so that device is surveyed according to output clock in duty ratio school
The duty ratio of signal adjusts the length of each time delay chain.
In one embodiment, as shown in Figure 3, further includes:
S400: the encoded radio in the register that decoder is read is obtained, to obtain current clock signal frequency.
S500: according to current clock signal frequency, control unit adjustment is located at the initial length of the time delay chain of head end extremely
Roughly close to the extension position of current clock signal frequency half；It is also used to adjust the initial length of remaining time delay chain into
Between extension position.
In one embodiment, as shown in Figure 3, further includes:
S600: the signal exported according to duty cycle detector, each counter of control unit adjust corresponding time delay chain
Length simultaneously records.
The utility model embodiment provides a kind of semiconductor memory, the clock duty cycle including such as above-mentioned first aspect
Calibrate circuit.
The utility model embodiment has the advantage that 1, as the clock signal frequency of chip changes, real-time clock synchronization
Important time delay chain carries out corresponding adjusting and guarantees final clock so as to improve calibration result in clock duty detection circuit
Signal quality is intact to meet DRAM SPEC design requirement.2, the reliability and accuracy of clock duty cycle detection circuit are improved.
3, it by the multiple time delay chains for adjusting different accuracies of setting, can be realized in any clock signal frequency, it can be quickly smart
Quasi- calibrates the duty ratio of clock, guarantees the duty ratio of the clock signal of final output 50% ± 1%.
Above description is only a specific implementation of the present invention, but the protection scope of the utility model is not limited to
In this, anyone skilled in the art within the technical scope disclosed by the utility model, it is each can to readily occur in it
Kind change or replacement, these should be covered within the scope of the utility model.Therefore, the protection scope of the utility model
It should be based on the protection scope of the described claims.
In the description of the present invention, it should be understood that term " center ", " longitudinal direction ", " transverse direction ", " length ", " width
Degree ", " thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside",
The orientation or positional relationship of the instructions such as " clockwise ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " is based on the figure
Orientation or positional relationship is merely for convenience of describing the present invention and simplifying the description, rather than the dress of indication or suggestion meaning
It sets or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as to the utility model
Limitation.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more of the features.The meaning of " plurality " is two or two in the description of the present invention,
More than, unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " Gu
It is fixed " etc. terms shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be
Mechanical connection, is also possible to be electrically connected, can also be communication；It can be directly connected, the indirect phase of intermediary can also be passed through
Even, the connection inside two elements or the interaction relationship of two elements be can be.For those of ordinary skill in the art
For, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.
In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or it
"lower" may include that the first and second features directly contact, and also may include that the first and second features are not direct contacts but lead to
Cross the other characterisation contact between them.Moreover, fisrt feature includes above the second feature " above ", " above " and " above "
One feature is right above second feature and oblique upper, or is merely representative of first feature horizontal height higher than second feature.First is special
Sign includes fisrt feature right above second feature and oblique upper under the second feature " below ", " below " and " below ", or only
Indicate that first feature horizontal height is less than second feature.
Above disclosure provides many different embodiments or example is used to realize the different structure of the utility model.
In order to simplify the disclosure of the utility model, above the component of specific examples and setting are described.Certainly, they are only
Example, and purpose does not lie in limitation the utility model.In addition, the utility model can in different examples repeat reference numerals
And/or reference letter, this repetition are for purposes of simplicity and clarity, itself not indicate discussed various embodiments
And/or the relationship between setting.In addition, the example of various specific techniques and material that the utility model provides, but this
Field those of ordinary skill can be appreciated that the application of other techniques and/or the use of other materials.
Claims (9)
1. a kind of clock duty cycle calibration circuit characterized by comprising
Be delayed chain group, including at least three concatenated time delay chains, and delay chain group input clock signal based on the received passes through
Each time delay chain generates the time delayed signal for adjusting the input clock signal duty ratio；Wherein, positioned at the delay of head end
The delay precision of the time delayed signal of chain output can make the duty ratio of the input clock signal roughly close to 50%, be located at
The delay precision of the time delayed signal of the time delay chain output of tail end can be such that the duty ratio of the input clock signal reaches
To 50% ± 1%；
Clock generator, for receiving the delay letter of the input clock signal and the time delay chain output positioned at tail end
Number, and issue output clock signal；
Duty cycle detector is connect with the clock generator, for detect it is described output clock signal duty ratio, and according to
The duty ratio of the output clock signal adjusts the length of each time delay chain.
2. clock duty cycle calibration circuit as described in claim 1, which is characterized in that further include:
Decoder, for being connected to register, the decoder obtains the clock letter according to the encoded radio in the register
Number current clock signal frequency；
Control unit is connected between the decoder and the delay chain group, for adjusting the time delay chain for being located at head end
Initial length to roughly close to the extension position of the current clock signal frequency half；It is also used to adjust described in remaining
The initial length of time delay chain is to intermediate length position.
3. clock duty cycle calibration circuit as claimed in claim 2, which is characterized in that described control unit also with the duty
It is connected than detector, the signal for being exported according to the duty cycle detector adjusts the length of each time delay chain.
4. clock duty cycle calibration circuit as claimed in claim 3, which is characterized in that described control unit includes multiple countings
Device, the quantity of the counter are corresponding with the quantity of the time delay chain；The counter is for counting corresponding time delay chain
Current length, and the signal exported according to the duty cycle detector, adjust the length of the corresponding time delay chain.
5. clock duty cycle calibration circuit as claimed in claim 4, which is characterized in that the letter of the duty cycle detector output
Number include increase signal and reduce signal；
When the counter receives the increase signal, increase the length of the time delay chain；When the counter receives
When the reduction signal, the length of the time delay chain is reduced.
6. clock duty cycle calibration circuit as claimed in claim 2, which is characterized in that the clock signal frequency includes
1600MHz is to the frequency between 666.5MHz.
7. clock duty cycle calibration circuit as described in claim 1, which is characterized in that the delay chain group includes three series connection
The time delay chain, be used to the time delayed signal being adjusted to the first precision positioned at the time delay chain of head end, be located in the middle
The time delay chain is used to the time delayed signal for being adjusted to first precision being adjusted to the second precision, described in tail end
Time delay chain is used to the time delayed signal for being adjusted to second precision being adjusted to third precision.
8. clock duty cycle calibration circuit as claimed in claim 7, which is characterized in that positioned at the tune of the time delay chain of head end
Adjusting range is 200ps-3200ps, and first precision is 187.5ps；The adjustable range for being located in the middle the time delay chain is
0ps-200ps, second precision are 12.5ps；Adjustable range positioned at the time delay chain of tail end is 0ps-16ps, described
Third precision is 1ps.
9. a kind of semiconductor memory, which is characterized in that including the clock as described in any one of claim 1 to 8 claim
Duty-ratio calibrating circuit.
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| CN201821876357.6U CN208890769U (en) | 2018-11-14 | 2018-11-14 | Clock duty cycle calibration circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111193498A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Clock duty ratio calibration circuit and calibration method |
| CN112698683A (en) * | 2020-12-28 | 2021-04-23 | 深圳市合信自动化技术有限公司 | Method and device for solving error of transmission delay data by configurable bus and PLC |
-
2018
- 2018-11-14 CN CN201821876357.6U patent/CN208890769U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111193498A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Clock duty ratio calibration circuit and calibration method |
| CN112698683A (en) * | 2020-12-28 | 2021-04-23 | 深圳市合信自动化技术有限公司 | Method and device for solving error of transmission delay data by configurable bus and PLC |
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