KR20110081958A - 출력 지연 조정을 가진 직렬 연결 메모리 시스템 - Google Patents

출력 지연 조정을 가진 직렬 연결 메모리 시스템 Download PDF

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Publication number
KR20110081958A
KR20110081958A KR1020117006956A KR20117006956A KR20110081958A KR 20110081958 A KR20110081958 A KR 20110081958A KR 1020117006956 A KR1020117006956 A KR 1020117006956A KR 20117006956 A KR20117006956 A KR 20117006956A KR 20110081958 A KR20110081958 A KR 20110081958A
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KR
South Korea
Prior art keywords
command
clock signal
output
input
signal
Prior art date
Application number
KR1020117006956A
Other languages
English (en)
Korean (ko)
Inventor
학준 오
Original Assignee
모사이드 테크놀로지스 인코퍼레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/241,832 external-priority patent/US8181056B2/en
Priority claimed from US12/241,960 external-priority patent/US8161313B2/en
Application filed by 모사이드 테크놀로지스 인코퍼레이티드 filed Critical 모사이드 테크놀로지스 인코퍼레이티드
Publication of KR20110081958A publication Critical patent/KR20110081958A/ko

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

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  • Dram (AREA)
  • Memory System (AREA)
  • Pulse Circuits (AREA)
  • Static Random-Access Memory (AREA)
KR1020117006956A 2008-09-30 2009-09-17 출력 지연 조정을 가진 직렬 연결 메모리 시스템 KR20110081958A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12/241,832 US8181056B2 (en) 2008-09-30 2008-09-30 Serial-connected memory system with output delay adjustment
US12/241,960 US8161313B2 (en) 2008-09-30 2008-09-30 Serial-connected memory system with duty cycle correction
US12/241,960 2008-09-30
US12/241,832 2008-09-30

Publications (1)

Publication Number Publication Date
KR20110081958A true KR20110081958A (ko) 2011-07-15

Family

ID=42072981

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020117006956A KR20110081958A (ko) 2008-09-30 2009-09-17 출력 지연 조정을 가진 직렬 연결 메모리 시스템

Country Status (6)

Country Link
EP (1) EP2329496A4 (zh)
JP (2) JP2012504263A (zh)
KR (1) KR20110081958A (zh)
CN (1) CN102165529B (zh)
TW (1) TW201027556A (zh)
WO (1) WO2010037205A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11061577B2 (en) 2018-10-30 2021-07-13 Samsung Electronics Co., Ltd. System on chip performing training of duty cycle of write clock using mode register write command, operating method of system on chip, electronic device including system on chip

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JP6232313B2 (ja) * 2014-02-25 2017-11-15 新日本無線株式会社 同期式シリアル通信方法およびスレーブ装置
KR20180033368A (ko) * 2016-09-23 2018-04-03 삼성전자주식회사 케스-케이드 연결 구조로 레퍼런스 클록을 전달하는 스토리지 장치들을 포함하는 전자 장치
KR20190009534A (ko) * 2017-07-19 2019-01-29 에스케이하이닉스 주식회사 반도체장치
KR101999125B1 (ko) * 2017-11-24 2019-07-11 파밀넷 주식회사 Rs-422와 rs-485 시리얼 통신을 위한 출력신호 자동 제어기
JP2020155841A (ja) * 2019-03-18 2020-09-24 キオクシア株式会社 半導体集積回路及び送信装置
US10937468B2 (en) * 2019-07-03 2021-03-02 Micron Technology, Inc. Memory with configurable die powerup delay
CN112332881B (zh) * 2020-10-19 2022-04-26 深圳市信锐网科技术有限公司 使能电路及通信装置
CN112698683A (zh) * 2020-12-28 2021-04-23 深圳市合信自动化技术有限公司 一种可配置总线解决传输延时数据出错的方法、装置及plc

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US7308524B2 (en) * 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
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US7352219B2 (en) * 2005-08-30 2008-04-01 Infineon Technologies Ag Duty cycle corrector
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11061577B2 (en) 2018-10-30 2021-07-13 Samsung Electronics Co., Ltd. System on chip performing training of duty cycle of write clock using mode register write command, operating method of system on chip, electronic device including system on chip

Also Published As

Publication number Publication date
WO2010037205A1 (en) 2010-04-08
CN102165529B (zh) 2014-12-31
TW201027556A (en) 2010-07-16
JP2013008386A (ja) 2013-01-10
EP2329496A1 (en) 2011-06-08
EP2329496A4 (en) 2012-06-13
JP2012504263A (ja) 2012-02-16
JP5599852B2 (ja) 2014-10-01
CN102165529A (zh) 2011-08-24

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