WO2010013470A1 - 半導体モジュールおよび半導体モジュールを備える携帯機器 - Google Patents

半導体モジュールおよび半導体モジュールを備える携帯機器 Download PDF

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Publication number
WO2010013470A1
WO2010013470A1 PCT/JP2009/003598 JP2009003598W WO2010013470A1 WO 2010013470 A1 WO2010013470 A1 WO 2010013470A1 JP 2009003598 W JP2009003598 W JP 2009003598W WO 2010013470 A1 WO2010013470 A1 WO 2010013470A1
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Prior art keywords
semiconductor module
protruding
semiconductor element
electrode
apparatus provided
Prior art date
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Ceased
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PCT/JP2009/003598
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English (en)
French (fr)
Inventor
小林初
中里真弓
臼井良輔
柳瀬康行
齋藤浩一
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication date
Priority claimed from JP2008199072A external-priority patent/JP5484694B2/ja
Priority claimed from JP2008255795A external-priority patent/JP5484705B2/ja
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to US13/056,851 priority Critical patent/US8373281B2/en
Priority to US17/954,718 priority patent/USRE50741E1/en
Publication of WO2010013470A1 publication Critical patent/WO2010013470A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
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    • H10W42/261—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions
    • H10W42/276—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
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    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
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    • H10W70/01—Manufacture or treatment
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    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
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    • H10W70/40—Leadframes
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
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    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
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    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
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    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/241—Dispositions, e.g. layouts
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/29—Bond pads specially adapted therefor
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    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
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    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
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    • H10W90/00—Package configurations
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
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    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

　配線層２０の上に形成された絶縁樹脂層３０に搭載された半導体素子４０が封止樹脂５０により封止されている。配線層２０には、半導体素子４０の側に突出する突起電極２２と突起部８０とがそれぞれ一体的に形成されている。そして、突起電極２２は、絶縁樹脂層３０を貫通して半導体素子４０の素子電極４２と電気的に接続されている。突起部８０は、半導体素子４０の四辺に沿って半導体素子４０を取り囲むように配置され、突起電極２２と素子電極４２との接合部分よりも上方の位置にまで封止樹脂５０内に埋め込まれている。
PCT/JP2009/003598 2008-07-31 2009-07-29 半導体モジュールおよび半導体モジュールを備える携帯機器 Ceased WO2010013470A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/056,851 US8373281B2 (en) 2008-07-31 2009-07-29 Semiconductor module and portable apparatus provided with semiconductor module
US17/954,718 USRE50741E1 (en) 2008-07-31 2009-07-29 Semiconductor module and portable apparatus provided with semiconductor module

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2008-199072 2008-07-31
JP2008199072A JP5484694B2 (ja) 2008-07-31 2008-07-31 半導体モジュールおよび半導体モジュールを備える携帯機器
JP2008-255795 2008-09-30
JP2008255795A JP5484705B2 (ja) 2008-09-30 2008-09-30 半導体モジュールおよび半導体モジュールを備える携帯機器

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WO2010013470A1 true WO2010013470A1 (ja) 2010-02-04

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US (2) US8373281B2 (ja)
WO (1) WO2010013470A1 (ja)

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CN112151390A (zh) * 2019-06-27 2020-12-29 立昌先进科技股份有限公司 一种贴片式单颗小尺寸及阵列型的芯片半导体元件的封装方法

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JP6219155B2 (ja) * 2013-12-13 2017-10-25 東芝メモリ株式会社 半導体装置の製造方法
JP6163421B2 (ja) * 2013-12-13 2017-07-12 株式会社東芝 半導体装置、および、半導体装置の製造方法
US10163813B2 (en) 2016-11-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure including redistribution structure and conductive shielding film
JP7083256B2 (ja) 2018-02-19 2022-06-10 富士電機株式会社 半導体モジュール及びその製造方法
KR102570270B1 (ko) * 2018-10-30 2023-08-24 삼성전자주식회사 반도체 패키지
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JP2003007904A (ja) * 2001-06-27 2003-01-10 Hitachi Ltd 半導体装置
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