WO2009139264A1 - コンタクト形成方法、半導体装置の製造方法および半導体装置 - Google Patents
コンタクト形成方法、半導体装置の製造方法および半導体装置 Download PDFInfo
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- WO2009139264A1 WO2009139264A1 PCT/JP2009/057726 JP2009057726W WO2009139264A1 WO 2009139264 A1 WO2009139264 A1 WO 2009139264A1 JP 2009057726 W JP2009057726 W JP 2009057726W WO 2009139264 A1 WO2009139264 A1 WO 2009139264A1
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- silicide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title claims description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 85
- 239000002184 metal Substances 0.000 claims abstract description 85
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 41
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 41
- 238000010438 heat treatment Methods 0.000 claims abstract description 26
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 150000002500 ions Chemical class 0.000 claims abstract description 11
- 230000003213 activating effect Effects 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 38
- 229910052763 palladium Inorganic materials 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 230000004913 activation Effects 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052741 iridium Inorganic materials 0.000 claims description 4
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052762 osmium Inorganic materials 0.000 claims description 4
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910052702 rhenium Inorganic materials 0.000 claims description 4
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 claims description 4
- 229910052703 rhodium Inorganic materials 0.000 claims description 4
- 239000010948 rhodium Substances 0.000 claims description 4
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 39
- 239000010408 film Substances 0.000 description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 10
- 230000002779 inactivation Effects 0.000 description 7
- 238000002441 X-ray diffraction Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
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- 238000002955 isolation Methods 0.000 description 4
- 238000013507 mapping Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
Definitions
- the present invention relates to an MIS type semiconductor device widely used for ICs, LSIs, and the like, and more particularly to formation of a low resistance contact between a high concentration Si portion and a metal silicide in a source region and a drain region.
- Non-patent document 1 describes that the contact resistance must be reduced.
- FIG. 1 shows the contact resistivity dependence of saturation current in a MIS (Metal Insulator Semiconductor) transistor. It can be seen that when the contact resistivity is 1 ⁇ 10 ⁇ 7 ⁇ cm 2 according to the prior art, only about 35% of the capability of the transistor can be extracted.
- MIS Metal Insulator Semiconductor
- Rc is the contact resistance between the high-concentration Si layer and the metal / metal silicide
- ⁇ b is the work function difference between the high-concentration Si layer and the metal / metal silicide
- mn is the effective mass of electrons
- m p is the effective mass of holes
- n is the electron density in the n + region
- p is the hole density in the p + region
- ⁇ s is the dielectric constant of silicon
- h is the Planck constant.
- B boron used in the high-concentration Si layer is likely to be inactivated due to plasma damage caused by ion irradiation during semiconductor device manufacturing.
- B boron
- FIG. 2 B is a trivalent atom with respect to Si, which is covalently bonded, and thus has one less covalent bond and has a longer interatomic distance because the atomic radius is smaller than Si. This is because the Coulomb force for covalent bonding is weakened.
- the prior art maximizes the impurity concentration of the high-concentration Si layer because the inactivation of the high-concentration Si region is inevitable even when metal silicide with a small work function difference is used for the high-concentration Si layer. I can't. Therefore, in the prior art, it has been difficult to reduce the contact resistivity.
- the high concentration Si layer in the source region and the drain region is required to expand and the junction depth is extremely shallow.
- the entire high-concentration Si layer may be silicidized due to the formation of the silicide, and the junction may be destroyed. This makes it difficult for the prior art to spread the high-concentration Si layer and make the junction depth extremely shallow.
- an object of the present invention is to provide a contact formation method capable of increasing the impurity concentration while minimizing the inactivation of impurities due to the plasma damage of the high concentration impurity layer in the contact region.
- Another object of the present invention is to provide a semiconductor device in which a low-resistivity contact is formed from a metal silicide such that the metal has a higher composition than Si.
- a method for forming contacts to a source region and a drain region of a semiconductor device wherein the contact region is formed without performing heat treatment after ion implantation for forming a high-concentration Si layer.
- a contact formation method is obtained in which a metal film is formed, and one or both of activation and silicidation of the high-concentration Si layer is performed by subsequent heat treatment.
- the step of ion-implanting p-type or n-type impurities into the Si layer portion to be the p-type or n-type contact region of the semiconductor device, and the implantation is performed after the ion implantation step.
- Forming a metal film for contact on the surface of the contact region without performing heat treatment for activating the ions, and reacting the metal of the metal film with the Si layer portion by heating to form a silicide of the metal A method for manufacturing a semiconductor device including a step of forming a semiconductor device is obtained.
- the step of amorphizing the surface of the Si layer portion by ion-implanting p-type or n-type impurities into the Si layer portion to be the p-type or n-type contact region of the semiconductor device ion-implanting p-type or n-type impurities into the Si layer portion to be the p-type or n-type contact region of the semiconductor device.
- a method of forming a contact metal film on the surface of the amorphous Si portion, and a step of reacting a metal of the metal film with the amorphous Si portion by heating to form a silicide of the metal Is obtained.
- the metal of the contact metal film is preferably a metal that forms a silicide having a work function difference of 0.3 eV or less with respect to the high-concentration Si layer or the Si layer.
- the method further includes a step of activating the implanted ions by a heat treatment after the metal film is formed.
- the step of forming the silicide and the step of activating are performed simultaneously.
- the contact region may be a source region or a drain region of a field effect transistor. Furthermore, the contact region is preferably a p-type region, the p-type impurity ion-implanted into the contact region is preferably boron, and the metal is preferably palladium.
- a source region and a drain region made of Si wherein a contact portion to at least one of the source region and the drain region includes a predetermined metal silicide, and forms the silicide.
- a metal a semiconductor device using a metal whose silicide composition is larger than that of Si can be obtained.
- the predetermined metal is palladium
- the silicide is a (104) plane of Pd 2 Si.
- the present invention it is possible to increase the impurity concentration by avoiding inactivation of the high-concentration impurity region in the contact portion, and therefore to reduce the resistivity at the contact.
- the semiconductor device when silicidation is used, palladium that consumes less silicon Si is used, so that the breakdown of the junction due to the formation of silicide is prevented, the high-concentration Si layer in the source region and the drain region is expanded, and the junction depth is increased. As a result, the semiconductor device can be miniaturized.
- FIG. 4 is a diagram showing a reciprocal space mapping image of X-ray diffraction when palladium is formed on a Si (100) surface and heat-treated at different temperatures for silicidation.
- FIG. 5 is a diagram showing a reciprocal lattice space mapping image of X-ray diffraction when palladium is formed on a Si (110) surface and heat-treated at different temperatures for silicidation.
- FIG. 3 is a diagram showing a reciprocal space mapping image of X-ray diffraction when palladium is formed on a Si (551) surface and heat-treated at different temperatures for silicidation.
- 1 is a schematic diagram of a CMOS using element isolation by a shallow trench, two-layer wiring, and chemical mechanical polishing according to a first embodiment of the present invention.
- FIG. It is a figure for demonstrating a part of manufacturing process for obtaining CMOS of FIG. It is a figure for demonstrating the remainder of the manufacturing process following FIG.
- It is a schematic diagram of the Kelvin resistance for contact resistivity evaluation which is the 2nd Example of this invention.
- It is a figure which shows the current-voltage characteristic of the Kelvin resistor for contact resistivity evaluation which is the 2nd Example of this invention.
- It is a figure which shows the current-voltage characteristic of the Kelvin resistance produced with the conventional manufacturing method.
- the work function difference is small compared to the high-concentration Si layer, and an appropriate contact material is used to form a metal silicide having a composition rich in metal relative to Si.
- a process for suppressing inactivation of impurities in the concentration layer is executed.
- [First embodiment] 3 to 5 show X-ray diffraction reciprocal lattices when palladium is deposited on Si (100), Si (110), and Si (551) surfaces and heat-treated at different temperatures for silicidation. A spatial mapping image is shown.
- Pd 2 Si having a composition rich in metal with respect to Si is formed, and the plane orientation is changed from the (001) plane to the (401) plane.
- Table 1 shows the work function difference (unit: eV) from p-type Si at this time. It can be seen that by realizing the (401) plane of Pd 2 Si, a work function difference of substantially 0.3 eV or less can be realized regardless of the plane orientation of Si.
- FIG. 6 is a schematic diagram of a CMOS using element isolation by two-layer wiring and chemical mechanical polishing (CMP), which is a first embodiment of the present invention, using shallow trenches (STI: Shallow Trench Isolation). Show.
- CMP chemical mechanical polishing
- FIG. 6 A manufacturing process for obtaining the structure of FIG. 6 will be described with reference to FIGS.
- an element isolation region 1 having an STI structure similar to the conventional method is formed, and an n well 2 and a p well 3 are formed and activated. Thereafter, a silicon oxide film having a thickness of 2 nm is formed as the gate insulating film 4. On this, a gate electrode 5 was formed of polysilicon.
- boron is used for n well 2 and p + region 3 is used for p well 3.
- Phosphorus was ion-implanted at 6 ⁇ 10 15 cm 2 to form 20 nm high concentration regions 6 (p + region) and 7 (n + region). A schematic diagram in this state is shown in FIG.
- the sidewall 8 is formed as shown in FIG. 8 by depositing an oxide film by CVD (Chemical Vapor Deposition) and performing etching without performing heat treatment. After the formation of the sidewalls 8, palladium was deposited to a thickness of 20 nm as a metal for contact with the high concentration regions 6 and 7 and the gate electrode 5.
- CVD Chemical Vapor Deposition
- heat treatment is performed at 550 ° C. for 1 hour in a nitrogen atmosphere to activate not only the silicidation (formation of the contact silicide layer 9) but also the high concentration layers 6 and 7 that have not been performed previously. At the same time. Due to the heat treatment at a low temperature, diffusion in the high concentration region can be suppressed. At this time, Pd 2 Si is silicided by consuming silicon of the high-concentration layers 6 and 7 only for the base 13.6 nm. A schematic diagram in this state is shown in FIG.
- one of the high concentration layers 6 and 7 is a source (S), and the other of the high concentration layers 6 and 7 is a drain (D).
- the metal film is formed without performing the heat treatment for impurity activation, and then the heat treatment is performed to form the high concentration Si layer by the activation of the impurity.
- the formation and the metal silicide are simultaneously performed. As a result, a transistor having a work function difference of 0.3 eV or less and a contact resistivity of 8.0 ⁇ 10 ⁇ 10 ⁇ cm 2 was formed.
- FIG. 9 shows a schematic diagram of a Kelvin resistance for contact resistivity evaluation, which is a second embodiment of the present invention.
- Si (100) with boron element region 31 of the surface subjected to 6 ⁇ 10 15 cm 2 ion implantation to form a high-concentration p region 32 an interlayer insulating film 33 without heat treatment.
- a contact hole 34 that exposes the contact region is formed in the interlayer insulating film 33.
- a 20 nm palladium film is formed as a metal film, and a high-concentration Si layer 32 and a metal silicide 35 are formed by activating impurities at 550 ° C. for 3 hours in a nitrogen gas atmosphere. .
- the formed metal silicide 35 is formed of Pd 2 Si having a composition rich in metal with respect to Si, has a film thickness of 14 nm, has a plane orientation of (104) plane, and a work function with p-type Si. The difference is 0.3 eV or less.
- the electrodes / wirings 36 were formed of aluminum to be completed.
- FIG. 10 shows the current-voltage characteristics of the Kelvin resistor for contact resistivity evaluation according to the second embodiment of the present invention.
- FIG. 11 by a conventional technique, after ion implantation, heat treatment is performed to form a high-concentration Si layer, and then an interlayer insulating film and a contact region are formed, and then a metal film is formed, The current-voltage characteristic of the Kelvin resistance when the metal film is silicided again by heat treatment is shown.
- plasma damage during sputtering deposition is reduced, inactivation of the high-concentration Si region is suppressed, and the resistivity is reduced to some extent.
- the activation of impurities is performed after the metal film is formed, thereby minimizing the plasma damage due to the sputter film formation and forming the metal film on the amorphous Si after the ion implantation.
- silicidation easily proceeds by silicidation by heat treatment. Thereby, the resistivity is further reduced as compared with FIG. 11, and a low contact resistivity of 8.0 ⁇ 10 ⁇ 10 ⁇ cm 2 is realized.
- the plane orientation of silicon is not limited to the (100) plane, but may be any plane orientation such as the (110) and (551) planes.
- the metal is not only palladium, but also at least one of cobalt, nickel, rhodium, rhenium, osmium, iridium, platinum, and gold, and a silicide having a work function difference of 0.3 eV or less with respect to the high concentration layer. Any metal material can be used.
- the present invention has been described with reference to a plurality of embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the spirit and scope of the present invention described in the claims. For example, at least one of the activation and silicidation of the high-concentration layer may be performed, and not only when both are performed, but also may be performed separately.
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Abstract
Description
図3~図5に、Si(100)面、Si(110)面、Si(551)面上にそれぞれパラジウムを成膜し、異なる温度で熱処理を行いシリサイド化したときのX線回折の逆格子空間マッピング像を示す。図3~図5のいずれにおいても、温度を上げるにつれて、Siに対し、金属の多い組成であるPd2Siが形成され、また面方位が(001)面から(401)面に変化していることが分かる。このときのp型Siとの仕事関数差(単位はeV)を表1に示す。Pd2Siの(401)面を実現することにより、Siの面方位によらず実質上0.3eV以下の仕事関数差を実現できることが分かる。
図9に、本発明の第2の実施例であるコンタクト抵抗率評価用のケルビン抵抗の模式図を示す。Si(100)面の素子領域31にボロンを6×1015cm2イオン注入を行って高濃度p領域32を形成した後、熱処理を行わずに層間絶縁膜33を成膜する。続いて、層間絶縁膜33にコンタクト領域を露出させるコンタクトホール34の形成を行う。その後、金属膜として20nmのパラジウムの成膜を行い、窒素ガス雰囲気で550℃、3時間の熱処理を行うことにより不純物の活性化による高濃度Si層32の形成と、金属シリサイド35の形成を行う。このとき、形成される金属シリサイド35は、Siに対し金属の多い組成であるPd2Siが形成されて膜厚は14nmとなり、その面方位は(104)面でありp型Siとの仕事関数差は0.3eV以下である。その後、電極・配線36をアルミニウムで形成し完成とした。
Claims (16)
- 半導体装置のソース領域、ドレイン領域へのコンタクト形成方法であって、高濃度Si層形成のためのイオン注入後、熱処理を行わずに、コンタクト用の金属膜を成膜し、その後の熱処理によって前記高濃度Si層の活性化およびシリサイド化の一方または両方を行うことを特徴とするコンタクト形成方法。
- 前記コンタクト用の金属膜の金属は、前記高濃度Si層に対して仕事関数差が0.3eV以下のシリサイドを形成する金属であることを特徴とする請求項1に記載のコンタクト形成方法。
- 前記コンタクト用の金属膜の金属は、パラジウム、コバルト、ニッケル、ロジウム、レニウム、オスミウム、イリジウム、白金、および金の少なくとも一つであることを特徴とする請求項1に記載のコンタクト形成方法。
- 半導体装置のp型またはn型コンタクト領域となるべきSi層部分へp型またはn型不純物をイオン注入する工程と、
イオン注入工程の後に、注入されたイオンを活性化するための熱処理を行うことなしに前記コンタクト領域表面にコンタクト用の金属膜を形成する工程と、
加熱によって前記金属膜の金属を前記Si層部分と反応させ前記金属のシリサイドを形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 半導体装置のp型またはn型コンタクト領域となるべきSi層部分へp型またはn型不純物をイオン注入して該Si層部分の表面をアモルファス化する工程と、
アモルファスSi部分表面にコンタクト用の金属膜を形成する工程と、
加熱によって前記金属膜の金属を前記アモルファスSi部分と反応させ前記金属のシリサイドを形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記イオン注入により注入されたイオンを前記金属膜が形成された後の熱処理によって活性化する工程をさらに含むことを特徴とする請求項4または5に記載の半導体装置の製造方法。
- 前記シリサイドを形成する工程と前記活性化する工程とが同時に行われることを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記コンタクト領域が電界効果トランジスタのソースまたはドレイン領域であることを特徴とする請求項4または5に記載の半導体装置の製造方法。
- 前記コンタクト用の金属膜の金属は、前記p型またはn型コンタクト領域となるべきSi層部分に対して仕事関数差が0.3eV以下のシリサイドを形成する金属であることを特徴とする請求項4または5に記載の半導体装置の製造方法。
- 前記コンタクト用の金属膜の金属は、パラジウム、コバルト、ニッケル、ロジウム、レニウム、オスミウム、イリジウム、白金、および金の少なくとも一つであることを特徴とする請求項4または5に記載の半導体装置の製造方法。
- 前記コンタクト領域がp型領域であることを特徴とする請求項4または5に記載の半導体装置の製造方法。
- 前記コンタクト領域にイオン注入されるp型不純物がボロンであることを特徴とする請求項11に記載の半導体装置の製造方法。
- 前記金属がパラジウムであることを特徴とする請求項4または5に記載の半導体装置の製造方法。
- Siによるソース領域、ドレイン領域を有し、前記ソース領域およびドレイン領域の少なくとも一方へのコンタクト部分が所定の金属のシリサイドを含む半導体装置において、
前記シリサイドを形成する前記金属が、前記シリサイドの組成がSiに対して前記金属が多くなるような金属であることを特徴とする半導体装置。 - 前記所定の金属がパラジウムであることを特徴とする請求項14に記載の半導体装置。
- 前記所定の金属がパラジウムであり、前記シリサイドが、Pd2Siの(104)面であることを特徴とする請求項14に記載の半導体装置。
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