WO2009116204A1 - Dispositif de traitement de données et procédé de traitement de données - Google Patents

Dispositif de traitement de données et procédé de traitement de données Download PDF

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Publication number
WO2009116204A1
WO2009116204A1 PCT/JP2008/071407 JP2008071407W WO2009116204A1 WO 2009116204 A1 WO2009116204 A1 WO 2009116204A1 JP 2008071407 W JP2008071407 W JP 2008071407W WO 2009116204 A1 WO2009116204 A1 WO 2009116204A1
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bit
bits
code
symbol
row direction
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PCT/JP2008/071407
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English (en)
Japanese (ja)
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諭志 岡田
塁 阪井
横川　峰志
山本　真紀子
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ソニー株式会社
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6552—DVB-T2
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/3405—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power
    • H04L27/3416—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power in which the information is carried by both the individual signal points and the subset to which the individual points belong, e.g. using coset coding, lattice coding, or related schemes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/3488—Multiresolution systems

Definitions

  • the present invention relates to a data processing apparatus and a data processing method, and more particularly, to a data processing apparatus and a data processing method capable of improving, for example, tolerance against data errors.
  • LDPC Low Density Parity Check
  • LDPC codes have been found to have performance close to the Shannon limit as the code length is increased, as is the case with turbo codes and the like.
  • the LDPC code has the property that the minimum distance is proportional to the code length, its characteristic is that the block error probability characteristic is good, and furthermore, the so-called error floor phenomenon observed in the decoding characteristic such as turbo code is observed.
  • An advantage is that it hardly occurs.
  • LDPC code is a linear code and does not necessarily need to be binary, but will be described here as being binary.
  • LDPC code is characterized by the fact that the parity check matrix that defines the LDPC code is sparse.
  • a sparse matrix is a matrix in which the number of “1” s in the matrix is very small (a matrix in which most elements are 0).
  • FIG. 1 shows an example of a parity check matrix H of an LDPC code.
  • the weight of each column (column weight) (the number of “1”) (weight) is “3”, and the weight of each row (row weight) is “6”. .
  • a generator matrix G is generated based on the check matrix H, and the generator matrix G is multiplied by binary information bits to generate a codeword (LDPC code). ) Is generated.
  • the generator matrix G is a K ⁇ N matrix
  • the encoding device multiplies the generator matrix G by a bit string (vector u) of information bits made up of K bits to generate a code made up of N bits.
  • Generate the word c ( uG).
  • the code word (LDPC code) generated by this encoding device is received on the receiving side via a predetermined communication path.
  • LDPC code decoding is an algorithm proposed by Gallager called probabilistic decoding (Probabilistic Decoding), which consists of a variable node (also called a message node) and a check node (check node). This can be done by a message passing algorithm based on belief propagation on a so-called Tanner graph.
  • the variable node and the check node are also simply referred to as nodes as appropriate.
  • FIG. 2 shows a procedure for decoding the LDPC code.
  • a real value representing the “0” likelihood of the value of the i-th code bit of the LDPC code (1 codeword) received on the receiving side as a log likelihood ratio will be received.
  • the value is u 0i .
  • a message output from the check node is u j and a message output from the variable node is v i .
  • step S11 the LDPC code is received, the message (check node message) u j is initialized to “0”, and the counter of the iterative process is used.
  • the variable k taking the integer of is initialized to “0”, and the process proceeds to step S12.
  • step S12 based on the received value u 0i obtained by receiving an LDPC code, the message (variable node message) v i is obtained by performing the calculation shown in Equation (1) (variable node calculation), further, Based on the message v i , the message u j is obtained by performing the calculation (check node calculation) shown in Expression (2).
  • variable node calculation of Expression (1) the message input from the edge (line connecting the variable node and the check node) to which the message is to be output, respectively.
  • the computation range is 1 to d v -1 or 1 to d c -1.
  • the check node calculation of equation (2) actually creates a table of function R (v 1 , v 2 ) shown in equation (3) defined by one output for two inputs v 1 and v 2 in advance. In addition, this is performed by using it continuously (recursively) as shown in Equation (4).
  • step S12 the variable k is further incremented by “1”, and the process proceeds to step S13.
  • step S13 it is determined whether or not the variable k is larger than a predetermined iterative decoding count C. If it is determined in step S13 that the variable k is not greater than C, the process returns to step S12, and thereafter the same processing is repeated.
  • step S13 determines whether the variable k is larger than C. If it is determined in step S13 that the variable k is larger than C, the process proceeds to step S14, and a message v i as a decoding result to be finally output is obtained by performing the calculation shown in equation (5). And the LDPC code decoding process ends.
  • equation (5) is performed using messages u j from all branches connected to the variable node.
  • FIG. 3 shows an example of a parity check matrix H of a (3, 6) LDPC code (coding rate 1/2, code length 12).
  • the column weight is 3 and the row weight is 6, as in FIG.
  • FIG. 4 shows a Tanner graph of the check matrix H in FIG.
  • check nodes and variable nodes correspond to the rows and columns of the parity check matrix H, respectively.
  • the connection between the check node and the variable node is an edge, and corresponds to “1” of the check matrix element.
  • the branch represents that the sign bit corresponding to the variable node has a constraint condition corresponding to the check node.
  • FIG. 5 shows variable node calculation performed in the variable node.
  • the message v i corresponding to the branch to be calculated is the variable node of the formula (1) using the messages u 1 and u 2 from the remaining branches connected to the variable node and the received value u 0i. It is obtained by calculation. Messages corresponding to other branches are obtained in the same manner.
  • FIG. 6 shows a check node operation performed at the check node.
  • sign (x) is 1 when x ⁇ 0, and ⁇ 1 when x ⁇ 0.
  • the message u j corresponding to the branch to be calculated is the messages v 1 , v 2 , v 3 , v 4 , v from the remaining branches connected to the check node. It is obtained by the check node calculation of Equation (7) using 5 . Messages corresponding to other branches are obtained in the same manner.
  • DVB-S.2 ETSI EN 302 307 V1.1.2 (2006-06)
  • the LDPC code is applied to terrestrial digital broadcasting, and the next generation that combines the LDPC code specified in the DVB-S.2 standard and the modulation method specified in the DVB-T standard.
  • the DVB-T.2 standard which is a standard for terrestrial digital broadcasting, has been formulated.
  • the LDPC code with a coding rate of 3/5 is inferior to the LDPC codes with other coding rates.
  • the present invention has been made in view of such a situation, and is intended to improve resistance to errors in data such as LDPC codes.
  • code bits of LDPC Low Density Parity Check
  • code bits of LDPC Low Density Parity Check
  • the storage means stores mb bits in the row direction, where b is a predetermined positive integer.
  • N / (mb) bits are stored in the column direction, and the sign bit of the LDPC code is written in the column direction of the storage means, and then read in the row direction, and the row bits of the storage means
  • the allocation rule for allocating the code bits of the LDPC code to the symbol bits representing the symbols are replaced by a replacement means that replaces the code bits of the mb bits and uses the replaced code bits as the symbol bits, and the allocation rule includes a group that groups the code bits according to an error probability.
  • a group of grouping the symbol bits according to an error probability is a symbol bit group, and the code bit group of the code bit and the symbol bit to which the code bit of the code bit group is assigned
  • Data processing that is a rule that defines a group set that is a combination with the symbol bit group, the code bit group of the group set, and the number of code bits and the number of symbol bits of each of the symbol bit groups It is the location.
  • code bits of LDPC Low Density Parity Check
  • code bits of LDPC Low Density Parity Check
  • the storage means stores mb bits in the row direction, where b is a predetermined positive integer.
  • N / (mb) bits are stored in the column direction, and the sign bit of the LDPC code is written in the column direction of the storage means, and then read in the row direction, and the row bits of the storage means
  • a data processing device that performs data interleaving converts a code bit of the LDPC code into a symbol representing the symbol.
  • the code bits of the mb bits are replaced, and the code bits after the replacement are used as the symbol bits.
  • the allocation rule includes grouping the code bits according to an error probability.
  • the group to be divided is a code bit group, and the group in which the symbol bits are grouped according to an error probability is a symbol bit group, and the code bit group of the code bit and the code bit of the code bit group A group set that is a combination of the symbol bits to which the symbol bits are assigned, the code bit group of the group set, and the code bits and the symbol bits of each of the symbol bit groups It is a data processing method which is the rules that govern the Wattage.
  • LDPC Low Density Parity Check
  • code bits having a code length of N bits are written in the column direction of the storage means for storing in the row direction and the column direction, and are read out in the row direction.
  • the storage means stores mb bits in the row direction and N in the column direction, where b is a predetermined positive integer.
  • a group that groups the code bits according to an error probability is a code bit group
  • a group that groups the symbol bits according to an error probability is a symbol bit group
  • the code bits A group set which is a combination of the symbol bit group of the symbol bit group and the symbol bit group of the symbol bit to which the code bit of the code bit group is assigned, and each of the code bit group of the group set and the symbol bit group The code bits and the number of symbol bits are defined.
  • a code bit of an LDPC (Low Density Parity Check) code having a code length of N bits is written in the column direction of the storage means for storing in the row direction and the column direction,
  • LDPC Low Density Parity Check
  • the storage means stores mb bits in the row direction, where b is a predetermined positive integer.
  • N / (mb) bits are stored in the column direction, and the sign bit of the LDPC code is written in the column direction of the storage means, and then read in the row direction, and the row bits of the storage means
  • the code bits of the mb bits read out in the direction are b symbols
  • the code bits of the LDPC code are assigned according to an assignment rule for assigning the code bits to the symbol bits representing the symbols.
  • the mb bit code bit is replaced, and the LDPC code is provided with a replacement means that uses the replaced code bit as the symbol bit, and the LDPC code has a coding rate defined by the DVB-S.2 standard of 3 / 5 is an LDPC code having a code length N of 64,800 bits, the m bits is 4 bits, the integer b is 2, and the 4 bits of the code bits are 16QAM as one symbol.
  • the storage means has 8 columns storing 4 ⁇ 2 bits in the row direction, and 64800 / (4 ⁇ 2) bits in the column direction storing said replacement means, the i + 1-th bit from the most significant bit of the 4 ⁇ 2 code bits read out in the row direction of said storage means, as well as the bit b i, two consecutive said I + 1 bit from the most significant bit of the 4 ⁇ 2 symbol bits of the symbol
  • the door eyes as bit y i, the bit b 0, the bit y 0, the bit b 1, the bit y 1, the bit b 2, the bit y 4, the bit b 3, the bit y 2, the bit
  • This is a data processing device that performs replacement by assigning b 4 to bit y 3 , bit b 5 , bit y 5 , bit b 6 , bit y 6 , bit b 7 , and bit y 7 .
  • code bits of an LDPC (Low Density Parity Check) code having a code length of N bits are written in the column direction of the storage means for storing in the row direction and the column direction, and read out in the row direction.
  • LDPC Low Density Parity Check
  • the storage means stores mb bits in the row direction and N in the column direction, where b is a predetermined positive integer.
  • the LDPC code is an LDPC code defined in the DVB-S.2 standard, with a coding rate of 3/5, a code length N of 64,800 bits, the m bits of 4 bits, and the The integer b is 2, and 4 bits of the sign bit are mapped as one symbol to any one of 16 signal points defined by 16QAM.
  • the storage means has eight columns for storing 4 ⁇ 2 bits in the row direction, and stores 64800 / (4 ⁇ 2) bits in the column direction.
  • the i + 1 bit from the most significant bit of the 4 ⁇ 2 bit code bit read in the row direction of the storage means is set to bit b i and 4 ⁇ 2 of the two consecutive symbols.
  • bit y i bit b 0 , bit y 0 , bit b 1 , bit y 1 , bit b 2 , bit y 4 , Bit b 3 , bit y 2 , bit b 4 , bit y 3 , bit b 5 , bit y 5 , bit b 6 , bit y 6 , bit b 7 , bit y 7 , Each of them is replaced.
  • a code bit of an LDPC (Low Density Parity Check) code having a code length of N bits is written in the column direction of the storage means for storing in the row direction and the column direction,
  • LDPC Low Density Parity Check
  • the storage means stores mb bits in the row direction, where b is a predetermined positive integer.
  • N / (mb) bits are stored in the column direction, and the sign bit of the LDPC code is written in the column direction of the storage means, and then read in the row direction, and the row bits of the storage means
  • the code bits of the mb bits read out in the direction are b symbols
  • the code bits of the LDPC code are assigned according to an assignment rule for assigning the code bits to the symbol bits representing the symbols.
  • the mb bit code bit is replaced, and the LDPC code is provided with a replacement means that uses the replaced code bit as the symbol bit, and the LDPC code has a coding rate defined by the DVB-S.2 standard of 3 / 5 is an LDPC code having a code length N of 64,800 bits, the m bits are 6 bits, the integer b is 2, and the 6 bits of the code bits are 64QAM as one symbol.
  • the storage means has 12 columns storing 6 ⁇ 2 bits in the row direction, and 64800 / (6 ⁇ 2) bits in the column direction
  • the replacement means sets the i + 1 bit from the most significant bit of the 6 ⁇ 2 bit code bits read in the row direction of the storage means as bit b i, and the two consecutive I + 1 bit from the most significant 6x2 symbol bit
  • bit y i the bit b 0, the bit y 2, the bit b 1, the bit y 0, the bit b 2, the bit y 1, the bit b 3, the bit y 6, the bit b 4 , bit y 7 , bit b 5 , bit y 3 , bit b 6 , bit y 8 , bit b 7 , bit y 4 , bit b 8 , bit y 5 , bit the b 9, the bit y 10, the bit b 10, the bit y 9, the bit b 11, the bit y 11, a data processing apparatus
  • code bits of an LDPC (Low Density Parity Check) code having a code length of N bits are written in the column direction of the storage means for storing in the row direction and the column direction, and read out in the row direction.
  • the storage means stores mb bits in the row direction and N in the column direction, where b is a predetermined positive integer.
  • the LDPC code is an LDPC code defined in the DVB-S.2 standard, with a coding rate of 3/5, a code length N of 64,800 bits, the m bits of 6 bits, and the An integer b is 2, and 6 bits of the sign bit are mapped as one symbol to any one of 64 signal points defined by 64QAM.
  • the storage means has 12 columns storing 6 ⁇ 2 bits in the row direction, and stores 64800 / (6 ⁇ 2) bits in the column direction.
  • the i + 1-th bit from the most significant bit of the 6 ⁇ 2 code bits read in the row direction of the storage means is set to bit b i and 6 ⁇ 2 of the two consecutive symbols.
  • bit b 8 is assigned to the bit y 5
  • bit b 9 is assigned to the bit y 10
  • bit b 10 is assigned to the bit y 9
  • bit b 11 is assigned to the bit y 11 .
  • a code bit of an LDPC (Low Density Parity Check) code having a code length of N bits is written in the column direction of the storage means for storing in the row direction and the column direction,
  • LDPC Low Density Parity Check
  • the storage means stores mb bits in the row direction, where b is a predetermined positive integer.
  • N / (mb) bits are stored in the column direction, and the sign bit of the LDPC code is written in the column direction of the storage means, and then read in the row direction, and the row bits of the storage means
  • the code bits of the mb bits read out in the direction are b symbols
  • the code bits of the LDPC code are assigned according to an assignment rule for assigning the code bits to the symbol bits representing the symbols.
  • the mb bit code bit is replaced, and the LDPC code is provided with a replacement means that uses the replaced code bit as the symbol bit, and the LDPC code has a coding rate defined by the DVB-S.2 standard of 3 / 5 is an LDPC code having a code length N of 64800 bits, the m bits is 8 bits, the integer b is 2, and the 8 bits of the code bits are 256QAM as one symbol.
  • the storage means has 16 columns storing 8 ⁇ 2 bits in the row direction, and 64800 / (8 ⁇ 2) bits in the column direction storing said replacement means, the i + 1-th bit from the most significant bit of the 8 ⁇ 2 code bits read out in the row direction of said storage means, as well as the bit b i, two consecutive said I + 1 from the most significant bit of the 8 ⁇ 2 symbol bits of the symbol
  • the Tsu bets eyes as bit y i, the bit b 0, the bit y 8, the bit b 1, the bit y 3, the bit b 2, the bit y 12, the bit b 3, the bit y 4, Bit b 4 to bit y 10 bit b 5 to bit y 2 bit b 6 to bit y 9 bit b 7 to bit y 1 bit b 8 to bit y 11 the bit b 9, the bit y 0, the bit b 10, the bit y 13, the bit b 11, the bit y 5, the bit b 12, the
  • code bits of an LDPC (Low Density Parity Check) code having a code length of N bits are written in the column direction of the storage means for storing in the row direction and the column direction, and read out in the row direction.
  • LDPC Low Density Parity Check
  • the storage means stores mb bits in the row direction and N in the column direction, where b is a predetermined positive integer.
  • the LDPC code is an LDPC code defined in the DVB-S.2 standard, with a coding rate of 3/5, a code length N of 64,800 bits, the m bits of 8 bits, and the The integer b is 2, and 8 bits of the code bit are mapped as one symbol to any one of 256 signal points defined by 256QAM.
  • the storage means has 16 columns storing 8 ⁇ 2 bits in the row direction, and stores 64800 / (8 ⁇ 2) bits in the column direction.
  • the i + 1-th bit from the most significant bit of the 8 ⁇ 2 bit to be read in the row direction of the storage means is set to bit b i and 8 ⁇ 2 of the two consecutive symbols.
  • bit y i bit b 0 , bit y 8 , bit b 1 , bit y 3 , bit b 2 , bit y 12 , Bit b 3 , bit y 4 , bit b 4 , bit y 10 , bit b 5 , bit y 2 , bit b 6 , bit y 9 , bit b 7 , bit y 1 , Bit b 8 , bit y 11 , bit b 9 , bit y 0 , bit b 10 , bit y 13 , bit b 11 , bit y 5 , bit b 12 , bit y 14 the bit b 13, the bit y 6, the bit b 14, the bit y 15, the bit b 15, the bit y 7, replacement of allocating is performed respectively.
  • code bits of LDPC Low Density Parity Check
  • code bits of LDPC Low Density Parity Check
  • the storage means stores mb bits in the row direction, where b is a predetermined positive integer.
  • N / (mb) bits are stored in the column direction, and the sign bit of the LDPC code is written in the column direction of the storage means, and then read in the row direction, and the row bits of the storage means
  • the code bits of the mb bits read out in the direction are b symbols
  • the code bits of the LDPC code are assigned according to an assignment rule for assigning the code bits to the symbol bits representing the symbols.
  • the mb bit code bit is replaced, and the LDPC code is provided with a replacement means that uses the replaced code bit as the symbol bit, and the LDPC code has a coding rate defined by the DVB-S.2 standard of 3 / 5 is an LDPC code having a code length N of 16200 bits, the m bits are 4 bits, the integer b is 2, and the 4 bits of the code bits are 16QAM as one symbol.
  • the storage means has 8 columns storing 4 ⁇ 2 bits in the row direction, and 16200 / (4 ⁇ 2) bits in the column direction storing said replacement means, the i + 1-th bit from the most significant bit of the 4 ⁇ 2 code bits read out in the row direction of said storage means, as well as the bit b i, two consecutive said I + 1 bit from the most significant bit of the 4 ⁇ 2 symbol bits of the symbol
  • the door eyes as bit y i, the bit b 0, the bit y 0, the bit b 1, the bit y 1, the bit b 2, the bit y 4, the bit b 3, the bit y 2, the bit
  • This is a data processing device that performs replacement by assigning b 4 to bit y 3 , bit b 5 , bit y 5 , bit b 6 , bit y 6 , bit b 7 , and bit y 7 .
  • a code bit of an LDPC (Low Density Parity Check) code having a code length of N bits is written in the column direction of the storage means for storing in the row direction and the column direction, and is read in the row direction.
  • the storage means stores mb bits in the row direction and N in the column direction, where b is a predetermined positive integer.
  • the LDPC code is an LDPC code defined in the DVB-S.2 standard, with a coding rate of 3/5, a code length N of 16200 bits, the m bits is 4 bits, and the The integer b is 2, and 4 bits of the sign bit are mapped as one symbol to any one of 16 signal points defined by 16QAM.
  • the storage means has 8 columns for storing 4 ⁇ 2 bits in the row direction, and stores 16200 / (4 ⁇ 2) bits in the column direction.
  • the i + 1 bit from the most significant bit of the 4 ⁇ 2 bit code bits read in the row direction of the storage means is set to bit b i and 4 ⁇ 2 of the two consecutive symbols.
  • bit y i bit b 0 , bit y 0 , bit b 1 , bit y 1 , bit b 2 , bit y 4 , Bit b 3 , bit y 2 , bit b 4 , bit y 3 , bit b 5 , bit y 5 , bit b 6 , bit y 6 , bit b 7 , bit y 7 , Each of them is replaced.
  • code bits of LDPC Low Density Parity Check
  • code bits of LDPC Low Density Parity Check
  • the storage means stores mb bits in the row direction, where b is a predetermined positive integer.
  • N / (mb) bits are stored in the column direction, and the sign bit of the LDPC code is written in the column direction of the storage means, and then read in the row direction, and the row bits of the storage means
  • the code bits of the mb bits read out in the direction are b symbols
  • the code bits of the LDPC code are assigned according to an assignment rule for assigning the code bits to the symbol bits representing the symbols.
  • the mb bit code bit is replaced, and the LDPC code is provided with a replacement means that uses the replaced code bit as the symbol bit, and the LDPC code has a coding rate defined by the DVB-S.2 standard of 3 / 5 is an LDPC code having a code length N of 16200 bits, the m bits are 6 bits, the integer b is 2, and the 6 bits of the code bits are 64QAM as one symbol.
  • the storage means has 12 columns storing 6 ⁇ 2 bits in the row direction, and 16200 / (6 ⁇ 2) bits in the column direction
  • the replacement means sets the i + 1 bit from the most significant bit of the 6 ⁇ 2 bit code bits read in the row direction of the storage means as bit b i, and the two consecutive I + 1 bit from the most significant 6x2 symbol bit
  • bit y i the bit b 0, the bit y 2, the bit b 1, the bit y 0, the bit b 2, the bit y 1, the bit b 3, the bit y 6, the bit b 4 , bit y 7 , bit b 5 , bit y 3 , bit b 6 , bit y 8 , bit b 7 , bit y 4 , bit b 8 , bit y 5 , bit the b 9, the bit y 10, the bit b 10, the bit y 9, the bit b 11, the bit y 11, a data processing apparatus for
  • code bits of LDPC Low Density Parity Check
  • code bits of LDPC Low Density Parity Check
  • the storage means stores mb bits in the row direction and N in the column direction, where b is a predetermined positive integer.
  • the LDPC code is an LDPC code defined in the DVB-S.2 standard, with a coding rate of 3/5, a code length N of 16200 bits, the m bits is 6 bits, and the An integer b is 2, and 6 bits of the sign bit are mapped as one symbol to any one of 64 signal points defined by 64QAM.
  • the storage means has 12 columns storing 6 ⁇ 2 bits in the row direction, and stores 16200 / (6 ⁇ 2) bits in the column direction.
  • the i + 1-th bit from the most significant bit of the 6 ⁇ 2 code bits read in the row direction of the storage means is set to bit b i and 6 ⁇ 2 of the two consecutive symbols.
  • bit b 8 is assigned to the bit y 5
  • bit b 9 is assigned to the bit y 10
  • bit b 10 is assigned to the bit y 9
  • bit b 11 is assigned to the bit y 11 .
  • code bits of an LDPC (Low Density Parity Check) code having a code length of N bits are written in the column direction of the storage means for storing in the row direction and the column direction,
  • LDPC Low Density Parity Check
  • the storage means stores mb bits in the row direction, where b is a predetermined positive integer.
  • N / (mb) bits are stored in the column direction, and the sign bit of the LDPC code is written in the column direction of the storage means, and then read in the row direction, and the row bits of the storage means
  • the code bits of the mb bits read out in the direction are b symbols
  • the code bits of the LDPC code are assigned according to an assignment rule for assigning the code bits to the symbol bits representing the symbols.
  • the mb bit code bit is replaced, and the LDPC code is provided with a replacement means that uses the replaced code bit as the symbol bit, and the LDPC code has a coding rate defined by the DVB-S.2 standard of 3 / 5 is an LDPC code having a code length N of 16200 bits, the m bits is 8 bits, the integer b is 1, and the 8 bits of the code bits are 256QAM as one symbol.
  • the storage means has 8 columns for storing 8 ⁇ 1 bits in the row direction, and 16200 / (8 ⁇ 1) bits in the column direction storing said replacement means, the i + 1-th bit from the most significant bit of the sign bit of the 8 ⁇ 1 bits read in the row direction of said storage means, as well as the bit b i, of one of the symbols
  • a code bit of an LDPC (Low Density Parity Check) code having a code length of N bits is written in the column direction of the storage means for storing in the row direction and the column direction, and is read in the row direction.
  • the storage means stores mb bits in the row direction and N in the column direction, where b is a predetermined positive integer.
  • the LDPC code is an LDPC code defined in the DVB-S.2 standard, with a coding rate of 3/5, a code length N of 16200 bits, the m bits is 8 bits, and the The integer b is 1, and 8 bits of the code bit are mapped as one symbol to any one of 256 signal points defined by 256QAM.
  • the storage means has eight columns for storing 8 ⁇ 1 bits in the row direction, and stores 16200 / (8 ⁇ 1) bits in the column direction.
  • the (i + 1) -th bit from the most significant bit of the 8 ⁇ 1 bit code bit read in the row direction of the storage means is set to bit b i, and the 8 ⁇ 1 bit of one symbol
  • the bit i + 1 from the most significant bit of the symbol bit is designated as bit y i , bit b 0 , bit y 2 , bit b 1 , bit y 4 , bit b 2 , bit y 0 , bit b 3 to bit y 6 bit b 4 to bit y 7 bit b 5 to bit y 1 bit b 6 to bit y 3 bit b 7 to bit y 5 Allocation is performed.
  • the data processing apparatus may be an independent apparatus or an internal block constituting one apparatus.
  • FIG. 3 is a block diagram illustrating a configuration example of a transmission device 11.
  • FIG. It is a figure which shows a check matrix. It is a figure which shows a parity matrix.
  • FIG. 3 is a block diagram illustrating a configuration example of an LDPC encoding unit 21.
  • FIG. 4 is a flowchart for explaining processing of an LDPC encoding unit 21. It is a figure which shows the check matrix initial value table prescribed
  • FIG. 6 is a diagram for explaining processing of a demultiplexer 25.
  • FIG. 6 is a diagram for explaining processing of a demultiplexer 25.
  • Fig. 10 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5 is modulated by 16QAM. It is a figure which shows an allocation rule in case the LDPC code whose code length N is 64800 bits and a coding rate is 3/5 is modulated by 16QAM.
  • Fig. 10 is a diagram illustrating exchanging of code bits according to an allocation rule when an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5 is modulated by 16QAM.
  • Fig. 11 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length N of 64800 bits and a coding rate of 3/5 is modulated by 64QAM.
  • Fig. 10 is a diagram illustrating an allocation rule when an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5 is modulated by 64QAM. It is a figure which shows replacement
  • FIG. 10 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5 is modulated by 256QAM.
  • Fig. 10 is a diagram illustrating an allocation rule when an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5 is modulated by 256QAM.
  • Fig. 10 is a diagram illustrating exchanging of code bits according to an allocation rule when an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5 is modulated by 256QAM.
  • FIG. 10 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length N of 16200 bits and a coding rate of 3/5 is modulated by 16QAM.
  • Fig. 10 is a diagram showing an allocation rule when an LDPC code having a code length N of 16200 bits and a coding rate of 3/5 is modulated by 16QAM.
  • Fig. 10 is a diagram illustrating exchanging of code bits according to an allocation rule when an LDPC code having a code length N of 16200 bits and an encoding rate of 3/5 is modulated by 16QAM.
  • FIG. 10 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length N of 16200 bits and a coding rate of 3/5 is modulated by 64QAM.
  • Fig. 10 is a diagram showing an allocation rule when an LDPC code having a code length N of 16200 bits and a coding rate of 3/5 is modulated by 64QAM.
  • Fig. 10 is a diagram illustrating exchanging of code bits according to an allocation rule when an LDPC code having a code length N of 16200 bits and a coding rate of 3/5 is modulated by 64QAM.
  • FIG. 10 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length N of 16200 bits and a coding rate of 3/5 is modulated by 256QAM. It is a figure which shows an allocation rule in case the LDPC code whose code length N is 16200 bits and a coding rate is 3/5 is modulated by 256QAM.
  • Fig. 10 is a diagram illustrating exchanging of code bits according to an allocation rule when an LDPC code having a code length N of 16200 bits and a coding rate of 3/5 is modulated by 256QAM. It is a figure which shows BER about the replacement process performed by each of the present system and a new replacement system. It is a figure which shows BER about the replacement process performed by each of the present system and a new replacement system. It is a block diagram which shows the structural example of one Embodiment of the computer to which this invention is applied.
  • 11 transmitting device 12 receiving device, 21 LDPC encoding unit, 22 bit interleaver, 25 demultiplexer, 26 mapping unit, 27 orthogonal modulation unit, 31 memory, 32 replacement unit, 101 encoding processing unit, 102 storage unit, 111 Encoding rate setting unit, 112 Initial value table reading unit, 113 Check matrix generation unit, 114 Information bit reading unit, 115 Encoding parity calculation unit, 116 Control unit, 701 bus, 702 CPU, 703 ROM, 704 RAM, 705 hard disk , 706 output unit, 707 input unit, 708 communication unit, 709 drive, 710 input / output interface, 711 removable recording medium
  • FIG. 7 is a diagram of a transmission system to which the present invention is applied (a system refers to a logical collection of a plurality of devices, regardless of whether or not each configuration device is in the same housing). The structural example of embodiment is shown.
  • the transmission system includes a transmission device 11 and a reception device 12.
  • the transmission device 11 transmits, for example, a television broadcast program. That is, the transmission device 11 encodes target data to be transmitted, such as image data and audio data as a television broadcast program, into an LDPC code and transmits the encoded data through, for example, a satellite line or a terrestrial wave.
  • target data to be transmitted such as image data and audio data as a television broadcast program
  • the receiving device 12 is, for example, a tuner or a television receiver that receives a television broadcast program.
  • the receiving device 12 receives an LDPC code transmitted from the transmitting device 11, decodes it into target data, and outputs it.
  • the LDPC code used in the transmission system of FIG. 7 exhibits extremely high capability in an AWGN (Additive White Gaussian Noise) channel.
  • AWGN Additional White Gaussian Noise
  • FIG. 8 shows a configuration example of the transmission apparatus 11 of FIG.
  • the transmission device 11 includes an LDPC encoding unit 21, a bit interleaver 22, a mapping unit 26, and an orthogonal modulation unit 27.
  • the target data is supplied to the LDPC encoding unit 21.
  • the LDPC encoding unit 21 performs LDPC encoding on the target data supplied thereto according to a parity check matrix in which a parity matrix that is a portion corresponding to the parity bit of the LDPC code has a staircase structure, Output LDPC code as information bits.
  • the LDPC encoding unit 21 performs LDPC encoding that encodes the target data into, for example, an LDPC code defined in the DVB-S.2 standard, and outputs an LDPC code obtained as a result.
  • the LDPC code defined in the DVB-S.2 standard is an IRA (Irregular-Repeat-Accumulate) code
  • the parity matrix in the parity check matrix of the LDPC code has a staircase structure.
  • the parity matrix and the staircase structure will be described later.
  • IRA codes for example, “Irregular Repeat-Accumulate Codes,” H. Jin, A. Khandekar, and R. J. McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics-8 , Sept. 2000.
  • the LDPC code output from the LDPC encoding unit 21 is supplied to the bit interleaver 22.
  • the bit interleaver 22 is a data processing device that interleaves data, and includes a demultiplexer (DEMUX) 25.
  • DEMUX demultiplexer
  • the demultiplexer 25 obtains a symbol with enhanced resistance against AWGN by performing a replacement process for replacing the positions of two or more code bits of the LDPC code as a symbol with respect to the LDPC code from the LDPC encoding unit 21, and performs mapping. To the unit 26.
  • the mapping unit 26 maps the symbol from the demultiplexer 25 to each signal point determined by the orthogonal modulation (multilevel modulation) modulation method performed by the orthogonal modulation unit 27.
  • mapping unit 26 displays symbols from the demultiplexer 25 on an IQ plane (IQ constellation) defined by an I axis representing an I component in phase with a carrier wave and a Q axis representing a Q component orthogonal to the carrier wave. Are mapped to signal points determined by the modulation method.
  • IQ plane IQ constellation
  • a modulation method of the orthogonal modulation performed by the orthogonal modulation unit 27 for example, a modulation method including a modulation method defined in the DVB-T standard, for example, QPSK (Quadrature Phase Shift Keying), There are 16QAM (Quadrature Amplitude Modulation), 64QAM, 256QAM, 1024QAM, 4096QAM, etc.
  • QPSK Quadrature Phase Shift Keying
  • 16QAM Quadrature Amplitude Modulation
  • 64QAM Quadrature Amplitude Modulation
  • 64QAM Quadrature Amplitude Modulation
  • 256QAM 256QAM
  • 1024QAM 1024QAM
  • 4096QAM 4096QAM
  • the symbol mapped to the signal point by the mapping unit 26 is supplied to the orthogonal modulation unit 27.
  • the quadrature modulation unit 27 performs quadrature modulation of the carrier according to the symbols from the mapping unit 26, and transmits a modulation signal obtained as a result.
  • FIG. 9 shows a parity check matrix H used for LDPC encoding in the LDPC encoding unit 21 of FIG.
  • LDGM Low-Density Generation Matrix
  • the number of information bits and the number of parity bits in the code bits of one LDPC code are referred to as information length K and parity length M, respectively, and one LDPC.
  • the information length K and the parity length M for an LDPC code having a certain code length N are determined by the coding rate.
  • the parity check matrix H is an M ⁇ N matrix with rows ⁇ columns. Then, the information matrix H A, becomes the matrix of M ⁇ K, the parity matrix H T is a matrix of M ⁇ M.
  • Figure 10 illustrates a parity matrix H T of the parity check matrix H of an LDPC code prescribed in the standard of DVB-S.2.
  • the row weight of the parity matrix H T is 1 for the first row and 2 for all the remaining rows.
  • the column weight is 1 for the last column and 2 for all the remaining columns.
  • LDPC codes of the check matrix H the parity matrix H T has a staircase structure can be using the check matrix H, readily produced.
  • an LDPC code (one codeword), together represented by a row vector c, and column vector obtained by transposing the row vector is represented as c T. Further, in the row vector c which is an LDPC code, the information bit portion is represented by the row vector A, and the parity bit portion is represented by the row vector T.
  • the row vector T can be represented by the row vector with the element of the row vector T on the right side.
  • FIG. 11 shows a parity check matrix H of LDPC codes and column weights defined in the DVB-S.2 standard.
  • a in FIG. 11 shows the parity check matrix H of the LDPC code defined in the DVB-S.2 standard.
  • the column weight is X
  • the column weight is 3
  • the column weight is 2
  • the column weight is 1, respectively.
  • KX + K3 + M-1 + 1 is equal to the code length N.
  • B in FIG. 11 shows the column numbers KX, K3, and M and the column weight X for each coding rate of the LDPC code defined in the DVB-S.2 standard.
  • the DVB-S.2 standard specifies LDPC codes with a code length N of 64800 bits and 16200 bits.
  • the LDPC encoding unit 21 waits for the target data to be supplied thereto, encodes the target data into an LDPC code in step S51, and supplies the LDPC code to the bit interleaver 22 for processing. Advances to step S52.
  • bit interleaver 22 bit interleaving is performed on the LDPC code from the LDPC encoding unit 21 in step S52.
  • step S52 in the bit interleaver 22, the demultiplexer 25 follows the assignment rule for assigning the code bit of the LDPC code to the symbol bit representing the symbol, and the code bit of the LDPC code from the LDPC encoding unit 21 is obtained.
  • a replacement process is performed in which the code bits after replacement are used as symbol bits of symbols (bits representing symbols).
  • the bit interleaver 22 supplies the symbol obtained by the replacement process to the mapping unit 26.
  • step S53 the mapping unit 26 maps the symbol from the demultiplexer 25 to a signal point determined by the modulation method of the orthogonal modulation performed by the orthogonal modulation unit 27, and supplies the signal point to the orthogonal modulation unit 27. Proceed to S54.
  • step S54 the quadrature modulation unit 27 performs quadrature modulation of the carrier wave in accordance with the signal point (mapped symbol) from the mapping unit 26, and the process proceeds to step S55, where the modulated signal obtained as a result of the quadrature modulation Is sent to finish the process.
  • the DVB-S.2 standard defines two types of LDPC codes with a code length N of 64800 bits and 16200 bits.
  • LDPC codes having a code length N of 64,800 bits eleven coding rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4 / 5, 5/6, 8/9, and 9/10 are defined, and for LDPC codes with a code length N of 16200 bits, 10 coding rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are defined (B in FIG. 11).
  • the LDPC encoding unit 21 performs such encoding (error correction encoding) using an LDPC code having a code length N of 64800 bits or 16200 bits for each code length and for each code rate. This is performed according to the prepared check matrix H.
  • FIG. 13 shows a configuration example of the LDPC encoding unit 21 of FIG.
  • the LDPC encoding unit 21 includes an encoding processing unit 101 and a storage unit 102.
  • the encoding processing unit 101 includes an encoding rate setting unit 111, an initial value table reading unit 112, a parity check matrix generation unit 113, an information bit reading unit 114, an encoded parity calculation unit 115, and a control unit 116.
  • the target data supplied to the conversion unit 21 is subjected to LDPC encoding, and the resulting LDPC code is supplied to the bit interleaver 22 (FIG. 8).
  • the coding rate setting unit 111 sets the code length N and the coding rate of the LDPC code in accordance with, for example, an operator's operation.
  • the initial value table reading unit 112 reads, from the storage unit 102, a parity check matrix initial value table (to be described later) corresponding to the code length N and the coding rate set by the coding rate setting unit 111.
  • the information bit reading unit 114 reads (extracts) information bits for the information length K from the target data supplied to the LDPC encoding unit 21.
  • the encoded parity calculation unit 115 reads the parity check matrix H generated by the parity check matrix generation unit 113 from the storage unit 102, calculates parity bits for the information bits read by the information bit reading unit 114 based on a predetermined formula, Generate a word (LDPC code).
  • LDPC code Generate a word
  • the control unit 116 controls each block constituting the encoding processing unit 101.
  • the storage unit 102 stores a plurality of parity check matrix initial value tables and the like corresponding to each of the plurality of coding rates shown in FIG. 11 for each of the two code lengths N of 64800 bits and 16200 bits. .
  • the storage unit 102 temporarily stores data necessary for the processing of the encoding processing unit 101.
  • FIG. 14 is a flowchart for explaining the processing of the LDPC encoding unit 21 of FIG.
  • step S101 the coding rate setting unit 111 determines (sets) a code length N and a coding rate r for performing LDPC coding.
  • step S102 the initial value table reading unit 112 reads, from the storage unit 102, a predetermined parity check matrix initial value table corresponding to the code length N and the coding rate r determined by the coding rate setting unit 111. .
  • step S103 the parity check matrix generation unit 113 uses the parity check matrix initial value table read from the storage unit 102 by the initial value table reading unit 112, and the code length N and the coding rate determined by the coding rate setting unit 111.
  • a parity check matrix H of the LDPC code of r is obtained (generated), supplied to the storage unit 102, and stored.
  • step S105 the encoded parity calculation unit 115 sequentially calculates the parity bits of the code word c satisfying the equation (8).
  • c represents a row vector as a code word (LDPC code), and c T represents transposition of the row vector c.
  • the information bit portion is represented by the row vector A and the parity bit portion is represented by the row vector T.
  • the code word c is 648000 bits or 16200 bits.
  • step S106 the control unit 116 determines whether or not to end the LDPC encoding. If it is determined in step S106 that the LDPC encoding is not finished, that is, for example, if there is still target data to be LDPC encoded, the process returns to step S101, and the processes of steps S101 to S106 are repeated thereafter. It is.
  • step S106 If it is determined in step S106 that the LDPC encoding is to be ended, that is, for example, if there is no target data to be LDPC encoded, the LDPC encoding unit 21 ends the process.
  • the parity check matrix initial value table corresponding to each code length N and each coding rate r is prepared, and the LDPC encoding unit 21 uses a predetermined code length N and a predetermined coding rate.
  • LDPC encoding of r is performed using a parity check matrix H generated from a parity check matrix initial value table corresponding to the predetermined code length N and the predetermined coding rate r.
  • the parity check matrix initial value table includes an information matrix H A corresponding to an information length K corresponding to the code length N of the LDPC code (LDPC code defined by the parity check matrix H) and the coding rate r of the parity check matrix H (FIG. 9). ) Is a table that represents the position of one element every 360 columns, and is created in advance for each check matrix H of each code length N and each coding rate r.
  • FIG. 15 to 18 show the parity check matrix initial values for the parity check matrix H defined in the DVB-S.2 standard and having the code length of 64,800 bits and the code rate r of 3/5 shown in FIG. Shows the table.
  • FIG. 16 is a diagram following FIG. 15
  • FIG. 17 is a diagram following FIG.
  • FIG. 18 is a figure following FIG.
  • FIG. 19 shows a parity check matrix initial value table for a parity check matrix H defined in the DVB-S.2 standard and having a code length of 16200 bits and a code rate r of 3/5 shown in FIG. ing.
  • Check matrix generation unit 113 obtains check matrix H using the check matrix initial value table as follows.
  • FIG. 20 shows a method for obtaining the parity check matrix H from the parity check matrix initial value table.
  • parity check matrix initial value table in FIG. 20 is the parity check matrix initial value table shown in FIG.
  • the parity check matrix initial value table includes 360 columns of positions of one element of the information matrix H A (FIG. 9) corresponding to the information length K corresponding to the code length N of the LDPC code and the coding rate r.
  • the row number of the 1 element in the 1 + 360 ⁇ (i ⁇ 1) column of the parity check matrix H (the row number of the first row of the parity check matrix H is set to 0).
  • Row number are arranged by the number of column weights of the 1 + 360 ⁇ (i ⁇ 1) th column.
  • the number of rows k + 1 in the parity check matrix initial value table differs depending on the information length K.
  • Equation (9) The relationship of Equation (9) is established between the information length K and the number k + 1 of rows in the parity check matrix initial value table.
  • the column weights of the parity check matrix H obtained from the parity check matrix initial value table in FIG. 20 are 12 from the first column to the 1 + 360 ⁇ (10 ⁇ 1) ⁇ 1 column, and 1 + 360 ⁇
  • the number from the (10-1) th column to the Kth column is 3.
  • the first row of the parity check matrix initial value table in FIG. 20 is 2765, 5713, 6426,..., Which means that the row numbers in the first column of the parity check matrix H are 2765, 5713, 6426,. This indicates that the element in the row of... Is 1 (and the other elements are 0).
  • the row number is 1495, 211, 2208,...
  • the parity check matrix initial value table represents the position of one element of the information matrix HA of the parity check matrix H for every 360 columns.
  • the 2 + 360 ⁇ (i-1) column is the 1 + 360 ⁇ (i-1) column cyclically shifted downward by M / 360
  • the following 3 + 360 ⁇ (i-1) column is 1 + 360 ⁇ (i-1) column cyclically shifted downward by 2 ⁇ M / 360 (2 + 360 ⁇ (i-1) column
  • the eye is cyclically shifted downward by M / 360).
  • the numerical value of the i-th row (i-th from the top) and j-th column (j-th from the left) of the parity check matrix initial value table is represented as h i, j and j items in the w-th column of the parity check matrix H. If the row number of the first element is represented as H wj , the row number H of the first element in the w column, which is a column other than the 1 + 360 ⁇ (i ⁇ 1) column of the parity check matrix H wj can be obtained by Expression (10).
  • mod (x, y) means a remainder obtained by dividing x by y
  • q represents a value M / 360 obtained by dividing the parity length M by 360.
  • the parity check matrix generation unit 113 (FIG. 13) specifies the row number of the 1 element in the 1 + 360 ⁇ (i ⁇ 1) column of the parity check matrix H using the parity check matrix initial value table.
  • the parity check matrix generation unit 113 calculates the row number H wj of one element of the w column that is a column other than the 1 + 360 ⁇ (i ⁇ 1) column of the parity check matrix H by the formula ( 10) to generate a parity check matrix H in which the element of the row number obtained as described above is 1.
  • the error rate (error probability) is lower as the code bit corresponding to the column having the larger column weight of the check matrix H.
  • the column weight on the head side (left side) tends to be large, and therefore corresponds to the parity check matrix H.
  • the first code bit tends to be more resistant to errors (is more resistant to errors), and the last code bit tends to be weaker to errors.
  • FIG. 21 shows an arrangement on the IQ plane of 16 symbols (corresponding signal points) when 16QAM is performed by the orthogonal modulation unit 27 of FIG.
  • a in FIG. 21 indicates a 16QAM symbol.
  • the 16 symbols are arranged so that the I direction ⁇ Q direction is a 4 ⁇ 4 square shape with the origin of the IQ plane as the center.
  • the four bits represented by one symbol of 16QAM are bit y 0 in order from the most significant bit. , y 1 , y 2 , y 3 .
  • the modulation method is 16QAM
  • the 4 bits of the code bits of the LDPC code are converted into 4 bits y 0 to y 3 symbols.
  • FIG. 21B shows bit boundaries for 4 bits (hereinafter also referred to as symbol bits) y 0 to y 3 represented by 16QAM symbols.
  • the symbol bit y i represented by a symbol is more likely to be erroneous (lower error probability) as there are more symbols far from the bit boundary, and more likely to be erroneous (higher error probability) as there are more symbols near the bit boundary.
  • strong to errors a bit that is hard to error
  • weak to errors a bit that is easy to error
  • 4 symbol bits y 0 to y 3 of a 16QAM symbol 4 symbol bits y 0 to y 3 of a 16QAM symbol .
  • the most significant symbol bit y 0 and the second symbol bit y 1 are strong bits
  • the third symbol bit y 2 and the fourth symbol bit y 3 are weak bits. .
  • One symbol bit of 64QAM can be expressed as bits y 0 , y 1 , y 2 , y 3 , y 4 , y 5 in order from the most significant bit.
  • the 6 code bits of the LDPC code are the symbol bit y 0 no 6-bit to the symbol y 5.
  • FIG. 22 shows bit boundaries for the most significant symbol bit y 0 and the second symbol bit y 1 among the symbol bits y 0 to y 5 of the 64QAM symbol, and FIG. th symbol bit y 2, the bit boundaries for the fourth symbol bit y 3, respectively, FIG. 24, the fifth symbol bit y 4, the bit boundaries for the sixth symbol bit y 5, respectively, each Show.
  • the symbol bits y 0 of the uppermost bit boundaries for the second symbol bit y 1, respectively, has at one place. Also, as shown in FIG. 23, there are two bit boundaries for the third symbol bit y 2 and the fourth symbol bit y 3 , and the fifth symbol bit is shown in FIG. There are four bit boundaries for bit y 4 and sixth symbol bit y 5 .
  • the most significant symbol bit y 0 and the second symbol bit y 1 are strong bits, and the third symbol bits y 2 and 4 th symbol bit y 3 has become a strong bit to the next.
  • the fifth symbol bit y 4 and the sixth symbol bit y 5 are weak bits.
  • the LDPC code output from the LDPC encoding unit 21 includes a code bit resistant to errors and a code bit vulnerable to errors.
  • the symbol bits of the orthogonal modulation symbol performed by the orthogonal modulation unit 27 include a strong bit and a weak bit.
  • FIG. 25 is a diagram for explaining the processing of the demultiplexer 25 in FIG.
  • a in FIG. 25 shows a functional configuration example of the demultiplexer 25.
  • the demultiplexer 25 includes a memory 31 and a replacement unit 32.
  • the memory 31 is supplied with the LDPC code from the LDPC encoding unit 21.
  • the memory 31 has a storage capacity for storing mb bits in the row (horizontal) direction and N / (mb) bits in the column (vertical) direction, and the LDPC supplied thereto The sign bit of the code is written in the column direction, read in the row direction, and supplied to the switching unit 32.
  • m represents the number of code bits of the LDPC code that is one symbol
  • b is a predetermined positive integer, which is a multiple used to multiply m by an integer.
  • N represents the code length of the LDPC code as described above.
  • FIG. 25A shows a configuration example of the demultiplexer 25 when the modulation scheme is 64QAM. Therefore, the number m of code bits of the LDPC code that is one symbol is 6 bits.
  • the multiple b is 1. Therefore, the memory 31 has a storage capacity of N / (6 ⁇ 1) ⁇ (6 ⁇ 1) bits in the column direction ⁇ row direction.
  • the storage area of the memory 31 extending in the column direction and having a 1-bit row direction is hereinafter referred to as a column as appropriate.
  • the code bits of the LDPC code are written from the top to the bottom (column direction) of the columns constituting the memory 31 from the left to the right columns.
  • the sign bit When writing of the sign bit is completed to the bottom of the rightmost column, the sign bit is changed in units of 6 bits (mb bits) in the row direction from the first row of all the columns constituting the memory 31. It is read out and supplied to the replacement unit 32.
  • the exchanging unit 32 performs an exchanging process of exchanging the positions of the 6-bit code bits from the memory 31, and the 6 bits obtained as a result are replaced with 6 symbol bits y 0 , y 1 , y 2 , y representing one symbol of 64QAM. Output as 3 , y 4 , y 5 .
  • mb bits (6 bits in this case) of code bits are read from the memory 31 in the row direction, and the i-th bit from the most significant bit of the mb bits of code bits read from the memory 31 is read out.
  • bit b i the 6-bit code bits read out from the memory 31 in the row direction are bits b 0 , It can be expressed as b 1 , b 2 , b 3 , b 4 , b 5 .
  • the sign bit in the direction of bit b 0 is a sign bit that is resistant to errors
  • the sign bit in the direction of bit b 5 is a sign bit that is vulnerable to errors. ing.
  • the 6-bit code bits b 0 to b 5 from the memory 31 are assigned the error-sensitive code bits to the strong bits of the 64QAM 1-symbol symbol bits y 0 to y 5. As shown in the figure, it is possible to perform an exchange process for exchanging the positions of the 6-bit code bits b 0 to b 5 from the memory 31.
  • FIG. 25B shows the first replacement method
  • FIG. 25C shows the second replacement method
  • FIG. 25D shows the third replacement method.
  • FIG. 26 shows a case where the modulation scheme is 64QAM (therefore, the number m of code bits of the LDPC code mapped to one symbol is 6 bits as in FIG. 25) and the multiple b is 2.
  • the demultiplexer 25 and a fourth replacement method are shown.
  • FIG. 26A shows the order of writing LDPC codes to the memory 31.
  • the code bits of the LDPC code are written from the top to the bottom (column direction) of the columns constituting the memory 31, and the rows from the left to the right Is called.
  • the sign bit When the writing of the sign bit is completed to the bottom of the rightmost column, the sign bit is set in units of 12 bits (mb bits) in the row direction from the first row of all the columns constituting the memory 31. It is read out and supplied to the replacement unit 32.
  • the exchanging unit 32 performs an exchanging process of exchanging the positions of the 12-bit code bits from the memory 31 by the fourth exchanging method, and the 12 bits obtained as a result represent 2 symbols (b symbols) of 64QAM. 12 bits, that is, 6 symbol bit y 0 representing a symbol of 64QAM, y 1, y 2, y 3, y 4, and y 5, 6 symbol bits y 0 representing the next one symbol, y 1, y 2 , y 3 , y 4 , y 5
  • B of FIG. 26 shows a fourth replacement method of the replacement processing by the replacement unit 32 of A of FIG.
  • mb code bits are allocated to mb symbol bits of b consecutive symbols.
  • bit (symbol bit) y i the (i + 1) th bit from the most significant bit of the mb bit of b consecutive symbols.
  • the LDPC code of the parity check matrix H having the coding rate r of 3/5 obtained from the parity check matrix initial value table defined in the DVB-S.2 standard shown in FIGS. It is known that the performance is inferior to the LDPC code with the coding rate of.
  • the code bit replacement method is determined without considering that the performance of the LDPC code with a coding rate r of 3/5 is inferior. Yes.
  • FIG. 27 shows an example of replacement processing of the current method when the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5.
  • a of FIG. 27 is an LDPC code in which the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and the modulation scheme is 16QAM, and the multiple b is 2.
  • the replacement process of the current method is shown.
  • the replacement unit 32 Sign bit b 0 to symbol bit y 7 Sign bit b 1 to symbol bit y 1 Sign bit b 2 to symbol bit y 4 Sign bit b 3 to symbol bit y 2 Sign bit b 4 to symbol bit y 5 Sign bit b 5 to symbol bit y 3 Sign bit b 6 into symbol bit y 6
  • the sign bit b 7 to the symbol bit y 0 Replace each assigned.
  • 27B shows an LDPC code in which the code length N is 64800 bits and the code rate is 3/5, and the modulation method is 64QAM and the multiple b is 2. Shows an example of the replacement process.
  • the replacement unit 32 Sign bit b 0 to symbol bit y 11 Sign bit b 1 to symbol bit y 7 Sign bit b 2 to symbol bit y 3 Sign bit b 3 to symbol bit y 10 Sign bit b 4 to symbol bit y 6 Sign bit b 5 to symbol bit y 2 Sign bit b 6 to symbol bit y 9 Sign bit b 7 to symbol bit y 5 Sign bit b 8 to symbol bit y 1 Sign bit b 9 to symbol bit y 8 Sign bit b 10 to symbol bit y 4
  • the sign bit b 11 to the symbol bit y 0 Replace each assigned.
  • 27C shows an LDPC code in which the code length N is 64800 bits, the code rate is 3/5, and the modulation scheme is 256QAM, and the multiple b is 2. Shows an example of the replacement process.
  • the replacement unit 32 Sign bit b 0 to symbol bit y 15 Sign bit b 1 to symbol bit y 1 Sign bit b 2 into symbol bit y 13 Sign bit b 3 to symbol bit y 3 Sign bit b 4 to symbol bit y 8 Sign bit b 5 to symbol bit y 11 Sign bit b 6 to symbol bit y 9 Sign bit b 7 to symbol bit y 5 Sign bit b 8 to symbol bit y 10 Sign bit b 9 to symbol bit y 6 Sign bit b 10 to symbol bit y 4 Sign bit b 11 to symbol bit y 7 Sign bit b 12 into symbol bit y 12 The sign bit b 13 into the symbol bit y 2 Sign bit b 14 into symbol bit y 14 The sign bit b 15 to the symbol bit y 0 Replace each assigned.
  • FIG. 28 shows an example of the current system replacement process when the LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/5.
  • a in FIG. 28 is an LDPC code in which the code length N is 16200 bits, the code rate is 3/5, and the modulation scheme is 16QAM, and the multiple b is 2.
  • An example of the replacement process of the current method is shown.
  • the replacement unit 32 performs replacement for assigning the code bits b 0 to b 7 to the symbol bits y 0 to y 7 as in the case of A in FIG.
  • FIG. 28B shows a case where the LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/5, and further switching the current method when the modulation method is 64QAM and the multiple b is 2. An example of processing is shown.
  • the replacement unit 32 performs replacement for assigning the code bits b 0 to b 11 to the symbol bits y 0 to y 11 as in the case of B in FIG. 27 described above.
  • C in FIG. 28 is an LDPC code in which the LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/5, and further when the modulation method is 256QAM and the multiple b is 1.
  • An example of a replacement process is shown.
  • the replacement unit 32 Sign bit b 0 to symbol bit y 7 Sign bit b 1 to symbol bit y 3 Sign bit b 2 to symbol bit y 1 Sign bit b 3 to symbol bit y 5 Sign bit b 4 to symbol bit y 2 Sign bit b 5 to symbol bit y 6 Sign bit b 6 to symbol bit y 4
  • the sign bit b 7 to the symbol bit y 0 Replace each assigned.
  • the coding rate r is It is hard to say that the 3/5 LDPC code is highly resistant to errors.
  • the demultiplexer 25 in FIG. 8 performs a replacement process using the new replacement method described below.
  • the LDPC code with a coding rate r of 3/5 is resistant to symbol errors. Has come to improve.
  • the replacement unit 32 of the demultiplexer 25 performs replacement of the mb bit code bits according to a predetermined allocation rule.
  • Allocation rules are rules for allocating code bits of LDPC codes to symbol bits.
  • a group set that is a combination of a code bit group of a code bit and a symbol bit group of a symbol bit to which a code bit of the code bit group is allocated, and each of the code bit group and the symbol bit group of the group set.
  • the number of code bits and the number of symbol bits (hereinafter also referred to as the number of group bits) are defined.
  • the code bit group is a group that groups the code bits according to the error probability
  • the symbol bit group is a group that groups the symbol bits according to the error probability
  • FIG. 29 shows an LDPC code in which the code length N is 64800 bits, the LDPC code has a coding rate of 3/5, the modulation scheme is 16QAM, and the multiple b is 2. Symbol bit group.
  • the sign bit group Gb 1 includes the sign bit b 0
  • the sign bit group Gb 2 includes the sign bit b 1
  • the sign bit group Gb 3 includes the sign bits b 2 and b 3.
  • the code bit group Gb 4 includes the code bit b 4
  • the code bit group Gb 5 includes the code bits b 5 to b 7 .
  • symbol bit group Gy 1 includes symbol bits y 0 , y 1 , y 4 , and y 5
  • symbol bit group Gy 2 includes symbol bits y 2 , y 3 , y 6 , and y 7. Belong to each.
  • FIG. 30 shows an allocation rule when the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, a modulation scheme of 16QAM, and a multiple b of 2. ing.
  • the combination of the code bit group Gb 1 and the symbol bit group Gy 1 is defined as one group set.
  • the number of group bits of the group set is defined as 1 bit.
  • group set information the group set and the number of group bits are collectively referred to as group set information.
  • group set information the group set of the sign bit group Gb 1 and the symbol bit group Gy 1 and 1 bit which is the number of group bits of the group set are described as group set information (Gb 1 , Gy 1 , 1).
  • group set information (Gb 1 , Gy 1 , 1), group set information (Gb 2 , Gy 1 , 1), (Gb 3 , Gy 1 , 1), (Gb 3 , Gy 2 , 1), (Gb 4 , Gy 2 , 1), (Gb 5 , Gy 1 , 1), (Gb 5 , Gy 2 , 2) are defined.
  • the group set information (Gb 1 , Gy 1 , 1) means that one bit of a code bit belonging to the code bit group Gb 1 is assigned to one bit of a symbol bit belonging to the symbol bit group Gy 1 .
  • the code bit group is a group that groups the code bits according to the error probability
  • the symbol bit group is a group that groups the symbol bits according to the error probability. Therefore, it can be said that the allocation rule defines a combination of an error probability of a code bit and an error probability of a symbol bit to which the code bit is allocated.
  • the allocation rule that defines the combination of the error probability of the code bit and the error probability of the symbol bit to which the code bit is assigned is determined so as to improve the resistance to errors (resistance to noise).
  • group set information that minimizes the BER (Bit Error Rate), that is, the sign bit group of the sign bit and the symbol bit group of the symbol bit to which the sign bit of the sign bit group is assigned And the number of sign bits and the number of symbol bits (number of group bits) of each group bit set (group set) and the symbol bit group of the group set are defined as allocation rules.
  • the code bits may be exchanged so that the code bits are assigned to the symbol bits.
  • FIG. 31 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 31 is an LDPC code in which the code length N is 64800 bits and the coding rate is 3/5, and the modulation scheme is 16QAM and the multiple b is 2.
  • FIG. 30 shows a first example of code bit replacement according to the allocation rule of FIG. 30.
  • the LDPC code is an LDPC code having a code length N of 64,800 bits, a coding rate of 3/5, and a modulation scheme of 16QAM and a multiple b of 2, as described with reference to FIG.
  • the replacement unit 32 Sign bit b 0 to symbol bit y 0 Sign bit b 1 to symbol bit y 1 Sign bit b 2 to symbol bit y 4 Sign bit b 3 to symbol bit y 2 Sign bit b 4 to symbol bit y 3 Sign bit b 5 to symbol bit y 5 Sign bit b 6 into symbol bit y 6 Sign bit b 7 to symbol bit y 7 Replace each assigned.
  • B in FIG. 31 is an LDPC code in which the code length N is 64800 bits, the coding rate is 3/5, the modulation scheme is 16QAM, and the multiple b is 2. 2 shows a second example of exchanging code bits according to the allocation rule.
  • Sign bit b 0 to symbol bit y 5 Sign bit b 1 to symbol bit y 1 Sign bit b 2 to symbol bit y 4 Sign bit b 3 into symbol bit y 7
  • Sign bit b 4 to symbol bit y 6 Sign bit b 5 to symbol bit y 0
  • Sign bit b 7 into symbol bit y 2 Replace each assigned.
  • the allocation method of the sign bit b i to the symbol bit y i shown in A of FIG. 31 and B of FIG. 32 is in accordance with the allocation rule of FIG. 30 (observing the allocation rule). ).
  • FIG. 32 shows an LDPC code in which the code length N is 64800 bits, the code rate is 3/5, and the code bit group when the modulation method is 64QAM and the multiple b is 2. Symbol bit group.
  • the sign bit group Gb 1 includes the sign bits b 0 and b 1
  • the sign bit group Gb 2 includes the sign bit b 2
  • the sign bit group Gb 3 includes the sign bits b 3 to b 3 .
  • b 6 is the sign bit group Gb 4
  • the code bit b 7 is the sign bit group Gb 5, to no code bit b 8 b 11 are each belonging.
  • symbol bit group Gy 1 includes symbol bits y 0 , y 1 , y 6 , and y 7
  • symbol bit group Gy 2 includes symbol bits y 2 , y 3 , y 8 , and y 9.
  • symbol bits y 4 , y 5 , y 10 , and y 11 belong to the symbol bit group Gy 3 , respectively.
  • FIG. 33 shows an allocation rule when the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, a modulation scheme of 64QAM, and a multiple b of 2. ing.
  • group set information (Gb 1 , Gy 1 , 1), (Gb 1 , Gy 2 , 1), (Gb 2 , Gy 1 , 1), (Gb 3 , Gy 1 , 2), (Gb 3 , Gy 2 , 2), (Gb 4 , Gy 3 , 1), (Gb 5 , Gy 2 , 1), (Gb 5 , Gy 3 , 3) are defined.
  • FIG. 34 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 34 is an LDPC code in which the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and further, when the modulation scheme is 64QAM and the multiple b is 2.
  • FIG. 34 shows a first example of code bit replacement according to the allocation rule of FIG.
  • the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and further, when the modulation scheme is 64QAM and the multiple b is 2, as described with reference to FIG.
  • the replacement unit 32 Sign bit b 0 to symbol bit y 2 Sign bit b 1 to symbol bit y 0 Sign bit b 2 to symbol bit y 1 Sign bit b 3 into symbol bit y 6 Sign bit b 4 to symbol bit y 7 Sign bit b 5 to symbol bit y 3 Sign bit b 6 to symbol bit y 8 Sign bit b 7 to symbol bit y 4 Sign bit b 8 to symbol bit y 5 Sign bit b 9 to symbol bit y 10 Sign bit b 10 to symbol bit y 9 Sign bit b 11 to symbol bit y 11 Replace each assigned.
  • B in FIG. 34 is an LDPC code in which the code length N is 64800 bits, the code rate is 3/5, and the modulation scheme is 64QAM, and the multiple b is 2. 2 shows a second example of exchanging code bits according to the allocation rule.
  • Sign bit b 0 to symbol bit y 9 Sign bit b 1 to symbol bit y 0
  • Sign bit b 2 into symbol bit y 7
  • Sign bit b 3 into symbol bit y 6
  • Sign bit b 4 to symbol bit y 1
  • Sign bit b 6 to symbol bit y 8 Sign bit b 7 to symbol bit y 10
  • Sign bit b 10 to symbol bit y 2 Sign bit b 11 to symbol bit y 11 Replace each assigned.
  • FIG. 35 illustrates an LDPC code in which the code length N is 64800 bits, the LDPC code has a coding rate of 3/5, the modulation scheme is 256QAM, and the multiple b is 2. Symbol bit group.
  • code bit group Gb 1 includes code bits b 0 to b 2
  • code bit group Gb 2 includes code bit b 3
  • code bit group Gb 3 includes code bits b 4 to b 4
  • b 8 is the sign bit group Gb 4
  • the code bit b 9 is, the code bit group Gb 5
  • the code bit b 10 to b 15 are each belonging.
  • symbol bit group Gy 1 includes symbol bits y 0 , y 1 , y 8 , and y 9
  • symbol bit group Gy 2 includes symbol bits y 2 , y 3 , y 10 , and y 11.
  • symbol bit group Gy 3 includes symbol bits y 4 , y 5 , y 12 , and y 13
  • symbol bit group Gy 4 includes symbol bits y 6 , y 7 , y 14 , and y 15 , respectively. .
  • FIG. 36 shows an allocation rule when the LDPC code is an LDPC code having a code length N of 64,800 bits, a coding rate of 3/5, a modulation scheme of 256QAM, and a multiple b of 2. ing.
  • the group set information (Gb 1 , Gy 1 , 1), (Gb 1 , Gy 2 , 1), (Gb 1 , Gy 3 , 1), (Gb 2 , Gy 3 , 1), (Gb 3 , Gy 1 , 2), (Gb 3 , Gy 2 , 3), (Gb 4 , Gy 1 , 1), (Gb 5 , Gy 3 , 2), (Gb 5 , Gy 4 , 4) It is prescribed.
  • FIG. 37 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 37 is an LDPC code in which the code length N is 64800 bits and the coding rate is 3/5, and the modulation scheme is 256QAM and the multiple b is 2. 37 shows a first example of code bit replacement according to the allocation rule of FIG.
  • the LDPC code is an LDPC code having a code length N of 64,800 bits, a coding rate of 3/5, and a modulation scheme of 256QAM and a multiple b of 2, as described with reference to FIG.
  • the replacement unit 32 Sign bit b 0 to symbol bit y 8 Sign bit b 1 to symbol bit y 3 Sign bit b 2 into symbol bit y 12 Sign bit b 3 to symbol bit y 4 Sign bit b 4 to symbol bit y 10 Sign bit b 5 to symbol bit y 2 Sign bit b 6 to symbol bit y 9 Sign bit b 7 to symbol bit y 1 Sign bit b 8 to symbol bit y 11 Sign bit b 9 into symbol bit y 0 Sign bit b 10 into symbol bit y 13 Sign bit b 11 to symbol bit y 5 Sign bit b 12 to symbol bit y 14 Sign bit b 13 into symbol bit y 6 Sign bit b 14 into symbol bit y 15 Sign bit b 15 to symbol bit y 7 Replace each assigned.
  • B in FIG. 37 is an LDPC code in which the code length N is 64800 bits and the coding rate is 3/5, and the modulation scheme is 256QAM and the multiple b is 2. 2 shows a second example of exchanging code bits according to the allocation rule.
  • Sign bit b 0 to symbol bit y 1 Sign bit b 1 to symbol bit y 3
  • Sign bit b 2 to symbol bit y 5
  • Sign bit b 4 to symbol bit y 10
  • Sign bit b 8 to symbol bit y 11 Sign bit b 9 into symbol bit y 0
  • the sign bit b 11 is changed to the symbol bit y 13
  • Sign bit b 12 to symbol bit y 7
  • Sign bit b 13 Sign bit b 13 into symbol bit y 6
  • Sign bit b 14 into symbol bit y 15
  • Sign bit b 15 into symbol bit y 14 Replace each assigned
  • FIG. 38 shows an LDPC code in which the code length N is 16200 bits, the code rate is 3/5, and the code bit group in the case where the modulation scheme is 16QAM and the multiple b is 2. Symbol bit group.
  • the code bit group Gb 1 is the sign bit group Gb 2
  • the code bit b 1 is the sign bit group Gb 3
  • the code bits b 2 and b 3 belong to the code bit group Gb 4
  • the code bit b 4 belongs to the code bit group Gb 5
  • the code bits b 5 to b 7 belong to the code bit group Gb 5 .
  • symbol bit group Gy 1 includes symbol bits y 0 , y 1 , y 4 , and y 5
  • symbol bit group Gy 2 includes symbol bit y. 2 , y 3 , y 6 and y 7 belong respectively.
  • FIG. 39 shows an allocation rule when the LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/5, a modulation scheme of 16QAM, and a multiple b of 2. ing.
  • the group set information (Gb 1 , Gy 1 , 1), (Gb 2 , Gy 1 , 1), (Gb 3 , Gy 1 , 1), ( Gb 3 , Gy 2 , 1), (Gb 4 , Gy 2 , 1), (Gb 5 , Gy 1 , 1), (Gb 5 , Gy 2 , 2) are defined.
  • FIG. 40 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 40 is an LDPC code in which the code length N is 16200 bits and the coding rate is 3/5, and the modulation scheme is 16QAM, and the multiple b is 2.
  • FIG. 40 shows a first example of code bit replacement according to the assignment rule of FIG.
  • the LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/5, and further having a modulation scheme of 16QAM and a multiple b of 2, as described with reference to FIG.
  • the replacement unit 32 is similar to the case of A in FIG. Sign bit b 0 to symbol bit y 0 Sign bit b 1 to symbol bit y 1 Sign bit b 2 to symbol bit y 4 Sign bit b 3 to symbol bit y 2 Sign bit b 4 to symbol bit y 3 Sign bit b 5 to symbol bit y 5 Sign bit b 6 into symbol bit y 6 Sign bit b 7 to symbol bit y 7 Replace each assigned.
  • B in FIG. 40 is an LDPC code in which the code length N is 16200 bits and the coding rate is 3/5, and the modulation scheme is 16QAM and the multiple b is 2. 2 shows a second example of exchanging code bits according to the allocation rule.
  • FIG. 41 shows an LDPC code in which the code length N is 16200 bits, the code rate is 3/5, and the code bit group when the modulation scheme is 64QAM and the multiple b is 2. Symbol bit group.
  • code bit group Gb 1 includes code bits b 0 and b 1
  • code bit group Gb 2 includes code bit b 2
  • code bit group the Gb 3 the code bit b 3 to b 6 are
  • the code bit group Gb 4 the code bit b 7 is the sign bit group Gb 5, to no code bit b 8 b 11 are each belonging.
  • symbol bit group Gy 1 includes symbol bits y 0 , y 1 , y 6 , and y 7
  • symbol bit group Gy 2 includes symbol bit y.
  • y 3 y 8
  • y 9 is the symbol bit group Gy 3
  • the symbol bits y 4, y 5, y 10 , y 11 are each belonging.
  • FIG. 42 shows an allocation rule when the LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/5, and further, the modulation scheme is 64QAM and the multiple b is 2. ing.
  • the group set information (Gb 1 , Gy 1 , 1), (Gb 1 , Gy 2 , 1), (Gb 2 , Gy 1 , 1), (Gb 3 , Gy 1 , 2), (Gb 3 , Gy 2 , 2), (Gb 4 , Gy 3 , 1), (Gb 5 , Gy 2 , 1), (Gb 5 , Gy 3 , 3) ing.
  • FIG. 43 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 43 is an LDPC code in which the code length N is 16200 bits, the code rate is 3/5, and the modulation scheme is 64QAM, and the multiple b is 2. 43 shows a first example of code bit replacement in accordance with the assignment rule of FIG.
  • the LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/5, and further having a modulation scheme of 64QAM and a multiple b of 2, as described with reference to FIG.
  • the replacement unit 32 is similar to the case of A in FIG. Sign bit b 0 to symbol bit y 2 Sign bit b 1 to symbol bit y 0 Sign bit b 2 to symbol bit y 1 Sign bit b 3 into symbol bit y 6 Sign bit b 4 to symbol bit y 7 Sign bit b 5 to symbol bit y 3 Sign bit b 6 to symbol bit y 8 Sign bit b 7 to symbol bit y 4 Sign bit b 8 to symbol bit y 5 Sign bit b 9 to symbol bit y 10 Sign bit b 10 to symbol bit y 9 Sign bit b 11 to symbol bit y 11 Replace each assigned.
  • B in FIG. 43 is an LDPC code in which the code length N is 16200 bits, the code rate is 3/5, the modulation scheme is 64QAM, and the multiple b is 2. 2 shows a second example of exchanging code bits according to the allocation rule.
  • Sign bit b 0 to symbol bit y 9 Sign bit b 1 to symbol bit y 0
  • Sign bit b 2 into symbol bit y 7
  • Sign bit b 3 into symbol bit y 6
  • Sign bit b 4 to symbol bit y 1
  • Sign bit b 6 to symbol bit y 8 Sign bit b 7 to symbol bit y 10
  • Sign bit b 10 to symbol bit y 2 Sign bit b 11 to symbol bit y 11
  • FIG. 44 shows code bit groups when the LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/5, a modulation scheme of 256QAM, and a multiple b of 1. Symbol bit group.
  • the sign bit group Gb 1 includes the sign bit b 0
  • the sign bit group Gb 2 includes the sign bit b 1
  • the sign bit group Gb 3 includes the sign bits b 2 and b 3.
  • the code bit group Gb 4 includes the code bit b 4
  • the code bit group Gb 5 includes the code bits b 5 to b 7 .
  • symbol bit group Gy 1 includes symbol bits y 0 and y 1
  • symbol bit group Gy 2 includes symbol bits y 2 and y 3
  • symbol bit group Gy 3 includes symbol bits.
  • y 4, y 5 are the symbol bit group Gy 4, the symbol bits y 6, y 7 are respectively belong.
  • FIG. 45 shows an allocation rule when the LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/5, a modulation scheme of 256QAM, and a multiple b of 1. ing.
  • group set information (Gb 1 , Gy 2 , 1), (Gb 2 , Gy 3 , 1), (Gb 3 , Gy 1 , 1), (Gb 3 , Gy 4 , 1), (Gb 4 , Gy 4 , 1), (Gb 5 , Gy 1 , 1), (Gb 5 , Gy 2 , 1), (Gb 5 , Gy 3 , 1) are defined.
  • FIG. 46 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 46 is an LDPC code in which the code length N is 16200 bits, the code rate is 3/5, and the modulation scheme is 256QAM, and the multiple b is 1. 46 shows a first example of code bit replacement according to the allocation rule of FIG.
  • the LDPC code is an LDPC code with a code length N of 16200 bits and a coding rate of 3/5, and further when the modulation scheme is 256QAM and the multiple b is 1, as described with reference to FIG.
  • the replacement unit 32 Sign bit b 0 to symbol bit y 2 Sign bit b 1 to symbol bit y 4 Sign bit b 2 to symbol bit y 0 Sign bit b 3 into symbol bit y 6 Sign bit b 4 to symbol bit y 7 Sign bit b 5 to symbol bit y 1 Sign bit b 6 to symbol bit y 3 Sign bit b 7 to symbol bit y 5 Replace each assigned.
  • B in FIG. 46 is an LDPC code in which the code length N is 16200 bits, the coding rate is 3/5, the modulation scheme is 256QAM, and the multiple b is 1. 2 shows a second example of exchanging code bits according to the allocation rule.
  • Sign bit b 0 to symbol bit y 3 Sign bit b 1 to symbol bit y 4 Sign bit b 2 to symbol bit y 1 Sign bit b 3 into symbol bit y 7
  • Sign bit b 4 to symbol bit y 6 Sign bit b 5 to symbol bit y 0
  • Sign bit b 7 to symbol bit y 5 Replace each assigned.
  • 47 and 48 show the results of BER simulations when the replacement process is performed in each of the current method and the new replacement method.
  • the horizontal axis represents E s / N 0 (signal power to noise power ratio per symbol), and the vertical axis represents BER.
  • the solid line represents the BER of the new replacement method, and the dotted line represents the BER of the current method.
  • FIG. 47 shows the BER when the replacement process for an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5 is performed for each of 16QAM, 64QAM, and 256QAM modulation schemes. Yes.
  • the multiple b is 2 for all of 16QAM, 64QAM, and 256QAM.
  • FIG. 48 shows the BER when the replacement process for an LDPC code having a code length N of 16200 bits and a coding rate of 3/5 is performed for each of 16QAM, 64QAM, and 256QAM modulation schemes. Yes.
  • the multiple b is 2 for 16QAM and 64QAM, and 1 for 256QAM.
  • the new replacement method has an improved BER as compared with the current method, and therefore an improved tolerance to errors.
  • the replacement unit 32 performs the replacement process for the code bit read from the memory 31, but the replacement process is performed in the memory 31. This can be done by controlling the writing and reading of the sign bit for.
  • the replacement process can be performed, for example, by controlling the address (read address) from which the code bits are read so that the code bits are read from the memory 31 in the order of the code bits after the replacement.
  • FIG. 49 shows a configuration example of an embodiment of a computer in which a program for executing the series of processes described above is installed.
  • the program can be recorded in advance in a hard disk 705 or a ROM 703 as a recording medium built in the computer.
  • the program is stored temporarily on a removable recording medium 711 such as a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disc, a DVD (Digital Versatile Disc), a magnetic disc, or a semiconductor memory. It can be stored permanently (recorded).
  • a removable recording medium 711 can be provided as so-called package software.
  • the program is installed in the computer from the removable recording medium 711 as described above, or transferred from the download site to the computer wirelessly via a digital satellite broadcasting artificial satellite, LAN (Local Area Network),
  • the program can be transferred to a computer via a network such as the Internet.
  • the computer can receive the program transferred in this way by the communication unit 708 and install it in the built-in hard disk 705.
  • the computer has a CPU (Central Processing Unit) 702 built-in.
  • An input / output interface 710 is connected to the CPU 702 via a bus 701, and the CPU 702 operates an input unit 707 including a keyboard, a mouse, a microphone, and the like by the user via the input / output interface 710.
  • a program stored in a ROM (Read Only Memory) 703 is executed accordingly.
  • the CPU 702 may be a program stored in the hard disk 705, a program transferred from a satellite or a network, received by the communication unit 708 and installed in the hard disk 705, or a removable recording medium 711 installed in the drive 709.
  • the program read and installed in the hard disk 705 is loaded into a RAM (Random Access Memory) 704 and executed.
  • the CPU 702 performs processing according to the above-described flowchart or processing performed by the configuration of the above-described block diagram.
  • the CPU 702 outputs the processing result from an output unit 706 configured with an LCD (Liquid Crystal Display), a speaker, or the like via an input / output interface 710, for example, or from a communication unit 708 as necessary. Transmission and further recording on the hard disk 705 are performed.
  • processing steps for describing a program for causing a computer to perform various types of processing do not necessarily have to be processed in time series according to the order described in the flowchart, but in parallel or individually. This includes processing to be executed (for example, parallel processing or processing by an object).
  • the program may be processed by a single computer, or may be processed in a distributed manner by a plurality of computers. Furthermore, the program may be transferred to a remote computer and executed.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Error Detection And Correction (AREA)

Abstract

L'invention porte sur un dispositif et un procédé de traitement de données dans lesquels la résistance à une erreur de données peut être améliorée. Un démultiplexeur (25) réarrange mb bits de bits de code et définit les bits de code réarrangés en tant que b éléments de symboles de bits de symbole conformément à une règle d'attribution pour attribuer les bits de code d'un code LDPC à des bits de symbole représentant des symboles. La règle d'attribution définit des groupes pour regrouper les bits de code et les bits de symbole conformément à une probabilité d'erreur sous la forme d'un groupe de bits de code et d'un groupe de bits de symbole, respectivement, une combinaison du groupe de bits de code et du groupe de bits de symbole de bits de symbole afin d'attribuer les bits de code du groupe de bits de code, et le nombre de bits de bits de code et de bits de symbole. Le dispositif et le procédé de traitement de données peuvent être appliqués, par exemple, à un système de transmission ou analogue pour transmettre un code LDPC.
PCT/JP2008/071407 2008-03-18 2008-11-26 Dispositif de traitement de données et procédé de traitement de données WO2009116204A1 (fr)

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