TW200952349A - Data processing device and data processing method - Google Patents

Abstract

Provided are a data processing device and a data processing method that are configured to improve a tolerance to a data error. A demultiplexer (25) conforms to an allocation rule to allocate code bits of an LDPC code to symbol bits for the expression of symbols. When a code bit of 10 x 2 bits and the (i+1)-th bit from the most significant symbol bit of the 10 x 2 bits of successive two symbols are bi and yi, respectively, the demultiplexer (25) carries out the following replacement by allocating, for example, b0 to y8, b1 to y6, b2 to y0, b3 to y1, b4 to y2, b5 to y3, b6 to y4, b7 to y5, b8 to y7, b9 to y10, b10 to y11, b11 to y12, b12 to y13, b13 to y16, b14 to y14, b15 to y15, b16 to y9, b17 to y18, b18 to y19, and b19 to y17, respecively. The present invention can be applied to a transmission system or the like to transmit the LDPC code, for instance.

Description

200952349 VI. Description of the Invention: [Technical Field] The present invention relates to a data processing device and a data processing method, and an encoding device and an encoding method, and more particularly to a data processing device capable of improving tolerance to, for example, errors And data processing method, coding device and coding method. [Prior Art] The LDPC (Low Density Parity Check) code has a high degree of error correction capability, and has been widely used in recent years for example, including DVB (Digital Video Broadcasting) conducted in Europe. A transmission method in which satellite digital broadcasting such as S.2 is performed (refer to, for example, Non-Patent Document 1). Moreover, the LDPC code is also reviewed for use in the next generation of terrestrial digital broadcasting. According to recent research, the LDPC code system is the same as the turbo code, and as the code length increases, the performance close to the Shannon limit is obtained. Moreover, since the LDPC code has a ® property in which the minimum distance is proportional to the code length, it is excellent in the characteristics of the error of the characteristic system block, and further, as an advantage, it is also observed that the decoding characteristics of the turbo code or the like are hardly observed. The so-called error floor phenomenon. Hereinafter, the LDPC code of this type will be specifically described. Further, the LDPC code is a linear code and is not necessarily binary, but is described here as a binary. The biggest feature of the LDPC code is that the parity check matrix (parity check matrix) defining the LDPC code is loose. Here, the loose matrix refers to a matrix with a very small number of matrix elements "1" (most of the elements are matrices of 0 137720.doc 200952349). Fig. 1 is a diagram showing an example of a check matrix LDP of an LDPC code. The weights (row weights) of the rows of the check matrix 图 in Fig. 1 (the number of "丨") are "3", and the weights of the columns (column weight) are "6". The encoding is performed by the LDPC code (LDPC encoding), for example, according to the checking matrix Η, and the generating matrix g is multiplied for the binary information bits, thereby generating a codeword (LDPC code). . Specifically, the coding apparatus for performing LDPC coding is first to calculate a generation matrix G in which the equation GHT = 成立 is established between the transposed matrix Ητ of the check matrix Η. Here, in the case where the generation matrix G is a KxN matrix, the encoding device generates a bit matrix (vector u) of the information bits composed of K bits for the generation matrix G to generate a N-bit. Code word c (= ug). The code word (LDPC code) generated by the encoding device is received on the receiving side via a specific communication channel. The LDPC code decoding system Gallager is called the algorithm proposed by Probabilistic Decoding (Probabilistic Decoding), which can be utilized by a variable node (also called a message node). )) and the message propagation algorithm of the belief propagation on the so-called Tanner graph composed of check nodes. Here, the variable node and the check node are also hereinafter simply referred to as nodes. Figure 2 is a diagram showing the decoding procedure of the LDPC code. In addition, hereinafter, the ith code bit 137720.doc 200952349 of the LDPC code (1 code word) received by the receiving side represented by the logarithmic probability ratio is suitably referred to as the received value U. ()i. From the variable node, the value of the value of the "〇" is similar to the value of the message. The message output by the node is set to Uj as Vj. First, in the decoding of the LDPC code, such as the received code, the message (check node information 2: the variable of the integer of the counter of ==:), and proceeds to step S12e in step S1 LDPC code The obtained received value is calculated according to the operation shown in the equation (1) (variable node transport), and the message is not sent (variable node information, and the equation (7) is performed according to the message V1'. The operation (check node operation) to find the message Uj. [Number 1] dv-1

Vi=u〇i+ X Uj j=1

[Number 2] ❹ tanh

Dc-1:Π tanh

Vi • (2) Here, the dv and de of the equations (1) and (2) respectively represent the arbitrarily selectable parameters of the number of "1" in the longitudinal direction (row) and the horizontal direction (column) of the inspection matrix H. For example, in the case of the code (3, 6), dv = 3 and de = 6. In addition, in the variable node operation of the equation (1) and the check node operation of (2), since the branch of the message to be output is not to be output (edge · edge), the point is changed and the point is verified. Line) The input message, as the object of calculation, 137720.doc 200952349 Therefore the calculation range is 1 to 1-1, 啖, and 1 to dc-l. Moreover, the check node operation of the equation (2) is actually produced by a table of the function (νι, ν2) represented by the equation (7) defined for the input of the two inputs, as shown in the equation (4). It is carried out continuously (returned). [Number 3] • · · (3) x=2tanh-Mtanh(v彳/2)tanh(V2/2) j =R(Vi, V2) [Number 4] uj=R (vt, R (v2) R (v3, -R (Vdc_2> Vd〇_l))))

And proceeding to step to repeat the number of decoding times, the process returns to step S12, and the variable k is further incremented only... S13. In step S13, it is determined whether the variable 1^ is greater than the special c. In step S13, it is determined that the variable k is not greater than C, S12, and the same processing is repeated below. ^ ^ „ 八 π κ W condition, push forward $ step S14, by who 彳α, _ into the wrong by the staring type (5) does not operate, seeking the final output of the reef & Industry dog as the most [number 5] solution of the strong fruit Vi'LDpc Ma's exhaustion treatment is finished. U,

Vi=U〇j+ J (5) : In this case, the arithmetic system of equation (5) is different from the variable node of equation (1) by using the magnetic resonance μ from the 涟 pile, and it is beneficial to all the branches of the variable. The _ field represents an example of a check matrix of 137720.doc 200952349 (10) (four) code (coding rate 1/2, code length 12). The check matrix 图 in Fig. 3 is the same as Fig. 1, and the weight of the row is 3 and the weight of the column is 6. 4 is a Tanner graph showing the inspection matrix η of FIG. "In this case, in Figure 4, the check nodes are represented by "+j" and the variable nodes are indicated by "=". The check node and the variable node correspond to the columns and rows of the check matrix 11, respectively. The line between the check node and the variable node is branched (edge: edge), which corresponds to the element "〗" of the check matrix. That is, when the element of the i-th row of the jth column of the check matrix is i, in FIG. 4, the branch node is connected from the upper variable node (the node of "=") and the jth school from the top. Check the node (the node of "+"). The branching system indicates that the code bit corresponding to the variable node has a constraint condition corresponding to the check node. In the LDPC Ma decoding method, the arithmetic algorithm _ Algorithm, repeat variable node operation and check node operation. Figure 5 shows the variable node operation performed at the variable node. The variable node 'corresponds to the branch of the branch to be calculated (4) by means of the message u丨 and U2 from the remaining branch connected to the variable node, and the formula (1) of the received value ^(4) Click the operation to find out. Corresponding to other messages, the same is obtained. Figure 6 shows the check node operation performed by the check node.

Here, the check node operation of equation (2) can utilize exp{ln(|a|)+ln(|b|)}xsign(a)xsign(b)^M (6). 1 is ·, , κ horse is the formula, Slgn (x) is 1 when xg 〇, and χ is χ. [Number 6] 137720.doc 200952349 /dr-1

Uj = 2tanh -1 : 2tanh' : 2tanh' V; TT tanh dc-1 exp exp

In tanhf-^ X TT s ignitanh /dc_1 ! Mv-,1 •Σ -In tanhi dc-1 x TI s ign(Vi) (6) Further, in Xg〇, if the function φ(χ) is defined as Since the formula (J)(X)=ln(tanh(X/2)), the equation φ-丨(x)=2tanh-i(ex) holds, and therefore the formula (6) can be transformed into the formula (7). [Number 7] ./dc_1 \ dc-i

Uj = 0-M Σ 0(|vil) X π sign(Vi) (7) At the check node, the check node operation of equation (2) is performed according to equation (7), that is, at the check node, As shown in Fig. 6, the message 4 corresponding to the branch to be calculated is obtained by using the check node operation of the message of the remaining branch from the connected pure node:: =4 (7). The message corresponding to the other branches is also obtained in the same manner. In addition, the function φ(χ) of the formula (7) can also be expressed as (4) = "Χ). When the function φ(χ) = 2 is used, the LUT (Look Up Table is installed on the hardware but both become the same _LUT. - Ge table) is installed. 137720.doc 200952349 Non-Patent Document 1: DVB -S.2: ETSI ΕΝ 302 307 Vl.1.2 (2006-06) SUMMARY OF THE INVENTION Problems to be Solved by the Invention The LDPC code is based on the DVB-S.2 specification of satellite digital broadcasting or the terrestrial digital broadcasting of the next generation. The specification is adopted in DVB-T.2. Further, the LDPC code is intended to be used in the next-generation CATV (Cable Television) digital broadcasting specification DVB-C.2. In the case of digital playback according to DVB specifications such as DVB-S.2, the LDPC code is used as a symbol of quadrature modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying). ), the symbol is mapped to a signal point and sent. In the symbolization of the LDPC code, the replacement of the code bits of the LDPC code is performed in units of code bits of 2 bits or more, and the replaced code bit is used as the bit of the symbol. The replacement of the code bits for the symbolization of the LDPC code has been proposed in various ways, but the way in which the proposal is more tolerant of errors than the way in which it has been proposed is proposed. Further, regarding the LDPC code itself, it is also required to propose an LDPC code which improves the LDPC code which is more resistant to errors than the DVB specification such as DVB-S.2. The present invention has been made in view of such a situation, and the tolerance to errors can be improved. Technical Solution for Solving the Problem 137720.doc 200952349 The data processing device or data processing method according to the first aspect of the present invention includes a replacement mechanism or a replacement step of LDPC having an N-bit memory length in the course direction and the wale direction. Low Density Parity Check: the m-bit of the code bit of the aforementioned LDPC code written in the aforementioned wale direction of the memory cell of the code bit of the low-density parity check) 1 symbol, and a specific positive integer is set to b, the memory means memorizes mb bits in the direction of the preceding row, and stores N/(mb) bits in the longitudinal direction, and the code bits of the LDPC code are as described above. Writing in the wale direction of the memory means, and then reading in the horizontal direction, the code bits of the mb bits read in the direction of the memory of the memory means are taken as b. , replacing the code bit of the mb bit, and replacing the replaced code bit as a symbol bit representing the symbol; the foregoing LDPC code is a code specified by the specification of DVB-S.2 or DVB-T.2 LDPC code with a length N of 64,800 bits and a coding rate of 2/3; The m-bit is 8 bits, and the integer b is 2, and the octet of the code bit is mapped as one of the 256 signal points determined by 256QAM as one of the symbols; the memory mechanism includes Memory 16 x 8 bits of 8x2 bits in the horizontal direction, 64800/(8x2) bits in the longitudinal direction; 8x2 bits of code bits read from the direction of the memory mechanism from the highest order The i+th bit is set to the bit bi from the bit count, and the i+th bit of the 8x2 bit of the preceding two symbols is set as the bit from the highest order bit. Yi, the following substitution is made: the bit b〇 is assigned to the bit y! 5, the bit b! is assigned to the bit y7, the bit b2 is assigned to the bit y 1, and the bit b3 is assigned to the bit y 5, assigning bit b4 to bit y6, assigning bit b5 to bit y 13, assigning bit b6 to bit y! 1, and assigning bit b7 to 137720.doc -10- 200952349 bit The element y9 'is assigned the bit t>8 to the bit ys, the bit b9 to the bit y 14 'the bit b 1 〇 is assigned to the bit y〗 2 'The bit bi! is assigned to the bit y 3, assign bit b! 2 to bit yG The bit bn is assigned to bit y1Q, the bit b 14 to the bit-membered y4 'will be assigned to the bit b i 5 bit y 2. In the first aspect of the above, the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3 as defined by the specifications of DVB-S.2 or DVB-T.2, and the aforementioned m bits. The element is 8 bits, and the integer b is 2, and the octet of the code bit is mapped to one of the 256 letter ® points determined by 25 6QAM as one of the symbols, and the memory means includes Memory 16 bits of 8x2 bits in the horizontal direction 'When the memory is 64800/(8x2) bits in the wale direction, the 8x2 bit code bits read in the direction of the memory mechanism are read. The i+H epoch is set to the bit bi from the highest order octet, and the symbol octet of 8 X 2 bits of two consecutive suffixes is counted from the highest order bit by the first +1. The bit is set to bit yi, and the following substitution is made: the bit b() is assigned to the bit y 1 5 'the bit ratio is assigned to the bit y?, and the bit b2 is assigned to the bit y 1, and Q is Bit b3 is assigned to bit y5, bit b4 is assigned to bit y6, bit b5 is assigned to bit yu 'location bit be is assigned to bit yn, bit 卜 is assigned to bit 疋丫9' Assign bit bs to bit ys, bit b9 Assigned to bit yi4' assigns bit b1Q to bit y12, bit bn to bit y3, bit 疋bu to bit yG, bit b13 to bit yiG, bit fcl4 Assigned to bit y4, bit b15 is assigned to bit y2. The encoding apparatus or encoding method according to the second aspect of the present invention includes an encoding unit or a step of performing an encoding of ldpc>6 horses having a code length of 64,800 bits and a coding rate of 2/3; and an inspection matrix of the aforementioned LDpc code According to the inspection matrix 137720.doc 200952349, the first element of the information matrix defined by the check matrix initial value table is arranged in the row direction every 360-row period, and the check matrix initial value table will be the same as the foregoing code length and the foregoing code. The position of the 1 element of the aforementioned information matrix corresponding to the information length corresponding to the information length is represented by every 360 rows; the initial value matrix of the foregoing inspection matrix includes: 317 2255 2324 2723 3538 3576 6194 6700 9101 10057 12739 17407 21039 1958 2007 3294 4394 12762 14505 14593 14692 16522 17737 19245 21272 21379 127 860 5001 5633 8644 9282 12690 14644 17553 19511 19681 20954 21002 2514 2822 5781 6297 8063 9469 9551 11407 11837 12985 15710 20236 20393 〇 1565 3106 4659 4926 6495 6872 7343 8720 15785 16434 16727 19884 21325 706 3220 8568 10896 12486 13663 16398 16599 19475 19781 20625 20961 21335 4257 10449 1240 。 。 。 。 。 。 。 19938 0 212026483155 38526888 12258 14821 15359 16378 16437 17791 2061421025 1085 2434 5816 7151 8050 9422 10884 12728 15353 17733 18140 18729 20920 856 1690 12787 6532 7357 9151 4210 16615 18152 11494 14036 17470 2474 10291 10323 1778 6973 10739 137720.doc -12- 200952349

4347 9570 18748 2189 11942 20666 3868 7526 17706 8780 14796 18268 160 16232 17399 1285 2003 18922 4658 17331 20361 2765 4862 5875 4565 5521 8759 3484 7305 15829 5024 17730 17879 7031 12346 15024 179 6365 11352 2490 3143 5098 2643 3101 21259 4315 4724 13130 594 17365 18322 5983 8597 9627 10837 15102 20876 10448 20418 21478 3848 12029 15228 708 5652 13146 5998 7534 16117 2098 13201 18317 137720.doc -13 - 200952349 9186 14548 17776 5246 10398 18597 3083 4944 21021 13726 18495 19921 6736 10811 17545 10084 12411 14432 1064 13555 17033 679 9878 13547 3422 9910 20194 3640 3701 10046 5862 10134 11498 5923 9580 15060 1073 3012 16427 5527 20113 20883 7058 12924 15151 9764 12230 17375 772 7711 12723 555 13816 15376 10574 11268 17932 15442 17266 20482 390 3371 8781 10512 12216 17180 4309 14068 15783 3971 11673 20009 137720.doc 200952349 9259 14270 17199 2947 5852 20101 3965 9722 15363 1429 5689 16771 6101 6849 12781 3676 9347 18761 350 11659 18342 5961 14803 16123 ® 2113 9163 13443 2155 9808 1288 5 2861 7988 11031 7309 9220 20745 6834 8742 11977 2133 12908 14704 10170 13809 18153 13464 14787 14975

Q 799 1107 3789 3571 8176 10165 5433 13446 15481 3351 6767 12840 8950 8974 11650 1430 4250 21332 6283 10628 15050 8632 14404 16916 137720.doc •15· 200952349

6509 10702 16278 15900 16395 17995 8031 18420 19733 3747 4634 17087 4453 6297 16262 2792 3513 17031 14846 20893 21563 17220 20436 21337 275 4107 10497 3536 7520 10027 14089 14943 19455 1965 3931 21104 2439 11565 17932 154 15279 21414 10017 11269 16546 7169 10161 16928 10284 16791 20655 36 3175 8475 2605 16269 19290 8947 9178 15420 5687 9156 12408 8096 9738 14711 4935 8093 19266 2667 10062 15972 137720.doc -16- 200952349 6389 11318 14417 8800 18137 18434 5824 5927 15314 6056 13168 15179 3284 13138 18919 13115 17259 17332. In the second aspect as described above, encoding is performed by an LDPC code having a code length of 64,800 bits and a coding rate of 2/3. The inspection matrix of the LDPC code is configured by arranging one element of the information matrix defined by the check matrix initial value table of the check matrix in the row direction every 360-row period, and the check matrix initial value table will be the same as the foregoing code length. And the position of the 1 element of the information matrix corresponding to the information length corresponding to the foregoing coding rate is represented by 360 lines; the foregoing check matrix initial value table includes: 317 2255 2324 2723 3538 3576 6194 6700 9101 10057 12739 17407 21039 1958 2007 3294 439412762 14505 14593 1469216522 17737 19245 21272 21379 _ 127 860 5001 5633 8644 9282 12690 14644 17553 19511 19681 20954 21002 ❹ 2514 2822 5781 6297 8063 9469 9551 11407 11837 12985 15710 20236 20393 1565 3106 4659 4926 6495 6872 7343 8720 15785 16434 16727 19884 21325 7063220 8568 10896 12486 13663 16398 16599 19475 19781 20625 20961 21335 4257 10449 12406 14561 16049 16522 17214 18029 18033 18802 19062 19526 20 748 412 433 558 2614 2978 4157 6584 9320 11683 11819 13024 14486 16860 777 5906 7403 8550 8717 8770 11436 12846 13629 14755 156 88 16392 16419 4093 5045 6037 7248 8633 9771 10260 10809 11326 12072 17516 19344 19938 137720.doc •17· 200952349 2120 2648 3155 3852 6888 12258 14821 15359 16378 16437 17791 20614 21025 1085 2434 5816 7151 8050 9422 10884 12728 15353 17733 18140 18729 20920 856 1690 12787 6532 7357 9151 4210 16615 18152 11494 14036 17470 2474 10291 10323 1778 6973 10739 4347 9570 18748 2189 11942 20666 3868 7526 17706 8780 14796 18268 160 16232 17399 1285 2003 18922 4658 17331 20361 2765 4862 5875 4565 5521 8759 3484 7305 15829 5024 17730 17879 7031 12346 15024 179 6365 11352 2490 3143 5098 2643 3101 21259 4315 4724 13130 137720.doc -18- 200952349 594 17365 18322 5983 8597 9627 10837 15102 20876 10448 20418 21478 3848 12029 15228 708 5652 13146 5998 7534 16117 2098 13201 18317 ® 9186 14548 17776 5246 10398 18597 3083 4944 21021 13726 18495 19921 6736 10811 17545 10084 12411 14432 1064 13555 17033 679 9878 13547 ❹ 3422 991020194 3640 3701 10046 5862 10134 11498 5923 9580 15060 1073 3012 16427 5527 20113 20883 7058 12924 15151 9764 12230 17375 137720.doc •19- 200952349 772 7711 12723 555 13816 15376 10574 11268 17932 15442 17266 20482 390 3371 8781 10512 12216 17180 4309 14068 15783 3971 11673 20009 9259 14270 17199 2947 5852 20101 3965 9722 15363 1429 5689 16771 6101 6849 12781 3676 9347 18761 350 11659 18342 5961 14803 16123 2113 9163 13443 2155 9808 12885 2861 7988 11031 7309 9220 20745 6834 8742 11977 2133 12908 14704 10170 13809 18153 13464 14787 14975 137720.doc 200952349

799 1107 3789 3571 8176 10165 5433 13446 15481 3351 6767 12840 8950 8974 11650 1430 4250 21332 6283 10628 15050 8632 14404 16916 6509 10702 16278 15900 16395 17995 8031 18420 19733 3747 4634 17087 4453 6297 16262 2792 3513 17031 14846 20893 21563 17220 20436 21337 275 4107 10497 3536 7520 10027 14089 14943 19455 1965 3931 21104 2439 11565 17932 154 15279 21414 10017 11269 16546 7169 10161 16928 137720.doc -21 - 200952349 10284 16791 20655 36 3175 8475 2605 16269 19290 8947 9178 15420 5687 9156 12408 8096 9738 14711 4935 8093 19266 2667 10062 15972 6389 11318 14417 8800 18137 18434 5824 5927 15314 6056 13168 15179 3284 13138 18919 13115 17259 17332. The data processing device or the data processing method according to the third aspect of the present invention includes a replacement mechanism or a replacement step of LDPC (Low Density Parity Check) having a memory code length of N bits in the horizontal direction and the longitudinal direction. The m-bit of the code bit of the LDPC code read in the preceding direction of the memory cell of the code bit of the code bit is written as one symbol and a specific positive integer Let b be, the memory means memorize mb bits in the horizontal direction, and store N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism. And then read in the above-mentioned course direction, and the code bits of the mb bits read in the aforementioned direction of the memory mechanism are replaced as b symbols 137720.doc -22- 200952349 The code bit of the mb bit, the replaced code bit is used as the symbol bit indicating the symbol; the LDPC code has a code length N of 64800 bits and an LDPC code with a coding rate of 2/3; The m bit is 8 bits, and the aforementioned integer b is 2; the aforementioned code bit The 8-bit is mapped to one of the 256 signal points determined by 256QAM as one of the aforementioned symbols; the memory mechanism includes 16 vertical lines of 8x2 bits in the horizontal direction and 64800/ in the vertical direction. (8x2) bit; the 8x2 bit code bit read out in the direction of the memory mechanism is set to the bit bi from the highest order bit, and will be consecutive 2 The symbolic element of the 8x2 bit of the preceding symbol is set to the bit yi from the highest order bit, and the following replacement is performed: the bit b〇 is allocated to the bit y7, and the bit is allocated. Bi is assigned to bit y2, bit b2 is assigned to bit y9, bit t>3 is assigned to bit y〇, bit b4 is assigned to bit y4, and bit b5 is assigned to bit y6, The bit b6 is assigned to the bit y 13, the bit b7 is assigned to the bit y3, the bit b8 is assigned to the bit y14, the bit b9 is assigned to the bit y1(), and the bit b1G is assigned to the bit Element y15, assigning bit b!! to bit y 5, assigning bit b! 2 to bit y 8, assigning bit b 3 to bit y! 2, allocating bit b! Give bit y 11, assign bit b] to bit y!; the inspection matrix of the LDPC code is configured by arranging one element of the information matrix defined by the check matrix initial value table of the check matrix in the row direction every 360 rows, and the check matrix initial value table will be as described above. The code length N and the position of the first element of the information matrix corresponding to the information length corresponding to the foregoing coding rate are represented by 360 lines; the foregoing check matrix initial value table includes: 317 2255 2324 2723 3538 3576 6194 6700 9101 10057 12739 17407 21039 137720.doc •23- 200952349 1958 2007 3294 4394 1276214505 14593 14692 16522 17737 19245 21272 21379 127 860 5001 5633 8644 9282 12690 14644 17553 19511 19681 20954 21002 2514 2822 5781 6297 8063 9469 9551 11407 11837 12985 15710 20236 20393 1565 3106 4659 4926 6495 6872 7343 8720 15785 16434 16727 19884 21325 706 3220 8568 108% 12486 13663 16398 16599 19475 1978120625 20961 21335 4257 10449 12406 14561 16049 16522 17214 18029 18033 18802 19062 19526 20 748 412 433 558 2614 2978 4157 6584 9320 11683 11819 13024 14486 16860 777 5906 7403 8550 8717 8770 11 436 12846 13629 14755 15688 16392 16419 4093 5045 6037 7248 8633 9771 10260 10809 11326 12072 17516 19344 19938 21202648 3155 38526888 12258 14821 15359 16378 16437 17791 2061421025 1085 2434 5816 7151 8050 9422 10884 12728 15353 17733 18140 18729 20920 856 1690 12787 6532 7357 9151 4210 16615 18152 11494 14036 17470 2474 10291 10323 1778 6973 10739 4347 9570 18748 2189 11942 20666 3868 7526 17706 8780 14796 18268 160 16232 17399 1285 2003 18922 137720.doc -24- 200952349 4658 17331 20361 2765 4862 5875 4565 5521 8759 3484 7305 15829 5024 17730 17879 7031 12346 15024 179 6365 11352 2490 3143 5098 ® 2643 3101 21259 4315 4724 13130 594 17365 18322 5983 8597 9627 10837 15102 20876 10448 20418 21478 3848 12029 15228 708 5652 13146 ❹ 5998 7534 16117 2098 13201 18317 9186 14548 17776 5246 10398 18597 3083 4944 21021 13726 18495 19921 6736 10811 17545 10084 12411 14432 137720.doc -25- 200952349

1064 13555 17033 679 9878 13547 3422 991020194 3640 3701 10046 5862 10134 11498 5923 9580 15060 1073 3012 16427 5527 20113 20883 7058 12924 15151 9764 12230 17375 772 7711 12723 555 13816 15376 10574 11268 17932 15442 17266 20482 390 3371 8781 10512 12216 17180 4309 14068 15783 3971 11673 20009 9259 14270 17199 2947 5852 20101 3965 9722 15363 1429 5689 16771 6101 6849 12781 3676 9347 18761 137720.doc -26- 200952349 350 11659 18342 5961 14803 16123 2113 9163 13443 2155 9808 12885 2861 7988 11031 7309 9220 20745 6834 8742 11977 2133 12908 14704 ® 10170 13809 18153 13464 14787 14975 799 1107 3789 3571 8176 10165 5433 13446 15481 3351 6767 12840 8950 8974 11650 1430 4250 21332 ❹ 6283 10628 15050 8632 14404 16916 6509 10702 16278 15900 16395 17995 8031 18420 19733 3747 4634 17087 4453 6297 16262 2792 3513 17031 137720.doc -27- 200952349 14846 20893 21563 17220 20436 21337 275 4107 10497 3536 7520 10027 14089 14943 19455 1965 3931 21104 2439 11565 17932 154 15279 21414 10017 11269 16546 7 169 10161 16928 10284 16791 20655 36 3175 8475 2605 16269 19290 8947 9178 15420 5687 9156 12408 8096 9738 14711 4935 8093 19266 2667 10062 15972 6389 11318 14417 8800 18137 18434 5824 5927 15314 6056 13168 15179 3284 13138 18919 13115 17259 17332. 137720.doc 200952349 In the third aspect of the above, the aforementioned [mouth corpus code length N is 64800 bits, the coding rate is 2/3 LDPC code; the aforementioned m bit is 8 bits' and the aforementioned integer b is 2; the octet of the aforementioned code bit is mapped to one of the 256 signal points determined by 256QAM as one of the aforementioned symbols; the memory mechanism contains 16 vertical memories of 8x2 bits in the horizontal direction. Line 'memorizes 64800/(8x2) bits in the wale direction; the iq bit of 8x2 bits read from the direction of the memory mechanism is set from the highest order bit to the i+1th bit The bit bi, and the symbol bits of the 8x2 bits of the preceding two symbols are set from the highest order bit to the i+1th bit as the bit yi, and the following replacement is performed: the bit b〇 Assigned to bit y7, assign bit b! to bit y2 'Assign bit b2 to bit y9, assign bit b3 to bit y〇' to assign bit to bit y4, place bit B5 is assigned to bit y6, bit t»6 is assigned to bit y 13, bit b7 is assigned to bit y3, bit b8 is assigned to bit yμ, bit b9 is assigned to bit y 1 . Assigning the bit b 1 g to the bit y 15, assigning the bit b 1 ! to the bit y5 , assigning the bit b 12 to the bit y8 , and assigning the bit bi3 to the bit yi2 , the bit Bi4 is assigned to bit yn, and bit b15 is assigned to bit y!. Further, the inspection matrix of the LDPC code is configured by arranging one element of the information matrix defined by the check matrix initial value table of the check matrix in the row direction every 360-row period, and the check matrix initial value table is the same as the code The position of the first element of the information matrix corresponding to the information length corresponding to the foregoing coding rate is represented by every 360 lines; the initial value table of the foregoing check matrix includes: 317 2255 2324 2723 3538 3576 6194 6700 9101 10057 12739 17407 21039 1958 2007 3294 43941276214505 14593 146921652217737 19245 21272 21379 137720.doc •29- 200952349 127 860 5001 5633 8644 9282 12690 14644 17553 19511 19681 20954 21002 2514 2822 5781 6297 8063 9469 9551 11407 11837 12985 15710 20236 20393 1565 3106 4659 4926 6495 6872 7343 8720 15785 16434 16727 19884 21325 706 3220 8568 10896 12486 13663 16398 1659919475 19781 20625 20961 21335 4257 10449 12406 14561 16049 16522 17214 18029 18033 18802 19062 19526 20 748 412 433 558 2614 2978 4157 6584 9320 11683 11819 13024 14486 16860 777 5906 7403 8550 8717 8770 1 1436 12846 13629 14755 15688 16392 16419 4093 5045 6037 7248 8633 9771 10260 10809 11326 12072 17516 19344 19938 2120 2648 3155 3852 6888 12258 14821 15359 16378 16437 1779120614 21025 1085 2434 58167151 80509422 10884 12728 15353 17733 18140 1872920920 856 1690 12787 6532 7357 9151 4210 16615 18152 11494 14036 17470 2474 10291 10323 1778 6973 10739 4347 9570 18748 2189 11942 20666 3868 7526 17706 8780 14796 18268 160 16232 17399 1285 2003 18922 4658 17331 20361 137720.doc -30- 200952349 2765 4862 5875 4565 5521 8759 3484 7305 15829 5024 17730 17879 7031 12346 15024 179 6365 11352 2490 3143 5098 2643 3101 21259 4315 4724 13130 594 17365 18322 5983 8597 9627 10837 15102 20876 10448 20418 21478 3848 12029 15228 708 5652 13146 5998 7534 16117 2098 13201 18317 9186 14548 17776 5246 10398 18597 3083 4944 21021 13726 18495 19921 6736 10811 17545 10084 12411 14432 1064 13555 17033 137720.doc -31 - 200952349 679 9878 13547 3422 9910 20194 3640 3701 10046 5862 10134 11498 5923 9580 15060 1073 3 012 16427 5527 20113 20883 7058 12924 15151 9764 12230 17375 772 7711 12723 555 13816 15376 10574 11268 17932 15442 17266 20482 390 3371 8781 10512 12216 17180 4309 14068 15783 3971 11673 20009 9259 14270 17199 2947 5852 20101 3965 9722 15363 1429 5689 16771 6101 6849 12781 3676 9347 18761 350 11659 18342 137720.doc -32- 200952349 5961 14803 16123 2113 9163 13443 2155 9808 12885 2861 7988 11031 7309 9220 20745 6834 8742 11977 2133 12908 14704 10170 13809 18153 13464 14787 14975 799 1107 3789 3571 8176 10165 5433 13446 15481 3351 6767 12840 8950 8974 11650 1430 4250 21332 6283 10628 15050 8632 14404 16916 6509 10702 16278 15900 16395 17995 8031 18420 19733 3747 4634 17087 4453 6297 16262 2792 3513 17031 14846 20893 21563 137720.doc -33- 200952349 17220 20436 21337 275 4107 10497 3536 7520 10027 14089 14943 19455 1965 3931 21104 2439 11565 17932 154 15279 21414 10017 11269 16546 7169 10161 16928 10284 16791 20655 36 3175 8475 2605 16269 19290 8947 9178 15420 5687 9156 12408 8096 9738 147 11 4935 8093 19266 2667 10062 15972 6389 11318 14417 8800 18137 18434 5824 5927 15314 6056 13168 15179 3284 13138 18919 13115 17259 17332. In addition, the data processing device and the encoding device may each be a separate device, 137720.doc -34- 200952349 or may be an internal block constituting one device. [Embodiment] Effect of the Invention The Japanese cut < Fig. 7 is a view showing an example of a configuration in which an embodiment of the present invention is applied to a plug of the present invention (the system collectively refers to a logically aggregated object, regardless of whether or not each structure is disposed in the same casing).

In Fig. 7, the transmission system is constituted by a transmission device 11 and a receiving device 12. The transmitting device 11 performs, for example, transmission (playback) (transmission) of a television broadcast program. In other words, the transmission device i is, for example, an image data to be transmitted as image data or audio data of a television broadcast program, and is encoded as an LDPC code 'via, for example, a satellite line, a ground wave, an Internet, or the like. The communication channel 13 is sent. The receiving device 12 is, for example, a pacer or a television receiver that receives a television broadcast program, an STB (Set Top Box), and a PC that receives IpTV (Internet Protocol Televisi〇n: Internet Protocol Television) (pers〇nai) Computer: PC) receives an LDPC code transmitted from the transmitting device u via the communication channel 13, decodes it into a target data, and outputs it. The LDpc code used in the transmission system of Fig. 7 is known to have an extremely high capacity in the AWGN (Additive White Gaussian Noise) communication channel. However, in the communication channel 13 of the ground wave or the like, a burst error or erasure may occur. For example, 〇FDM (Orthogonal Frequency 137720.doc ·35· 200952349

Divisi〇n Multip: Exing: Orthogonal Frequency Division Multiplex) In the system, the multipath that should be (Desiredt〇UndesiredRatio: U/unwanted rate) is not required = the power of the echo is equal to the power required = the power of the main path In the environment, there is a delay (delay) in response to the echo (eehG) (path of the main path), and the power of the specific symbol becomes 〇 (erased). Moreover, even if it is a flutter (a delay is 〇 and adds a communication channel that costs the echo of the frequency of the d〇PP丨er), in the case of d/u being a sin, Eindler When the frequency is generated, the power of the entire symbol of the dereliction of duty at a specific time becomes 0 (erased). Further, 'the reception device 12 side may also have a disconnection from a receiving unit (not shown) such as an antenna that receives a signal from the transmitting device U to the receiving device 12, or the power supply of the receiving device 12 may be unstable. Make a mistake. ❹ On the other hand, in the decoding of the LDPC code, the line of the check matrix H, even the variable node corresponding to the code bit of the LDPC code, is accompanied by the code of the LDPC code as described above. The addition of the element (the received value of 11.) is variable (ie, the point operation). Therefore, if an error occurs in the code bit used in the variable node operation, the accuracy of the obtained message is lowered.

Then, in the decoding of the LDPC code, in the check node, the checksum of the equation (7) is performed by using the message obtained by the variable node connected to the check node, so that the complex number is variable if connected When the number of check nodes of the node (corresponding LDPC code) becomes an error (including erasure), the performance of decoding deteriorates. That is, for example, if the check node is connected to the variable node of the check node 2 137720.doc • 36 · 200952349 or more and becomes erased at the same time, the rate of returning the value to all the variable nodes and the accuracy of 1 are equal. The message of the rate. In this case, the check node of the message that returns the equal rate does not contribute to the decoding process (the variable node operation and the check node operation of the 1 set), and as a result, the number of repetitions of the decoding process is required. The decoding performance is degraded, and further, the power consumption of the receiving device 12 that performs decoding of the LDPC code increases. Therefore, in the transmission system of Fig. 7, it is desirable to maintain the performance of the AWGN communication channel while improving the tolerance to burst errors or erasures. ® Fig. 8 is a view showing an example of the configuration of the transmitting device 11 of Fig. 7. In Fig. 8, the transmitting apparatus 11 is composed of an LDPC encoding unit 21, a bit interleaver 22, a mapping unit 26, and a quadrature modulation unit 27. The target data is supplied to the LDPC encoding unit 21. The LDPC encoding unit 21 performs LDPC encoding on the target data supplied to the location, corresponding to the parity bit of the LDPC code, that is, the check matrix in which the parity matrix is a ladder structure, and outputs the LDPC code which uses the target data as the information bit. . In other words, the LDPC encoding unit 21 performs LDPC encoding of the LDPC code specified by the specification of DVB-S.2 or DVB-T.2, and outputs the LDPC code obtained as a result. Here, the specification of DVB-T.2 is intended to adopt the LDPC code specified by the specification of DVB-S.2. The LDPC code defined by the specification of DVB-S.2 is an IRA (Irregular Repeat Accumulate) code, and the parity matrix of the check matrix of the LDPC code becomes a ladder structure. The co-located matrix and the ladder structure will be described later. Furthermore, the IRA code system 137720.doc -37- 200952349 is contained in, for example, "Irregular Repeat-Accumulate Codes", H. Jin, A. Khandekar, and R. J- McEliece, in

Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1-8, Sept. 2000 o The LDPC code output from the LDPC encoding unit 21 is supplied to the bit interleaver 22 ° bit interleaver 22 interleaves the data The data processing device is composed of a parity interleaver 23, a column twist interleaver 24, and a demultiplexer (DEMUX) 25. The parity interleaver 23 performs co-located interleaving, interleaving the parity bits of the LDPC code from the LDPC coder 21 to the positions of the other parity bits, and supplying the parity interleaved LDPC code to the walody twist interleaver 24. The whirling torsion interleaver 24 is for the TWpcu horse supply & to the demultiplexer 25 for the whirling of the equidistant interleaver stone horse. That is, the LDPC code is used by the mapping unit 26, which will be described later, to map the code bits above the stone horse bits to the signal points indicating the orthogonal modulation, and transmit them. The vertical twist interleaver 24 is not included in one symbol in order to make the complex nd% of the LDPC stone horse corresponding to any one of the check matrices used in the LDpc encoding unit 21, and is rearranged from the same position. For the rearrangement processing of the code bit of the interleaver code, for example, the vertical twist interleave multiplexer 25 to be described later is a code bit of 2 or more of the LDPC code which is replaced by the vertical twist interleaver 242LDpc. The position is replaced by 137720.doc -38- 200952349, thereby obtaining an LDPC code that has been enhanced to withstand AWGN. Then, the demultiplexer 25 supplies the code bits of 2 or more of the LDPC codes obtained by the replacement processing to the mapping unit 26 as symbols. The mapping unit 26 maps the symbols from the demultiplexer 25 to the respective signal points determined by the modulation method of the quadrature modulation (multi-value modulation) by the orthogonal modulation unit 27. That is, the mapping unit 26 maps the LDPC code from the demultiplexer 25 to an IQ plane defined by the I axis representing the I component in phase with the carrier and the Q axis representing the Q component orthogonal to the carrier. The signal point determined by modulation in the (IQ constellation). Here, as a modulation method of the quadrature modulation performed by the quadrature modulation unit 27, there is, for example, a modulation method including a modulation method defined by a specification of DVB-T, that is, for example, QPSK (Quadrature Phase Shift Keying) : Quadrature phase key shift) or 1 6QAM (Quadrature Amplitude Modulation) '64QAM, 256QAM, 1024QAM, 4096QAM, etc. The quadrature modulation unit 27 preliminarily sets the orthogonal modulation by a certain modulation method in accordance with, for example, the operation of the operator of the transmission device 11. Further, in the quadrature modulation unit 27, for example, 4PAM (Pulse Amplitude Modulation) and other orthogonal modulation can be performed. The symbol mapped to the signal point by the mapping unit 26 is supplied to the orthogonal modulation unit 27. The orthogonal modulation unit 27 performs carrier wave in accordance with a signal point (a symbol mapped to the signal point) from the mapping unit 26. The quadrature modulation is transmitted, and the modulated signal obtained as a result is transmitted via the communication channel 13 (FIG. 7). 137720.doc -39- 200952349 Next, Fig. 9 shows an inspection matrix 用于 for LDPC encoding by the LDPC encoding unit 21 of Fig. 8. The check matrix Η is an LDGM (Low-Density Generation Matrix) low-density generation matrix structure, and the information matrix HA corresponding to the information bit in the code bit of the LDPC code and the co-located corresponding to the parity bit The matrix Ητ is expressed as the equation H=[HA|HT] (the elements of the information matrix Ha are set to the left side element, and the elements of the parity matrix Ητ are set as the matrix of the right side element). Here, the number of bits of information bits and the number of bits of the parity bits in the code bits of one LDPC code (1 code word) are respectively referred to as information length K and parity length, and one LDPC code. The number of bits of the code bit is called the code length Ν (=Κ+Μ). Regarding the LDPC of a certain length, the tribute and the same position are determined by the coding rate. Moreover, check the matrix of the matrix Η series X behavior. Then, the information matrix is a matrix of ΜχΚ, and the parity matrix Ητ is a matrix of ΜχΜ. Figure 10 is a diagram showing the parity matrix Ητ of the check matrix LDP of the LDPC code specified by the specifications of DVB-S.2 (and DVB-T.2). The parity matrix of the inspection matrix LDP of the LDPC code defined by the specification of DVB-S.2 is shown in Fig. 10, and the elements which become 1 are arranged in a so-called stepped structure. The column weight of the co-located matrix Ητ is 1 for the first column and 2 for the remaining columns. Moreover, the row weight is 1 for the last row and the remaining behavior is 2. As described above, the LDPC code in which the parity matrix Ητ is a stepped structure check matrix can be easily generated using the check matrix. That is, the LDPC code (1 codeword) is represented by the column vector c, and the row vector obtained by transposing the column 137720.doc - 40 - 200952349 vector is denoted as cT. Moreover, the column vector A represents the portion of the information bit in the column vector c of the LDPC code and the column vector τ represents the portion of the parity bit. In this case, the column vector c can be used as a column of information bits.

The quantity A and the column vector T which is a parity bit are represented by the formula C = [A|T] (the element of the column vector A is set to the left side element, and the element of the column vector T is set to the column element of the right side element). ❹ Check matrix Η and column vector C=[A|T] as LDPC code must conform to

Hc 'as a column vector T constituting a parity bit of the column vector C=[A|T] of the formula HcT=〇, can be obtained by checking the parity matrix Ητ of the matrix h=[ha|Ht] In the case of the step structure shown in the figure, the elements of the first row from the row vector h of the formula hct=〇 are sequentially obtained by sequentially making the elements of the respective columns 〇. The diagram indicates the check matrix and row weight of the LDPC code specified by the specifications of DVB-S_2 (and DVB-T.2). ’ That is, the diagram indicates the inspection matrix of the LDPC code specified in the specifications of DVB-S.2. Separately, regarding the check matrix Η from the first row, the row weight is X 'about the next 3 rows, the row weight is 3, and the subsequent Μ-1 row, the row weight is 2, about the last 1 Line, the row weight is 1. Here, ΚΧ+Κ3+Μ-1 + 1 is equal to Shima Changyu. For the specifications of DVB-S.2, the number of lines ΚΧ, Κ3 and Μ (co-located length), and the weight of the line X are as shown in Figure 11Β.

That is, Fig. 11 shows the number of lines ΚΧ, K3 and Μ, and the row weight X of the respective coding rates of the LDPC 137720.doc -41 · 200952349 code prescribed by the specifications of DVB-S.2. In the specification of DVB-S.2, there are LDPC codes with a length of 64,800 bits and 16,200 bits. Then, as shown in FIG. 11A, regarding the LDPC Ma with a code length of 64,800 bits, 11 encoding rates (nominal rate) of 1/4, 1/3, 2/5, 1/2 are specified. , 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10. For an LDPC code with a code length N of 16,200 bits, 10 encoding rates I/4 are specified. , 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6 and 8/9. Regarding the LDPC code, it is known that the code bit corresponding to the row having the larger row weight of the check matrix has a lower error rate. The more the check matrix Η' specified in the specification of DVB-S.2 shown in FIG. 11 is the row on the head side (left side), the greater the row weight tendency, and therefore the more the LDPC code corresponding to the check matrix ' It is the beginning of the code bit 'the stronger the error (there is a response to the error), the more the last bit of the code bit' is more vulnerable to the wrong tendency. Next, Fig. 12 shows an arrangement on the IQ plane of 16 symbols (corresponding signal points) in the case where 16QAM is performed by the quadrature modulation unit 27 of Fig. 8. That is, Fig. 12A shows the symbol of 16QAM. In 16QAM, 1 symbol represents 4 bits, and there are 16 (= 24) symbols. Then, the 16 symbols are arranged in a square shape of 4x4 in the 1-direction xQ direction centering on the origin of the IQ plane. Now, if the bit string represented by the 1 symbol is counted from the highest order bit and the bit of the i+th bit is represented as the bit yi, the 4 symbol represented by the 1 symbol of 16QAM is the highest. The order bits can be expressed as bit 丫〇, 丫 1, 72, and 于 720720.doc -42- 200952349 The change mode is 1 6QAM, the 4 bits of the LDPC code are treated as 4 bits. (symbolized to be a 4-bit 7 () to 73 symbol (symbol value). Fig. 1 2B shows the bit boundary of the 4-bit (hereinafter also referred to as the symbol bit) y〇 to y3 represented by the symbol of 16QAM, respectively. Here, the bit boundary of the symbol element yi (i = 〇, i, 2, 3 in Fig. 12) means that the symbol bit yi becomes the symbol of 〇 and the boundary of the symbol of 丨. As shown in FIG. 12B, regarding the 4-bit meta-bit y0 to the highest-order symbol bit represented by the symbol of 16QAM, only the i-axis of the Q-axis of the IQ plane becomes a bit boundary, and regarding the second ( The symbol element yi of the second) from the highest order bit is only the bit boundary of the I axis of the IQ plane. Further, regarding the third symbol bit, two of the 4x4 symbols from the left to the i-th row and the second row, and between the third row and the fourth row become the bit boundary. Progression 3, regarding the fourth symbol element 丫3, 4x4 symbols from the above, between the first column and the second column, and between the third column and the fourth column become the bit boundary . ❹ The symbolic element represented by 疋 yi is the more symbols that are far from the bit boundary, the more difficult it is to make mistakes (low error rate), the more symbols near the boundary of the bit, the more likely it is to make mistakes (the error rate is high now) If the bit that is not easy to be mistaken (for the strong error) is called the "strong bit" and the bit that is easy to make mistakes (for the weak position of the error) is called the "weak bit", then the 4 symbol of the symbol of 16QAM Bit Wei, the highest position of the symbol, and the second symbol yi become a strong bit, and the third and fourth symbols become weak bits. Fig. 15 shows a configuration on the plane of 64 symbols (corresponding signal points) in the case of 64QAM 137720.doc -43-200952349 by the quadrature modulation unit 27 of Fig. 8. On 64QAM, 1 symbol The element represents 6 bits, and there are 64 (=26) symbols. Then the '64 symbols are centered on the origin of the iq plane, and are arranged in a square shape of 8x8 in the direction of the x direction of the I direction. The symbol element of the symbol is from the highest order bit, which can be expressed as bits yQ, yi, y2, y3, y4, y5. In the case where the mode is 64QAM, the 6-bit code bit of the LDPC code is used as the symbol of the 6-bit symbol bit y 〇 to ys. Here, FIG. 13 is a symbol representing the symbol of 64QAM, respectively. The highest bit of the meta-bit y0 to ys is the bit boundary of the highest-order symbol y〇 and the second-character bit; FIG. 14 is a representation of the third symbol y2 and the fourth symbol, respectively. The bit line of the element 兀^3; Fig. 15 shows the bit boundary of the fifth symbol bit and the sixth symbol y5, respectively. As shown in Fig. 13, respectively, the highest bit The bit boundary of the meta-bit y〇 and the second symbol bit y! is one. Moreover, as shown in the figure, the third symbol bit and the fourth symbol bit are respectively The boundary line is 2; as shown in Fig. 15, the bit boundary of the 5th symbol bit w and the 6th symbol bit ys are respectively 4. In this case, the symbol of the symbol of 64QAM is used. The bit "to", the highest bit 〇 〇 and the second symbol yi become strong bits, and the third symbol 丫 2 and the fourth symbol y3 become the second strongest Bit. Then, the fifth symbol bit h and The sixth symbol bit" becomes a weak bit. From Fig. 12, it can be further seen from Fig. 13 to Fig. 15 that with respect to the symbol bit of the symbol of the quadrature modulation, the high bit becomes a strong bit, and the low bit The bit becomes a tendency of the weak bit in the case of 137720.doc -44 - 200952349. Here, as illustrated in Fig. 11, regarding the LDPC code outputted by the LDPC encoding section 21 (Fig. 8), there are code bits and pairs which are strong against errors. In addition, as described with reference to FIGS. 12 to 15, the symbol bit of the symbol of the quadrature modulation performed by the quadrature modulation unit 27 has a strong bit and a weak bit. Therefore, if the error bit of the LDPC code is assigned to the weak symbol bit of the orthogonally modulated symbol, the tolerance to the error will be reduced as a whole. Therefore, an interleaver is proposed which interleaves the code bits of the LDPC code by assigning the error bit of the LDPC code to the strong bit (symbol bit) of the quadrature modulated symbol. yuan. The multiplexer 25 of Figure 8 can perform the processing of the interleaver. Figure 16 is a diagram for explaining the processing of the multiplexer 25 of Figure 8. That is, Fig. 16A shows an example of the functional configuration of the demultiplexer 25. The multiplexer 25 is composed of a memory 31 and a replacement unit 32. The LDPC code from the LDPC encoding unit 21 is supplied to the memory 31. The memory 3 1 contains a memory mb bit in the row (horizontal) direction, and memorizes the memory capacity of the N/(mb) bit in the column (longitudinal) direction, and is supplied thereto. The code bits of the LDPC code are written in the wale direction, read out in the course direction, and supplied to the replacement unit 32. Here, N (= information length K + co-located length M) is the code length of the LDPC code as described above. Further, m is a bit 137720.doc -45- 200952349 which is a bit of a symplectic LDPC code, and b is a specific positive integer which is used to make m an integer multiple. The multiplexer 25 is as described above, and the code bit of the LDPC code is used as a symbol (symbolized). The multiple b indicates the number of the multiplexer 25 obtained by the so-called 丨 符 。. Fig. 16A shows an example of the configuration of the demultiplexer 情况 in the case where the modulation method is 64QAM. Therefore, the number of bits m of the code bit of the LDPC code which becomes the symbol is 6 bits.

Further, in Fig. 16A, the multiple b is 1, so that the memory 31 has a memory capacity in which the direction of the X direction is Ν/(6χ1)χ(6χ1). Q Here, the course direction of the memory 31 is a memory area in which the 丨 bit extends in the waling direction, and is hereinafter referred to as a waling. In Fig. 6A, the memory 3 1 is composed of 6 (= 6X 1) vertical lines. In the multiplexer 25, the code bits of the LDPC code are written from the top left direction to the right direction in the vertical direction (the wale direction) constituting the memory 31. Then, if the code bit is written to the bottom of the rightmost vertical line, the first column of all the wales constituting the memory 31 is read in units of 6 bits © (mb bits) in the course direction. The bit is output and supplied to the replacement unit. The replacing unit 32 performs replacement processing for replacing the position of the 6-bit code bit from the memory 3丨, and the 6-bit obtained as a result is used as the 6-symbol bit representing the symbol of 64QAM... ^ Heart and output. That is, from the memory 3 1, the code bits of the mb bits (here, 6 bits) are read in the course direction, and if the code bits of the claw bits read from the memory 31 are from The highest order bit counts the i-th bit (_〇, !,·· represents the bit 137720.doc -46· 200952349 I from the memory 31, the 6-bit readout in the course direction From the highest order bit, the meta-system can be used to represent the positional disease, bl, b2, b into b5. The relationship between the weights of the rows described in Figure 11 is located in the direction of the bit b. A strong code bit, the code bit in the direction of the bit element becomes a code bit that is weak to the error.

In the replacement unit 32, in order to make the 6-bit code bit b from the memory 31. The code bit element to the error of the error is assigned to the symbol y, which is called the symbol of Yan Zhifu. The strong bit in 5 can be replaced by a replacement process from the position of the 6-bit code bits bG to bs of the memory 31. Here, as a replacement of the 6-bit code bit from the memory 31 B〇至匕, and assigned to each of the 6 symbolic elements y❶ to force of the symbol, there are various ways to propose from each company. Fig. 1 6B shows the first alternative, Figure j 6C denotes a second alternative, and FIG. 16D shows a third alternative. In FIGS. 16B to 16D (the same applies to FIG. 17 described later), the line segment connecting the bit (4) A means that the code bit 4 is assigned to the symbol. The symbol of the element is replaced by the position of the symbol bit y.) As a first alternative, any of the alternatives of the three types of FIG. 163 is adopted, and the second alternative is proposed as the second alternative. Any one of the alternatives of the types. As a third alternative, it is proposed to sequentially select the type of the six types of FIG. 16D, and that the modulation mode is 64QAM (hence, the code bits of the LDPC code mapped to one symbol) The number of bits m is 6 bits as shown in Fig. 6 and the multiple 匕137720.doc -47-200 952349 is a configuration example of the multiplexer 25 and a fourth alternative. When the multiple b is 2, the memory 31 has a wale direction < the course direction is Ν/(6Χ2)χ The memory capacity of the (6χ2) bit is composed of 12 (=6χ2) vertical lines. Fig. 1 7A shows the writing order of the LDPC code to the memory 3. The demultiplexer 25' is illustrated in Fig. 16. The writing position of the LDpc code in the wales constituting the memory 31 from the top to the bottom (the waling direction) is performed from the left to the right direction. Then, if the code bit is written to the most When the bottom of the right vertical line is finished, the code bit is read out from the first column of all the wales constituting the memory 31, and the code bit is read out in the direction of the column by ">2 bits (mb bits), and is supplied to the replacement portion. 32. The replacing unit 32 performs a replacement process of replacing the position of the code bit from the 12-bit memory of the memory 31 with the fourth alternative, and obtains the 12-bit obtained as a result of the 64QAM22 symbol. The symbol is a bit, which is the 6-symbol y〇, yi, y2, y3, y4, y5 representing the 64QAMi i symbol and the symbol 1 6 symbol bits 7〇, ;/1,>^, 丫3,;^4,;/5 are output. Here, Fig. 17B shows the replacement by the replacement unit 32 of Fig. 17A. The fourth alternative of the processing. In addition, when the multiple b is 2 (the same applies for the case of 3 or more), the code bits of the replacement processing mb bits are allocated to the mb bits of the consecutive b symbols. Bit το. Including FIG. 17, the following is for the sake of explanation, the i+1th bit from the highest order bit of the mb bit of the consecutive b symbols is represented as a bit (symbol) Bit) yi. Moreover, the appropriate replacement method, that is, how to improve the error rate of the AWGN pass 137720.doc -48- 200952349 channel, is different according to the coding rate or code length and modulation mode of the LDPC code. Next, the co-interleaving by the parity interleaver 23 of Fig. 8 will be explained with reference to Figs. 18 to 20 . Fig. 18 is a Tanner diagram (part portion) showing a check matrix of an LDPC code. If the check node is as shown in FIG. 18, two or more of the variable nodes (corresponding code bits) connected to the check node are simultaneously erased and the like, and the pair is connected to the check node. For all variable nodes, the value of the return value is the same as the rate of accuracy. Since &, if the complex variable nodes connected to the same check node are erased at the same time, the decoding performance is degraded. However, the LDPC code defined by the DVB_S22 standard outputted by the LDPC encoding unit 21 of Fig. 8 is an IRA code, and the parity matrix Ητ of the check matrix H is a stepped structure as shown in Fig. 10 . Fig. 19 is a graph of the parity matrix Ητ which does not become a step structure and a Tanner graph corresponding to the parity matrix Ητ. That is, Fig. 19A shows the parity matrix Ητ which is a step structure; Fig. 19 shows the collocation diagram of the collocated matrix corresponding to Fig. 19Α. In the case where the collocated matrix Ητ is a ladder structure, it is in the same matrix. The wiper uses the LDPC code corresponding to the parity matrix and the value of the variable node of the information in the adjacent code bit (the parity bit) of the line of the element is connected to the same check node. Errors or erasures, etc., the above-mentioned adjacent parity bits become errors at the same time, and are connected to complex variable nodes corresponding to the complex parity bits that become erroneous (variable sections using the parity bits to obtain information 137720.doc The check node of -49-200952349) will send the message of the value of the correct rate and the accuracy of the correct rate to the variable node connected to the check node, so the decoding performance will be degraded. The decoding performance is further deteriorated when the length (the number of bits that become the error due to the burst) is very large. Therefore, the parity interleaver 23 (Fig. 8) is to prevent the degradation of the above decoding performance from being performed. The parity bits of the LDPC code of the LDPC encoding section 21 are interleaved to the co-located interleaving of the positions of the other parity bits. Fig. 20 is a diagram showing the check matrix of the LDPC code corresponding to the co-located interleaver 23 of Fig. 8. The information matrix HA of the check matrix corresponding to the LDPC code defined by the specification of DVB-S.2 is a tour structure. The tour structure refers to a line and other lines. The configuration after the cyclic shift (rotation) is consistent, and includes, for example, every P row, the position of each of the columns of the P row is the initial row of the P row, and only the value obtained by dividing the parity is q. The proportional value is the structure of the position after the cyclic shift in the row direction. Hereinafter, the P row of the tour structure is appropriately referred to as the number of rows of the tour structure. The DVB-S.2 outputted by the LDPC encoding unit 21 The LDPC code specified in the specification is as shown in Fig. 11. There are two types of LDPC codes of code length N of 64800 bits and 16200 bits. Now, if the code length N is concerned, it is 64800 bits and 16200 bits. The code length N of the two types of LDPC codes is an LDPC code of 64,800 bits. The code length N of the LDPC code of coding rate of 64,800 yuan system illustrated in FIG. 11, 11.

Regarding the LDPC 137720.doc -50· 200952349 code of which the code length N of each of the 11 coding rates is 64,800 bits, the specification of the DVB-S.2 specifies that the number of rows P of the unit of the tour structure is One of the divisors of the same position and one of the divisors of 360. Further, regarding the LDPC codes in which the code lengths of the 11 coding rates are 64,800 bits, the parity is a value other than the prime number expressed by the formula M = qxP = qx360, using a value q different depending on the coding rate. Therefore, the value q is also the same as the number of rows P of the unit of the patrolling structure, and the other one of the divisors of the collocation structure, and the other number of the circumstance, the number of rows in the unit of the patrolling structure is divided by the number of rows Μ 获得 获得 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( As described above, when the information length is set to K, and the integer of 0 or more and less than P is set to X, and the integer of 0 or more and less than q is set to y, it will be from the LDPC as a parity interleaving. The Κ+qx+y+l code bits in the same bit of the K+1 to K+M (=N) code bits of the LDPC code of the encoding unit 21 are interleaved to the K+Py+x +1 location of the code bit. According to the co-located interleaving, since the variable nodes (corresponding co-located bits) connected to the same check node are only separated by the number of rows P of the unit of the tour structure, that is, only 360 bits apart, When the length is less than 360 bits, a plurality of variable nodes connected to the same check node can be prevented from becoming an error at the same time, and the result is improved tolerance to burst errors. In addition, the LDPC code after the Κ+qx+y+1 code bits are interleaved to the position of the Κ+Py+x+l code bits is the same as the original check matrix 将The +qx+y+1 row is replaced by the row K+Py+x+1 row 137720.doc -51 - 200952349 The LDPC codes of the check matrix (hereinafter also referred to as the conversion check matrix) obtained are identical. Further, in the parity matrix of the conversion check matrix, as shown in Fig. 20, a pseudo-tour structure in which P rows (360 rows in Fig. 20) are used as a unit appears. Here, the pseudo-tour structure means that a part of the structure is a structure of the tour structure. For the check matrix of the ldpc code specified by the specification of DVB-S.2, the conversion check matrix obtained by the row replacement corresponding to the co-located interlace is part of 36 (^) x36 in the right corner portion (described later) The shift matrix) only lacks the element of the solid (the element of 〇), so it is a non-(complete) tour structure and becomes a pseudo-tour structure. In addition, the conversion check matrix of Fig. 20 becomes the original check matrix Η ' In addition to the permutation of the co-located interleaving, the permutation (column permutation) for arranging the constituent matrices to be described later in the conversion matrix is also applied. Referring to FIG. 21 to FIG. The vertical twisting of the rearrangement process performed by the twisting interleaver 24 is performed. The t-feeding device u' of the figure is used to increase the frequency, and the LDPCm is as long as the 'bits of ', and the horse is more than 2 bits. 1 symbol is sent. That is, for example, when the mother of the mother- _ change mode is used as the case of one symbol, the W WQPSK is used as the character. '' 'As a modulation method, for example, 16QA M. So, 'will exhaust the eve, &, if the 2 digits or more are sent as a symbolic element of a symbol, then the symbol (allocated to the symbol is wrong) (Erase) 137720.doc 200952349 Therefore, in order to improve the decoding performance, reducing the number of variable nodes (corresponding code bits) connected to the same check node becomes the erasure accuracy, and must avoid corresponding to 1 The variable node of the symbol bit of each symbol is connected to the same check node. On the other hand, as described above, the check matrix H of the LDPC code specified by the specification of DVB_S 2 output by the LDPC encoding unit 21, the information moment Ηα Containing a tour structure, the co-located matrix ΗΤ contains a step structure. Then, as illustrated in Figure 2〇, the check matrix of the LDPC stone horse after the co-interlace is the conversion check matrix, and the patrol structure also appears in the parity matrix (correctly, as described above Fig. 21 is a conversion check matrix. That is, Fig. 21A shows a conversion check of the check matrix η of the LDPC code whose code length is 648 bits and the coding rate (1) is 3/4. Matrix. Figure 21Α In the conversion check matrix, the position of the element with a value of 1 is represented by a dot (·). The LDpc code of the conversion check matrix of Fig. 21Α, that is, the LDPC code of the same bit interleaved as the object 'represents the solution multiplexer 25 (Figure B 〇 〇 。 。 。 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于In the longitudinal direction of the memory 31, the code bits written in the wale direction are in the course direction, and are read in units of 4 bits to become 1 symbol. In the case of '4' 'It is also possible to become a 4-bit code bit of 1 symbol. I37720.doc -53- 200952349 is a code bit corresponding to 1 of any one of the columns of the conversion check matrix of Fig. 21A. Next, corresponding to the ice code position 兀B 〇, B], B2, B3 variable point is connected to the same check node. Therefore, in the 4-bit of 1 symbol, find the η horse position τ〇Β0, Β丨, Β2, Β3 to correspond to any of the conversion check matrix! In the case where the column ί 1 兀 兀 , , , , 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元As a result, the exhaustion performance deteriorates. The coding rate, which also corresponds to the complex digital bit connected to the variable node, may also be used as

Regarding the coding rate of 3/4, the complex number of the same check node can be one symbol of 16QAM. Thus, the whirling torsion interleaver 24 performs the interleaving of the code bits of the LDPC code interleaved from the co-located interleaver 23, and interleaves the wobbles B to correspond to any i-column located in the conversion check matrix. The complex digital bit is not included in one symbol. Fig. 22 is a view showing the longitudinal twisting and interlacing. That is, FIG. 22 shows the memory 31 of the multiplexer 25 (FIG. 16, FIG. 屺, the hidden body 31 is as illustrated in FIG. 16 and has a memory level in the vertical (longitudinal) direction, and is in the course. The memory capacity of the (horizontal) direction memory N/(mb) bit is composed of a walt. Then, the wales are twisted and interleaved. The H24 system is used to control the LDpc code. In the row direction, the writing position is started at the time of reading in the horizontal direction, thereby performing the directional twisting interleaving. That is, the 'longitudinal twisting interleaver 24, for the plural wales, is suitable for the 137720.doc -54 200952349 to change the start code. The start of the write position of the bit, so that the complex-matrix as the 1-symbol read in the horizontal direction does not become the code bit corresponding to one of the arbitrary ones of the conversion check matrix (heavy The code bits of the LDPC code are arranged such that the complex digital bits corresponding to any one of the columns of the check matrix are not included in the same symbol. Here, FIG. 22 shows that the modulation mode is 16QAM and FIG. 16 A configuration example of the memory 3 1 in the case where the multiple b of the description is 1. Therefore, the LDPC code which is the i symbol is used. The number m of bits of the code bit is 4 bits, and the memory 3 1 ® is composed of 4 (= mb) wales. The whirling twist interleaver 24 (instead of the multiplexer 25 of Fig. 16) The writing of the LDPC code from the four vertical lines constituting the memory 31 from the top to the bottom (the waling direction) is performed in the wales from the left to the right direction. Then, if the code bits are written When the rightmost vertical line ends, the vertical twist interleaver 24 reads the code bits in units of 4 bits (mb bits) in the row direction from the first column of all the wales constituting the memory 31. And the LDPC code after the twisting of the wales is output to the replacement unit 32 of the multiplexer 25 (Figs. 16 and 17). Here, in the reticular interleaver 24, if the wales are at the beginning (the most The address of the position above is set to 〇, and the address of each position in the waling direction is represented by an integer in ascending order. For the leftmost wales, the start writing position is set to the position where the address is ' 'About (from left) In the second vertical line, the start write position is set to the position where the address is 2, and regarding the third vertical line, the start write position is set to the position where the address is 4, and regarding the 4th vertical line, it will be opened. The initial write position is set as the address for the position. In addition, the start write position is the position other than the position where the address is 137 137720.doc -55- 200952349 仃 仃 'write the code bit 至 to the bottom position , return to the beginning (the address is the location of 〇), write until the position before the start of the write position. Then, write from the next (right) wales. Longitudinal torsion interleaving, the code length N specified by the specification of dvb_S 2 is 648〇〇, and all the coding rates 2LDpc^^ can avoid the complex digital bits corresponding to the complex variable nodes connected to the same-check node. As a result of 1 symbol of 16QAM (including the same symbol), the decoding performance of the erased communication channel can be improved. FIG. 23 is an LDpc code for a code rate N of 648 oo specified by the specification of DVB_S 2, and the number of wales of the memory 3 必要 necessary for the wobble interleaving according to each modulation mode and the start of writing. The location of the location. Since the multiple b is 1, and the modulation method is, for example, QpSK, if the number of bits of the symbol is 1!! is 2 bits, according to FIG. 23, the memory h is stored in the direction of the memory 2xl (= The mb) two wales of the bit store 64800/(2x1) bits in the wale direction. Then, in the two wales of the memory 31, the start write position of the first wales is set to the position of 〇, and the start write position of the second traverse is set to the position of address 2. In the case where the replacement of the demultiplexer 25 (Fig. 8) is used as an alternative to the first to third alternatives of Fig. 16, the multiple b becomes 1. Since the multiple b is 2, and the modulation method is, for example, QpSK, where the number of bits m of the 1 symbol is 2 bits, according to FIG. 23, the switching system stores 2x2 bits in the horizontal direction. The four vertical lines, in the vertical line J 137720.doc -56- 200952349 recall 64800 / (2x2) bits. Then, in the four wales of the suffix 31, the start write position of the first squad line is set to the position where the address is 0, and the start write position of the second traverse line is set as the address for the position of the third vertical line. The start write position is set to the position where the address is 4, and the start write position of the 4th vertical line is set to the position where the address is 7. Further, when the fourth alternative of the figure is used as an alternative to the replacement processing of the demultiplexer 25 (Fig. 8), the multiple b becomes two. ❹ 由于 由于 倍 倍 倍 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于4 vertical lines, 64800/(4x1) bits in the longitudinal direction. After 2, in the 4 wales of the memory 31, the write position of the first row is set to the address of 0, and the write position of the 2nd row is set to the address of 2, the third vertical The start write position of the line is set to the position where the address is 4, and the start write position of the *th vertical line is set to the position where the address is 7. ❹ * Since the multiple 匕 is 2' and the modulation method is, for example, 16QAM, if the number of bits of the 1 symbol is 4 4 bits, according to Fig. 23, the memory 31 contains 4 χ 2 bits in the horizontal direction. 8 vertical lines, remembering 64800/(4x2) bits in the wale direction. Then, in the eight wales of the 'memory' body 31, the start position of the first wall line is set as the address of the 〇, and the start position of the second traverse is set to the position of the address 帛3 vertical The start write position of the line is set to the position where the address is 2, the start write position of the 4th vertical line is set to the position where the address is 4, and the start write position of the 5th vertical line is set to the position where the address is 4, the sixth position The starting position of the wales is set as the address 137720.doc -57- 200952349 2 5.2 position π The starting position of the 7th waling is set to the position of the address 7, and the starting writing position of 緃仃 is set as the address is 7 position. For example, 64QAM is used because of the multiples, and the Α Α 因此 因此 因此 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ (4) The six vertical lines of the bit position are in the vertical direction, then, in the six vertical lines of the memory 31, the position is set to be 0, and the position of the start of the second is set. ^ The start position of the 2nd vertical is set as the address. The write position of the 3rd vertical line is set to the position where the address is 5, and the start position of the 4th is set to the position of the address of 9, The starting position of the first wales is set to the address of 1 * * the address is 13. The write position is set as the bit b is 2' and the modulation method is, for example, 64QAM, = bit number. In the case of 6 bits, 'If according to Fig. 23, the memory system 3 has 6X2 bits in the horizontal direction. The 12 vertical lines of Yuan, the memory of 64800/(6x2) bits.

Then, among the 12 wales of the memory 31, the start of the mth line is set to the position where the address is 〇, and the start position of the second traverse is set to the position where the address is 0, and the third vertical The start write position of the line is set to the position where the address is 2, the start write position of the right trajectory is set to the position where the address is 2, and the start write position of the 5th vertical line is set to the position where the address is 3, the sixth vertical The start write position of the line is set to the position where the address is 4 'the start position of the 7th vertical line is set to the position where the address is 4'. The start write position of the 8th vertical line is set to the position where the address is 5, the ninth position The starting position of the wales is set to the address of 5, the beginning of the first line of writing Z 137720.doc 200952349 is set to the address of 7, the starting position of the 丨丨 丨丨 is set as the address is At the position of 8, the start position of the 12th wales is set to the position of the address 9. Since the multiple b is 1 ' and the modulation method is, for example, 256qAM, if the number of bits of the 1 symbol is 8 bits, according to FIG. 23, the memory 31 contains 8x1 bits in the horizontal direction. The 8 wales store 64800/(8x1) bits in the wale direction. Then, in the eight wales of the memory 3 1 , the start write position of the 丨 丨 设 is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address. The write position of the third vertical line is set to the position where the address is 2, the start write position of the fourth vertical line is set to the position where the address is 4, and the start write position of the fifth vertical line is regarded as the position of the address of 4. The write position of the sixth vertical line is set to the position where the address is 5, the start write position of the seventh vertical line is set to the position where the address is 7, and the start write position of the eighth vertical line is set as the address for the position. . Since the multiple b is 2, and the modulation method is, for example, 256QAM, if the number of bits of the 1 symbol is 8 bits, the memory body 31 is stored in the horizontal direction to store 8x2 bits. Longitudinal, remembering 64800/(8x2) bits in the wale direction. ^In the 16 wales of the 3rd recalled body 3, the starting write position of the 丨 丨 设 is set as the address of 〇 'the start position of the 2nd waling is set to the position where the address is 2' The start position of the third wales is set to the position where the address is 2, and the start write position of the fourth wales is set to the position where the address is 2, and the fifth wales are opened. Write location. The address of the address is 2, and the write position of the sixth vertical line is set to the position where the address is 3'. The start position of the 7th vertical line is set to the position where the address is 7 and the write position of the 8th vertical line is started. The address is set to the location, the write position of the ninth vertical line 137720.doc -59- 200952349 is set to the address of 16, and the write position of the 10th vertical line is set to the address of 20, the first The start position of the 11 wales is set to the position of the address 22, and the start write position of the 12th wales is set to the position where the address is 22'. The start write position of the 13th waling is set to the position of 27, The write position of the 14th wales is set to the address of 27, the start write position of the 15th ordinate is set to the address of 28, and the write position of the 16th trajectory is set to the address of 3 2 position. Since the multiple b is 1, and the modulation method is, for example, 1024qam, when the number of bits of the 1-symbol is ^bit, according to FIG. 23, the memory_3 is stored in the horizontal direction. 〇x 1 bit 〇 纵 纵, memory 64800 / (1 〇 xl) bits in the waling direction. Then, in the 10 wales of the memory 3 1 , the start write position of the 丨 丨 设 is set as the address of 〇, and the write position of the 2nd ordinate is set as the position of the address 3, The start position of the 3 wales is set to the position where the address is 6, the start position of the 4th rowth is set to the position of the address 8, and the start write position of the 10000th line is set to the position of the address of 11, The start position of the sixth wales is set to the position of the address 13, and the start position of the seventh traverse is set to the address of 15 ©. The position of the eighth octant is written as the address 丨7 At the position, the start position of the ninth wales is set to the position of the address 18, and the start write position of the first wales is set to the position of the address of 20. Since the multiple b is 2' and the modulation method is, for example, 1〇24qAM, when the number of bits of the 1# element is i 〇 bit, the memory 31 is stored in the horizontal direction according to the figure. ; < 20 wales of 2 bits, remembering 64800/(10x2) bits in the wale direction. ]3772〇.doc -60· 200952349 Then, in the 20 wales of the memory 3 1 , the start write position of the ith walt is set as the address of 〇, and the write position of the second row is set as The address of the address is 1 and the write position of the 3rd ordinate is set to the address of 3, the write position of the 4th traverse is set to the address of 4, and the write position of the 5th trajectory is set as the start position. The address of the address is 5, the write position of the sixth vertical line is set to the address of the address 6, the start position of the seventh vertical line is set to the address of the address of 6 and the write position of the eighth vertical line is set as the start position. The address of the address is 9 and the start write position of the 9th vertical line is set to the address of 13, and the start write position of the 1st vertical line is set to the position of the address, and the start of the U vertical line is written. The position is set to the address of 14 and the start of the 12th traverse is set to the address of "the position of the 13th wales. The write position is set to the address of 2 1 , and the 4th traverse The start write position is set to the position where the address is 21, the start write position of the 15th vertical line is set to the position of the address 23, and the start write position of the 16th vertical line is set to the position of the address 25 At the beginning of the 17th ordinate, the write position is set to the position of the address, the start position of the 18th ordinate is set to the position where the address is %, and the start write position 6 of the first vertical ❹/亍 is the address At the position of 28, the write position of the first vertical line is set to the position of 3 〇. Since the multiple b is 1, and the modulation method is, for example, 4〇96QAm, the number of bits of the 1 symbol is 12 bits. In this case, according to Fig. 23, the memory 3 1 system 3 stores 2 wales of 12 χ 1 bit in the course direction, and stores 64800 / (12x1) bits in the wale direction. Then, the memory 31 Among the 12 wales, the start write position of the 丨 丨 设 is set to the position of 〇, the start position of the second traverse is set to the position of 〇, and the write position of the third trajectory is set. The address is 2, 137720.doc -61 - 200952349 The starting position of the 4th traverse is set to the position of the address 2, the first collateral. The write position sighs the address to the position of 3 '... The start position of the wales is set to the position where the address is 4, 'the start position of the 7th waling is set to the position where the address is *', and the write position of the 8th waling is set. The address of the address is 5, the start position of the ninth wales is set to the address of 5, and the beginning of the first line is written as the position of the address 7. The start position of the UD is set. The address of the address is 8 and the start position of the 12th trajectory is set to the position of the address 9. The multiple b is 2' and the modulation method is, for example, 4〇96qam, so the 1st 7L bit reads „! In the case of 12 bits, according to Fig. U, the memory η is stored in 24 wales of the horizontal direction memory >< 2 bits, and 64800 / (12x2) bits are stored in the vertical direction. Then, among the 24 wales of the memory 31, the start write position of the first wales is set as the address of the ' position. The start position of the second wales is set to the position where the address is 5, and the third vertical position The start write position of the line is set to the address of 8, the start write position of the 4th vertical order is set to the address of the address 8, and the start write position of the first vertical line is set to the address of the address of 8, the sixth The start position of the wales is set to the address of 8, the start position of the 7th ordinate is set to the address of 忉, and the write position of the 8th traverse is set to the address of 1〇. The start position of the ninth wales is set to the position of 1 ,, and the start write position of the first 〇 设 is set to the position where the address is 12'. The start position of the utitudinal line is set to address 13 The position of the beginning of the 12th waling is set to the position where the address is μ, the starting writing position of the 13th waling is set as the address of the mouth, and the starting writing position of the thy collateral is set as the address is The position of the beginning of the 15th ordinate is set to the address of 21, and the write position of the 16th waling is set to 137720.doc -62· 200952349 is 22 The write position of the 17th wales is set to the position where the address is 23'. The write position of the 18th ordinate is set to the address of 26, and the write position of the 19th traverse is set to the address of 37. The position of the start of the 20th wales is set to the position of the address 39, the start write position of the 21st wales is set to the address of 40, and the write position of the 22nd walt is set as the address. The position of the 41th position is the position where the address is set to 4, and the write position of the first line is set to the position of 41. Fig. 24 is an LDPC code for a coding rate of 162 码 for a code length of DVB-S.2, and a memory 3 1 for vertical wobble interleaving according to each modulation method. The number of wales and the address at which to start writing. Since the multiple b is 1, and the modulation method is, for example, QpSK, the number of bits of the symbol „! is 2 bits, and according to FIG. 24, the memory is stored in the horizontal direction to store 2×1 bits. Two vertical lines, which store 16200/(2 XI) bits in the wale direction. Then, in the two wales of the memory 31, the start of the 丨 丨 写 write position is set as the address of the 〇 The start position of the second wales is set to the position where the address is 0. Since the L number b is 2' and the modulation method is, for example, QpsK, the number of bits of 1 symbol _ 2 bits is determined according to In Fig. 24, the memory "containing 4 wales of 2x2 bits in the horizontal direction and 16200/(2x2) bits in the waling direction. Then, in the four wales of the memory 31, the start write position of the first hidden line is set to the position where the address is 0, and the start write position of the second vertical line is set to the position where the address is 2, the third vertical line The start write position is set to the position where the address is 3, and the start write position of the 4th 137720.doc -63- 200952349 is set to the position where the address is 3. Since the multiple b is 1, and the modulation method is, for example, i6qam, the number of bits of the 兀! is 4 bits, and according to Fig. 24, the memory system contains 4xl in the horizontal direction. 4 wales of the bit, 16200/(4 xl) bits in the wales. Then, in the 4 wales of memory and body 3!, the starting write position of the first scent line is set to address 0. Position, the start position of the 2nd wales is set to the position where the address is 2, the start write position of the 3rd ordinate is set to the address of 3, and the write position of the 4th traverse is set to the address of 3 Since the multiple b is 2 and the modulation method is, for example, 16QAM, if the number of bits of the 1-symbol m is 4 bits, the memory 31 is stored in the horizontal direction according to FIG. 8 vertices of 4x2 bits, 16200/(4x2) bits are memorized in the wale direction. Then, in the 8 wales of the memory 31, the start write position of the 丨 丨 is set to be 0. Position, the start position of the 2nd wales is set as the address of 〇, and the write position of the 3rd ordinate is set to the position of 〇, and the start of the 4th trajectory The position where the address is 1 is set to 'the start position of the 5th vertical line is set to the position where the address is 7, and the start write position of the 6th vertical line is set to the position where the address is 20'. The start of the 7th vertical line The write position is set to the position of the address (10), and the start write position of the eighth vertical line is set to the position of the address 21. Since the multiple b is 1, and the modulation method is, for example, 64qam, the 1-bit symbol In the case where the number m is 6 bits, 'According to Fig. 24, the memory 3 1 contains 6 vertical lines of 6 χ 1 bits in the course direction, and '16200/(6x1) bits are memorized in the wale direction. 137720.doc • 64· 200952349 Then, in the six wales of the memory 31, the start write position of the first vertical line is set to the position where the address is 0, and the start write position of the second vertical line is set as the address is In the position of the 〇, the start position of the third wales is set to the position where the address is 2, the start write position of the *th walt is set to the position where the address is 3, and the start write position of the 5th traverse is set as the address. For the position of 7, the start position of the sixth wales is set to the position of the address 7. Since the multiple b is 2, and the modulation method is, for example, 64Qam, ❹1 In the case where the number of bits m is 6 bits, according to FIG. 24, the memory 31 contains 12 vertical lines in which 6 χ 2 bits are stored in the horizontal direction, and 16200/(6×2) bits are stored in the vertical direction. Then, in the 12 wales of the memory 3 1 , the start write position of the first wales is set as the address of the 〇, and the start write position of the second traverse is set as the address of the ,, the first 3 The starting position of the vertical line is set to the position of the address, the writing position of the 4th vertical line is set to the position where the address is 2, and the writing position a of the 5th vertical line is set to the position of the address 2. The write position of the sixth vertical line is set to the position where the Q address is 2, the start write position of the seventh vertical line is set to the position where the address is 3, and the start write position of the eighth vertical line is set to the address of 3 At the position, the start position of the ninth wales is set to the position where the address is 3, the start write position of the first wales is set to the position where the address is 6, and the start write position of the 丨丨 丨丨 is set as the position. The address is the position of 7, and the start position of the 12th wales is set to the position of the address 7. Since the multiple b is 1, and the modulation method is, for example, 256Qam, if the number of bits 111 of the 1-bit is 8 bits, according to FIG. 24, the memory 3 1 is stored in the horizontal direction. The 8 vertical lines of the bit store 16200/(8x1) bits in the wale direction. 137720.doc -65- 200952349 = In the arbitrage of the continent, the division of (four) m rows ❹ Γ5 is the location of the location of G. The start of the second trajectory is set as the address: the location of the ' '3 The start position of the wales is set to the position where the address is G, the start write position of the 4th wales is set to the position where the address is 2, and the start write position of the first line is set to the position where the address is 2' The start position of the wales is set to the position where the address is 2'. The write position of the 7th ordinate is set to the address of 2, and the write position of the 8th traverse is set to the position of 2, the first 9 vertical line: the initial write position is set to the address of 5, the first write position of the 1st vertical line is set to the address of 5, and the write position of the 11th vertical line is set to the address of 5 Position, the start position of the 12th wales is set to the position where the address is 5, the start write position of the 13th wales is set to the address of 5, and the start write position of the 14th ordinate is set to the address of 7 At the position, the start position of the 15th wales is set to the position where the address is 7, and the start write position of the 16th ordinate is set to the position where the address is 7 'the start position of the 17th walt is set as the position. For the position of 7, the write position of the 18th wales is set to the position of the address 8, the start position of the 19th traverse is set to the address of 8, and the write position of the 20th wal is set as the bit. The location is 1 〇. Since the multiple b is 1, and the modulation method is, for example, 4096QAM, the number of bits of the first symbol „! is 12 bits, and according to FIG. 24, the memory 31 contains 12x1 bits in the horizontal direction. 12 wales of the element, remembering 16200/(12x1) bits in the waling direction. Then, in the 12 wales of the memory 3 1 , the writing position of the first waling is set as the position of the 〇 The write position of the 2nd wales is set to the position of 〇, and the write position of the 3rd ordinate is set to the position of 0, 137720.doc -67- 200952349 The start position of the 4th wales The address is set to the position of 2, the write position 3 of the 5th vertical line is the position where the address is 2, and the write position of the 6th vertical line is set to the position of the address 2, the beginning of the 7th vertical line The write position is set to the position where the address is 3, the start write position of the 8th vertical line is set to the position where the address is 3, and the start write position of the 9th vertical line is set to the position where the address is 3, the first vertical line The start write position is set to the address of the address 6, the start position of the U vertical line is set to the address of the address 7, and the start position of the 12th vertical line is set to the address of 7 Since the multiple b is 2, and the modulation method is, for example, 4〇96QAM, if the number of bits of the 1 symbol is 12 bits, the memory module 31 is included in the course direction according to Fig. 24 . Memory 12><2 octaves of 24 bits, memory 16200/(12x2) bits in the wales direction. Then, in the 24 wales of the memory 31, the start position of the 丄 丄 分别 is set as The address of the address is 〇, the write position of the second traverse is set to the address of 〇, the write position of the third traverse is set to the address of 〇, and the write position of the fourth trajectory is set. The address of the address is 〇, the write position of the 5th ordinate is set to the address of 〇. The start position of the 6th row is set as the address of 〇, and the write position of the 7th ordinate is started. Set the address to be the position of the © 置 置 第 第 第 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写The start write position is set to the position where the address is 1, and the start write position of the uth vertical line is set to the position where the address is 2, and the start write position of the 12th vertical line is set as The address is the position of 2, the start write position of the Bth vertical line is set to the position where the address is 2, the first write position of the μth vertical line is set to the position where the address is 3, and the write position of the 15th vertical line is recognized. The address of the address is 7 and the write position of the 16th traverse is set to the address of 9 137720.doc -68- 200952349, and the write position of the 17th traverse is set to the address of the address 9, The start position of the 18 wales is set to the position of the address 9. The start position of the 19th wales is set to the address of 10, and the write position of the 20th traverse is set to the address of 1 0. Position, the start position of the 2nd wales is set to the address of 10, the write position of the 22nd wales is set to the address of 10, and the write position of the 23rd traverse is set as the address. At the position of 10, the start position of the 24th wales is set to the position where the address is 11. Next, the transmission processing performed by the transmitting apparatus 11 ® of Fig. 8 will be described with reference to the flowchart of Fig. 25. The LDPC encoding unit 2 1 waits for the supply of the target data, and encodes the target data into an LDPC code in step S1 01, supplies the LDPC code to the bit interleaver 22, and the processing proceeds to step S102. In step S102, the bit interleaver 22 performs bit interleaving on the LDPC code from the LDPC encoding unit 21, and supplies the symbolized symbol of the LDPC code interleaved to the mapping unit 26 for processing. The process proceeds to step S103. That is, in step S102, in the bit interleaver 22, the parity interleaver 23 performs the co-located interleaving with the LDPC code from the LDPC encoding unit 21, and supplies the co-interleaved LDPC code to the directional twist. Interleaver 24. The whirling twist interleaver 24 takes the LDPC code from the co-located interleaver 23 as a target, performs wobble interleaving, and supplies it to the demultiplexer 25. The demultiplexer 25 replaces the code bits of the LDPC code which are longitudinally twisted and interleaved by the wobble interleaver 24, and causes the replaced code bit to become a symbol of 137720.doc -69 - 200952349 Replacement processing of the bit (indicating the bit of the symbol). Here, the replacement processing by the demultiplexer 25 may be performed in accordance with the first to fourth alternatives shown in Figs. 16 and 17 and may be performed in accordance with the distribution rule. The allocation rule is a rule for assigning the code bits of the LDPC code to the symbol bits representing the symbols, which will be described later in detail. The symbols obtained by the replacement processing of the demultiplexer 25 are supplied from the demultiplexer 25 to the mapping unit 26. In step S103, the mapping unit 26 maps the symbols from the demultiplexer 25 to the signal points determined by the modulation method of the quadrature modulation by the quadrature modulation unit 27, and supplies them to the orthogonal modulation. The variable portion 27, the processing system proceeds to step S104. The quadrature modulation unit 27 performs the orthogonal modulation of the carrier in accordance with the signal point from the mapping unit 26 in step S104, and the processing proceeds to step S105 to transmit the modulated signal obtained as a result of the quadrature modulation. And ended up processing. Further, the transmission processing of Fig. 25 is repeated in the pipeline. As described above, by performing the co-located interleaving or the wobble interleaving, the tolerance for erasing or bursting errors in the case where the complex digital bit of the LDPC code is transmitted as one symbol can be improved. Here, in FIG. 8, for convenience of explanation, the parity interleaver 23 which is a block which performs the co-interlacing, and the vertical twist interleaver 24 which is a block which performs the wagger interleaving are individually formed, but the parity interleaver 23 and the vertical The row twisting interleaver 24 can also be constructed integrally. That is, any of the parity interleaving and the vertical twist interleaving can be performed by writing and reading the memory bit by the code bit, and can be written by the 137720.doc • 70- 200952349 which performs the code bit. The address (write address) is converted into a matrix of addresses (read addresses) from which the code bits are read. Therefore, if the matrix obtained by multiplying the matrix representing the co-located interlace and the matrix representing the wobble interleaving of the wales are obtained in advance, by using the matrix to convert the code bit, the co-located interleaving can be obtained, and the co-located interleaving is further performed. The LDPC code is the result of the twisted interleaving. Further, the demultiplexer 25 may be integrally formed in addition to the co-interleaver 23 and the whirling interleaver 24. That is, the replacement process performed by the demultiplexer 25 can also be represented by converting the write address of the memory 31 of the memory LDPC code into a matrix of read addresses. Therefore, if the matrix representing the co-located interlace, the matrix representing the wobble interleave, and the matrix obtained by the matrix representing the replacement process are obtained in advance, the matrix interleave, the wobble interleave, and the replacement process can be performed by the matrix. . Further, regarding the co-interlacing and the whirling twisting, only one or both of them may not be performed. Next, with reference to Figs. 26 to 28, an simulation of the measurement error rate (bit error rate) performed with respect to the transmitting apparatus 11 of Fig. 8 will be described. The analog system uses a channel with a D/U of 0 dB flutter. Figure 26 is a diagram showing the model of the communication channel used for the simulation. That is, Fig. 26A shows a model of the flutter used in the simulation. 137720.doc -71 - 200952349 Moreover, Fig. 26B shows a model of the chattering channel of the flutter represented by the model of Fig. 26A. Further, in Fig. 26B, Η represents the model of the flutter of Fig. 26A. Further, in Fig. 26, Ν denotes ICI (Inter Carrier Interference), and in the simulation, the expected value E[N2] of the power is approximated by AWGN. Fig. 27 and Fig. 28 show the relationship between the error rate obtained by the simulation and the frequency fd of the flutter. Further, Fig. 27 shows the relationship between the error rate and the Doppler frequency fd in the case where the modulation method is 16QAM and the coding rate (r) is 3/4, and the alternative is the first alternative. Further, Fig. 28 shows the relationship between the error rate and the Doppler frequency fd in the case where the modulation method is 64QAM and the code rate (r) is 5/6, and the alternative is the first alternative. Further, in FIGS. 27 and 28, the thick line indicates the relationship between the error rate and the Doppler frequency fd in the case of performing the co-located interleaving, the longitudinal torsional interleaving, and the replacement processing, and the thin line indicates that only the co-interlacing is performed. The relationship between the error rate in the case of the twisting interleaving and the replacement processing in the replacement processing and the Doppler frequency fd. As shown in any of Figs. 27 and 28, it can be seen that the case where all of the co-located interleaving, the whirling twist interleaving, and the replacement processing are performed is a case where only the replacement processing is performed, and the error rate is increased (smaller). Next, the LDPC encoding unit 21 of Fig. 8 will be further explained. As illustrated in Fig. 11, in the specification of DVB-S.2, there are two LDPC codes of code length N of 64800 bits and 16200 bits. Then, regarding the LDPC code with a code length N of 64,800 bits, there are 11 137720.doc -72-200952349 encoding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3. 3/4, 4/5, 5/6, 8/9, and 9/10. For an LDPC code with a code length N of 16,200 bits, one encoding rate of 1/4, 1/3, 2/ is specified. 5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6 and 8/9 (Fig. 11B). The LDPC encoding unit 21 performs encoding by using an LDPC code of a code length N of 64800 bits or 16200 bits in accordance with an inspection matrix 每 prepared per code length N and per coding rate (error correction coding) ). FIG. 29 shows an example of the configuration of the LDPC encoding unit 21 of FIG. The LDPC encoding unit 2 1 is composed of an encoding processing unit 60 1 and a storage unit 602. The encoding processing unit 610 is composed of a coding rate setting unit 611, an initial value table reading unit 612, a check matrix generating unit 613, an information bit reading unit 614, a coded parity calculating unit 615, and a control unit 616. The LDPC code of the target data supplied to the LDPC encoding unit 21 is supplied, and the LDPC code obtained as a result is supplied to the bit interleaver 22 (Fig. 8). In other words, the coding rate setting unit 61 sets the code length N and the coding rate of the LDPC code in response to, for example, the operation of the operator. The initial value table reading unit 612 reads out the check matrix initial value table described later in accordance with the code length N and the coding rate set by the coding rate setting unit 从11 from the storage unit 602. The inspection matrix generation unit 613 is arranged in accordance with the inspection matrix initial value table read by the initial value table reading unit 612 in a cycle of 36 lines (the number of rows P of the circuit structure) in the row direction. The rate setting unit 6 generates the information of the code length N and the coding rate κ (= code length N_the same length M) 137720.doc -73- 200952349 The element of the matrix HAil, generates the inspection matrix 11 and stores it in Memory Department (9). The information bit reading unit 6丨4 reads (takes) the information bit of the information length from the target material supplied to the L D p c encoding unit 2丨. The coded parity calculating unit 615 reads the check matrix 生成 generated by the check matrix generating unit 613 from the storage unit 6〇2, and calculates the parity bit of the information bit read by the information bit reading unit 614 based on the specific expression. Generating Codeword (LDpc Code) 0 The control unit 616 controls each block constituting the encoding processing unit 60A. The memory unit 602 stores a complex check matrix initial value table corresponding to the complex code rates shown in Fig. 2 for the two code lengths N of 648 及 and 162 分别, respectively. Further, the storage unit 〇2 temporarily stores the data necessary for the processing of the encoding processing unit 601. Fig. 30 is a flow chart for explaining the processing of the LDPC encoding unit 21 of Fig. 29. In step S201, the coding rate setting unit 611 determines (sets) the code length N and the coding rate r for performing LDpc coding. In step S202, the initial value table reading unit 6丨2 reads out from the storage unit 6〇2 the initial check matrix corresponding to the code length N and the coding rate determined by the coding rate setting unit 61丨. Value table. In step S203, the check matrix generation unit 613 obtains (generates) the code length N determined by the coding rate setting unit 6U by the check matrix initial value table read from the storage unit 602 by the initial value table reading unit 612. And the inspection matrix η ' of the coding rate ri LDPC code is supplied to the memory unit 6〇2 and stored. In step S204, the information bit reading unit 614 reads out the target data supplied from the LDpc encoding unit 21, and reads the code length N and the rate information corresponding to the 137720.doc • 74- 200952349 determined by the encoding rate setting unit 6 ι. The IK (= 资讯 information bit) is read from the memory unit _ and the test matrix 求出 obtained by the check matrix generation unit 613 is supplied to the edited parity calculation unit 65. In step S205, the coded parity calculation unit 615 The parity bits of the codeword c conforming to equation (8) are sequentially operated.

HcT = 〇 / • · (8) In equation (8), c denotes a column vector as a codeword (LDpc code), and j denotes a transpose of the column vector c. ❹ ❹ = This, as described above, in the column vector e of LDPC^'| (1 code word), the column vector A indicates the portion of the information bit, and the column vector indicates the portion of the parity bit '' The column vector c can be represented by the column vector A as the information bit and the column vector τ as the parity bit, and expressed by the equation c=[a|t]. Check matrix Η and column vector as LDPC code C = [A 丨] must be consistent

Hc ~ 〇, as the column vector τ constituting the parity bit of the column vector c=[a ]] of the formula Hct=〇 can be obtained by checking the parity matrix Ητ of the matrix h=[Ha|Ht] In the case of the ladder structure shown, the equation HcT=〇i row vector

The elements of the second column of HcT are sequentially obtained by making the elements of each column 〇. If the parity bit calculating unit 615 obtains the parity bit τ for the information bit a, the code word c=[AiT] represented by the information bit A and the parity bit T is used as the LDPC of the information bit A. The result is encoded and output. Further, the code word c is 64,800 bits or 16,200 bits. Thereafter, in step S206, the control unit 616 determines whether or not the LDpc code is terminated. In the case where it is determined in step S206 that the LDPC encoding is not completed, that is, 137720.doc -75· 200952349, for example, if there is still object data to be LDPC-encoded, the processing returns to step S201, and the processing of steps S201 to S206 is repeated as follows. . Further, in the case where it is determined in step S206 that the LDPC encoding is ended, that is, for example, when there is no object data to be LDPC-encoded, the LDPC encoding unit 21 terminates the processing. As described above, the check matrix initial value table corresponding to each code length N and each code rate r is prepared, and the LDPC encoding unit 21 encodes the LDPC of the specific code rate r of the specific code length N, and uses the corresponding code length corresponding to the specific code length. N and the check matrix generated by the check matrix initial value table of the specific coding rate r are performed. The check matrix initial value table will check the information matrix Ha (Fig. 9) of the information length K corresponding to the code length 因 corresponding to the LDPC code (the LDPC code defined by the check matrix )) and the coding rate r. The position of the element is expressed in a table of every 360 lines (the number of rows P of the circuit structure), and is prepared in advance according to the code length N and the inspection matrix of each coding rate r. 31 to 58 show a plurality of check matrix initial value tables defined by the specifications of DVB-S.2. That is, Fig. 31 is a table showing the check matrix initial value of the check matrix 对于 for the coding rate r of the code length r of 16200 bits as defined by the specification of DVB-S.2. Fig. 32 through Fig. 34 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code rate 64 of 64,800 bits with a code length r of 2/3 as defined by the specification of DVB-S.2. Further, Fig. 33 is continued from Fig. 32, and Fig. 34 is continued from Fig. 33. 137720.doc -76- 200952349 Figure 35 is a table showing the check matrix initial value of the check matrix 编码 for a code rate N of 16200 bits with a code length N of 3/4 as defined by the specification of DVB-S.2. Fig. 36 to Fig. 39 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code rate 64 of 64,800 bits with a code length r of 3/4 as defined by the specification of DVB-S.2. Further, Fig. 37 is a view continuing from Fig. 36, and Fig. 38 is a view continuing from Fig. 37. Moreover, Fig. 39 is continued from Fig. 38. Fig. 40 is a table showing the initial value of the check matrix of the check matrix 编码 for the code length r of 16200 ® bits, which is 4/5, as defined by the specification of DVB-S.2. Fig. 41 to Fig. 44 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code length 64 of 64 800 bits with a code length r of 4/5 as defined by the specification of DVB-S.2. Further, Fig. 42 is continued from Fig. 41, and Fig. 43 is continued from Fig. 42. Moreover, Fig. 44 is a view subsequent to Fig. 43. Fig. 45 is a table showing the check matrix initial value of the check matrix 编码 of the code rate r of 5/6 with a code length 16 of 16200 bits as defined by the specification of DVB-S.2. ❹ Figs. 46 to 49 show the check matrix initial value table of the check matrix 编码 for the code length 64 of 64,800 bits and the code rate r of 5/6 as defined by the specification of DVB-S.2. Further, Fig. 47 is a view continuing from Fig. 46, and Fig. 48 is a view continuing from Fig. 47. Moreover, Fig. 49 is continued from Fig. 48. Fig. 50 is a table showing the check matrix initial value of the check matrix 编码 for the coding rate r of the code length r of 16200 bits as defined by the specification of DVB-S.2. Figure 51 to Figure 54 show the specifications for DVB-S.2 for code length Ν 137720.doc -77- 200952349

The check matrix initial value table is a check matrix of 64800 bits with an encoding rate r of 8/9. Further, Fig. 52 is continued from Fig. 51, and Fig. 53 is continued from Fig. η. Moreover, Fig. 54 is continued from Fig. 53. Fig. 55 to Fig. 58 are diagrams showing the check matrix initial value table of the check matrix H for the coding rate 49/1 of the code length n of 64_bit as defined by the specification of DVB_S2. Further, Fig. 56 is continued from Fig. 55, and Fig. 57 is continued from Fig. Moreover, Fig. 58 is continued from Fig. 57. The inspection matrix generation unit 613 (FIG. 29) uses the inspection matrix initial value table to obtain the inspection matrix 以下 as follows. That is, Fig. 59 shows a method of obtaining the inspection matrix η from the inspection matrix initial value table. In addition, the check matrix initial value table of FIG. 59 indicates that the code length specified by the specification of DVB-S.2 shown in FIG. 31 is 162 bits, and the code rate is 2/3 check matrix η. Check the matrix initial value table. The check matrix initial value table is as described above, and corresponds to the position of the element corresponding to the information matrix Ha (Fig. 9) corresponding to the code length N of the LDpc code and the information rate r, in every 360 lines (tour structure) The table of the number of rows in the unit p), in its column i, check the column number of the element of the l+360x(M) line of the matrix ( (the column number of the first column of the check matrix 设 is set as 〇 The number of the row is only the number of rows of the row of the 1+36〇χ(Μ) row. Here, since the parity matrix Ητ ( FIG. 9 ) corresponding to the parity M of the check matrix 决定 is determined as shown in FIG. 19 , the check matrix can be obtained according to the check matrix initial value 137720.doc • 78- 200952349 table. Η corresponds to the information matrix 资讯α of information length K (Figure 9). The number of columns k+Ι of the check matrix initial value table differs depending on the information length K. The relationship of equation (9) holds between the information length K and the number of columns k + 检查 of the check matrix initial value table. K = (k + l) x 360 -- - (9) Here, 360 of the formula (9) is the number P of the unit of the tour structure explained in Fig. 20 . Ο W In the check matrix initial value table of Fig. 59, there are 13 values arranged from the 1st column to the 3rd column, and 3 values are arranged from the 4th column to the k+th column (the 30th column in Fig. 59). . Therefore, the row weight of the check matrix H obtained from the check matrix initial value table of Fig. 59 is from the 1st line to the 1+36〇χ(3-1)-1 behavior 13 from the 1+36〇\ (3-1) Go to the action 〖 Behavior 3. The first column of the check matrix initial value table of Fig. 59 is 〇, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622, which is shown in the first row of the inspection matrix η. The elements whose column numbers are 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451 '4620, 2622 are i (and other elements are 0). Moreover, the second column of the check matrix initial value table of FIG. 59 is 1, ι 22, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, 3108, which is shown in the check matrix η 361 (=1+36〇χ(2-1)) lines, column numbers 1, 122, 1516, 3448, 137720.doc -79- 200952349 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, The element of 3108 is 1. As described above, the check matrix initial value table checks the position of the element of the information matrix Ha of the matrix H by every 360 lines. Check the line other than the l+36〇x(il) line of the matrix ,, that is, the line from the 2+360x0-1) to the 36th xi line will be determined by checking the matrix initial value table. +36〇x(il)! The elements are periodically arranged in a downward direction (downward direction of the line) in accordance with the same length M. That is, for example, the 2+36 (^(^) line only shifts the 1+36〇χ(Μ) line downward by only M/360 (=q), and then the 3+36〇x ( Il) The 1360 (i 1) line is only cyclically shifted by 2XM/36〇 (=2xq) in the down direction (the second 2+36〇x(il) line is only cyclically shifted M/36〇 (=q)) Now, if the value of the jth row (jth from the left) of the third column (the first one from the top) of the check matrix initial value table is expressed, and the matrix H is checked The column number of the jth 1st element of the Wth line is expressed as Hw_j, and then the column number of the element after the wth line of the line other than the 1st + 36〇x(ii) line of the matrix ! is checked!!... 〗 can be obtained from the formula (1〇).

Hw.j=mod{hiJ+m〇d((w-l),P)xq, Μ) • · · (10) where ‘mod(x,y) means the remainder after y is divided by χ. Further, ρ is the number of rows of the above-described tour structure, for example, the specification of kdvb_S.2 is 36〇 as described above. Further, fq is a value M/360 obtained by dividing the co-located length M by the number of rows p (= 36 〇) of the early position of the tour structure. 137720.doc -80- 200952349 The check matrix generation unit 613 (Fig. 29) specifies the column number of the element 1 of the 1+3 60 x (il) line of the check matrix 0 by the check matrix initial value table. Further, the inspection matrix generation unit 613 (FIG. 29) obtains the column number Hw_j of the element of the w-th row of the row other than the first +3 60x(il) row of the inspection matrix 按照 according to the equation (10). 'And generate an inspection matrix 作为 that takes the element of the column number obtained above as one. However, the LDPC code of 2/3 of the coding rate specified by the specification of DVB-S.2 is known to be an LDPC code difference (high) of other coding rates compared to the wrong floor. Here, as S/N (Es/N〇) becomes higher, the failure rate (BER) is reduced and passivated, and the phenomenon that the error rate does not decrease (wrong floor phenomenon) occurs, and the error rate when the voltage is not lowered is the wrong floor. If the wrong floor is high, in general, the communication channel 丨3 (Fig. 7) is less tolerant to errors, so countermeasures for improving tolerance to errors should be applied. φ is a countermeasure for improving the tolerance to errors, for example, a replacement process performed by the demultiplexer 25 (Fig. 8). The replacement process 'as an alternative to the code bit replacing the LDPC code is, for example, the above-described first to fourth alternatives, but the proposal is required to be more resistant to errors than the ones including the first to fourth alternatives. The way to improve it. Therefore, in the demultiplexer 25 (Fig. 8), as illustrated in Fig. 25, the replacement processing can be performed in accordance with the allocation rule. In the following, the replacement processing according to the distribution rule will be described. 137720.doc 81 200952349 describes the replacement method by the proposed method (hereinafter also referred to as the replacement processing currently performed. Referring to FIG. 60 and FIG. 61, This replacement processing is performed in the case where the replacement multi-device 25 is assumed to perform the replacement processing in the current manner. Fig. 60 is a diagram showing the LDPC code of the LDPC code weight 648 && An example of the replacement process of the current mode.

That is, FIG. 60A shows that the LDPC code is an LDPC code having a code length of N4 648 、 bits and a coding rate of 3/5, and the current mode is replaced in the case where the step modulation mode is 16qam and the multiple 匕 is 2. One example. In the case where the modulation method is 16QAM, the 4 (=111) bits of the code bit are mapped to i 6 Q A M as one symbol! Any of the 6 signal points. Further, when the code length N is 64,800 bits and the multiple 1 is 2, the memory 31 of the multiplexer 25 (FIG. 16, FIG. 17) contains 4x2 (= mb) bits in the horizontal direction. 8 vertical lines of the yuan, remembering 64_bits in the longitudinal direction. The code bit of the multiplexer 25' LDPC code is written in the direction of the vertical direction of the memory 31, and if the writing of the 64800-bit code bit codeword is finished, it is written in the memory 31. The code bits are successively arranged in the horizontal direction, in units of 4x2 (= mb) bits, and supplied to the replacement unit 32 (Fig. i6, Fig. 7). The replacement unit 32 is configured to assign a code bit 读出 of 4 χ 2 (= mb) bits read from the memory 3 兀, for example, as shown in FIG. 6A to 4x2 (= mb) of consecutive 2 (outer) symbols. The bit yQ, yi, y2, y3, y4, y5, y6, yA of the bit, replaces the code bit of the 4x2 (= mb) bit b〇 to b7e 137720.doc -82- 200952349, that is, The replacing unit 32 assigns the code bit bQ to the symbol bit y7, assigns the code bit b! to the symbol bit yi, assigns the code bit b2 to the symbol bit y4, and sets the code bit b3. Assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y5, the code bit b5 is assigned to the symbol bit y3, and the code bit b6 is assigned to the symbol bit y6, ® Bit b7 is assigned to the symbol bit y〇 and is replaced. Fig. 60B shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 64,800 bits and a code rate of 3/5, and a further modulation method is 64QAM, and the multiple b is 2. In the case where the modulation method is 64QAM, the 6 (=m) bits of the code bit are mapped to one of the 64 signal points determined by 64QAM as one symbol. Further, when the code length N is 64,800 bits and the multiple b is 2, the memory 31 of the multiplexer 25 (Figs. 16 and 17) is stored in the horizontal direction memory >< 2 (= Mb) 12 vertical lines of bits, remembering 64800/(6x2) bits in the wale direction. In the demultiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 3 1 , and if the writing of the 64800 bit code bit (1 code word) is finished, it is written in the memory 31. The code bits are read in the horizontal direction, in units of 6x2 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17). 137720.doc -83- 200952349 The replacement unit 32 is to read the code bits from the 6 χ 2 (= mb) bits of the memory 3 1 , 1) 1, 1) 2, 13, 匕 4, 1) 5,1)6,1)7,1)8,59,1)1〇,1)11, for example, as shown in Fig. 603, assigned to 6x2 (= mb) bits of consecutive 2 (=b) symbols Fuyuan bit 丫〇山,丫2,丫3,;^4,丫5,76,丫7,78,丫9,71〇,)^1, replace 6><2( = 1111) The bit elements bG to bn of the bit. That is, the replacing unit 32 assigns the code bit bG to the symbol bit yn, assigns the code bit h to the symbol bit y7, and assigns the code bit b2 to the symbol bit y3, and sets the code bit. Element b3 is assigned to symbol bit 710, code bit b4 is assigned to symbol bit y6, code bit b5 is assigned to symbol bit y2, and code bit 156 is assigned to symbol bit y9, The code bit b7 is assigned to the symbol bit y5, the code bit 1)8 is assigned to the symbol bit y, the code bit b9 is assigned to the symbol bit y8, and the code bit b1G is assigned to the symbol Bit y4, the code bit b! 1 is assigned to the symbol bit y, and is replaced. Fig. 60C shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length of 64,800 bits and a coding rate of 3/5, and a further modulation method is 256QAM, and the multiple b is 2. In the case where the modulation mode is 256QAM, the 8 (=111) bits of the code bit are mapped to one of the 256 signal points determined by 256QAM as one symbol and 137720.doc •84·200952349 one. Further, when the code length N is 64,800 bits and the multiple 5 is 2, the memory 31 (FIG. 16, FIG. 17) of the multiplexed H 25 contains 8x2 (= mb) bits in the horizontal direction. 16 wales, memory 648 〇〇 / (^ bit in the wale direction / / multiplexer 25, LDPC code code bits are written in the longitudinal direction of the memory 31, if 64800 bits When the writing of the code bit (1 code word) is completed, the code bit written in the memory 31 is in the course direction, and is read out in 8x2 (= mb) bit units and supplied to the replacement unit 32 (Fig. 16. Fig. 17) The replacement unit 32 assigns the code bits read from the memory 3128x2 (= mb) bits 兀 boA 'bhbhb bsbhbhbhbhbhbmbmbababM, !^, for example, as shown in Fig. 60C to consecutive 2 (= b) The symbol of the 8x2 (= mb) bit of the symbol 兀ythyhyaW'yhysyhyhyhyhyhyhyyn'yaymywyMt* type 'replaces the code bits b8 to b15 of 8x2 (= mb) bits. That is, the 'replacement part 32 separates the code The bit b G is assigned to the symbol bit y 丨 5, 码 the code bit b 1 is assigned to the symbol bit y J , and the code bit b 2 is assigned to the symbol bit y 丨 3 , Element b 3 is assigned to symbol element y 3, and code bit b4 is divided For the symbol bit y8, the code bit b5 is assigned to the symbol bit y丨1, the code bit b6 is assigned to the symbol bit y9, and the code bit b7 is assigned to the symbol bit y5. The code bit b 8 is assigned to the symbol bit y! 〇, 137720.doc -85- 200952349 The code bit b9 is assigned to the symbol bit y6, and the code bit b! 〇 is assigned to the symbol bit y 4. Assign the code bit b π to the symbol y 7 ' to assign the code bit b 12 to the symbol y 1 2 ' to assign the code bit b! 3 to the symbol y 2, The code bit b 4 is assigned to the symbol bit y 1 4, and the code bit b 15 is assigned to the symbol bit y 〇 ' for replacement. Fig. 61 shows that the LDPC code is code length N is 16,200 bits. An example of the replacement processing of the current mode in the case of an LDPC code having a coding rate of 3/5. That is, Fig. 61A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 3/5. An example of the replacement processing of the current mode in the case where the modulation method is 16QAM and the multiple b is 2. When the modulation method is 16QAM, the 4 (=m) bits of the code bit are used as one symbol. And mapped to 16 signal points determined by 1 6QAM Further, when the code length N is 16,200 bits and the multiple b is 2, the memory 3 1 of the multiplexer 25 (Fig. 16, Fig. 17) contains 4x2 in the horizontal direction (= Mb) 8 vertical lines of bits, remembering 16200/(4x2) bits in the wale direction. In the demultiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 3 1 , and if the writing of the 16200 bit code bit (1 code word) is finished, it is written in the memory 3 The code bits of 1 are read in the horizontal direction, read in units of 4 X2 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17). 137720.doc -86- 200952349 The replacement unit 32 is to read the code bits 兀%,1>1,152,1)3,154,1)5,136,1) from the memory 31i4x2 (=inb) bits. 7. For example, as shown in Fig. 61, the symbol bits of the 4x2 (= mb) bits assigned to consecutive 2 (= 13) symbols are replaced by the code bits bG to b7 of 4x2 (= mb) bits. That is, the replacing unit 32 performs the same as the case of the above-described Fig. 60A, and performs replacement of the code bits b 〇 to t > 7 to the symbol bits 70 to ^7. Fig. 61B shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5, and a further modulation method is 64QAM, and a multiple of 1 is 2. In the case where the modulation method is 64QAM, the 6 (=111) bits of the code bit are mapped to one of the 64 signal points determined by 64QAM as one symbol. Further, when the code length N is 16,200 bits and the multiple 1 is 2, the memory 31 of the multiplexer 25 (Fig. 16, Fig. 17) contains 6x2 (= mb) bits in the horizontal direction. The 12 vertical lines of the yuan store ΐ62〇〇/(6χ2) bits in the longitudinal direction. 0 / in the multiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 31, and if the writing of the 16200 bit code bit (1 code word) is finished, it is written in the memory The code bits of 31 are read in the horizontal direction, read in units of 6x2 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17). The _ replacement unit 32 is a code bit to be read from the memory 3R6x2 (= mb) bits ^ 151, 132, 133, 1 ? 4, 135, 136, 1) 7, 138, 1 ? 9, 7 1 ( ), 1311, for example, as shown in FIG. 618, the symbol bits y〇'yi'y2, y3, y4, y5, y6, y7 are assigned to 6x2 (= mb) bits of consecutive 2 (= b) symbols. Y8, y9, yI 〇, yn way, replace 6 χ 2 卜) 137720.doc -87 · 200952349 bit code bits bQ to bu. That is, the replacing unit 32 is the same as the case of the above-described Tuna', and the replacement of the code bits bG to bn to the symbol bits or the like is performed. Fig. 61C shows that the LDPC code is an LDPC code whose code length N is 162 bits 3/5, and the modulation method is 256qam. In the case of the replacement method of the current mode, an example of the replacement process is . In the case where the modulation mode is 256QAM, the 8 bits of the code bit are (=111) bits.

It is mapped to one of the 256 signal points determined by 256QAM for one symbol. Further, the code length N is 16,200 bits, and when the multiple is {5 is 1, the memory Zhao 31 (FIG. 16, FIG. 17) of the multiplexer 25 is included in the horizontal direction memory kithb. Longitudinal, memory 16 employees in the waling direction / (8 χΐ: bit. / multiplexer 25' LDPC code code bits are written in the direction of memory 3 ι, S 16200 bits of code bits When the writer of (1 code word) is finished, the code bits written in the memory 31 are in the course direction, read out in 8-bit units, and supplied to the replacement unit 32 (Fig. j 6 and Fig. 17). The replacement unit 32 assigns the code bits read from the memory 31 < 8xl (== mb) bits, ^^^^^^, for example, as shown in Fig. 4, to 8x1 of the ten-symbol symbol ( =mb) The bit yG, yi y2, y3, y4, y5, y6, y7 of the bit 'replaces the code bit of the 8xl (= mb) bit ~ to !^. That is, the replacement part 32 The code bit bG is assigned to the symbol bit y7, respectively, and the code bit b! is assigned to the symbol bit y3, 137720.doc • 88 - 200952349 The code bit b2 is assigned to the symbol bit y 1, The code bit b3 is assigned to the symbol bit y5, and the code bit b4 is assigned to the symbol bit y2. The code bit b 5 is assigned to the symbol bit y 6, the code bit b6 is assigned to the symbol bit y4, and the code bit b7 is assigned to the symbol bit y〇 for replacement. Replacement processing of the distribution rule (hereinafter also referred to as replacement processing of the new replacement method). Fig. 62 to Fig. 64 are diagrams showing a new alternative. In the new alternative, the replacement unit 32 of the multiplexer 25 is in advance. Determining the allocation rule to replace the MM bit code bits. The allocation rule is a rule for assigning the code bits of the LDPC code to the symbol bits. The allocation rule specifies: the code bit of the code bit a group, a combination of a group of symbol bits corresponding to a symbol bit of a code bit group of the code bit group; and a group of code bits and a symbol bit of the group set; The number of bits of the symbol group and the number of bits of the symbol element (hereinafter also referred to as the group bit number). Here, the code bit element is as described above, and the error bit rate is different, and the symbol bit element is also There is a difference in the error rate. The code bit group is a group that distinguishes the code bits according to the error rate. The bit group is grouped into groups of symbol bits according to the error rate. Fig. 62 shows that the LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 2/3, and the modulation mode is further modified. 256QAM, the case where the multiple b is 2, 137720.doc • 89-200952349, the megabyte group and the cryption group. In this case, the 8x2 (= mb) bit read from the memory 31 The code bits 13〇 to 13]5 are grouped into 5 code bit groups GbbGbhGbhGbhGh according to the difference in error correction rates as shown in FIG. 62A. Here, the code bit group Gbi is a group whose subscript 丨 is smaller, and the code bit belonging to the code bit group Gbi has a better error rate (smaller). In FIG. 62A, respectively, the code bit group Gbi is a code bit element, the code bit group Gh is a code bit b, and the code bit group Gb3 is a code bit h to b. Included, the code bit group Gb4 is the code bit element, the code bit group _ group Gb5 is the code bit 13 „1 to 1)15. The modulation mode is 256QAM, in the case of multiples, the 符 元 位 位Yuanxiao 0 to >^5 is based on the difference in error correction rate, as shown in Fig. 62]3, the group can be divided into a group of symbolic elements ^"々^,^^^々%. Here, the pay unit group Gyi is the same as the code bit group, and the smaller the lower i is, the smaller the error rate of the symbol bit belonging to the symbol bit group Gyi is. In FIG. 62B, respectively, the symbol element group Gyi is represented by the symbol element ❹ 7〇71, 78, 79, and the symbol element group 〇 72 is the symbol element, 3? 3, 〇 belongs to the 'character bit group Gy; the system element bit"..., ^^~ belongs to the 'character bit group G> U is the symbol element y6, y7, y14 y15 belongs to. Figure 63 The LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 2/3, and an allocation rule in the case where the modulation mode is 25 6QAM and the multiple b is 2. The allocation rule 'code position in FIG. 63 The combination of the meta group 〇 151 and the symbol element group Gy4 137720.doc 90· 200952349 is used as a group renter _ , ^ 砰, and 杲〇, which is the first one from the left in the figure. Then The group number of the group of the group is defined as a unit. Here, the group set and the number of its group bits are collectively referred to as group set information. For example, the code bit group is The group of the group of the symbol and the group of the symbol, and the number of the group of the group, that is, the number of bits, are recorded as the group collection information (Gbl, Gy4, 1}. The distribution rule in Figure 63 'In addition to group collection information (10) In addition to (3), there is also a group collection information (10) Office... (3) (4) Rushan, (Gb35Gy3, 2), (Gb3, Gy4, 2), (Gb4, Gy3, l), (Gbs^yj,!), (Gb5 , Gy2, 3), (Gb5, Gy3, l). For example, group collection information (Gb», Gy4, i) means that it will belong to the code bit group.

The unit of the code bit of Gh is assigned to the 1-bit of the symbol bit belonging to the symbol bit group Gy*. Therefore, the allocation rule in FIG. 63 is defined as follows: According to the group collection information (Gb^Gy4, !), the one bit of the code bit of the first good mother bit group Gb! of the error correction rate is assigned to The error rate is the 1st bit of the symbol bit of the 4th good symbol group Gy4; according to the group set information (Gb2, Gy4, l), the error correct rate 2nd good code bit group Gt> 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error rate; according to the group set information (Gt>3, Gyi, 3) ' The third bit of the code bit of the third good stone horse bit group Gt>3 of the error rate is assigned to the three bits of the symbol bit of the j-good symbol group Gy! According to the group collection information (Gb^Gy^l), assign the error rate to the error rate of the third digit of the 137720.doc •91 · 200952349 code bit group Gt> 2 1 bit of the symbol element of the good symbol group Gy2; according to the group set information (Gb3, Gy3, 2), the code position of the 3rd good code bit group Gbs of the error rate is determined. The 2 bits are allocated to the 2nd bit of the symbol bit of the 3rd good symbol group Gy3 of the error rate; according to the group set information (Gb3, Gy4, 2), the error rate is 3rd. The 2 bits of the code bit of the code bit group Gb3 are allocated to the 2 bits of the symbol bit of the 4th good symbol bit group Gy4 of the error correction rate; according to the group set information (Gb^Gy3, !), assigning the 1st bit of the code bit of the 4th good ❹ code bit group Gb4 of the error rate to the 1st bit of the symbol bit of the 3rd good symbol bit group Gys. According to the group set information (Gb^G^, 〗), the 码 bit of the code bit of the 5th good code bit group Gbs of the error rate is assigned to the error correct rate Jth good symbol bit group One bit of the symbol bit of the group Gy!; according to the group set information (Gbs, Gy2, 3), assign the fifth bit of the error rate to the third bit of the code bit of the group Gbs, The error rate is the 3rd bit of the second good symbol group Gy2; ❿ and according to the group collection information, the error rate is 5th good code group 码 group Gbs code bit Shu bit, assigned to the error rate determined Shu good bit of the third symbol bit group of the symbol bits. As described above, the code bit group distinguishes the groups of code bits according to the error correction rate, and the symbol bit group is grouped according to the error correction rate. Therefore, the allocation rule can also be a combination of the error rate of the specified code bit and the error rate of the symbol bit that assigns the code bit. 137720.doc •92· 200952349 In this way, the allocation rule that specifies the combination of the error rate of the code bit and the error rate of the symbol bit that assigns the code bit is determined by improving, for example, the simulation of the BER. Tolerance of errors (tolerance to noise). Furthermore, even if the allocation of the code bits of a certain code bit group is changed in the bit of the same symbol bit group, (almost) does not affect the tolerance to errors. Therefore, in order to improve the tolerance to errors, the group set information that minimizes the BER (Bit Error Rate) of the wrong floor is specified, that is, the code bit group of the specified code bit is A combination (group set) of the symbol bit groups of the symbol bits of the code bit group of the code bit group, a code bit group of the group set, and a symbol bit group respectively The code bit and the number of bits of the symbol bit (group bit number) are used as an allocation rule, and the code bit is allocated to the symbol bit according to the allocation rule to replace the code bit. Among them, according to the allocation rule, the specific allocation method of which code bit is assigned to which symbol must be determined before the transmitting device 11 and the receiving device 12 (Fig. 7). Figure 64 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 63. That is, FIG. 64A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and the further modulation method is 256QAM, and the multiple b is 2, and the allocation rule according to FIG. 63 is used. The first example of the replacement of the code bit.

The LDPC code is an LDPC 137720.doc -93 - 200952349 code with a code length N of 64800 bits and a coding rate of 2/3, and a further modulation mode of 256QAM and a multiple of 1) is 2, in the case of the multiplexer 25 In the direction of the X direction, the direction of the X course is (648〇〇/(8χ2)) χ(8χ2). The 6 bits of the memory are written in the horizontal direction to 8x2 (= mb). The bit unit is read and supplied to the replacement unit 32 (Fig. 6, Fig. 17). The replacing unit 32 reads the code bits 1) of the 8><2 (=11113) bits from the memory 3 1 to the |315 according to the allocation rule of FIG. 63, for example, as shown in FIG. Give the symbolic y of 8x2 (= mb) bits of consecutive 2 (= b) symbols. To yis, replace the code bits of 8x2 (= mb) bits 1). To 1315. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y丨5, assigns the code bit b] to the symbol bit y 7, and assigns the stone element b 2 to the symbol. Bit yj, assign code bit b3 to symbol bit y 5, assign code bit b4 to symbol bit y 6, assign code bit b to symbol bit yi3, and code bit B6 is assigned to the symbol bit yn, the code bit b is assigned to the symbol y9, the code bit be is assigned to the symbol y8, and the code bit b9 is assigned to the symbol y 丨4 , the code bit b 1 〇 is assigned to the symbol bit y 丨 2, the code bit b π is assigned to the symbol y 3 , and the code bit b 12 is assigned to the symbol y 〇 , The bit b 13 is assigned to the symbol bit y], and the code bit b 14 is assigned to the symbol bit y 4, 137720.doc • 94- 200952349 The code bit b! 5 is assigned to the symbol bit y 2, and replace it. 64B is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and further modulation is 256QAM, and the multiple b is 2, and the code bit according to the allocation rule of FIG. 63 is used. The second example of replacement. According to Fig. 64B, the replacing unit 32 performs the following replacement for the code bits bG to b! 5 of the 8 X2 (= mb) bits read from the memory 3 in accordance with the allocation rule of Fig. 63:

The code bit bG is assigned to the symbol bit y! 5, the code bit b! is assigned to the symbol bit y! 4, the code bit b2 is assigned to the symbol bit ys, and the code bit b3 is assigned. To the symbol y5, assign the tilde b4 to the symbol y6, assign the locator b5 to the symbol y4, and assign the coder b6 to the symbol y2. Bit b7 is assigned to symbol bit y丨, code bit b8 is assigned to symbol bit y9, code bit b9 is assigned to symbol bit y7, and code bit b 1 〇 is assigned to symbol bit Yuan y! 2, assigning the m-bit b!! to the p-bit y 3, assigning the code bit b 1 2 to the symbol y 1 3, and assigning the code bit b 丨 3 to the symbol bit Yuan yi 〇, assign code bit b! 4 to symbol bit y 〇, and assign code bit b ! 5 to symbol y!!. 137720.doc -95- 200952349 Here, the code bit bi shown in FIG. 64A and FIG. 64B is assigned to the symbol bit yi in accordance with the allocation rule of FIG. 63 (according to the allocation rule). Figure 65 is a diagram showing the case where the replacement process of Figure 64A in the replacement process of the new alternative mode illustrated in Figures 62 to 64 has been performed, and the BER (Bit) in the case where the replacement process described in Figure 60C of the current mode has been performed. Error Rate: The result of the simulation of the bit error rate. That is, FIG. 65 shows an LDPC code defined by the specification of DVB-S.2 having a code length n of 64800 and a coding rate of 2/3, 256QAM as a modulation method, and 2 as a multiple b. BER in case. . ❿ In addition, in Fig. 65, the horizontal axis represents Es/N〇, the vertical axis represents BER ^, and the circle mark indicates that the BER 'star (star mark) in the case where replacement processing of the new replacement method has been performed indicates that the current The BER in the case of the replacement of the mode. Comparing the current resistance to the error As can be seen from Fig. 65, in the replacement processing of the replacement method of the new replacement method, the wrong floor drastically reduces the improvement of the reliability. In addition, in the present embodiment, for convenience of explanation, in the multiplexer, the section 32 performs the reading of the code bit from the memory 31 as an object: processing 'but the replacement processing can be controlled by The writing or reading of the memory is performed. < That is, the replacement processing can be performed by, for example, controlling the address), by reading out the bits in the order of the addresses of the 兀 饭 # - - - 读 四 四 四 四 四 四 四 四 四 四 四 四 四 四 。 。 。 。 。 。 。 。 。 。 The code of the hidden body 3 1 is then used as a table to improve the tolerance to errors. In addition to the replacement of 137720.doc • 96· 200952349 to reduce the wrong floor, there is also an LDPC code that reduces the wrong floor. The method. Therefore, in the LDPC encoding unit 21 (Fig. 8), the LDPC code having a code length R of 64,800 bits and a coding rate r of 2/3 is different from the check matrix initial value table defined by the specification of DVB-S.2. The inspection matrix initial value table of the appropriate inspection matrix is obtained, and the inspection matrix obtained from the inspection matrix initial value table can be encoded to obtain an LDPC code with good performance. Here, the appropriate check matrix is low Es/N 〇 (signal power per 1 power signal to noise power ratio) or Eb / N 〇 (signal power to noise power ratio per 1 bit) When the modulated signal of the LDPC code obtained from the check matrix is transmitted, the BER (Bit Error Rate) is made smaller to meet the check condition of the specific condition. Moreover, the LDPC code with good performance is obtained from the LDPC code of the appropriate check matrix. A suitable check matrix can be obtained by, for example, performing a simulation to transmit a BER simulation of a modulated signal of an LDPC code obtained from various check matrices satisfying a specific condition at a low Es/N〇. As a specific condition that should be met by an appropriate inspection matrix, for example, an analytical result obtained by an analytical method called a code property called Density Evolution is good, and a check matrix does not exist as a loop 4 The loop of the feature, the loop 6 does not exist, and so on. Here, the density evolution and the actual system are described, for example, in "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit", SYChung, GDForney, TJ Richardson, R. Urbanke, IEEE Communications Leggers , 137720.doc -97- 200952349 VOL_5, NO.2, Feb 2001. For example, on the AWGN channel, if the discrete value of the noise increases from 0, the expected value of the error correction rate of the LDPC code is initially 0, but if the discrete value of the noise becomes a certain threshold or more, then No longer 0. If the density is evolved, the performance of the LDPC code can be determined by comparing the threshold value of the discrete value of the noise whose expected value is no longer zero (hereinafter also referred to as the performance threshold). Sexuality. Here, as the performance threshold, Eb/N〇 when the BER starts to decrease (small) is employed. If the LDPC code (hereinafter also referred to as the specification code) whose code length N is 64800 and the coding rate r is 2/3 as defined by the specification of DVB-S.2 is analyzed by density, the performance limit of the specification code is obtained. The value, expressed as V, is selected in the simulation, and the performance threshold is selected as the value of V + Δ after V plus a certain margin Δ, and the code length Ν is 64800, and the coding rate r is 2/3. (Check matrix), come as a good performance LDPC code. 66 to 68 show the initial of one check matrix in the LDPC code (the code length Ν is 64800 and the code rate r is 2/3 LDPC code) whose Eb/N 性能 is less than V+Δ as the performance threshold. Value table. Further, Fig. 67 is continued from Fig. 66, and Fig. 68 is continued from Fig. 67. In the check matrix 求出 obtained from the check matrix initial value table of Figs. 66 to 68, there are no loop 4 and loop 6. Fig. 69 is a view showing an analog result of the BER of the LDPC code (hereinafter also referred to as a proposal code) of the check matrix 求 obtained from the check matrix initial value table of Figs. 66 to 68. 137720.doc -98- 200952349 That is, Fig. 69 shows the BER of the Es/N〇 for the specification code (indicated by a circle in the figure) in the case where the modulation mode is 256QAM, and the Es/N for the proposal code. BER BER (represented by a rectangle in the figure). Further, in Fig. 69, the replacement processing of the current mode of Fig. 60C is employed as the replacement processing. As can be seen from Fig. 69, the proposed code is better than the specification code, that is, the floor is particularly improved in error. Further, the specific condition that the appropriate inspection matrix should conform to can be appropriately determined from the viewpoints of improvement in decoding performance of the LDpc code or easiness (simplification) of decoding processing of the LDPC code. Next, Fig. 70 is a block diagram showing a configuration example of the receiving device 12 of Fig. 7. In Fig. 70, the receiving device 12 receives the modulated signal from the transmitting device u (Fig. 7), and is composed of a quadrature demodulating unit 51, a 罅 mapping unit 52, a deinterleaver 53 and an LDPC decoding unit 56. . The orthogonal demodulation unit 51 receives the modulated signal from the transmitting device π and performs 正交 quadrature demodulation, and supplies the signal point (the value in the I and Q-axis directions) obtained as a result to the demapping unit 52. The demapping unit 52 performs demapping of the symbol point from the orthogonal demodulation unit 51 as a symbol of the LDPC code, and supplies it to the deinterleaver 53. The deinterleaver 53 is composed of a multiplexer (MUX) 54 and a vertical twist deinterleaver 55, and performs deinterlacing of the symbol bits from the symbols of the demapping unit 52. That is, the multiplexer 54 takes the symbol bits 137720.doc -99 - 200952349 from the symbols of the demapping section 52 as objects, and performs the replacement processing by the multiplexer 25 corresponding to FIG. The replacement process (reverse processing of the replacement process), that is, the inverse replacement process of returning the position of the code bit (symbol bit) of the LDPC code replaced by the replacement process to the original position, and obtaining the result The LDPC code is supplied to the wale twist deinterleaver 55. The vertical twist deinterleaver 55 takes the LDPC code from the multiplexer 54 as a target, and performs the longitudinal twist deinterlacing of the vertical twist interlace as the rearrangement processing performed by the vertical twist interleaver 24 of FIG. (Reverse processing of the whirling and twisting interleaving), that is, as a code bit which changes the aligned LDPC code by the wobble interleave as the rearranging process, and returns to the anti-rearrangement process of the original arrangement, for example, the wales Reverse the deinterlacing. Specifically, the vertical twist deinterleaver 55 writes the code bits of the LDPC code and further reads them out by the memory for deinterleaving which is configured similarly to the memory 31 shown in FIG. 22 and the like. For longitudinal twist de-interlacing. Wherein, in the vertical twist deinterleaver 55, the writing of the code bit uses the read address from the reading of the code bit of the memory 31 as a write address, and is used for deinterleaving. The direction of the memory is in the direction of the column. Further, the reading of the code bit is performed by using the write address at the time of writing the code bit of the memory 31 as the read address, and in the wale direction of the memory for deinterleaving. The LDPC code obtained as a result of the wandering deinterleaving is supplied from the vertical twist deinterleaver 55 to the LDPC decoding unit 56. Here, in the LDPC code supplied from the demapping section 52 to the deinterleaver 53, the co-located interleaving, the wobble interleaving, and the replacement processing are applied in this order, but 137720.doc • 100- 200952349 is in the deinterleaver 53, Only the inverse replacement processing corresponding to the replacement processing and the vertical twist deinterlacing corresponding to the longitudinal twist interleaving are performed, so that the co-located deinterlacing corresponding to the co-located interleaving (the inverse processing of the co-located interleaving) is not performed, that is, The code bits of the LDPC code which are interleaved and changed and arranged are returned to the co-interleave of the original arrangement. Therefore, from the deinterleaver 53 (the vertical twist deinterleaver 55), the LDPC decoding unit 56 is supplied with an LDPC code which has undergone the inverse replacement processing and the vertical twist deinterleave, and which does not perform the co-located deinterleaving. The LDPC decoding unit 56 performs the LDPC code from the deinterleaver 利用 by using at least the conversion check matrix obtained by the LDPC encoding unit 21 for LDpC encoding in FIG. The LDPC is decoded, and the data obtained as a result is output as a decoding result of the target data. Figure 71 is a flow chart showing the receiving process performed by the receiving device 12 of Figure 70.正交 The orthogonal demodulation unit 51 is in step Sill, and receives the modulated signal from the transmitting device u. The processing proceeds to step S112, and orthogonal modulation of the modulated signal is performed. The signal point obtained by the demodulation unit 51 based on the result of the quadrature demodulation is supplied to the demapping unit 52, and the processing proceeds from step S112 to step S113. In step S113, the demapping section 52 performs demapping of the point 2 from the orthogonal demodulation section into a symbol, and supplies it to the deinterleaver 53, and the processing proceeds to step S114.

In step S114, the disassociation is performed by the crying "total", "A", and the deciphering of the symbol from the demapping section 52, and the processing proceeds to step S115. 137720.doc In the step S14, the multiplexer 54 performs the inverse replacement processing on the symbol bit from the symbol of the demapping unit 52, and obtains the LDPC obtained as a result. The code bit is supplied to the vertical twist deinterleaver 55. The vertical twist deinterleaver 55 takes the LDPC code from the multiplexer 54 as a target, performs the longitudinal twist deinterlacing, and obtains the LDPC obtained as a result. The code is supplied to the LDPC decoding unit 56. In step S115, the LDPC decoding unit 56 performs at least the conversion check matrix obtained by the row replacement of the parity interleave using the check matrix 用于 for LDPC encoding by the LDPC encoding unit 21 of Fig. 8 . The LDPC decoding of the LDPC code from the vertical twist deinterleaver 55 is performed, and the data obtained as a result is output as the decoding result of the target data, and the processing ends. Further, the reception processing of Fig. 71 is repeated. Figure 70 also In the same manner as in Fig. 8, for convenience of explanation, the multiplexer 54 for performing the reverse replacement processing and the vertical twist deinterleaver 55 for performing the longitudinal twist deinterlacing are separately formed, but the multiplexer 54 and the longitudinal twist deinterleaver Further, in the case where the transmitting device 11 of Fig. 8 does not perform the whirling and twisting, the receiving device 12 of Fig. 70 does not need to provide the whirling twist deinterleaver 55. Next, further explanation is given. The LDPC decoding unit 56 of Fig. 70 performs LDPC decoding by the LDPC decoding unit 56 of Fig. 70. As described above, the LDPC encoding unit 21 for LDPC encoding of Fig. 8 is used to perform at least 137720.doc - 102- 200952349 The LDpc decoding of the LDPC code from the vertical twist deinterlacing (4) is performed by the inverse twist interleaving (4), and the LDPC code is not deinterlaced. Here, an LDPC decoding has been proposed, which can suppress the circuit scale by using the conversion check matrix to perform LDPC decoding, and at the same time reduce the operating frequency to a fully achievable range (see For example, LDPC decoding regarding the utilization conversion check matrix proposed first is explained with reference to Fig. 72 to Fig. 75. Fig. 72 shows that the code length N is 90, and encoding is performed. An example of the check matrix LDP of the LDPC code of 2/3 is shown as follows. In Fig. 72 (the same as Fig. 73 and Fig. 74 described later), 0 is represented by a period (1). In the check matrix of Fig. 72, the parity matrix becomes Fig. 73 is a check matrix Η' obtained by performing the row replacement of the equation (11) and the row replacement of the equation (12) in the inspection matrix 图 of Fig. 72. ❹ column permutation · 6s+t+ column 1 - 5t + s + column 1 · · · (11) row permutation: 6x + y + line 61 - 5y + x + line 61 · . (12) where, (11) and (12), s, t, X, and y are integers in the range of OS s < 5, 〇 St < 6, 0 $ χ < 5, 0 $ t < If the column is replaced by the formula (11), the substitution is performed in the following cases: the first, seventh, third, fourth, and fifth columns divided by the sixth remainder are replaced by the first, second, third, fourth, and fifth columns, respectively. The 2nd, 8th, 14th, 20th, and 26th columns with 6 remainders are replaced by the sixth, seventh, eighth, ninth, and tenth columns, respectively. 137720.doc -103 - 200952349 Furthermore, if the row is replaced according to the equation (12), for the 61st row and later (the parity matrix), the substitution is performed by dividing the remainder by 6 to the 61st, 67th, 73rd, and 79th. 85 lines are replaced by the other ij, the sixth, 62, 63, 64, 65 lines, divided by the sixth remainder of 2, the 62nd, 68th, 74th, 80th, and 86th lines are replaced by the 66th, 67th, 68th, 69th, respectively. 70 lines. Thus, the matrix obtained by performing column and row permutation on the inspection matrix 图 of Fig. 72 is the inspection matrix Η' of Fig. 73. Here, even if the column replacement of the inspection matrix is performed, the arrangement of the code bits of the LDPC code is not affected. Moreover, the row permutation of the equation (12) is equivalent to the information length of the co-interleaving in which the above-mentioned Κ+qx+y+l code bits are interleaved to the position of the Κ+Py+x+l code bits. K is 60, and the number of rows P of the unit of the tour structure is 5 and the parity of the parity of the same length M (here, 30) is q (=M/P) is 6. For the check matrix of FIG. 73 (hereinafter referred to as a replacement check matrix as appropriate) H', the LDPC code multiplied by the check matrix of FIG. 72 (hereinafter referred to as the original check matrix) H is the same as the equation (12). After the replacement matrix, a 0 vector is output. That is, if the column vector obtained by the row permutation of the equation (12) is expressed as c' in the column vector c of the LDPC code (1 codeword) which is the original inspection matrix, the nature of the matrix is checked. Look, HcT becomes a 0 vector, so of course it becomes a 0 vector. According to the above, the conversion check matrix H' of Fig. 73 is based on the LDPC code c of the original check matrix ,, and the check matrix of the LDPC code c' obtained by the row replacement of the equation (12) is performed. Therefore, in the original LDPC code c of the check matrix, the 137720.doc -104-200952349 row permutation of the equation (12) is performed, and the LDPC code C' of the row replacement is decoded by the conversion check matrix of FIG. 73 (LDPC) The decoding is performed by applying the inverse permutation of the row of the equation (12) to the decoding result, whereby the decoding result of the same manner as the case where the LDPC code of the original inspection matrix 利用 is decoded by the inspection matrix 可获得 can be obtained. Fig. 74 is a diagram showing the conversion check matrix 图· of Fig. 73 with a space of 5 χ 5 in intervals. In FIG. 74, the conversion check matrix Η is represented by a combination of the following matrices: 单位 5x5 unit matrix; one or more of the unit matrix 〇 is a matrix of 〇 (hereinafter suitably referred to as a quasi-unit matrix); A matrix of cyclic shifts of a unit matrix or a quasi-unit matrix (hereinafter referred to as a shift matrix as appropriate); a sum of 2 or more of a unit matrix, a quasi-unit matrix, or a shift matrix (hereinafter suitably referred to as sum Matrix); and 5 〇 matrix. The conversion check matrix brother of Fig. 74 can be composed of a unit matrix of 5 χ 5, a quasi-unit matrix, a shift matrix, and a matrix and a unitary matrix. Therefore, the 5x5 matrix constituting the conversion check matrix Η1 is hereinafter referred to as a constituent matrix as appropriate.解码 The decoding of the LDPC code represented by the check matrix represented by the constituent matrix of ΡΧΡ can be performed by using an architecture that simultaneously performs check node operations and variable node operations. Fig. 75 is a block diagram showing a configuration example of a decoding apparatus that performs such decoding. That is, Fig. 75 shows the structure of a decoding apparatus for decoding the LDPC code by using the check matrix H of Fig. 72 and at least the conversion check matrix H'' of Fig. 74 obtained by the row replacement of the equation (12). example. The decoding device of FIG. 75 includes: 137720.doc-105-200952349 branch data storage memory 300 composed of 6 bays 17〇3〇〇1 to 3〇〇6, and selecting 1?117〇30〇1 to 3〇〇6 selector 301, check node calculation unit 3〇2, 2 cyclic shift circuits 3〇3 and 308, and 18? The branch data storage memory 304 composed of 抒〇3〇41 to 3〇418, the selector 305 for selecting FIF03041 to 3 0418, the received data storage unit 306 storing the received information, the variable node calculation unit 307, and decoding The word calculation unit 309, the received data rearrangement unit 310, and the decoded data rearrangement unit 311. First, a description will be given of a method of storing data for the memory 300 and 304 for branching data storage. The branch data storage memory 300 is composed of six FIF0300 to 3006, which are the number of columns 30 of the conversion check matrix H' of the figure, which are divided by the number of columns 5 of the matrix. FIF〇3〇〇y (y=12,6) is composed of a memory area of a plurality of segments, and the memory regions of each segment can simultaneously read or write 5 columns corresponding to the number of columns and rows of the constituent matrix. Branched message. Moreover, the number of segments of the memory area of the FIFO 300y is the maximum number of the number of the column of the conversion check matrix of Fig. 74 (Hamming weight), that is, 9. In FIF0300!, corresponding to the position of the transition check matrix 11 of Fig. 74, the position between the second column and the fifth column (the message from the variable node is stored in the form of horizontally padding each column (to ignore In other words, if the i-th row of the j-th column is represented as (j, i), then in the memory segment of the FIFO 300i, the memory corresponding to the conversion check matrix 储存 is stored, from (1, 1) to (5, 5) The position of the position of the unit matrix of 5x5. In the second segment memory area, there is a shift matrix corresponding to the conversion check matrix H from (1, 21) to (5, 25) ( The data of the position where the unit matrix of 5χ5 is rotated to the right by only three shifting matrices). The memory area from the third to the eighth segment is also the same as the conversion check matrix H, which is assigned to 137720.doc 200952349. And the data is stored. Then, the memory area of the 9th segment is stored in the unit matrix corresponding to the conversion check matrix H' from (1, 86) to (5, 90) (the unit matrix of 5 < 5 After the first column is replaced by 〇, and the left is only cyclically shifted to the position of 1 of the shift matrix). 〇2, storing the data corresponding to the position of the sixth column to the first column of the conversion check matrix of the figure, that is, the jth knowing '°Hidden area' of the fif〇3 is stored corresponding to the composition Converting the check matrix H' from the sum matrix of (6,1) to ❹(1〇'5) (only shifting the unit matrix of 5x5 to the right by only shifting the first shift matrix of i, and only cyclically shifting to the right The position of the position of the first shift matrix of the sum of the two second shift matrices). Further, the second-stage memory area 'stores the corresponding change check matrix H, from (^) to 0〇, 5) The data of the position of the 1st shift matrix of the sum matrix. Also, I7 relates to a constituent matrix having a weight of 2 or more, a unit matrix of pxp having a weight of 1, a quasi-unit matrix of one or more of the elements 1 being 0 or a cyclic shift of the unit matrix or the quasi-unit matrix. The form of the sum of the complex moments in the Q-array of the shifting moment represents the position of the unit matrix, the quasi-unit matrix or the position of the shift matrix 1 (corresponding to the unit matrix, the quasi-quantity) The information of the branch of the unit matrix or the shift matrix is stored in the same FIF of the same address 0 〇 3〇〇1 to 3〇〇6). The following paragraphs are stored in the memory areas from the third to the ninth segments, and are also associated with the conversion check matrix H'. The FIFOs 30O3 to 3〇〇6 are also associated with the conversion check matrix 而 to store data. The branch data storage memory 304 is divided by the number of rows constituting the matrix, that is, 5, 137720.doc -107 - 200952349, by the conversion check matrix, and 18 of the rows 90. It consists of Tingyi 3041 to 30418. The FIFO 304x (x=l, 2, ..., 18) is composed of a plurality of segments of the memory area, and the number of rows and rows corresponding to the conversion check matrix H' can be simultaneously read or written in the memory area of each segment. The number of 5 branches of the message. The data corresponding to the position of the 1st line to the 5th line of the conversion check matrix H1 of FIG. 74 (the message Uj from the check node) is stored in the form of vertical packing of each line (to ignore) Form). That is, in the first segment memory area of the FIFO 304, data corresponding to the position of the unit matrix of 5x5 of the conversion check matrix H' from (1, 1) to (5, 5) is stored. In the second segment memory area, there is stored a sum matrix corresponding to the transition check matrix H, from (6, ^ to (1〇, 5) (the fifth shift of the unit matrix of 5x5 to the right is only shifted by one) The position of the position of the first shift matrix of the bit matrix and the sum of the second shift matrix which is only cyclically shifted to the right, and the third segment s The data of the position of the second shift matrix of the sum matrix of (6, 丨) to (10, 5) is formed by the conversion check matrix H. That is, the weight of the constituent matrix having the weight of 2 or more is weighted as a unit matrix of 1 ρ χ ρ, a quasi unit matrix in which one or more of the elements are 0, or a sum of a plurality of shift matrices in which the unit matrix or the quasi-unit matrix is cyclically shifted When constructing a matrix, the data corresponding to the position of the unit matrix, the quasi-unit matrix, or the shift matrix of 1 (corresponding to the branch belonging to the unit matrix, the quasi-unit matrix, or the shift matrix) is stored in The same address (the same FIFO in FIF〇304i to 3〇418) 〇 The 4th and 5th memory areas are also stored with the data of the conversion check obstacle barrier 137720.doc • 108 - 200952349 Η'. The number of segments of the memory area of the j^Fc^ot is the conversion check matrix H, from the The maximum number of 1s in the direction of the 1st row to the 5th row (Hamming weight) is 5. The FIFOs 3042 and 3043 are also assigned to the conversion check matrix H, and the data is stored, and the length (number of segments) is 5 respectively. The FIFOs 3044 to 30412 are also stored in correspondence with the conversion check matrix H', and the lengths are respectively 3. The FIFOs 304 to 3:304!8 are also assigned to the conversion check matrix H, and the data is stored, respectively, and the length is 2 Next, the operation of the decoding device of Fig. 75 will be described. The branch data storage memory 300 is composed of 6 intimidation 03001 to 3006, which is supplied by the cyclic shift circuit 3 〇 8 of the segment. The message D3 11 belongs to the column of the conversion check matrix H' (Matrix data) D3 12, selects the FIFO storing the data from FIF03〇〇1 to 30〇6, and stores the five messages D311 sequentially in the selection. FIFO. Moreover, branching data storage When the data is read, the five messages D3 00! are sequentially read from the FIF 030 , 1 and supplied to the selector 3 次 of the second stage. The memory 300 for branch data storage is from the FIF 〇 After the reading of the message of 3〇〇i is finished, the message is sequentially read from FIF030〇2 to 30〇6, and supplied to the selector 301. The selector 301 selects from the selection signal D301, and selects from ^117030 (^ to The 5 messages of the FIFO of the data are now read out in the 〇〇6, and are supplied to the check node calculation unit 3 〇2 as the message D3 02. The check node calculation unit 3 02 is composed of five check node calculators 3〇2 i to 3 025, and uses the message 〇2 supplied through the selector 3〇1 (D302! to 137720.doc • 109- 200952349) D3025) (Message Vi of equation (7)), perform check node operation according to equation (7), and obtain 5 messages 1 to D3035 obtained by the result of the check node operation (message Uj of equation (7) ) is supplied to the cyclic shift circuit go. The cyclic shift circuit 303 cyclically shifts the information of several original unit matrices by converting the five motion centers D303 to D3035 obtained by the check node calculating unit 3〇2, and correspondingly branching the conversion check matrix H. (Matrix data) D3 〇5 is cyclically shifted, and the result is supplied to the branch data storage memory 304 as the message D3〇4. The branch data storage memory 3〇4 is composed of 18 1st 〇3041 to 30418, and 5 messages D304 supplied from the previous stage cyclic shift circuit 3〇3 belong to the conversion check matrix H, The information d3〇5, select FIF〇 for storing data from household scare 03041 to 30418, and store 5 messages D3〇4 and sequentially store them in the selected FIF〇. Further, the branch data storage memory unit 304 sequentially reads out five messages D306! from the FIF 〇 3 〇 4i when reading the data, and supplies it to the selector 3 〇 5 of the second stage. The branch data storage memory 304 is sequentially read out from the FIFOs 3042 to 304^ after the reading of the data from the FIF〇3〇4i is completed, and is supplied to the selector 305. The selector 305 follows the selection signal. D307, choose from? The five messages of the FIF number of the data to be read from the Ting〇3〇41 to 3〇4u are supplied to the variable node calculation unit 3〇7 and the decoded word calculation unit 3〇9 as the message D308. On the other hand, the received data rearrangement unit 3 rearranges the LDPC code D313 received through the communication channel by performing the line replacement of the equation (12), and supplies it to the received data as the received data D3 14 . Memory 3〇6. Receiving funds 137720.doc -110· 200952349 The material used in the self-receiving data rearrangement unit 3 receives the data D3 14, and counts and memorizes the reception]^LR (logarithm ratio ratio), Five of the receivers are supplied to the variable node calculation unit 3 〇7 and the decoded word calculation unit 3〇9 as the reception value D 3 0 9 . The variable node calculation unit 307 is composed of five variable node calculators 3071 to 3〇75 'using the message D3〇8 (d308i to D3085) supplied by the transmission selector 305 (the message Uj of the equation (1)) and From the received value D309 (the received value U()i of the equation (1)) supplied from the received data memory 3〇6, the variable node operation is performed according to the equation 'The message obtained by the result of the calculation 〇31 〇 (〇31〇1 to D31〇5) (the message Vi of the equation (1)) is supplied to the cyclic shift circuit 3〇8. The cyclic shift circuit 308 is configured to convert the information D3 1 0! to D3 1 〇5 calculated by the variable node calculation unit 307 into the conversion check matrix H by corresponding branches, and cyclically shift the information of several original unit matrices into The basis is cyclically shifted, and the result is supplied to the branch data storage memory 3 as the message D3 11. By patrolling the above operation once, the LDPC code can be decoded once. The decoding apparatus of Fig. 75 decodes the ldpc code only a specific number of times, and obtains the final decoding result in the decoding word calculation unit 309 and the decoded data rearrangement unit 311, and outputs the result. That is, the 'decode word calculation unit 3〇9 is composed of five decoded word calculators 3〇9ι to 3〇9s', and the five messages d308 (D308i to D3 08s) output by the selector 305 (Equation (5) The message Uj) and the five received values D309 (the received value U()i of the equation (5)) supplied from the received data memory 3〇6 are calculated as the final segment of the plurality of decodings according to the equation (5). The decoding result (decode word) is supplied to the decoded data rearrangement unit 3 11 by the decoded data D3 15 obtained as a result. 137720.doc -111 - 200952349 The decoding data rearrangement unit 311 performs the inverse permutation of the line replacement of the equation (12) by using the decoded data leg 5 supplied from the decoded word calculation unit 309 as a target, and rearranges the order. And output as the final decoding result Mb. As described above, 'one or both of the column permutation and row permutation are applied to the inspection matrix (original inspection matrix) to be converted into a unit matrix of ρχρ, and one or more of the elements of the element are one or more of the quasi unit matrices. The combination of the matrix of the shift matrix, the unit matrix, the quasi-unit matrix or the shift matrix of the unit matrix or the quasi-unit matrix, and the matrix of the zero matrix, which can form a matrix Combine to check the 10 matrix (conversion check matrix), can the decoding of the LDPC code be used simultaneously? The architecture of the check node operation and the variable node operation (archhect is called to perform P node operations at the same time, and the operating frequency can be lowered to an achievable range, and a lot of repeated decoding is performed. The receiving device 122LDpc decoding unit constituting FIG. 70 is constructed. The 56 system is the same as the decoding device of Fig. 75, and performs LDPC decoding by performing p check node operations and variable node operations simultaneously. That is, now, for the sake of simplicity, the transmitting device constituting Fig. 8 will be constructed. The check matrix of the LDPC code rotated by the LDPC encoding unit 21 is set such that the parity matrix of the stepped structure is a check matrix H of the ladder structure, for example, the parity of the parity device 23 of the transmitting device 11 will be Κ+qx+ The y+l code bits are interleaved to the position of the K+Py+x+1 code bits. The parity interleave system sets the information length κ to 60, and the row number p of the tour structure unit is set to 5. The same bit length The divisor μ of q (=M/P) is set to 6. Since the co-located interleaving is equivalent to the row substitution of the equation (12), 137720.doc - 112· 200952349 is not required to be performed by the LDPC decoding unit 56 ( 12) The replacement of the line. Therefore, the receiving device 1 of Fig. 70 As described above, the LDPC decoding unit 56 supplies the LDPC code which is not subjected to the co-located deinterleaving, that is, the LDPC code in the state in which the line replacement of the equation (12) has been performed, in the LDPC. The decoding unit 56 performs the same processing as the decoding apparatus of Fig. 75 except that the line replacement of the equation (12) is not performed. That is, Fig. 76 shows a configuration example of the LDPC decoding unit 56 of Fig. 70. The LDPC decoding unit 56 is configured in the same manner as the decoding device of FIG. 75 except that the received data weighting unit 3 1 0 of FIG. 75 is not provided, and the row replacement is performed without the equation (12). Since the decoding apparatus performs the same processing, the description thereof is omitted. As described above, since the LDPC decoding unit 56 is not provided with the received data rearrangement unit 310, the decoding apparatus can be reduced in size compared with the decoding apparatus of Fig. 75. 76, in order to simplify the description, the code length N of the LDPC code is set to 90, the information length K is set to 60, the number of rows of the unit of the tour structure (the number of columns and the number of rows of the matrix) P is set to 5, and the same position. The number q (=M/P) of the long Μ is set to 6, but the code length Ν, information length Κ, tour The number of rows P and the number q (=M/P) of the unit of the structure are not limited to the above values. That is, in the transmitting device 11 of Fig. 8, the LDPC encoding unit 21 outputs, for example, the code length N is set as 64800 or 16200, the information length K is set as N-Pq (=NM), the number of rows P of the unit of the tour structure is set to 360 and the approximate number q is set as the LDPC code of Μ/P, but the LDPC decoding unit 56 in Fig. 76 will This type of LDPC code can be applied as an object while performing P check node operations and variable node operations, thereby performing LDPC decoding. 137720.doc -113 - 200952349 Next, the series of processes described above can be performed by hardware. When the software is used for serial processing, the program of =: is installed on a general-purpose computer. Therefore, Fig. 77 shows an example of a configuration in which one of the computers of the program for executing the above-described series of processes is installed. The program can be recorded in advance on a hard disk 705 or ROM 703 built into the computer as a recording medium. Alternatively, the program can be temporarily or permanently stored (recorded) on a floppy disk, CD-ROM (C〇mpact Disc Read 〇nly Mem〇ry: micro-disc read-only memory), MO (Magnet〇〇ptical: magneto-optical) Disc,

Versatile Disc: Digital versatile disc), magnetic disc, semiconductor memory and other portable recording media 711. This type of removable recording (4) 7 ι can be provided as a so-called set of software. ~ In addition, the program can be wirelessly transmitted to the computer via the LANaod Am Network: regional network from the download page, via the artificial satellite of digital satellite playback, in addition to the portable recording medium 7 ιι as described above. The network of the Internet is transmitted to the computer by wire, and the computer transmits the program thus transmitted to the built-in hard disk 705 by the communication unit 708. The CPU is equipped with a CPU (Central Pr〇cessing Unh) 702. In the CPU 702, an input/output interface 71 is connected via the bus bar 7〇1, and the input unit 7〇7 constituted by a keyboard, a mouse, a microphone, or the like is operated by the user via the input/output interface 71〇. To input the instruction, the CPU 702 executes it according to it and stores it at 137720.doc 200952349

Memory: Read only memory) 703 program. Alternatively, the CPU 702 reads a program stored in the hard disk 705, a program transmitted from the satellite or the network, received by the communication unit 708, and mounted on the hard disk 705, or read from the portable recording medium 711 loaded on the disk drive 709. The program that is installed and installed on the hard disk 705 is loaded into a RAM (Random Access Memory) 7〇4 and executed. Thereby, the CPU 702 performs the processing according to the above-described flowchart or the processing performed by the above-described block diagram. Then, the CPU 702 outputs the processing result to the output unit 706 composed of an LCD (Liquid Crystal Display) or a speaker, for example, via the input/output interface 710, or transmits it from the communication unit 708, and further makes it possible. It is recorded on the hard disk 705 and the like. Here, the processing steps of the program for causing the computer to perform various processes are described in the present specification, and it is not necessary to process them in time series according to the sequence described in the flowchart, and also includes processing performed in parallel or individually (for example, juxtaposition Handling or handling by object). Moreover, the program can be processed by one computer or distributed by a plurality of computers. Further, the program can also be transferred to a remote computer for execution. Next, the processing of LDPC encoding by the LDPC encoding section 21 of the transmitting apparatus 11 will be further explained. For example, in the specification of DVB-S.2, there are two LDPC codes of code length N of 64800 bits and 16200 bits. Then, regarding the LDPC code whose code length ^^ is 64800 bits, there are 11 coding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4 /5, 5/6, 8/9 137720.doc -115- 200952349 and 9/10, for LDPC codes with a code length N of 16,200 bits, 10 encoding rates of 1/4, 1/3, 2/ are specified. 5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6 and 8/9. The LDPC encoding unit 21 encodes the LDPC code of each encoding rate of 64800 bits or 16200 bits according to the check matrix 准备 prepared for each code length N and per coding rate (error correction) Ma). In other words, the LDPC encoding unit 21 stores the check matrix initial value table to be described later, based on the code length and the coding rate. Here, in the specification of DVB-S.2, as described above, there are two kinds of code lengths of 64800 bits and 16200 bits, and 11 codes are respectively specified for the LDPC code with a code length of 64800 bits. The rate is about 10 encoding rates for an LDPC code having a code length N of 16,200 bits. Therefore, when the transmitting apparatus 11 processes the apparatus according to the specifications of DVB-S.2, the LDPC encoding unit 21 stores an inspection matrix corresponding to 11 encoding rates for the LDPC codes having a code length N of 64,800 bits. The initial value table and the LDPC code having a code length N of 16,200 bits respectively correspond to a check matrix initial value table of 10 coding rates. The LDPC encoding unit 21 sets the code length N and the encoding rate r of the LDPC code in accordance with, for example, the operation of the operator, and appropriately sets the code length N and the encoding rate r set by the LDPC encoding unit 2, respectively. Also known as setting code length N and setting the encoding rate r. The LDPC encoding unit 21 sets the information length K corresponding to the set code length N and the set coding rate r according to the check matrix initial value table corresponding to the set code length N and the set coding rate r (=Nr=code length N-co-location The information matrix of length M) HAi 1 137720.doc -116- 200952349 is arranged in the 仃 direction to generate a check matrix 以 in the cycle of each row (the number of rows ρ of the circuit structure). Then, the LDPC encoding unit 21 is a target data to be transmitted from the image resource or the sound data supplied or transmitted, and the spine information length κ is 70. In the case of the LDpc encoding unit η According to the check matrix Η, a codeword (LDPC code) for generating a long code of the same bit for the information bit is calculated. That is, the LDPC encoding unit 21 sequentially calculates the parity bit of the codeword c according to the following formula. .

HcT = 于此 where 'C' denotes a column vector as a codeword (LDPC code), and cT denotes a transposition of the column vector C. As a column vector of an LDPC code (1 codeword), in the case where the column vector A represents a portion of the information bit 7L, and the column vector T represents a portion of the parity bit, the column vector c can be used as the information bit. The column vector a and the column vector T as the parity bits are represented by the formula C=[A|T;], and the 'check matrix Η can correspond to the information bit in the code bit of the LDPC code. The information matrix of part and the parity matrix Ητ ' corresponding to the parity bit are expressed as the formula H=[HA|HT] (the element of the information matrix HA is set to the left element. The element of the parity matrix Ητ is set as the matrix of the right element) Further, for example, in the specification of DVB-S.2, the parity matrix HT of the check matrix H = [HA|HT] becomes a ladder structure. The check matrix Η and the column vector c=[A|T] as the LDPC code must be The conformity HcT=0' can be used as the column vector 构成 constituting the column vector c=[A|T] of the formula hct=0, which can be used to check the matrix H=[HA|HT] When the co-located matrix Ητ is a ladder structure, the elements of the first column of the row vector HcT of the formula HcT=0 are sequentially arranged for each column element. The LDPC encoding unit 21 obtains the parity bit T for the information bit A, and then the code word c=[A| represented by the information bit A and the parity bit T. T] is output as the result of the LDPC encoding of the information bit A. As described above, the LDPC encoding unit 21 stores the code rate N and the set code rate of the check matrix initial value table 'set code length N' corresponding to each code rate r. The LDPC encoding of r is performed using the check matrix 生成 generated from the set code length N and the check matrix initial value table corresponding to the set coding rate r. The check matrix initial value table checks the matrix Η corresponding to the corresponding LDPC code ( The position of the element of the information matrix HA of 1 by the code length N of the LDPC code defined by the matrix 及 and the information length K of the coding rate r is represented by every 3 60 lines (the number of rows of the circuit of the tour structure P) The table is prepared in advance according to the code length N and the check matrix of each coding rate r. Fig. 78 to Fig. 123 show the check matrix initial value table specified by the specification of DVB-S.2 for generating various checks. Matrix check matrix initial value table. That is, Figure 78 shows the specifications of DVB-S.2. The check matrix initial value table of the check matrix 规定 for the code length Ν of 16200 bits is 2/3. Fig. 79 to Fig. 81 show the code length for the specification of DVB-S.2. The check matrix initial value table of the check matrix 64 of 64800 bits with the coding rate r of 2/3. 137720.doc -118· 200952349 In addition, Fig. 80 is continued from Fig. 79, and Fig. 81 is continued from Fig. 80. Fig. 82 is a table showing the check matrix initial value of the check matrix 编码 for the code rate n of 16200 bits with a code length N of 3/4 as defined by the specification of DVB-S.2. Fig. 83 to Fig. 86 are diagrams showing the check matrix initial value table of the check matrix 编码 for the coding rate r of 64800 bits with a code length 64 of 3/4 as defined by the specification of DVB-S.2. In addition, Fig. 84 is continued from Fig. 83, and Fig. 85 is continued from Fig. 84. Moreover, Fig. 86 is continued from Fig. 85. Fig. 87 is a table showing the check matrix initial value of the check matrix 编码 for the code rate r of 16200 bits with a code length N of 4/5 as defined by the specification of DVB-S.2. Fig. 88 to Fig. 91 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code length 64 of 64,800 bits and the code rate r of 4/5 as defined by the specification of DVB-S. Further, Fig. 89 is continued from Fig. 88, and Fig. 90 is continued from Fig. 89. Further, Fig. 91 is continued from Fig. 90. Fig. 92 is a table showing the check matrix initial value of the check matrix 编码 for the coding rate r of the code length r of 16200 bits as defined by the specification of DVB-S.2. Fig. 93 to Fig. 96 are diagrams showing the check matrix initial value table of the check matrix 编码 for the coding rate r of the code length 64 of 64,800 bits, which is defined by the specification of DVB-S.2, which is 5/6. Further, Fig. 94 is continued from Fig. 93, and Fig. 95 is continued from Fig. 94. Moreover, Fig. 96 is continued from Fig. 95. Figure 97 is a table showing the check matrix initial value of the check matrix for the code rate 16 of 16200 137720.doc -119- 200952349 bits with a code length r of 8/9 as defined by the specification of DVB-S.2. Fig. 98 to Fig. 1〇1 show the check matrix initial value table of the check matrix η for the coding rate 1* of 8/9 with a code length 64 of 64,800 bits as defined by the specification of DVB_S 2 . Further, Fig. 99 is continued from Fig. 98, and Fig. 100 is continued from Fig. 99. Further, Fig. 101 is continued from the diagram of Fig. 1〇0. Fig. 102 to Fig. 105 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code length 64 of 64,800 bits with a code length r of 9/10 as defined by the specification of DVB_S.2. Further, Fig. 1〇3 is continued from Fig. 1〇2, and Fig. 104 is continued from Fig. 1〇3. Moreover, Fig. 105 is continued from the diagram of Fig. 1〇4. Fig. 106 and Fig. 107 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code length 64 64800 bits, which is defined by the specification of DVB-S.2, which is 1/4. In addition, FIG. 107 is a diagram continued from FIG. Fig. 108 and Fig. 109 show the check matrix initial value table of the inspection matrix 码 for the code length Ν 64800 bits defined by the specification of DVB-S.2. Moreover, Fig. 109 is continued from the diagram of Fig. 1-8. Fig. 110 and Fig. 111 are diagrams showing the check matrix initial value table of the check matrix 编码 for which the code length 〇 is 648 〇 0 bits and the code rate r is 2/5 as defined in the specification of DVB-S.2. In addition, FIG. 111 is continued from the diagram of FIG. Figure 112 to Figure 114 show the check matrix initial value table of the inspection matrix η for the code length 137720.doc • 120- 200952349 N for the 64800 bits with a code rate r of 1/2 as specified in the specification of DVB-S.2. . In addition, FIG. 113 is continued from the diagram of FIG. 112, and FIG. U4 is continued from the diagram of FIG. Fig. 115 to Fig. 117 are diagrams showing the check matrix initial value table of the check matrix 对于 for the coding rate r of the code length N of 64,800 bits as defined by the specification of DVB_S.2. In addition, FIG. 116 is a diagram continued from FIG. 115, and FIG. 117 is a diagram connected to FIG. 116 Ο π. Figure 118 shows the code length specified by the specifications of DVB-S.2! ^ is the coding rate of 16200 bits]: is the check matrix initial value table of the check matrix of 丨/4. Fig. 119 is a table showing the initial value of the check matrix of the check matrix η for the code length \ is a coding rate of 16200 bits as defined in the specification of DVB-S.2. ❹ Figure I20 is a table showing the initial value of the check matrix of the check matrix η of 2/5 for the code rate N of 1 6200 bits as defined by the specification of DVB-S.2. Fig. 121 is a table showing the initial value of the check matrix of the check matrix η of the code length 1 > 16200 bits as defined by the specification of DVB_S.2. Figure 122 is a diagram showing the check matrix initial value of the check matrix η of the code rate Γ of 16200 bits for the code length 佾 of DVB-S.2, which is defined by the specification of DVB-S.2, 0 137720.doc -121 - 200952349 Figure 123 The check matrix initial value table of the check matrix 编码 with a code length n of 3/5 and a code length N of 16,200 bits can be used instead of the check matrix initial value table of FIG. The LDPC encoding unit 21 of the transmitting device 11 obtains the inspection matrix 如 by using the inspection matrix initial value table ' as follows. That is, Fig. 124 shows a method of obtaining the inspection matrix η from the inspection matrix initial value table. Further, the check matrix initial value table of Fig. 124 indicates a check matrix of the check matrix η having a code length ν of 16,200 bits and a code rate r of 2/3 as specified in the specification of DVB-S.2 shown in Fig. 78. Initial value table. The check matrix initial value table is as described above, and corresponds to the position of the element of the information matrix ηα corresponding to the length of the code and the coding rate of the Ldpc code!* in every 360 lines (the line of the unit of the tour structure) The table of the number ρ) is listed in the column of the element of the l + 36 〇 x (il) row of the check matrix 检查 in the i-th column (the column number of the first column of the check matrix is set as the column) The number) is only the number of rows of weights that the row of the l + 36〇x(il) line has. Here, the parity matrix Ητ corresponding to the parity length μ of the 'check matrix 系 is formed into a staircase structure', which has been determined in advance. According to the check matrix initial value table ', the information moment drop corresponding to the information length κ in the check matrix 可 can be obtained. The number of columns k+Ι of the check matrix initial value table differs depending on the information length κ. Between the information length K and the number k+1 of the check matrix initial value table, the relationship of the following formula holds. K=(k+l)x360 137720.doc 122· 200952349 Here, 3 60 of the above formula is the number of rows p of the unit of the tour structure. In the check matrix initial value table of Fig. 124, 13 values are arranged from the third column to the third column, and three values are arranged from the fourth column to the k+th column (the 30th column in Fig. 124). Therefore, the row weight of the check matrix H obtained from the check matrix initial value table of Fig. 124 is from the 1st line to the 1+360X(3-1)-1 behavior 13 from the 1+36〇χ(3) -1) Go to the third act 3.第 The first column of the check matrix initial value table of Fig. 124 is 〇, 2〇84, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622, which is shown in the inspection matrix. In the i-th row, the elements of the column numbers 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622 are! (and other elements are 0). Moreover, the second column of the check matrix initial value table of FIG. 124 is 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, ❾ 971, 4358, 3108, which is shown in the inspection matrix η The 361th (=1+360><(2-1)) line, the elements of the column numbers 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, 3108 Is 1. As above, the check matrix initial value table will check the position of the element of the matrix of the matrix 以 1 per 360 lines. Check the line other than the l+36〇x(M) line of the matrix ,, that is, the line from the 2+36〇x(ii) line to the 36〇xi line will be determined by checking the matrix initial value table. The element of the 1st l+36〇x(il) line is cyclically shifted according to the same position length 137 137720.doc •123· 200952349 downward direction (downward direction of the line). I5, for example, the 2+360x(i-1) line only shifts the 1 +3 60X(i-1) line downward by only M/360 (=q), followed by the 3+36〇x (M). The line is rotated by 2xM/360 (=2xq) in the downward direction of the 1+36〇X(i_1) line (the second 2+36〇x(il) line is only cyclically shifted M/36. 〇 (=q)). Now, if the value of the Jth row (jth from the left) of the first column (the i-th from the top) of the check matrix initial value table is expressed as hij, and the check matrix Η If the number of the elements of the j is indicated as Η—, check the column number of the first to the first line of the line other than the 1+360><(丨-1) line of the matrix ^^^1 ~ can be obtained by the following formula.

Hw.j=mod{hjj+mod((w-l), P)xq5 Μ) Here, 'mod(x, y) means dividing y by the remainder after χ. Further, p is the number of rows of the above-described tour structure, for example, the specification of dvb_S2 is 360. Further, q is a value M/360 obtained by dividing the parity length μ by the number of rows P (= 360) of the unit of the tour structure. The LDPC encoding unit 21 specifies the column number of the element of the first +3 6 〇 x (i-1) row of the check matrix 藉 by checking the matrix initial value table. Further, the LDPC encoding unit 21 obtains the column number Hw of the element after the wth row of the row other than the l+36〇x(il) row of the inspection matrix 11, and generates the above obtained. The element of the column number is set as the inspection matrix H of 丨. Next, an alternative manner of the code bit of the LDPC code for the replacement process performed by the replacement unit 32 of the demultiplexer 25 of the transmitting device U, that is, the code bit LDP of the LDPC code and the symbol representing the symbol will be described. The change of the bit allocation mode (hereinafter also referred to as the bit allocation mode). 137720.doc -124· 200952349 The multiplexer 25' LDPC code is stored in the vertical direction and the (N/(mb))X(mb) bit is stored in the vertical direction. The direction is written by the person, and then read in the horizontal direction in units of mb bits. Further, in the solution 25, the code bit replaced by the replacement unit 32 in the direction of the row of the memory 31 is replaced by the code bit of (continuous) b symbols. The bit of the bit. ❹

That is, the replacing unit 32 calculates the i-th i-th bit from the highest-order bit of the code bit of the mb bit read from the course direction of the memory 31 as the code bit h, and will (continuously The highest order bit of the symbol bit of the b symbol is calculated as the first bit as the symbol bit yi, and the code bit b of the mb bit is replaced according to the specific bit allocation pattern. Figure 125 shows that the LDPC code is an LDPC code with a code length of 1^ of 648 bits and a coding rate of 5/6 or 9/10. The further modulation method is 4〇96QAM, and the multiple b is 1. In the case of the bit allocation mode, the DPC code length n is 64800 bits, the coding rate is 5/6 or 9/1 〇 LDPC code, and the further modulation mode is 4096QAM, and the multiple b is 1. In the case of the multiplexer 25, the memory bits written in the memory 3 of the (64800/(12χl)) x (12x丨) bit in the wale direction X are in the course. The direction is read out in units of 12xl (= mb) and supplied to the replacement unit 32. The replacement unit 32 is configured to read the code bits tl b from the 12x1 (= mb) bits of the memory 31 to bu ' As shown in Fig. 125, the 12xU-mb) bits of the symbols are assigned to the Chuanzhi method to replace the code bit ratio of the 12xl (= mb) bits to ^^. 125, the replacement unit 32 is code length n is 64800 bits 137720.doc -125- 200952349 [〇? (: code rate in the code is 5/6 of 1^〇?<: code, and coding rate For the 9/10 LDPC code, for any LDPC code, respectively: divide the code bit b For the symbol bit y8, the code bit b! is assigned to the symbol bit y 〇, the code bit b2 is assigned to the symbol bit y6, and the code bit b3 is assigned to the symbol bit y 1, The imaginary element b4 is assigned to the symbol y4, the code bit b5 is assigned to the symbol y5, the code bit b6 is assigned to the symbol y2, and the coder p7 is assigned to the symbol y3. , the code bit b8 is assigned to the symbol bit y7, the code bit b9 is assigned to the symbol bit y 1 〇, and the code bit bi 〇 is assigned to the symbol bit y!!, the code bit b i is assigned to the symbol bit y 9, and is replaced. Figure 126 shows that the LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 5/6 or 9/10, and further modulation mode. An example of a bit allocation pattern that can be used in the case of 4096QAM and a multiple b is 2. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6 or 9/10, and further modulation is In the case of 4096QAM and the multiple b is 2, in the demultiplexer 25, the coded bit system written in the memory 31 of the (64800/(12χ2)) χ (12x2) bit in the wale direction X direction is stored. Read in the horizontal direction, in units of 12x2 (= mb) bits, Supply to the replacement unit 32 ° 137720.doc -126- 200952349 The replacement unit 32 is to assign the code bits bG to b23 read from the 12x2 (= mb) bits of the memory 31 to the consecutive 2 as shown in FIG. (=b) The way of the symbol bits y〇 to y23 of the 12x2 (= mb) bits of the symbol is replaced by the code bits be to b23 of the 12<2 (== mb) bits. That is, according to FIG. 126, the replacing unit 32 is an LDPC code having an encoding rate of 5/6 in an LDPC code having a code length N of 64,800 bits, and an LDPC code having a coding rate of 9/10. An LDPC code is equally divided into |J: the code bit b〇 is assigned to the symbol bit y8, the code bit b2 is assigned to the symbol bit y〇, and the code bit b4 is assigned to the symbol bit y6 , the code bit b6 is assigned to the symbol bit y , the code bit b8 is assigned to the symbol bit y4 , the code bit b is assigned to the symbol bit y 5 , and the code bit b 丨 2 is allocated The symbol bit y 2 ' is assigned to the symbol bit bi 4 to the symbol bit y 3 , the code bit b b 6 is assigned to the symbol bit y 7, and the code bit b 丨 8 is assigned to the symbol Bit y], assign code bit b 2 G to symbol bit y 1 1, assign code bit b22 to symbol bit ys >, assign code bit b! to symbol bit y2 〇, the code bit b3 is assigned to the symbol bit y 12, the code bit b5 is assigned to the symbol bit y! 8, the code bit b7 is assigned to the symbol bit y 13, and the code bit b9 Assigned to the symbol bit y 16, 137720.doc -127- 200952349 assigns the code bit b 11 to the symbol y 17 'Assigning code bit bi3 to symbol bit yi4' Assigning code bit b! 5 to symbol bit y 15 ' Assigning code bit b 17 to symbol bit y 19 ' Put code bit b 1 9 is assigned to the symbol bit y 2 2, the code bit b 1 is assigned to the symbol bit y23, and the code bit b 3 is assigned to the symbol bit y2 丨 for replacement. Here, the bit allocation pattern of Fig. 126 directly uses the bit allocation pattern of Fig. 125 in the case where the multiple b is 1. That is, in FIG. 126, the allocation manner of the code bit element b〇, b2, . . . , bu to the symbol bit yi and the code bit element b, the allocation manner of the b3, , ^^, and the 7G bit TLyi are both The code bit % to ^" of FIG. 125 is assigned in the same manner as the bit element yi. Figure 127 shows the modulation mode is 1〇24QAM, and the LDpc code is the case where the code length n is 16,200 bits TL, the coding rate is 3/4, 5/6 or the code multiple 匕 is 2, and the LDPC code is the code length. The 6-bit bit and the coding rate are one/6 or 9/1 (^LDPC code, and the multiple b is 2). The L code 长 code length N is 162 GG bit rate. For the 3/4, 5/6 or 8/9 code advance-step modulation mode is 1024QAM, and the multiple b is 2, in the traversing direction ^^ 益25' in the vertical direction χ 横 横 side (1 6200/ ( 1 〇χ 2)) χ / jq χ - 1 * ? |, , 兀 6 忆 己 3 1 1 1 1 3 3 1 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入And supplied to the replacement unit 137720.doc •128- 200952349 Moreover, the LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 3/4, 5/6 or 9/10, and further modulation mode is 1024QAM. When the multiple b is 2, the code written in the memory 31 of the (64800/(1〇χ2)) χ (1〇χ2) bit in the direction of the X direction in the multiplexer 25 is written. The bit is read in the horizontal direction, read in units of l〇x2 (= mb), and supplied to the replacement unit 32 °. The code bits bG to b19 read from the l〇x2 (= mb) bits of the memory 31 are allocated to consecutive 2 (=b) symbols of the symbol 1 1 〇 x2 (= mb as shown in FIG. 127). The bitwise symbol y〇 to y19 of the bit is substituted for the code bits 13〇 to b19 of the 1 〇x2 (= mb) bit. That is, according to FIG. 127, the replacing unit 32 is an LDPC code having an encoding rate of 3/4 in an LDPC code having a code length N of 16,200 bits, an LDPC code having a coding rate of 5/6, and a coding rate of 8/. An LDPC code of 9 and an LDPC code having a coding rate of 3/4 in an LDPC code having a code length N of 64,800 bits, an LDPC code having a coding rate of 5/6, and an LDPC code having a coding rate of 9/10, Regarding the LDPC codes, respectively, the code bit b〇 is assigned to the symbol bit y8, the code bit b! is assigned to the symbol bit y 3, and the code bit b2 is assigned to the symbol bit. Y7, assigning the code bit b3 to the symbol bit y! 0, assigning the code bit b4 to the symbol bit y 19, and assigning the code bit b 5 to the symbol bit y 4, the code bit B6 is assigned to the symbol bit y9, the code bit b7 is assigned to the symbol bit y5, 137720.doc -129- 200952349, the code bit b8 is assigned to the symbol bit y 17, and the code bit b9 is assigned to Symbol bit y6, assigning code bit bi 〇 to symbol bit y 14, assigning code bit b!! to symbol bit y 11, assigning code bit b! 2 to symbol bit y 2, assign the code bit b! 3 to the symbol bit yi 8, and divide the code bit b ! 4 For the symbol bit y 1 6, assign the code bit b 15 to the symbol bit y 丨 5, assign the code bit b ! 6 to the symbol y 〇, and assign the code bit b! 7 to The symbol bit y 1, the code bit b! 8 is assigned to the symbol bit y 13, and the code bit b ! 9 is assigned to the symbol bit y 1 2 for replacement. Figure 128 is a diagram showing that the modulation mode is 4096QAM, and the LDPC code is an LDPC code having a code length N of 16,200 bits, a coding rate of 5/6 or 8/9, a multiple b is 2, and an LDPC code is a code length N. An example of a bit allocation pattern that can be used in the case of a 64800-bit LDPC code having a coding rate of 5/6 or 9/10 and a multiple b of 2. The LDPC code is an LDPC code with a code length N of 1 6200 bits and a coding rate of 5/6 or 8/9. In the case where the modulation mode is 4096QAM and the multiple b is 2, the multiplexer 25 is used in the multiplexer 25 The memory bit written by the memory 31 in the row direction X direction is (16200/(12χ2)) χ (12x2) bits is in the horizontal direction, and is read in units of 12><2(=mb) bits. And is supplied to the replacement unit 32 ° 137720.doc -130· 200952349 Moreover, the LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 5/6 or 9/10, and the modulation method is 4096QAM. When the multiple b is 2, in the demultiplexer 25, the memory 31 written in the memory 31 of the (64800/(12χ2)) χ (12x2) bit in the wale direction X is tied to the horizontal The column direction is read out in 12x2 (= mb) bit units and supplied to the replacement portion 32 °. The replacement portion 32 is to read the code bits bG to b23 from the 12x2 (= mb) bits of the memory 31, such as The symbol bit y assigned to the consecutive 2 (=b) symbols of the ® 12 > 2 (= mb) bits is shown in FIG. In the manner of y23, the code bits bG to b23 of 12<2 (= mb) bits are replaced. That is, according to FIG. 128, the replacing unit 32 is an LDPC code having an encoding rate of 5/6 and an LDPC code having an encoding rate of 8/9 in an LDPC Ma having a code length N of 16,200 bits, and a code length N being For an LDPC code with a coding rate of 5/6 and an LDPC code with a coding rate of 9/10 in an LDPC code of 64,800 bits, respectively, for any LDPC code: respectively, the code bit bG is assigned to the symbol bit y ! 〇, 分配 Assign code bit b! to symbol bit y 15, assign code bit b2 to symbol y4, assign code bit b 3 to symbol y! 9, put code Bit b4 is assigned to symbol bit y21, code bit b5 is assigned to symbol bit y!6, code bit b6 is assigned to symbol bit y23, and code bit b7 is assigned to symbol bit Element y! 8, assigning code bit b8 to symbol bit yi!, 137720.doc -131 - 200952349 assigning code bit TO b9 to symbol bit y 1 4, assigning code bit 7C b 1 Q to Symbol bit y 2 2, assign code bit b 1 1 to symbol bit y 5 , assign code bit bi 2 to symbol bit y 6, assign code bit b13 to symbol bit Yn, the code bit b14 is assigned to the symbol bit 丫13, and the code bit b ! 5 is assigned to the symbol bit Element y 2〇, assign code bit b! 6 to symbol bit yi, assign code bit b ! 7 to symbol bit y 3, φ assign code bit b ! 8 to symbol bit y 9, assigning code bit bi9 to symbol bit y2, assigning code bit b G to symbol bit y7, and assigning bit b21 to symbol bit y 8, placing code bit b 2 is assigned to the symbol bit y 1 2, and the code bit b23 is assigned to the symbol bit y 〇 for replacement. According to the bit allocation pattern shown in FIG. 125 to FIG. 128, the LDPC code of the plural number type can adopt the same bit allocation mode, and any one of the LDPC codes of the plural type can make resistance to errors. Responsibility becomes the required performance. That is, 'Fig. 129 to Fig. 132 show simulation results of BER (Bit Error Rate) in the case where replacement processing is performed in accordance with the bit allocation pattern of Figs. 125 to 128. In addition, the horizontal axis of Fig. 129 to Fig. 132 indicates the signal of the symbol 137720.doc • 132· 200952349 power to noise power ratio), and the vertical axis indicates BEK. Further, the 'solid line indicates the BER in the case where the replacement processing has been performed, and the B E R in the case where the one-dot dash table is not subjected to the replacement processing. Figure 129 shows an LDPC code with a code length N of 64800 and a coding rate of 5/6 and 9/10 respectively. As a modulation method, 4〇96qAM is used, and the multiple is referred to as 1' according to the bit allocation mode of Fig. Replace the BER in the case of processing. Figure 130 shows that for a code length N of 64800 and a coding rate of 5/6 and 9/10, respectively, the code is used as a modulation method using 4〇96(^]^, and the multiple ^» is set to 2, BER in the case of replacement processing according to the bit allocation pattern of Fig. 126. Further, in Figs. 129 and 130, a graph with a triangular mark indicates a BER with respect to an LDPC code having a coding rate of 5/6, with a star attached thereto. The graph of the standard (star mark) indicates the BER of the LDPC code with a coding rate of 9A0. Fig. 13 1 shows the LDPC for the code length N of 16200 and the coding rates of 3/4, 5/6 and 8/9, respectively. The code and code length n are 64800, and the LDPC codes with the coding rates of 3/4, 5/6 and 9/10 respectively are used as the modulation method using 1〇24qAM, and the multiple b is set to 2' according to the bit allocation pattern of FIG. BER in the case of replacement processing. In addition, the graph attached to the star in Fig. 131 shows the BER of the LDPC code with a code length n of 64800 and a coding rate of 9/1 ,, with an upward triangular mark. The graph shows the BER of the LDPC code with a code length N of 64800 and a coding rate of 5/6. Moreover, the graph with the square mark indicates that the code length N is 64800, The code rate is BER of the LDPC code of 3/4. 137720.doc •133- 200952349 Further, the graph with a circle mark in 'Fig. 131' indicates an LDPC with a code length N of 16200 and a coding rate of 8/9. The BER of the code, with a downward-facing triangular mark, indicates the BER of the LDPC code with a code length N of 1 6200 and a coding rate of 5/6. Moreover, the graph with the positive mark indicates the code length. N is 16200, and the BER of the LDPC code with a coding rate of 3/4. Figure 132 shows the LDPC code with a code length N of 16200 and a coding rate of 5/6 and 8/9, respectively, and a code length N of 64800, a coding rate. The LDPC codes of 5/6 and 9/1, respectively, use 4096QAM as the modulation method, and BER ° in the case where the multiple b is set to 2' in accordance with the bit allocation mode of FIG. 128. Further, in FIG. The graph with the star indicates the BER of the LDPC code with a code length of 64800 and a coding rate of 9/10, and the graph with the upward-facing digonal mark indicates that the code length N is 64800 and the coding rate is 5/6. BER of the LDPC code. Moreover, in Fig. 132, a graph with a circle mark indicates B with respect to an LDPC code having a length of 16200 and a coding rate of 8/9. ER, a graph with a downward triangular mark indicates the BER of the LDPC code with a code length N of 16200 and a coding rate of 5/6. As can be seen from Fig. 129 to Fig. i32, the same bit allocation is used for the plural type. The mode, and with respect to any of a plurality of types of LDPC codes using the same bit allocation pattern, can make the tolerance to errors a desired performance. That is, when a plurality of types of LDPCs with different code lengths or coding rates are used in the case of the bit allocation mode dedicated to the LDPC code, 'the tolerance for errors is extremely high, but it must be different. Type 137720.doc • 134- 200952349 The LDPC code changes the bit allocation mode one by one. On the other hand, according to the bit allocation pattern of FIG. 125 to FIG. 128, the same bit allocation mode can be adopted for each of the plural types of LDPC codes having different code lengths or encoding rates, and it is not necessary to adopt the respective types of LDPC codes. In the case of the bit allocation mode dedicated to the LDPC code, the bit allocation pattern is changed one by one for different types of LDPC codes. Further, according to the bit allocation pattern of FIGS. 125 to 128, for each of the plural types of LDPC codes, even if it is slightly inferior to the bit allocation mode dedicated to the LDPC code®, even if this is the case, The correctness of the error is high performance. That is, for example, in the case where the modulation mode is 4096QAM, for an LDPC code having a code length N of 64800 and a coding rate of 5/6 and 9/10, respectively, any LDPC code can be used as shown in FIG. 125 or FIG. The same bit allocation mode. Then, even with the same bit allocation mode, the tolerance to errors can be made high performance. Further, for example, in the case where the modulation method is 1024QAM, the LDPC code with the code length N is 16200 and the coding rates are 3/4, 5/6, and 8/9, respectively, and the code length N is 64800, and the coding rate is For the LDPC codes of 3/4, 5/6, and 9/10, respectively, the same bit allocation pattern of FIG. 127 can be used for any LDPC code. Then, even if the same bit allocation mode is used, the tolerance to errors can be made high performance. Moreover, for example, in the case where the modulation mode is 4096QAM, the LDPC code having a code length N of 16200 and a coding rate of 5/6 and 8/9, respectively, and a code length N of 64800 and a coding rate of 5/6 and 9 respectively. For the LDPC code of /10, the same bit allocation pattern of Figure 128 can be used for any 137720.doc 135 - 200952349 LDPC code. Then, even with the same bit allocation mode, the tolerance to errors can be made high performance. Further explanation of the change in the bit allocation pattern. Figure 133 is a diagram showing the coding rate of the LDPC code defined by the check matrix 生成 generated by the check matrix initial value table shown in Figs. 78 to 123, in which the LDPC code is a code length N of 16,200 or 64,800 bits. In the case of the LDPC code other than 3/5, the further modulation method is qPSK, multiples! ^ is an example of the bit allocation mode that can be used in the case of 丨. ❿ LDPC code is an LDPC code with a code length N of 16200 or 64800 bits and a coding rate other than 3/5. In the case where the modulation method is QPSK and the multiple 13 is 1, the multiplexer 25 is used in the traversing. The direction of the x direction is (Ν / (2 χ 1)) χ (2 χ 1) bits of memory 3 1 written code bits are in the horizontal direction, read in 2xl (= mb) bit units, And supplied to the replacement unit 32. The replacing unit 32 assigns the code bits 兀bG and the ratio read from the memory 31i2x1 (= mb) bits to 1 (= 13) symbols 2 > 1 (=1^) as shown in FIG. The bitwise bit of the bit" and the way to replace the 2xl (= mb) bit of the code bits 〇 b 〇 and b 1 . That is, if according to FIG. 133, the replacing unit 32 respectively: The bit bQ is assigned to the symbol bit y〇, and the code bit b is assigned to the symbol bit yi, and is replaced. In addition, in this case, it is also possible to consider not replacing, and the code bit is directly used as Figure 134 shows an LDPC code in which the code length N is 16200 or 64800 bits and the coding rate is 3/5. The modulation method is further modified. 16QAM, an example of a bit allocation mode that can be used when the multiple b is 2. The LDPC code is an LDPC code with a code length N of 16200 or 64800 bits and a coding rate of 3/5, and the modulation mode is 16QAM. When the multiple b is 2, in the demultiplexer 25, the coded bits written in the memory 31 of the (Ν/(4χ2))χ(4χ2) bit in the wale direction X direction are in the horizontal direction. Column direction, to 4><2(=m b) The bit unit is read and supplied to the replacement unit 32. The replacement unit 32 is configured to allocate the code bits b to 4 from the 4x2 (= mb) bits of the memory 31, as shown in FIG. The code bits bG to b7 of the 4x2 (= mb) bits are replaced by the way of the 4x2 (= mb) bits of the consecutive 2 (= b) symbols from the symbol bits y 〇 y to y7. According to FIG. 1 34, the replacing unit 32 respectively assigns the code bit b〇 to the symbol bit y7, assigns the code bit b! to the symbol bit y!, and assigns the code bit b2 to the symbol. The meta-bit y4, 分配 assigns the code bit to the symbol bit y2, assigns the code bit b4 to the symbol bit y5, and assigns the code bit b 5 to the symbol bit y 3, and sets the code bit B6 is assigned to the symbol bit y6, and the code bit b7 is assigned to the symbol bit y〇, and is replaced. Figure 135 shows that the modulation mode is 64QAM, and the LDPC code is code length N is 16200 or 64800 bits. The LDPC code with a coding rate other than 3/5, the multiple b 137720.doc -137- 200952349 is an example of a bit allocation pattern that can be used in the case of 2. The LDPC code is a code length > 1 is 162 〇〇 or 648 〇〇 bits, encoding rate other than LDPC code, further modulation In the case of 64QAM, in the case of a wire, the memory multiplexer 25 is written in the memory multiplexer 25 in the direction of the traverse direction (Ν/(6χ2)) Χ (6χ2) bits. In the course direction, it is read in units of 6x2 (= mb) and supplied to the replacement unit 32 to read the code bits from the memory to the memory bit. ^, as shown in FIG. 135, the symbol bits of the 6x2 (= mb) bits of the consecutive 2 (leaf) symbols are replaced by the code bits of the reference element To bu. That is, if according to FIG. 1 35, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y, and assigns the code bit b ! to the symbol bit y 7, and the code bit b2 Assigned to the symbol bit y 3 , the code bit b3 is assigned to the symbol bit y 1 〇 , the code bit b4 is assigned to the symbol bit y6 , and the code bit b5 is assigned to the symbol bit y 2 ,码 Assign code bit b6 to symbol bit y9, assign code bit b7 to symbol bit .y5, assign code bit b8 to symbol bit y!, assign code bit b 9 to The symbol bit y 8 ' assigns the code bit b 〇 to the symbol y 4 ' and assigns the code bit b η to the symbol y 〇 and replaces it. 137720.doc -138- 200952349 Figure 136 is a table modulation mode is 256QAM, J_LDPC code is a bit length ^^ is 64800 bits, the encoding rate is 3/5 LDpc code multiples... An example of a pattern. The LDPC code is an LDPC code whose code length is 64_bit and whose coding rate is other than ^, and the modulation method is 256_ and multiple _; the multiplexer 25' is in the direction of the x direction (64800/).

❹ (8X2)) X (8X2) bit memory 3 1 writer's code bit is in the horizontal direction, read in 8x2 (four) b) bit units, and supplied to the replacement unit & replacement unit 32 to The code bits 兀b❶ to 读出 from the 8x2 (= mb) bits of the memory 3 1 are read, and are assigned to the symbol bits y of the 8x2 (= mb) bits of the consecutive 2 (four) symbols as shown in FIG. In the way to ~, replace the 8x2 (= mb) bits of code bits b〇 to b15. That is, according to FIG. 36, the replacing unit 32 respectively assigns the code bit bQ to the symbol bit 5, assigns the code bit b! to the symbol bit yi, and assigns the code bit h to Symbol bit. 3. Assign the code bit h to the symbol bit y3, assign the code bit b4 to the symbol bit y8, assign the code bit bs to the symbol bit yn, and assign the code bit b0 to the symbol The bit force, the code bit h is assigned to the symbol bit y5, the code bit bs is assigned to the symbol bit yi 〇, the code bit b9 is assigned to the symbol bit y6, and the code bit 1 is used. 1() is assigned to the symbol bit y4, 137720.doc • 139- 200952349 The code bit element t) Π is assigned to the symbol bit y 7, and the code bit !), 2 is assigned to the symbol bit 丫 12 The code bit b is assigned to the symbol bit y2, the code bit !^4 is assigned to the symbol bit 714, and the code bit bls is assigned to the symbol bit y〇 for replacement. Figure 137 shows that the modulation mode is 256qAM, and the ldpc code is the code length! ^ is an example of a bit allocation pattern that can be used in the case of a 16200-bit, LDpc code with a coding rate other than 3/5 and a multiple b of 1. The LDPC code is the code length! ^ is 162 〇〇 bits, the encoding rate is 3/5 other than the LDPC code, and the further modulation mode is 256QAM, the multiple ^^ is in the case of the multiplexer 25' in the waling direction X direction The code bits written by the memory 31 of (16200/(8xl)) x (8xl) bits are read in the horizontal direction, read in units of 8x1 (= mb) bits, and supplied to the replacement unit 32. The replacing unit 32 is configured to allocate the code bits b to 8 > 7 ' read from the 8x1 (= mb) bits of the memory 31 to i (= b) symbols as shown in FIG. 137 (= mb The way to replace the 8x1 (= nib) bits of code bits b〇 to b7. That is, according to FIG. 137, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y7, assigns the code bit ratio to the symbol bit y3, and assigns the code bit b2 to the symbol bit. y J, assigning code bit b3 to symbol bit y 5, assigning code bit b4 to symbol bit y2, 137720.doc -140- 200952349 assigning code bit b5 to symbol bit y6, The code bit b6 is assigned to the symbol bit y4, and the code bit b7 is assigned to the symbol bit y〇 for replacement. Figure 138 shows an LDPC code in which the LDPC code is 162 〇〇 or 648 〇〇 bits and the coding rate is 3/5. The further modulation method is QpsK and the multiple b is 1. An example of a meta-allocation model.

LDPC code 疋 code length N is 16200 or 64800 bits, encoding rate is 3/5 LDPC code, further modulation mode is QpsK, multiple ^ 丨, in the solution multiplexer 25, in the vertical direction X horizontal The code bits written in the memory 31 of the column direction (Ν/(2χ1))χ(2χ1) are in the course direction, read out in 2xl (=mb) bit units, and supplied to the replacement unit 32. . The replacing unit 32 is configured to assign the code bits read from the memory 3122x1 (= mb) bits to the 2x==== mb bits of 1 (=13) symbols as shown in FIG. The meta-bit yG&yi is used to replace the code bits b〇 and bj of 2xl (= mb) bits. That is, as shown in Fig. 1 38, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y, and assigns the code bit b to the symbol yi, and replaces it. In addition, in this case, it is also possible to consider the replacement of the code bit b. And h are directly used as the symbol bits yG and y, respectively. Figure 139 is a diagram showing that the LDPC code is a code length; ^ is 648 〇〇 bits, and the coding rate is 3/5 LDPC code, and the further modulation is mqam, and the multiple [) is 2 137720.doc -141 - 200952349 An example of a bit allocation pattern that can be used. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 16QAM and the multiple b is 2, the multiplexer 25 is in the X direction of the traversing direction. The code bits written in the memory 31 of the direction (64800/(4χ2)) χ (4χ2) bits are in the course direction, read out in units of 4x2 (= mb) bits, and supplied to the replacement unit 32. The replacing unit 32 assigns the code bits bG to b7 read from the 4><2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols 4 >;< 2 (= mb) bits of the symbol bits yG to y7, in place of the 4x2 (= mb) bits of code bits bG to b7. That is, according to FIG. 1 39, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y, assigns the code bit b! to the symbol bit y 5, and assigns the code bit b2. For the symbol bit y 1, the code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y4, and the code bit b5 is assigned to the symbol bit y7, the code bit is assigned The element b6 is assigned to the symbol bit y3, and the code bit b7 is assigned to the symbol bit y6 for replacement. Fig. 140 is a diagram showing an example in which the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5, and a bit allocation pattern which can be employed in the case where the modulation method is 16QAM and the multiple b is 2.

The LDPC code is an LDPC 137720.doc -142· 200952349 code having a code length N of 16,200 bits and a coding rate of 3/5. In the case where the modulation mode is 16QAM and the multiple b is 2, the multiplexer 25 is disposed. The code bits written in the memory 31 of the (16200/(4χ2)) χ (4χ2) bit in the wale direction X direction are in the course direction, and are read in units of 4x2 (= mb) bits. And supplied to the replacement unit 32. The replacing unit 32 assigns the code bits bG to b7 read from the 4x2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in Fig. 140 >< 2 (= mb) The bitwise symbol y〇 to y7 of the bit, replacing the code bits b〇 to b7 of the 4x2 (= mb) bit. That is, according to Fig. 140, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y7, assigns the code bit b! to the symbol bit y 1, and assigns the code bit to the symbol The meta-bit y4 assigns the code bit b3 to the symbol bit y2, the code bit b4 to the symbol bit ys, the code bit b5 to the symbol bit y3, and the code bit b6. Give the symbol y6,

Q assigns the code bit b7 to the symbol bit y〇 and replaces it. Figure 141 shows an example in which the modulation mode is 64QAM, and the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and a multiple of the bit allocation mode. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 64QAM and the multiple b is 2, the multiplexer 25 is arranged in the X direction of the traversing direction. The direction is (64800/(6χ2)) χ(6χ2) bits 137720.doc -143 - 200952349, the code bit system written by δ ** recall 3 1 of 6<2 (== mb) bits It is read out in the horizontal unit cell and supplied to the replacement unit 32. The replacing unit 32 is configured to allocate the code bits bo to bn of 6 x 2 (= mb) bits read from the memory 3, as shown in FIG. 141 to 6x2 (= mb) bits of two consecutive (four) symbols. The way of the symbol yjyn is to replace (4) the heart of the bit element bG to bn. That is, according to FIG. 41, the replacing unit 32 respectively assigns the code bit b〇 to the symbol bit y2, assigns the code bit b! to the symbol bit y7, 0 assigns the code bit b2 For the symbol bit y6, the code bit b3 is assigned to the symbol bit y9, the code bit b4 is assigned to the symbol bit y, and the code bit b5 is assigned to the symbol y3, and the code bit is The element]36 is assigned to the symbol bit yt, the code bit b7 is assigned to the symbol bit y8, the code bit b8 is assigned to the symbol bit y4, and the code bit b9 is assigned to the symbol bit yi The code bit b1G is assigned to the symbol bit y5, and the code bit bn is assigned to the symbol bit 710 for replacement. Figure 142 shows an example in which the modulation mode is 64QAM, and the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5, and a multiple of 1) is used.

The LDPC code is an LDPC with a code length N of 1,600 bits and a coding rate of 3/5. 137720.doc -144- 200952349 code '^-step modulation mode is 64QAM, multiple 4 2, in the case of the multiplexer 25 'In the wale direction x course direction is (16 shoulders (6χ2)) χ (4)) Bits: The code bits written by the memory 31 are in the horizontal direction, in units of 6><2(=mb) bits Read out and supply to the replacement unit 32. The replacing unit 32 assigns the code bits b to b' read from the 6x2 (= mb) bits of the memory 3 i to 6x2 of the consecutive 2 (= b) symbols as shown in FIG. Mb) The bitwise symbol y() to yn of the bit, replacing the 6χ2 claws... the bitwise bits bG to bu. That is, according to FIG. 142, the replacing unit 32 respectively assigns the code bit b〇 to the symbol bit yu, assigns the code bit b! to the symbol bit y7, and assigns the code bit b2 to the symbol. The bit y3, the code bit b3 is assigned to the symbol yi 〇, the code bit b4 is assigned to the symbol y6, the code bit b5 is assigned to the symbol y2, and the code bit b6 Assigned to the symbol bit y9, the code bit b7 is assigned to the symbol bit y 5 , the code bit b8 is assigned to the symbol bit y J , and the code bit b9 is assigned to the symbol bit y8 , The code bit b] is assigned to the symbol y4, and the megabyte bt ! is assigned to the symbol y 〇 and replaced. Figure 143 shows that the modulation mode is 256QAM, and the LDPC code is an LDPC code with a code length of ^64 for 64800 bits and a coding rate of 3/5. The case where the multiple b is 2 is 137720.doc -145-200952349 An example of a bit allocation pattern. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 256QAM and the multiple b is 2, the multiplexer 25 is disposed in the X direction of the traversing direction. The memory bit in the direction of (64800/(8χ2)) χ(8χ2) bit 3 1 is written in the horizontal direction, read out in 8 x 2 (= mb) bit units, and supplied to the replacement unit. 32. The replacing unit 32 assigns the code bits bG to b15 read from the 8 X2 (= mb) bits of the memory 3 1 to 8x2 of the consecutive 2 (= b) symbols as shown in FIG. Mb) the bit y of the bit. To the yi5 mode, replace the code bits b〇 to b of the 8<2(=mb) bits. That is, according to FIG. 143, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y2, assigns the m-bit b! to the symbol bit y π, and assigns the code bit b2 to the symbol. The bit position y3 assigns the code bit b3 to the symbol bit y4, the code bit b4 to the symbol bit y, and the code bit b5 to the symbol y9, and the code bit b6 Assigned to the symbol bit y!, the code bit b7 is assigned to the symbol bit y8, the code bit b8 is assigned to the symbol bit y! 〇, and the code bit b9 is assigned to the symbol bit y! 3. Assign the code bit b! 〇 to the symbol bit y 7, assign the code bit b! i to the symbol bit y! 4, and assign the code bit b ! 2 to the symbol bit y 6 , 137720.doc -146- 200952349 assigns the code bit b13 to the symbol bit 丫15, the code bit b14 to the symbol y5, and the code bit b15 to the symbol 丫12, and Replace it. Fig. 144 shows an example in which the modulation mode is 256 qaM, and the LDPC code is a bit allocation mode in the case where the code length N is 16,200 bits, the coding rate is 3/52 ldpC code, and the multiple 13 is 1.

The LDPC code is an LDpc code with a code length N of 162 bits and a coding rate of 3/5. In the case where the modulation mode is 256QAM and the multiple is 3, the solution is in the vertical direction. The code bit written in the memory 31 in the X-direction of (ΐ62〇〇/(8χ1))χ(8χ1) bits is in the horizontal direction, and is read out in 8xl (=mb) bit units and supplied To the replacement part 3 2 . The replacing unit 32 is configured to assign the code bits bG to h read from the memory 31i8x1 (= mb) bits to the symbol bits yG of the bits of 1 (= b) symbols as shown in FIG. In the manner of h, the code bits b〇 to b*7^ of 8xl (= mb) bits are replaced. That is, if the replacement unit 32 is respectively according to FIG. 1 44, the code bit bG is assigned to the symbol bit. Y7, assigning the code bit b to the symbol bit y3, assigning the code bit b2 to the symbol bit yi, assigning the code bit b3 to the symbol bit y5, and assigning the code bit b4 to the symbol The bit y2 assigns the code bit b5 to the symbol y6, and the code bit b6 to the symbol y4, 137720.doc • 147- 200952349 assigns the code bit b7 to the symbol y Oh, and replace it. Next, the deinterleaver 53 constituting the receiving device 12 will be described. Figure 145 is a diagram for explaining the processing of the multiplexer 54 constituting the deinterleaver 53. That is, 'Fig. 145' shows a functional configuration example of the multiplexer 54. The multiplexer 54 is composed of a reverse replacement unit 1〇〇1 and a memory 1〇〇2. The multiplexer 54 performs the inverse replacement processing (replacement processing) of the replacement processing performed by the demultiplexer 25 of the transmitting apparatus 11 with the symbol bit supplied from the symbol of the demapping section 52 of the preceding stage as a target. Reverse processing), that is, the position of the code bit (symbol bit) of the LDPC code replaced by the replacement processing is returned to the original position, and the LDPC code obtained by the result is supplied to the latter stage. The vertical twist deinterleaver 55, that is, 'in the multiplexer 54, supplies the symbol bit of the mb bit of the b symbol to the unit of (continuous) b symbols for the inverse replacement unit 1001. Y〇, y],. ", ymb-i 〇 替换 替换 1 1 1 1 进行 001 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb The replacement portion 32 of the demultiplexer 25 on the side of the transmitting device 11 is replaced by the reverse of the arrangement of the preceding code bits b〇 to bmb-, and the code position of the mb bit obtained by the result is output. The element b2 to bmw. The memory 1002 is the same as the memory 3 1 constituting the demultiplexer 25 on the side of the transmitting device 11 The row (horizontal) direction memorizes the mb bit, and memorizes the memory capacity of the N/(mb) bit in the column (longitudinal) direction. That is, the δ-recall cell 1002 is composed of memory N/( Mb) mb _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In the direction of the output, the writing of the LDPC code outputted by the anti-replacement unit 1001 is performed, and writing to the memory 1002 is performed in the direction of writing the code to the memory 31. The reading of the code bit 0 is the 'multiplexer 54 of the receiving device 12, as shown in FIG. 145A, and the code bit of the LDPC code outputted by the reverse part is in the horizontal unit. The direction writer is sequentially performed from the i-th column of the memory to the following. Then, if the writing of the code bit of 1 yard long is finished, the code bit is transmitted from the memory 1002 in the multiplexer W' It is read from the wale direction and supplied to the whirling twist deinterleaver 5 of the rear stage. Here, Fig. 145B shows the reading from the code bit of the memory 丨〇〇2. In the circumscribing device 54, the reading position of the LDPC code in the vertical direction Q □ constituting the memory 1 〇〇 2 is performed from the top left direction to the right direction. Fig. 146 is a diagram showing the processing of the vertical twist deinterleaver 55 constituting the deinterleaver 53 of the receiving device 12. The drawing shows the configuration example of the memory 1 2 of the multiplexer 54. The memory 1002 has a wales ( The vertical direction memory mb bits, and the memory capacity of the N/(mb) bits is stored in the horizontal (horizontal) direction, and is composed of mb wales. The vertical twist deinterleaver 55 controls the memory 1002 to control the start of the reading position when the code bits of the LDpc 137720.doc • 149·200952349 code are written in the course direction and read in the wale direction. Perform longitudinal twist de-interlacing. In other words, the vertical twist deinterleaver 55 appropriately changes the start reading position of the start code bit for each of the plurality of wales, thereby performing the code bit rearranged by the vertical twist parent error. Arrange back to the original rearrangement processing. Here, Fig. 146 shows an example of the configuration of the suffix 1002 in the case where the modulation method is 16QAM and the multiple 1 is 丄. Therefore, the number of bits of a symbol is 4 bits, and the memory 1 〇〇 2 is composed of 4 (= mb) vertical lines. The vertical twist deinterleaver 55 (instead of the multiplexer 54) sequentially performs the code bits of the LDJ>C code output from the replacement unit 1 〇〇1 from the first column of the memory 1〇〇2. Write to the direction of the column. Then, if the writing of the code bit of 1 code long is finished, the vertical twist deinterleaver 55 is a vertical line from the left to the right direction, and the code bit is moved from above the memory 1〇〇2 ( Read in the wale direction). The 'longitudinal twist deinterleaver 55' writes the vertical twist interleaver 24 on the transmitting device U side to the start writing position of the code bit as the starting read position of the code bit, and proceeds from the memory 1〇〇2. The reading of the code bit. That is, if the address of the position of the beginning (topmost) of each wales is set to 0', the address of each position in the walody direction is represented by an integer in ascending order, then the modulation mode is 16QAM and the multiple b is 1. In the case of the vertical twist deinterleaver 55' with respect to the leftmost vertical line, the start reading position is set to the position where the address is 〇, and the (second from left) the start position is set as the read position. The location where the address is 2 'About the 3rd ordinate' will start the read position and set the address to 4. 137720.doc -150- 200952349 Set 'About the 4th Queue' to start the read position as the address For the 7th position. Set. In addition, the beginning of the reading position is the vertical position of the position other than the position of the address, and the reading of the code bit is performed to the lowermost position, and then the head is returned (the address is the position of the 〇), and the Readout before reading the position before the position is read. Then, the reading from the next (right) wales is performed thereafter. The arrangement of the code bits rearranged by the longitudinal twist de-interlacing 'longitudinal twist interleaving as described above will return to the original arrangement. Next, the ® 147 is a block diagram showing another configuration example of the receiving device 12. The data processing device of the modulation signal of the receiving device 12 receiving the transmission device from Fig. 147 is composed of a quadrature demodulating unit 51, a demapping unit 52, a deinterleaver 53 and an LDPC decoding unit 1〇21. The intermodulation unit 51 receives the modulated signal from the transmitting device u, performs quadrature demodulation, and supplies the obtained symbol (1 and the x-axis direction & other value) to the demapping unit 52. The mapping unit 52 performs demapping of the symbols from the orthogonal demodulation unit 51 into code bits of the LDPC code, and supplies them to the deinterleaver 53. The deinterleaver 53 is composed of a multiplexer 54 and a vertical The line twist deinterleaver 55 and the parity deinterleaver 1011 are configured to perform deinterleaving of the code bits of the LDPC code from the demapping unit. In other words, the multiplexer 54 performs the inverse replacement processing (reverse processing of the replacement processing) corresponding to the replacement processing performed by the demultiplexer 25 of the transmitting device 作为 as the target from the demapping unit 522LDpc code, that is, The reverse replacement 137720.doc - 151 - 200952349 is performed to return the position of the code bit replaced by the replacement processing to the original position, and the LDPC code obtained as a result is supplied to the walt deinterleaver 55. The vertical twist deinterleaver 55 takes the LDPC code from the multiplexer 54 as a target, and performs a longitudinal twisting solution of the longitudinal twist interleaving performed as the rearrangement processing by the vertical twist interleaver 24 of the transmitting device 11. staggered. The LDPC code obtained as a result of the whirling de-interlacing is supplied from the wale twist deinterleaver 55 to the par-interleaver 1011. The parity deinterleaver 1011 performs the co-located deinterleaving (co-location) of the co-interleaving performed by the co-interleaver 23 of the transmitting device 11 with the code bit elements deinterlaced by the wobble deinterlacing of the wander twist deinterleaver 55 as a target. The inverse processing of the interleaving), that is, the parity bit of the LDPC code arranged by the co-located interleaving change is returned to the co-located deinterlacing of the original arrangement. The LDPC code obtained as a result of the co-deinterlacing is supplied from the parity deinterleaver 1011 to the LDPC decoding unit 1021. Therefore, in the receiving apparatus 12 of FIG. 147, the LDPC decoding unit 1021 is supplied with the LDPC code which has undergone the inverse replacement processing, the vertical twist deinterleave, and the colocated deinterleaving, that is, the LDPC code which is supplied by the inspection matrix. Obtained LDPC code. The LDPC decoding unit 1021 uses the LDPC encoding unit 21 of the transmitting device 11 for the LDPC-encoded check matrix Η itself or the conversion check matrix obtained by performing at least the interleave-interlaced row replacement for the check matrix. The LDPC code of the LDPC code of the interleaver 53 is decoded, and the data obtained as a result is output as a decoding result of the object data. Here, in the receiving apparatus 12 of FIG. 147, since the deinterleaver 53 (the same as 137720.doc - 152 - 200952349 bit deinterleaver 1011) supplies the LDPC decoding unit 1021 by LDPC encoding according to the check matrix When the LDPC code obtained by the LDPC encoding unit 21 of the transmitting apparatus 11 performs the LDPC decoding of the LDPC code by using the check matrix Η itself used for the LDPC encoding, the LDPC decoding unit 1021 can be sequentially performed, for example, by one node. A decoding device that performs LDPC decoding by performing a full serial decoding method for performing a message (check node message, variable node message), or by performing simultaneous (parallel) information processing for all nodes A decoding device that performs LDPC decoding by a full ® parallel decoding method. Further, the LDPC decoding unit 1021 performs LDPC decoding of the LDPC code by performing at least the conversion check matrix obtained by the row replacement of the co-interleave by the LDPC encoding unit 21 for the LDPC encoding by the LDPC encoding unit 21 of the transmitting device 11. In the case of a decoding device capable of performing an architecture of a check node operation and a variable node operation at the same time, and including the conversion of the LDPC code to obtain a conversion The row of the check matrix is replaced by the same row permutation, and is configured by rearranging the decoding means of the received data rearrangement unit 3 10 of the code bit of the LDPC code. In addition, in FIG. 147, for convenience of explanation, the multiplexer 54 for performing the inverse replacement processing, the vertical twist deinterleaver 55 for performing the wandering deinterlacing, and the colocated deinterleaver 1011 for performing the co-located deinterleaving are separately configured. However, two or more of the multiplexer 54, the vertical twist deinterleaver 55, and the in-position deinterleaver 1011 can be integrally formed in the same manner as the parity interleaver 23, the vertical twist interleaver 24, and the demultiplexer 25 of the transmitting device 11. . 137720.doc - 153 - 200952349 Next, Fig. 148 is a block diagram showing a first configuration example of a receiving system applicable to the receiving device 12. In Fig. 148, the receiving system is composed of an obtaining unit 11〇1, a channel decoding processing unit 1102, and an information source decoding processing unit 11〇3. The acquisition unit 1101 obtains, by means of, for example, terrestrial digital broadcasting, satellite digital broadcasting, CATV network, Internet, and other networks, a transmission channel including at least LDPC encoding of image data such as image data or audio data of the program. The signal of the obtained LDPC code is supplied to the transmission channel decoding processing unit 1102. Here, when the signal acquired by the acquisition unit 11 〇1 is played back from the broadcast station via a ground wave, a satellite wave, a CATV (Cable Television) network, or the like, the acquisition unit 11 〇 1 is adjusted. Or STB (Set τ〇ρ

Box, set-top box, etc. Further, the signal acquired by the acquisition unit 11〇1 is transmitted from a web server such as IPTV (Internet Pr〇t〇C()1 Televisi()n: Internet Protocol TV) by multicast. The acquisition unit 1101 is configured by, for example, a network I/F (Interface: Interface) such as an NIC (Network Interface Card). The channel decoding processing unit 1102 applies a channel gamma process to the signal acquired by the acquisition unit 101 via the transmission channel, and at least includes a process of processing the error generated by the channel, and supplies the signal obtained as a result. The information source decoding processing unit 11 〇3. That is, the signal obtained by the acquisition unit 11 〇1 via the transmission path is a signal obtained by at least performing error correction coding for correcting the error generated by the transmission path, and the transmission channel decoding processing unit 1102 is for such a signal. , 137720.doc • 154- 200952349 For example, the error correction processing such as the error correction processing. j is a code for error 5, such as LDpc code or Lie Solomon code. Here, at least LDPC encoding is performed as the error correction code. Moreover, the transport material processing may include demodulation of the modulated signal, and the like. The information source decoding unit applies the information source decoding process to the process of reading (4) the channel decoding processing by applying at least the information to be stretched into the original information. In other words, the signal acquired by the acquisition unit 1101 via the transmission path may be subjected to compression coding of compressed information in order to reduce the amount of data such as images or sounds of information. In this case, the information source solution processing unit 11G3 is used. For the signal subjected to the read channel decoding processing, information source decoding processing such as processing (stretching processing) of compressing the information into the original information is applied. Further, when the signal acquired by the acquisition unit 1101 via the transmission path is not subjected to compression coding, the information source decoding processing unit 11〇3 does not perform the process of expanding the information of the pressure Ifg into the original information. Here, as the stretching processing, for example, mpeg decoding or the like is used. Moreover, the channel decoding processing may include a descrambling code or the like in addition to the stretching processing. In the acquisition unit 1101 configured as described above, for example, for data such as images or sounds, compression coding such as MPEG encoding is applied, and the error correction correction code such as LDPC coding is acquired via the transmission path. It is supplied to the transmission channel decoding processing unit 1102. In the transmission channel decoding processing unit 1102, for example, the orthogonal demodulation unit 51 bites the 137720.doc-155-200952349 mapping unit 52 and deinterleaves the transmission channel decoding processing for the transmission channel decoding processing. In the same manner, the LDPC decoding unit 56 (or the LDPC decoding unit 1021) supplies the signal obtained as a result to the information source decoding processing unit 1103. The information source decoding processing unit 1103 performs information source decoding processing such as MPEG decoding on the k number from the channel decoding processing unit 1102, and outputs the image or sound obtained as a result. The receiving system as shown in Fig. 148 above can be applied to, for example, a television level adjuster that receives television broadcast as digital broadcasting. Further, the acquisition unit 11 〇1, the transmission channel decoding processing unit ii02, and the information source decoding processing unit 1103 can be configured as one independent device (hardware (integrated circuit) or the like) or a software module. . Further, the acquisition unit 1101, the channel decoding processing unit 11〇2, and the information source decoding processing unit 1103 can set the acquisition unit 1101 and the channel decoding processing unit 11〇2 or the channel decoding processing unit 11〇2 and The collection of the information source decoding processing unit 1103, the acquisition unit 11〇1, the transmission channel decoding processing unit ιι〇2, and the information source decoding processing unit 1103 are configured as separate devices. Figure 149 is a block diagram showing a second configuration example of a receiving system applicable to the receiving device 12. In the drawings, the same reference numerals are attached to the portions corresponding to those in the case of Fig. 148, and the description thereof will be omitted as appropriate. The receiving system of FIG. 149 is the same as the case of FIG. 148 except that the acquisition unit 丨丨〇丨, the channel decoding processing unit 11〇2, and the information source decoding processing unit 1103 are included, and the output unit “" is newly provided. This is different from the case of Figure 148. 137720.doc • 156 - 200952349 The output unit 1111 is, for example, a display device that displays an image or a speaker that emits sound, and outputs an image or sound output from the information source decoding processing unit 11G3. That is, the output section deletes the display image = sound. The receiving system as shown in Fig. 149 above can be applied to, for example, a TV (television receiver) that receives television broadcast as digital broadcasting, a money receiving broadcast broadcast receiver, and the like. Treatment

Further, when the signal acquired by the acquisition unit 11G1 is not subjected to compression coding, the signal output from the transmission channel decoding processing unit 1102 is supplied to the portion 1111. Figure 150 is a block diagram showing a third example of a receiving system applicable to the receiving device 12. In the drawings, the same reference numerals are attached to the portions corresponding to those in the case of Fig. 148, and the description thereof will be omitted as appropriate. The receiving system of Fig. 150 is common to the case of the acquisition unit 11〇1 and the transmission channel decoding unit 1102, as shown in Fig. 148. Here, the receiving system of Fig. 150 is different from the case of Fig. 148 in that the recording unit 1121 is newly provided without the information source decoding processing unit 11〇3. The recording unit 1121 is a unit that outputs the channel decoding processing unit 丨丨〇2. (For example, TS packet of TS of MPEG), recorded (memorized) in recording (memory) media such as optical film 7 or hard disk (magnetic disk), flash memory. The receiving system as shown in Fig. 150 above can be applied to a video recorder or the like that plays television. In addition, in FIG. 150, the receiving system sets the information source decoding processing unit I37720.doc • 157-200952349 1103 to constitute the information source decoding processing unit 11〇3, and can apply the information source by the recording unit ιΐ2ι Decoding the processed signal, that is, the image or sound obtained by the translation. However, if the replacement processing of the new replacement method of replacing the code bit as shown in FIG. 64 is performed according to the allocation rule according to FIG. 63, the replacement processing of the current mode of replacing the code bit as shown in FIG. Increased tolerance to errors (Figure 65). Further, according to the LDPC code (proposal code) of the inspection matrix 求出 obtained from the check matrix initial value table of Figs. 66 to 68, as shown in Fig. 69, the tolerance to errors can be improved compared with the specification @ code. . If the above is just a new replacement method or proposal code, it can also improve the tolerance for errors 'but by using the proposal code' and adopt the method of replacing the code bits according to the allocation rule that is appropriate for the proposal code. The replacement treatment (hereinafter also: the appropriate method) can improve the tolerance to errors. / Park 151 to Figure 155 are diagrams showing the appropriate mode.

That is, the graph indicates that the LDPC code is a code length material (4) (9) bit, and the rate is 2/3, which is obtained from the initial value table of the check matrix of FIG. 66 to FIG. 68. Check the matrix LDPC code (proposal code), further Modulation 3: And the number of symbol groups and symbols in the case of Zhao, multiples... _Brother, read from the memory 31 series with 8 axe bit position code ^ to 15 units, the 8 χ in response to the difference in error rate, such as 70 code position ^. To h system Figure 151A can not be grouped into 5 codes 137720.doc •158- 200952349 bit group GbbGbafbhGbhGbs. In FIG. 151A, respectively, the code bit group Gb is associated with the code bit b〇, the code bit group Gb>2 is the code bit bi, and the mom bit group Gb3 is the code bit h> 2 to b9 belong to the 'code bit group Gb4 code bit Xb1G, and the code bit group Gb5 is the code bit bu to b15. When the modulation mode is 256QAM and the multiple b is 2, the symbol bits y〇 to yis of the 8x2 (= mb) bits are different according to the error rate. As shown in FIG. 151B, the group can be divided into 4 characters. The meta-bit group 〇71, 〇72,0丫3, 0丫4. In FIG. 15 1B ' respectively, the symbol element group Gy! is a symbol element 丫〇, 丫 1, 78, 丫 9 belongs to the 'character bit group 〇丫 2 line symbol bit 72, 73, 71 (), 711 belongs to, the symbol element group Gy3 is a symbol element 74, 丫 5, 乂 12, 713 belongs to, the symbol element group Gy4 is a symbol element 丫 6, 77,) ^ 14, 715 Own. Figure 152 is a diagram showing an allocation rule of a suitable mode in the case where the LDPC code is a proposal code, the modulation method is 256QAM, and the multiple b is 2. In the distribution rule of Figure 152, group group information (Gbi, Gy4 l), (Gb2, Gy2, l), (Gb3, Gy, 2), (Gb3, Gy2, 2), (Gb3, Gy3, 2), (Gb3, Gy4, 2), (Gb4, Gy4, l), (Gb^Gy!, 〗), (Gb5, Gy2, l), (Gb5, Gy3, 2). Therefore, the allocation rule in FIG. 1 52 is defined as follows: According to the group set information (Gb^Gy^l), the 1-bit '1' of the code bit of the first good code bit group Gb 1 of the error rate is assigned. Give the 1st bit of the symbol bit of the 4th good symbol group Gy4 of the error rate; according to the group set > (Gb2, Gy2, 1)', the error rate is the 2nd good code bit group One bit of the code bit of the group Gb>2 is allocated to the one bit of the symbol bit of the second good symbol bit group Gy2 of the error correction rate; 137720.doc -159- 200952349 According to the group collection information (Gb3, G^, 2), assigning the 2 bits of the code bit of the error bit rate 3b to the code bit group Gh to the -μ 士 + σ block error rate 1st good symbol bit Group Gy丨 is a 2-bit symbol; according to the group collection information (Gb3, Gy2, 2), the error is tang ^ ^ Niu Di 3 good code position 兀 group Gh code bit 2 The bit is allocated to the 2-bit of the symbol bit of the second good symbol group Gy2 of the error rate; according to the group set information (GbhGyy), the error is confirmed _ the third good code group 70 group Group 2 of Gb3 code bits Yuan, assigned to the 3rd good symbol group Gy of the error rate; 2 bits of the symbol bit; according to the group set information (Gb3, Gy4, 2), the error rate is the 3rd good code point The 2 bits of the code bit of the meta-group Gbs are assigned to the 2-bit element of the error bit rate of the good symbol bit group Gy#; according to the group set information (Gb4, Gy4, l) , the error rate __ 卞 ang 4 good code position 兀 group GW code bit 丨 bit, assigned to the error rate of the * good symbol group Gy * symbol bit 1 Bits; according to the group set information (Gb5, Gyi, 2), assign the wrong error rate to the wrong bit of the coded bit of the group Gbs to the wrong bit - the hoof is the first good 2 bits of the symbol bit group Gy!; according to the group set information (Gbs, Gy2, l), the error rate is the 5th bar code bit group Gb5 of the code bit i Bit, assigned to the error rate, the 1st bit of the symbol of the second best symbol group Gys; and according to the group collection information (Gb5, Gy3, 2), the error rate is the best Code bit group Gb5 Bit 2 of the code bits allocated to the P well of the error rate determined symbol bits of the symbol bit group Gy3 2 of bits. 137720.doc 200952349 Figure 153 is an alternative representation of the code bits in accordance with the allocation rules of Figure 152. That is, FIG. 153A shows that the LDPC code is a proposal code having a code length N of 64800 bits and a coding rate of 2/3, and further modulation mode is 256QAM, and the multiple b is 2, according to the allocation rule of FIG. The first example of the replacement of the code bits. The LDPC code is a proposed code having a code length N of 64,800 bits and a coding rate of 2/3. In the case where the modulation method is 256QAM and the multiple b is 2, the multiplexer 25 is disposed in the X direction of the traverse direction. The memory bit in the direction of (64800/(8χ2))χ(8x2) bit® is written in the horizontal direction, read in 8x2 (=mb) bits, and supplied to the replacement unit. 32 (Fig. 16, Fig. 17). The replacing unit 32 assigns the code bits 15() to 1315 read from the 8><2 (=1111) bits of the memory 31 in accordance with the allocation rule of FIG. 152, for example, as shown in FIG. (=b) 8x2 (= mb) bit symbol bits >^ to y15 of the symbol to replace the code bits 5〇 to b15 of 8<2(=mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y7, 分配 assigns the code bit b! to the symbol bit y 2, and assigns the code bit b2 to the symbol bit ys> The code bit b3 is assigned to the symbol bit y〇, the code bit b4 is assigned to the symbol bit y4, the code bit b5 is assigned to the symbol bit y6, and the code bit b6 is assigned to the symbol Meta-bit y! 3, assign code bit b7 to symbol bit, assign code bit b8 to symbol y!4, 137720.doc -161 - 200952349 assign code bit 7〇b 9 to The symbol bit y 1 〇, assigning the code bit 7〇b 1 ο to the symbol bit y 15 ' assigns the code bit bi! to the symbol bit y 5 , and assigns the code bit b 1 2 to the symbol The meta-bit y 8 ' assigns the code bit b 13 to the symbol bit y 12 '. The code bit 兀b 1 4 is assigned to the symbol bit 兀 y 1 1, and the code bit b 15 is assigned to the symbol bit y 1 ' and replace it. 153B shows that the LDPC code is a coded code having a code length N of 64,800 bits and a coding rate of 2/3. Further modulation is 256QAM, and the multiple b is 2, and the code bit according to the allocation rule of FIG. The second example of replacement. According to FIG. 153B, the replacing unit 32 performs the following replacement for the code bits b〇 to b15 of the 8 x2 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 152: The code bit b〇 is assigned to the symbol bit y7, the code bit b丨 is assigned to the symbol bit y 2 , and the code bit b 2 is assigned to the symbol bit y 1 '. The code bit b 3 is allocated Assigning the symbol bit y 〇 ' to the symbol bit y 13 ' assigns the code bit b 5 to the symbol bit y 12 and assigns the code bit b 6 to the symbol bit y 6 'Assign code bit b 7 to symbol bit y 3 ' Assign code bit b 8 to symbol bit y 15 ' Assign code bit b 9 to symbol 兀 y 11 ' 137720. Doc -162- 200952349 Assigning the tilde b 1 q to the symbol y 14 ' assigning the code bit b η to the symbol y 5 ' assigning the code bit b 12 to the symbol y 8 The code bit b 13 is assigned to the symbol bit y 4 , the code bit b 14 is assigned to the symbol bit 丫 10 , and the code bit b 15 is assigned to the symbol bit y 9 . Here, the allocation of the megabytes 1^ to the symbol bits φ shown in Fig. 153 and Fig. 1536 is in accordance with the distribution rule of Fig. 152 (according to the allocation rule). Fig. 154 and Fig. 155 show the simulation results of the BER in the case where the replacement processing of the appropriate mode described in Figs. 151 to 153 has been performed. Further, in Figs. 154 and 155, the horizontal axis represents Es/N 〇 and the vertical axis represents BER. Further, in Figs. 154 and 155, the modulation method is 25 6QAM, and the multiple b is 2. Figure 154 is a diagram showing the BER (indicated by a circle in the figure) in the case of the replacement processing of Figure 153A in the applicable mode illustrated in Figures ι 51 to ι 53 for the proposal code, and the code length N is 64800, and the coding rate is The LDP (code) of the DVB-S.2 specification specified in 2/3 carries out the BER (indicated by a star in the figure) in the case of the replacement processing (the replacement processing of the current mode) described in FIG. 60C. As can be seen from Fig. 154, the replacement of the proposed code by the appropriate method can make the wrong floor drastically lower than the current mode of replacement processing for the specification code, and the tolerance to errors is improved. Figure 155 is a diagram showing the BER in the case where the proposal code is subjected to the replacement processing in the appropriate manner (indicated by a circle in the figure), and the replacement processing described in the figure 137720.doc-163-200952349 60C for the proposal code (the current mode) BER in the case of replacement processing (indicated by a star in the figure). As can be seen from Fig. 1 55, by adopting an appropriate replacement process for the proposal code, the BER can be lowered and the tolerance to errors can be improved compared with the case of the replacement process in the current mode. The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing a check matrix of an LDPC code. Figure 2 is a flow chart showing the decoding procedure of the LDPC code. Fig. 3 is a view showing an example of a check matrix of an LDPC code. Figure 4 is a diagram showing the Tanner graph of the inspection matrix. Figure 5 is a diagram showing a variable node. Figure 6 is a diagram showing a check node. Fig. 7 is a view showing an example of a configuration of an embodiment of a transport system to which the present invention is applied. FIG. 8 is a block diagram showing a configuration example of the transmitting device 11. Figure 9 is a diagram showing an inspection matrix. Fig. 10 is a view showing a parity matrix. Figure 11 is a diagram showing the check matrix and row weight of the LDPC code defined by the specifications of DVB-S.2. 12A and 12B are diagrams showing the signal point arrangement of 16QAM. Figure 13 is a diagram showing the signal point configuration of 64QAM. Figure 14 is a diagram showing the signal point configuration of 64QAM. 137720.doc -164- 200952349 Figure 1 5 is a diagram showing the signal point configuration of 64QAM. 16A to 16D are diagrams for explaining the processing of the multiplexer 25. 17A and 17B are diagrams for explaining the processing of the multiplexer 25. Figure 18 is a diagram showing a Tanner graph for decoding of an LDPC code. 19A and 19B are views showing a parity matrix Ητ which is a step structure and a Tanner graph corresponding to the parity matrix Ητ. Figure 20 is a diagram showing the parity matrix Ητ of the check matrix 对应 corresponding to the LDPC code after the co-located interleaving. 21A and 21 are views showing a conversion check matrix. Fig. 22 is a view showing the processing of the whirling twist interleaver 24. Fig. 23 is a view showing the number of wales of the memory 3 1 and the address at which the write position is started, which are necessary for the whirling of the wagger. Fig. 24 is a view showing the number of wales of the memory 3 1 and the address at which the writing position is started, which are necessary for the whirling of the wagger. Fig. 25 is a flow chart showing the transmission processing. 26A and 26B are views showing a model of a communication channel used in the simulation. Fig. 27 is a graph showing the relationship between the error rate obtained by the simulation and the Bucher frequency fd of the flutter. Fig. 28 is a graph showing the relationship between the error rate obtained by the simulation and the Buhler frequency fd of the flutter. FIG. 29 is a block diagram showing a configuration example of the LDPC encoding unit 21. Fig. 30 is a flow chart for explaining the processing of the LDPC encoding unit 21. Figure 31 is a diagram showing a check matrix initial value table 137720.doc - 165 - 200952349 of a coding rate of 2/3 and a code length of 16200. Figure 32 is a diagram showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 64,800. Figure 33 is a diagram showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 64,800. Fig. 34 is a view showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 64,800. Fig. 35 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 16200. Fig. 36 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 37 is a view showing a table of initial values of inspection matrices of a coding rate of 3/4 and a code length of 64,800. Fig. 38 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 39 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 40 is a view showing a check matrix initial value table of a coding rate of 4/5 and a code length of 16200. Figure 41 is a diagram showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Fig. 42 is a view showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Figure 43 is a diagram showing the check matrix initial value table 137720.doc • 166 - 200952349 of a coding rate of 4/5 and a code length of 64,800. Fig. 44 is a diagram showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Fig. 45 is a view showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 16200. Fig. 46 is a view showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800.

Figure 47 is a diagram showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Figure 48 is a diagram showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Figure 49 is a diagram showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Fig. 50 is a view showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 16200. Figure 51 is a diagram showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Figure 52 is a diagram showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Figure 53 is a diagram showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Fig. 54 is a view showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Fig. 55 is a diagram showing the table of initial values of the check matrix of the code rate of 9/10 and the code length of 64,800 137720.doc -167 - 200952349. Fig. 56 is a view showing a table of initial values of inspection matrices of a coding rate of 9/10 and a code length of 64,800. Fig. 57 is a view showing a table of initial values of inspection matrices of a coding rate of 9/10 and a code length of 64,800. Fig. 58 is a view showing a table of initial values of inspection matrices of a coding rate of 9/10 and a code length of 64,800. Fig. 59 is a view for explaining a method of obtaining a check matrix 从 from a check matrix initial value table. Figures 60A through C are diagrams illustrating the replacement process of the current mode. Fig. 61Α~C are diagrams showing the replacement processing of the current mode. 62A and 62B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 256QAM and the multiple b is 2. Fig. 63 is a diagram showing an allocation rule ij in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 256QAM and the multiple b is 2. Figs. 64A and 64B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 256QAM and the multiple b is 2. Fig. 65 is a view showing the BER of the case where the replacement processing of the new replacement mode has been performed and the case where the replacement processing of the current mode has been performed. Fig. 66 is a view showing an example of an inspection matrix initial value table of an LDPC code which is a good performance Eb/N 〇 compared with a specification code. Fig. 67 is a view showing an example of an inspection matrix initial value table of the LDPC code of the 137720.doc -168·200952349 which is a good performance limit Eb/N〇. Fig. 68 is a view showing an example of a check matrix initial value table of an LDPC code which is a good performance Eb/N 〇 compared with a specification code. Fig. 69 is a view showing the relationship between the specification code and the proposal code 2Es/N〇 and BER. Fig. 70 is a block diagram showing a configuration example of the receiving device 12. Figure 7 is a flow chart illustrating the receiving process. Fig. 72 is a view showing an example of a check matrix of an LDPC code. ❹ Fig. 73 is a diagram showing a matrix (conversion check matrix) after the column replacement and row replacement are performed on the inspection matrix. Fig. 74 is a view showing a conversion check matrix divided into 5 x 5 units. Fig. 75 is a block diagram showing an example of a configuration of a decoding apparatus for performing P node operations. Fig. 76 is a block diagram showing a configuration example of the LDPC decoding unit 56. Fig. 77 is a block diagram showing a configuration example of an embodiment of a computer to which the present invention is applied. Fig. 78 is a view showing an example of a check matrix initial value table of a coding rate of 2/3 and a code length of 16200. Fig. 79 is a view showing an example of a check matrix initial value table of a coding rate of 2/3 and a code length of 64,800. Fig. 80 is a view showing an example of a check matrix initial value table of a coding rate of 2/3 and a code length of 64,800. Fig. 81 is a diagram showing an example of a check matrix initial value table of a coding rate of 2/3 and a code length of 64,800. 137720.doc -169- 200952349 Fig. 82 is a diagram showing an example of an inspection matrix initial value table of a coding rate of 3/4 and a code length of 16200. Fig. 83 is a view showing an example of a check matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 84 is a view showing an example of a check matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 85 is a view showing an example of a check matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 86 is a diagram showing an example of a check matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 87 is a view showing an example of a check matrix initial value table of a coding rate of 4/5 and a code length of 16200. Fig. 88 is a diagram showing an example of a check matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Fig. 89 is a view showing an example of a check matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Fig. 90 is a view showing an example of a check matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Fig. 91 is a view showing an example of an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Fig. 92 is a diagram showing an example of a check matrix initial value table of a coding rate of 5/6 and a code length of 16200. Fig. 93 is a view showing an example of a check matrix initial value table of a coding rate of 5/6 and a code length of 64,800. 137720.doc -170- 200952349 Fig. 94 is a diagram showing an example of a check matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Fig. 95 is a view showing an example of a check matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Fig. 96 is a view showing an example of a check matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Fig. 97 is a diagram showing an example of a check matrix initial value table of a coding rate of 8/9 and a code length of 16200. 〇 Fig. 98 is a diagram showing an example of a check matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Fig. 99 is a view showing an example of a check matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Fig. 100 is a view showing an example of a table of initial values of a check matrix of a coding rate of 8/9 and a code length of 64,800. Fig. 101 is a view showing an example of a table of initial values of a check matrix of a coding rate of 8/9 and a code length of 64,800. Fig. 102 is a diagram showing an example of an initial value of a check matrix of a coding rate of 9/10 and a code length of 64,800. Fig. 103 is a view showing an example of a table of initial values of a check matrix of a coding rate of 9/10 and a code length of 64,800. Fig. 104 is a view showing an example of a table of initial values of a check matrix of a coding rate of 9/10 and a code length of 64,800. Fig. 105 is a view showing an example of an initial value of a check matrix of a coding rate of 9/10 and a code length of 64,800. 137720.doc -171 - 200952349 Figure 106 is a diagram showing an example of a table of initial values of a check matrix with a quartering rate of 1/4 and a code length of 648〇〇. Fig. 107 is a diagram showing an example of a table of initial values of a check matrix having a coding rate of 1/4 and a code length of 648 。. Fig. 108 is a diagram showing an example of a table of initial values of a check matrix having a coding rate of 1/3 and a code length of 64,800. Fig. 109 is a view showing an example of a table of initial values of a check matrix of a coding rate of 1/3 and a code length of 648 。. Fig. 110 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 2/5 and a code length of 64,800. Fig. 111 is a view showing an example of a table of initial values of a check matrix of a coding rate of 2/5 and a code length of 648 。. Figure 112 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/2 and a code length of 64,800. Fig. 113 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1 / 2 and a code length of 64,800. Fig. 114 is a view showing an example of a table of initial values of a check matrix of a knitting ratio 丨/2 and a code length of 64800. Fig. 115 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/5 and a code length of 64,800. Figure 116 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/5 and a code length of 64,800. Figure 117 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/5 and a code length of 64,800. 137720.doc 200952349 Fig. 118 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/4 and a code length of 16200. Figure 119 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/3 and a code length of 16200. Fig. 120 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 2/5 and a code length of 16200. Fig. 121 is a view showing an example of a table of initial values of a check matrix of a coding rate of 1/2 and a code length of 16,200. Ο Fig. 122 is a diagram showing an example of an initial value of a check matrix of a coding rate of 3/5 and a code length of 1,600. Fig. 123 is a view showing another example of the check matrix initial value table of the coding rate 3/5 and the code length 16200. Figure 124 is a diagram for explaining a method of obtaining a check matrix 从 from a check matrix initial value table. Figure 125 is a diagram showing an alternative of a code bit. Figure 126 is a diagram showing an alternative of a code bit. ❹ Figure 127 is a diagram showing an alternative of the code bits. Figure 128 is a diagram showing an alternative of a code bit. Figure 129 is a diagram showing the simulation result of BER. Figure 130 is a diagram showing the simulation result of BER. Fig. 131 is a view showing the simulation result of the BER. Figure 132 is a diagram showing the simulation result of BER. Figure 13 is a diagram showing an alternative of the code bits. Figure 134 is a diagram showing an alternative of a code bit. 137720.doc -173- 200952349 Figure 135 is a diagram showing an alternative to a code bit. Figure 136 is a diagram showing an alternative of a code bit. Figure 137 is a diagram showing an alternative of a code bit. Figure 138 is a diagram showing an alternative of a code bit. Figure (9) is a diagram showing an alternative to the table. Figure 140 is a diagram showing an alternative of a stone horse bit. Figure 141 is a diagram showing an alternative of the code bits. Figure 142 is a diagram showing an alternative of a code bit. Figure 143 is a diagram showing an alternative of a code bit. Figure 144 is a diagram showing an alternative of a code bit. 145A and 145B are views showing the multiplexer 54 constituting the deinterleaver 53. Figure 146 is a diagram illustrating the processing of the wobble twist deinterleaver 55. Figure 147 is a block diagram showing another configuration example of the receiving device 12. Figure 148 is a block diagram showing a first configuration example of a receiving system applicable to the receiving device 12. Figure 149 is a block diagram showing a second configuration example of a receiving system applicable to the receiving device 12. Figure 150 is a block diagram showing a third configuration example of a receiving system applicable to the receiving device 12. 151A and 151B are diagrams showing a code bit group and a symbol bit group in the case where the code number is 648 〇 () and the code rate is 2/3, and the multiple & . Figure 152 is a diagram showing the allocation rule in the case where the 256QAM modulation code length is 648 〇〇, the coding rate is 2/3, and the code b is 2, and the multiple b is 2. Figs. 153A and 153B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the 256QAM modulation code length 64800 and the coding rate 2/3 are proposed codes, and the multiple b is 2. Fig. 1 is a diagram showing a case where the replacement processing of the proposed code is performed in a suitable manner, and a BER in the case where the current mode is replaced by the specification code. Fig. 155 is a diagram showing the case where the replacement processing of the proposal code is performed in the appropriate manner, and the BER in the case where the replacement processing of the current mode is performed. [Description of main component symbols] 11 Transmitting device 12 Receiving device 21 LDPC encoding unit 22 Bit interleaver 23 Co-located interleaver 24 Vertical twist interleaver 25 Demultiplexer 26 Mapping unit 27 Quadrature modulation unit 31 Memory 32 replacement Unit 51 orthogonal demodulation unit 52 demapping unit 53 deinterleaver 137720.doc -175- 200952349 54 multiplexer 55 vertical twist deinterleaver 56 LDPC decoding unit 300 branch data storage memory 301 selector 302 Verification node calculation unit 303 Cyclic shift circuit 304 Branch data storage memory 305 Selector 306 Receive data memory 307 Variable node calculation unit 308 Cyclic shift circuit 309 Decode word calculation unit 310 Receive data rearrangement unit 311 Decode Data rearrangement unit 601 Encoding processing unit 602 Memory unit 611 Encoding rate setting unit 612 Initial value table reading unit 613 Check matrix generation unit 614 Information bit reading unit 615 Encoding parity calculation unit 616 Control unit 701 Confluence row 137720.doc - 176- 200952349

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CPU

ROM

RAM hard disk output unit input unit communication unit disk drive input/output interface removable recording medium reverse replacement unit memory co-located deinterleaver LDPC decoding unit acquisition unit transmission channel decoding processing unit information source decoding processing unit output unit recording unit 137720. Doc -177-

Claims (1)

200952349 VII. Patent application scope: 1. A data processing device, comprising: a replacement mechanism, which memorizes a code bit of an LDPC (Low Density Parity Check) code having a code length of N bits. The m-bit of the code bit of the LDPC code read in the row direction of the memory device in the course direction and the wale direction is written as one symbol and a specific positive integer Let b, the memory means memorize mb bits in the horizontal direction, and store N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism. And then reading in the horizontal direction, and replacing the code bits of the mb bits in the case where the code bits of the mb bits read in the row direction of the memory mechanism are used as the b symbols. a symbol, the replaced code bit is used as a symbol bit to represent the preceding symbol; and the foregoing LDPC code is as specified by the specification of DVB-S.2 or DVB-T.2, and the code length N is 64800 bits. An LDPC code having a coding rate of 2/3, the m-bit is octet, and The integer b is 2, and the octet of the code bit is mapped as one of the 256 signal points determined by 256QAM as one of the symbols, and the memory mechanism has a memory of 8×2 bits in the horizontal direction. Longitudinal and memorize 64800/(8x2) bits in the wale direction; the aforementioned replacement mechanism is 137720.doc 200952349 which will read the 8 x 2 bit code position read by the direction of the § recall mechanism The i+1th bit is set to the bit bi from the highest order bit, and the iq bit of the 8x2 bit of the preceding two symbols is counted from the highest order bit. Set bit y; to assign bit bG to bit y15, bit b! to bit y7, bit b2 to bit y!, bit b3 to bit y5 , bit b4 is assigned to bit y6, bit b5 is assigned to bit y!3, bit b6 is assigned to bit yi!, bit b7 is assigned to bit y9, bit b8 is assigned to Bit y8, bit b9 is assigned to bit y i4, bit b1G is assigned to bit y12, bit b! i is assigned to bit y 3, bit b 丨 2 is assigned to bit y 〇 Will B〗 element 3 to the bit y 1 billion, the bit b!. 4 bits assigned to y 4, the bit b! Assigned to each assigned 5-bit y2 'of replacement. 2. A data processing method comprising the following steps: a replacement step of memorizing a code bit of an LDPC (Low Density Parity Check) code of length N bits in a row 137720. Doc 200952349 The m-bit of the code bit of the LDPC code read in the preceding direction of the memory device in the direction and the wale direction is regarded as one symbol and a specific positive integer Let b, the memory means memorize mb bits in the horizontal direction, and store N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism. And then reading in the horizontal direction, and replacing the code bits of the mb bits in the case where the code bits of the mb bits read in the row direction of the memory mechanism are used as the b symbols. a symbol, the replaced code bit is used as a symbol bit to represent the preceding symbol; and the foregoing LDPC code is as specified by the specification of DVB-S.2 or DVB-T.2, and the code length N is 64800 bits. An LDPC code having a coding rate of 2/3, the m-bit is 8 bits, and the foregoing The integer b is 2, and the octet of the code bit is mapped as one of the 256 signal points determined by 256QAM as one of the symbols, and the memory mechanism has 16 bits of 8x2 bits stored in the horizontal direction. Longitudinally, and remembering 64800/(8x2) bits in the wale direction; in the foregoing replacement step, the code bits of 8x2 bits read out in the row direction of the memory mechanism are counted from the highest order bit The i+th bit is set to the bit bi, and the symbol bits of the 8x2 bits of the consecutive two preceding symbols are set to the bit yi from the highest order bit, and the i+1th bit is set as the bit yi. 137720.doc 200952349 Assigning bit bG to bit y 15 'Assign bit bi to bit y7 ' Assign bit b2 to bit y 1 ' Assign bit b3 to bit y5 ' Bit b4 Assigned to bit y6 'Assign bit b5 to bit y 13 ' Assign bit b6 to bit y 11 ' Assign bit b7 to bit y9 ' Assign bit b8 to bit y8 ' The element b9 is assigned to the bit yi4', the bit bi 〇 is assigned to the bit y 12, the bit bi! is assigned to the bit y 3 , and the bit b 丨 2 is assigned Y billion dollars, the bit b 13 to the bit y! Square, the bit b 4 to the bit y〗 4, the bit b!. 5 assigned to the bit y 2, the allocation of each alternative. 3. An encoding apparatus that performs encoding by an LDPC (Low Density Parity Check) code, and includes: an encoding mechanism that performs a code length of 64,800 bits and a coding rate of 2 And encoding the LDPC code of the LDPC code; and the check matrix of the LDPC code is configured by arranging the 1 element of the information matrix defined by the check matrix initial value table of the check matrix in the row direction every 36 〇 rows, the check The matrix initial value table indicates the position of the first element of the information matrix corresponding to the length of the information corresponding to the foregoing code 137720.doc 200952349 and the foregoing encoding rate in every 360 rows; the foregoing check matrix initial value table includes: 317 2255 2324 2723 3538 3576 6194 6700 9101 10057 12739 17407 21039 1958 2007 3294 439412762 14505 14593 14692165221773719245 21272 21379 127 860 5001 5633 86449282 12690 14644 17553 19511 19681 2095421002 2514 2822 5781 6297 8063 9469 9551 11407 11837 12985 15710 20236 20393 1565 3106 4659 4926 6495 6872 7343 8720 15785 16434 16727 19884 21325 706 3220 8568108961248613663 16398165 9919475 1978120625 2096121335 4257 10449 12406 14561 16049 16522 17214 18029 18033 18802 19062 19526 20 748 412 433 558 2614 2978 4157 6584 9320 11683 11819 13024 14486 16860 777 5906 7403 8550 8717 8770 11436 1284613629 14755 15688 1639216419 4093 5045 6037 7248 8633 9771 10260 1080911326 12072 17516 19344 19938 21202648 3155 3852 6888 12258 14821 1535916378 16437177912061421025 1085 2434 58167151 80509422 10884 12728 15353 17733 18140 1872920920 G 856 1690 12787 6532 7357 9151 4210 16615 18152 11494 14036 17470 2474 10291 10323 1778 6973 10739 4347 9570 18748 2189 11942 20666 137720.doc 200952349 3868 7526 17706 8780 14796 18268 160 16232 17399 1285 2003 18922 4658 17331 20361 2765 4862 5875 4565 5521 8759 3484 7305 15829 5024 17730 17879 7031 12346 15024 179 6365 11352 2490 3143 5098 2643 3101 21259 4315 4724 13130 594 17365 18322 5983 8597 9627 10837 15102 20876 10448 20418 21478 3848 12029 15228 708 5652 13146 5998 7534 16117 2098 13201 18317 9186 14548 17776 5246 10398 1859 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 555 13816 15376 ❹ 10574 11268 17932 15442 17266 20482 390 3371 8781 10512 12216 17180 4309 14068 15783 3971 11673 20009 9259 14270 17199 2947 5852 20101 137720.doc 200952349 3965 9722 15363 1429 5689 16771 6101 6849 12781 3676 9347 18761 350 11659 18342 5961 14803 16123 2113 9163 13443 2155 9808 12885 2861 7988 11031 7309 9220 20745 6834 8742 11977 2133 12908 14704 10170 13809 18153 13464 14787 14975 799 1107 3789 3571 8176 10165 5433 13446 15481 3351 6767 12840 8950 8974 11650 1430 4250 21332 6283 10628 15050 8632 14404 16916 6509 10702 16278 15900 16395 17995 137720.doc 200952349 8031 18420 19733 3747 4634 17087 4453 6297 16262 2792 3513 17031 14846 20893 21563 17220 20436 21337 275 4107 10497 3536 75 20 10027 Ο 14089 14943 19455 1965 3931 21104 2439 11565 17932 154 15279 21414 10017 11269 16546 7169 10161 16928 10284 16791 20655 _ 36 3175 8475 ❹ 2605 16269 19290 8947 9178 15420 5687 9156 12408 8096 9738 14711 4935 8093 19266 2667 10062 15972 6389 11318 14417 8800 18137 18434 137720.doc 200952349 5824 5927 15314 6056 13168 15179 3284 13138 18919 13115 17259 17332. 4. A method of encoding, which utilizes an encoding device encoded by an LDPC (Low Density Parity Check) code, and includes the following steps: The encoding device performs encoding with a code length of 64,800 bits. a step of encoding an LDPC code of 2/3; and the check matrix of the LDPC code is configured according to a period of every 360 lines of the information matrix of the check matrix initial value table of the check matrix. The check matrix initial value table indicates the position of the 1 element of the information matrix corresponding to the information length corresponding to the code length and the foregoing coding rate in every 360 rows; the foregoing check matrix initial value table includes: 317 2255 2324 2723 3538 3576 6194 6700 9101 10057 12739 17407 21039 19582007329443941276214505 14593 14692165221773719245 2127221379 127 860 5001 5633 86449282 12690 14644 17553 19511 19681 2095421002 25142822 5781 6297 8063 94699551 11407 11837 12985 1571020236 20393 1565 3106 4659 4926 6495 6872 7343 8720 15785 16434 16727 19884 21325 706 3220 8568 10896 12486 13663 16398 1659919475 1978120625 2096121335 4257 1044912406 14561 16049 16522 1721418029 18033 18802 19062 1952620 748 412 433 558 2614 2978 4157 6584 9320 11683 11819 13024 14486 16860 137720.doc -10- 200952349 77759067403 8550 87178770 11436 12846 13629 14755 15688 16392 16419 4093 5045 6037 7248 8633 9771 10260 1080911326 12072 17516 19344 19938 212026483155 38526888 12258 14821 15359 16378 16437177912061421025 1085 2434 5816 7151 80509422 10884 12728 15353 17733 18140 1872920920 856 1690 12787 6532 7357 9151 4210 16615 18152 11494 14036 17470 2474 10291 10323 1778 6973 10739 4347 9570 18748 2189 11942 20666 3868 7526 17706 8780 14796 18268 160 16232 17399 1285 2003 18922 4658 17331 20361 2765 4862 5875 4565 5521 8759 3484 7305 15829 5024 17730 17879 7031 12346 15024 179 6365 11352 2490 3143 5098 137720. Doc 200952349 2643 3101 21259 4315 4724 13130 594 17365 18322 5983 8597 9627 10837 15102 20876 10448 20418 21478 3848 12029 15228 708 5652 13146 5998 7534 16117 2098 13201 18317 9186 14548 17776 5246 10398 18597 3083 4944 21021 13726 18495 19921 6736 10811 17545 10084 12411 14432 1064 13555 17033 679 9878 13547 3422 9910 20194 3640 3701 10046 5862 10134 11498 5923 9580 15060 1073 3012 16427 5527 20113 20883 137720.doc 200952349 7058 12924 15151 9764 12230 17375 772 7711 12723 555 13816 15376 10574 11268 17932 15442 17266 20482 390 3371 8781 10512 12216 17180 ◎ 4309 14068 15783 3971 11673 20009 9259 14270 17199 2947 5852 20101 3965 9722 15363 1429 5689 16771 6101 6849 12781 _ 3676 9347 18761 G 350 11 659 18342 5961 14803 16123 2113 9163 13443 2155 9808 12885 2861 7988 11031 7309 9220 20745 6834 8742 11977 2133 12908 14704 137720.doc -13- 200952349 10170 13809 18153 13464 14787 14975 799 1107 3789 3571 8176 10165 5433 13446 15481 3351 6767 12840 8950 8974 11650 1430 4250 21332 6283 10628 15050 8632 14404 16916 6509 10702 16278 15900 16395 17995 8031 18420 19733 3747 4634 17087 4453 6297 16262 2792 3513 17031 14846 20893 21563 17220 20436 21337 275 4107 10497 3536 7520 10027 14089 14943 19455 1965 3931 21104 2439 11565 17932 154 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 18919 13115 17259 17332. ❹ 5. A data processing apparatus, comprising: a replacement mechanism for storing code bits of an LDPC (Low Density Parity Check) code having a code length of N bits in a horizontal direction and a vertical direction The m-bit of the code bit of the LDPC code read in the preceding direction of the memory direction in the row direction is defined as one symbol, and the specific positive integer is b, The memory mechanism memorizes mb bits in the foregoing direction, and stores the N/(mb) bits in the wale direction in the first 137720.doc -15-200952349, and the code bits of the LDPC code are in the foregoing wales of the foregoing memory mechanism. The direction is written, and then read in the horizontal direction, and the mb bit is replaced by the mb bit in the case where the mb bits of the mb bits read in the row direction of the memory mechanism are b symbols. a code bit, the replaced code bit is used as a symbol bit representing the symbol; and the LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 2/3, and the m bit Is 8 bits, and the aforementioned integer b is 2, and the octet of the aforementioned code bit is made One of the aforementioned symbols is mapped to any one of 256 signal points determined by 256QAM. The memory mechanism has 16 vertical lines that store 8x2 bits in the horizontal direction and 64800/(8x2) bits in the vertical direction. The replacement mechanism is that the 8x2 bit code bit read out in the row direction of the memory mechanism is calculated from the highest order bit, and the i + + bit is set as the bit bi, and will be consecutive 2 The symbolic element of the 8x2 bit of the symbol is set to the bit yi from the highest order bit, and the bit bG is allocated to the bit y7, and the bit b! is assigned to Bit y 2, assigning bit b2 to bit y9, assigning bit b3 to bit y, assigning bit b4 to bit y4, 137720.doc -16- 200952349 assigning bit b 5 to Bit y 6, assigning bit b6 to bit y 5 3, assigning bit b7 to bit y3, assigning bit b 8 to bit y丨4, and assigning bit b9 to bit y丨〇, assigning bit b丨〇 to bit y丨5, assigning bit b 11 to bit y 5, assigning bit b! 2 to bit y 8, and assigning bit b 13 to bit Yuan yi 2, the bit b 14 is assigned to the bit y 丨丨, the bit b ! 5 is assigned to the bit yj, and each of the allocations is replaced; the check matrix of the LDPC code is determined according to the check matrix initial value table of the check matrix One element of the information matrix is arranged in the row direction every 360-row period, and the check matrix initial value table is the ❹ 1 element of the information matrix corresponding to the information length corresponding to the code length and the encoding rate. The position is expressed in every 360 rows; the aforementioned inspection matrix initial value table includes 317 2255 2324 2723 3538 3576 6194 6700 9101 10057 12739 17407 21039 1958 2007 3294 43941276214505 14593 14692165221773719245 21272 21379 127 860 5001 5633 8644 9282 12690 14644 17553 19511 19681 20954 21002 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 412 433 558 2614 2978 4157 6584 9320 11683 11819 13024 14486 16860 777 5906 7403 8550 8717 8770 11436 12846 13629 14755 15688 16392 16419 4093 5045 6037 7248 8633 9771 10260 10809 11326 12072 17516 19344 19938 212026483155 38526888 12258 14821 15359 16378 16437 17791 2061421025 1085 2434 5816 7151 8050 9422 10884 12728 15353 17733 18140 18729 20920 856 1690 12787 6532 7357 9151 4210 16615 18152 11494 14036 17470 2474 10291 10323 1778 6973 10739 4347 9570 18748 2189 11942 20666 3868 7526 17706 8780 14796 18268 160 16232 17399 1285 2003 18922 4658 17331 20361 2765 4862 5875 4565 5521 8759 3484 7305 15829 5024 17730 17879 137720.doc •18, 200952349 7031 12346 15024 179 6365 11352 2490 3143 5098 2643 3101 21259 4315 4724 13130 594 17365 18322 5983 8597 9627 10837 15102 20876 Ο 10448 20418 21478 3848 12029 15228 708 5652 13146 5998 7534 16117 2098 13201 18317 9186 14548 17776 5246 10398 18597 Λ 3083 4944 21021 ❹ 13726 18495 19921 6736 10811 17545 10 084 12411 14432 1064 13555 17033 679 9878 13547 3422 9910 20194 3640 3701 10046 5862 10134 11498 137720.doc -19 200952349 5923 9580 15060 1073 3012 16427 5527 20113 20883 7058 12924 15151 9764 12230 17375 772 7711 12723 555 13816 15376 10574 11268 17932 15442 17266 20482 390 3371 8781 10512 12216 17180 4309 14068 15783 3971 11673 20009 9259 14270 17199 2947 5852 20101 3965 9722 15363 1429 5689 16771 6101 6849 12781 3676 9347 18761 350 11659 18342 5961 14803 16123 2113 9163 13443 2155 9808 12885 2861 7988 11031 137720.doc 200952349 7309 9220 20745 6834 8742 11977 2133 12908 14704 10170 13809 18153 13464 14787 14975 799 1107 3789 3571 8176 10165 5433 13446 15481 Ο 3351 6767 12840 8950 8974 11650 1430 4250 21332 6283 10628 15050 8632 14404 16916 6509 10702 16278 15900 16395 17995 义8031 18420 19733 ❹ 3747 4634 17087 4453 6297 16262 2792 3513 17031 14846 20893 21563 17220 20436 21337 275 4107 10497 3536 7520 10027 14089 14943 19455 137720.doc -21 200952349 1965 393 1 21104 2439 11565 17932 154 15279 21414 10017 11269 16546 7169 10161 16928 10284 16791 20655 36 3175 8475 2605 16269 19290 8947 9178 15420 5687 9156 12408 8096 9738 14711 4935 8093 19266 2667 10062 15972 6389 11318 14417 8800 18137 18434 5824 5927 15314 6056 13168 15179 3284 13138 18919 13115 17259 17332. 6. A data processing method, comprising the following steps: a replacement step of storing a code bit of an LDPC (Low Density Parity Check) code having a code length of N bits in a horizontal direction and The m-bit of the code bit of the LDPC code read in the preceding direction of the memory device in the wale direction is 137720.doc •22·200952349 as one symbol, and a specific positive integer is set to b, the memory means memorizes mb bits in the horizontal direction, and stores N/(mb) bits in the longitudinal direction, and the code bits of the LDPC code are in the foregoing wales of the memory mechanism. The direction is written, and then read in the horizontal direction, and in the case where the code bits of the mb bits read in the row direction of the memory mechanism are b symbols, the mb bits are replaced. a code bit element of the element, the replaced code bit element is used as a symbol bit element representing the symbol element; and the foregoing LDPC code system has a code length N of 64800 bits and an LDPC code with a coding rate of 2/3, the m bit The element is 8 bits, and the aforementioned integer b is 2, the aforementioned code position The octet is mapped to one of the 256 signal points determined by 256QAM as one of the preceding symbols, ^ the memory mechanism contains 16 wales of 8 χ 2 bits in the horizontal direction, in the traverse direction Memory 64800 from 8><2) bits; in the foregoing replacement step, the code bits of 8x2 bits read out from the direction of the memory mechanism are counted from the highest order bit by the i+th bit The bit b is set, and the symbol bit of 8 x 2 bits of the preceding two symbols is set as the bit yi from the highest order bit, and the bit bQ is allocated. Given bit y 7, assign bit b! to bit y 2, 137720.doc •23· 200952349 assign bit b2 to bit y9, bit b3 to bit y〇, bit b4 Assigned to bit y4, bit b5 is assigned to bit y6, bit b6 is assigned to bit y13, bit b7 is assigned to bit y3, bit b8 is assigned to bit y14, bit b9 is assigned Assigned to bit y! 〇, assign bit b1() to bit yi5, bit b! i to bit y 5, bit b! 2 to bit y 8, bit b ! 3 points The bit y 1 2 is assigned, the bit b ! 4 is assigned to the bit y 1 1, and the bit b! 5 is assigned to the bit y 1, and each allocation is replaced; the check matrix of the aforementioned LDPC code is based on the check matrix The first element of the information matrix defined by the check matrix initial value table is arranged in the row direction every 360-row period, and the check matrix initial value table is the aforementioned corresponding to the information length corresponding to the code length N and the encoding rate. The position of the 1 element of the information matrix is represented by every 360 rows; the foregoing check matrix initial value table includes 317 2255 2324 2723 3538 3576 6194 6700 9101 10057 12739 17407 21039 19582007329443941276214505 14593 146921652217737 192452127221379 127 860 5001 5633 86449282 12690 14644 17553 19511 19681 20954 21002 137720.doc -24- 200952349 25142822 5781 6297 8063 9469 9551 11407 11837 12985 157102023620393 1565 3106 4659 4926 6495 6872 7343 8720 15785 16434 16727 19884 21325 7063220 8568108961248613663 16398 1659919475 1978120625 2096121335 4257 1044912406 14561 1604916522 17214 18029 18033 18802 19062 1952620 748 412 433 558 2614 2978 4157 6584 9320 11683 11819 13024 14486 16860 777 5906 7403 8550 8717 8770 11436 12846 13629 14755 15688 16392 16419 4093 5045 6037 7248 8633 9771 10260 1080911326 12072 17516 19344 19938 21202648315538526888 12258 14821 15359 16378 16437177912061421025 10852434 58167151 8050 9422 10884 12728 15353 733 1 1 1 1 1 1 1 1 1 1 1 1 -25- 200952349 4565 5521 8759 3484 7305 15829 5024 17730 17879 7031 12346 15024 179 6365 11352 2490 3143 5098 2643 3101 21259 4315 4724 13130 594 17365 18322 5983 8597 9627 10837 15102 20876 10448 20418 21478 3848 12029 15228 708 5652 13146 5998 7534 16117 2098 13201 18317 9186 14548 17776 5246 10398 18597 3083 4944 21021 13726 18495 19921 6736 10811 17545 10084 12411 14432 1064 13555 17033 679 9878 13547 1 37720.doc 200952349 3422 9910 20194 3640 3701 10046 5862 10134 11498 5923 9580 15060 1073 3012 16427 5527 20113 20883 7058 12924 15151 9764 12230 17375 ❹ 772 7711 12723 555 13816 15376 10574 11268 17932 15442 17266 20482 390 3371 8781 10512 12216 17180 4309 14068 15783 _ 3971 11673 20009 Q 9259 14270 17199 2947 5852 20101 3965 9722 15363 1429 5689 16771 6101 6849 12781 3676 9347 18761 350 11659 18342 5961 14803 16123 137720.doc -27- 200952349 2113 9163 13443 2155 9808 12885 2861 7988 11031 7309 9220 20745 6834 8742 11977 2133 12908 14704 10170 13809 18153 13464 14787 14975 799 1107 3789 3571 8176 10165 5433 13446 15481 3351 6767 12840 8950 8974 11650 1430 4250 21332 6283 10628 15050 8632 14404 16916 6509 10702 16278 15900 16395 17995 8031 18420 19733 3747 4634 17087 4453 6297 16262 2792 3513 17031 14846 20893 21563 17220 20436 21337 137720.doc -28 - 200952349 275 4107 10497 3536 7520 10027 14089 14943 19455 1965 3931 21104 2439 11565 17932 154 15279 21414 10017 11269 16546 7169 10161 16928 10284 16791 20655 36 3175 8475 2605 16269 19290 8947 9178 15420 5687 9156 12408 8096 9738 14711 4935 8093 19266 _ 2667 10062 15972 ❹ 6389 11318 14417 8800 18137 18434 5824 5927 15314 6056 13168 15179 3284 13138 18919 13115 17259 17332. 137720.doc -29-