TWI389460B - Data processing device and data processing method - Google Patents

Description

Data processing device and data processing method

The present invention relates to a data processing apparatus and a data processing method, and an encoding apparatus and an encoding method, and more particularly to a data processing apparatus and a data processing method, and an encoding apparatus and an encoding method which can improve tolerance to, for example, errors.

LDPC (Low Density Parity Check) code has a high degree of error correction capability, and has been widely used in recent years for satellite digits such as DVB (Digital Video Broadcasting)-S.2 including Europe. The transmission method of playback (refer to, for example, Non-Patent Document 1). Moreover, the LDPC code is also reviewed for use in the next generation of terrestrial digital broadcasting.

According to recent research, the LDPC code system is the same as the turbo code and the like, and as the code length increases, the performance close to the Shannon limit is obtained. Moreover, since the LDPC code has a property that the minimum distance is proportional to the code length, it has a good error rate characteristic as its characteristic system block, and further, as an advantage, it is also said that the decoding characteristic of the turbo code or the like is hardly observed. Error floor phenomenon.

Hereinafter, the LDPC code of this type will be specifically described. Further, the LDPC code is a linear code and is not necessarily binary, but is described here as a binary.

The biggest feature of the LDPC code is that the parity check matrix (parity check matrix) defining the LDPC code is loose. Here, the loose matrix refers to a matrix in which the number of matrix elements "1" is very small (most of the elements are matrices of 0).

Fig. 1 is a diagram showing an example of an inspection matrix H of an LDPC code.

In the check matrix H of Fig. 1, the weight (row weight) of each row (the number of "1") is "3", and the weight of each column (column weight) is "6".

For encoding by LDPC code (LDPC encoding), for example, generating matrix G is generated according to inspection matrix H, and generating matrix G is multiplied for binary information bits, thereby generating a codeword (LDPC code) .

Specifically, the coding apparatus that performs LDPC coding first calculates a generation matrix G in which the equation GH ^T =0 is established between the transposed matrix H ^{T of the} inspection matrix H. Here, in the case where the generation matrix G is a K×N matrix, the encoding apparatus multiplies the bit matrix (vector u) of the information bits composed of the K bits by the generation matrix G, and generates the N-bits. The code word c(=uG) is composed. The codeword (LDPC code) generated by the encoding device is received on the receiving side via a specific communication channel.

The LDPC code decoding system Gallager is called the algorithm proposed by Probabilistic Decoding (Probabilistic Decoding), which can be utilized by a variable node (also called a message node). )) and the message propagation algorithm of the belief propagation on the so-called Tanner graph composed of check nodes. Herein, the variable node and the check node are also hereinafter simply referred to as nodes.

Figure 2 is a diagram showing the decoding procedure of the LDPC code.

In addition, the real value of the value of the "0" of the ith code bit of the LDPC code (1 code word) received by the receiving side expressed by the log likelihood ratio is suitably used hereinafter. , called the received value u _0i . Moreover, the message output from the check node is set to u _j , and the message output from the variable node is set to v _i .

First, in the decoding of the LDPC code, as shown in FIG. 2, in step S11, the LDPC code is received, the message (check node message) u _{j is} initialized to "0", and the variable of the integer which is the counter of the repeated processing is determined. k is initialized to "0", and proceeds to step S12. In step S12, the operation (variable node operation) represented by the equation (1) is performed by the received value u _0i obtained by receiving the LDPC code to obtain a message (variable node information) v _i and further borrowed The operation (check node operation) shown in the equation (2) is performed based on the message v _i to obtain the message u _j .

[Number 1]

[Number 2]

Here, d _v and d _c of the formulas (1) and (2) respectively indicate optional parameters of the number of "1" in the longitudinal direction (row) and the lateral direction (column) of the inspection matrix H, for example, In the case of the code (3, 6), d _v = 3 and d _c = 6.

In addition, the variable node operation of equation (1) and the check node operation of (2) are not branched from each other (edge: edge) (the line connecting the variable node and the check node) The input message is the object of the operation, so the operation ranges from 1 to d _v -1 or 1 to d _c -1. Moreover, the check node operation of the equation (2) is actually performed by a function R(v ₁ , v ₂ ) represented by the equation (3) defined for the output of 2 inputs v ₁ , v _{2 in} advance. The table was carried out continuously (regressively) as shown in the formula (4).

[Number 3]

×=2tanh ^-1 {tanh(v ₁ /2)tanh(v ₂ /2)}=R(v ₁ ,v ₂ ) ‧‧‧(3)

[Number 4]

In step S12, the variable k is further incremented by "1", and the process proceeds to step S13. In step S13, it is determined whether the variable k is greater than a specific number of repeated decodings C. If it is determined in step S13 that the variable k is not greater than C, the process returns to step S12, and the same process is repeated below.

Further, if it is determined in step S13 that the variable k is greater than C, the process proceeds to step S14, and by performing the operation shown in the equation (5), the message v _i which is the decoding result of the final output is obtained and output, and the LDPC code is obtained. The decoding process is over.

[Number 5]

Here, the calculation of the equation (5) is different from the variable node operation of the equation (1), and is performed using the message u _j from all the branches connected to the variable node.

Fig. 3 is a diagram showing an example of a check matrix H of a (3, 6) LDPC code (coding rate 1/2, code length 12).

The check matrix H of FIG. 3 is the same as FIG. 1, and the weight of the row is 3 and the weight of the column is 6.

4 is a Tanner diagram showing the inspection matrix H of FIG.

Here, in FIG. 4, the check node is represented by "+", and the variable node is represented by "=". The check node and the variable node correspond to the columns and rows of the check matrix H, respectively. The line between the check node and the variable node is a branch (edge: edge), which is equivalent to the element "1" of the check matrix.

That is, when the element of the i-th row of the jth column of the check matrix is 1, in FIG. 4, the i-th variable node (the node of "=") and the jth from the top are connected by branching. Check node (node of "+"). The branching system indicates that the code bit corresponding to the variable node has a constraint condition corresponding to the check node.

In the Sum Product Algorithm of the decoding method of the LDPC code, the variable node operation and the check node operation are repeated.

Figure 5 shows the variable node operation performed at the variable node.

At the variable node, the message v _i corresponding to the branch to be calculated is represented by the messages u ₁ and u ₂ from the remaining branches connected to the variable node, and the equation (1) using the received value u _0i Variable node operation to find. The message corresponding to the other branches is also obtained in the same manner.

Figure 6 shows the check node operation performed by the check node.

Here, the check node operation of equation (2) can be rewritten by the relationship of the formula a×b=exp{ln(|a|)+ln(|b|)}×sign(a)×sign(b) For the formula (6). Where sign(x) is 1 when x≧0 and -1 when x<0.

[Number 6]

Further, at x ≧ 0, if the function Φ(x) is defined as the formula Φ(x)=ln(tanh(x/2)), the equation Φ ^-1 (x)=2tanh ^-1 (e ^-x ) is established, so equation (6) can be transformed into equation (7).

[Number 7]

In the check node, the check node operation of equation (2) is performed according to equation (7).

That is, in the check node, as shown in FIG. 6, the message u _j corresponding to the branch to be calculated is by using the message v ₁ , v ₂ , v ₃ , v from the remaining branches connected to the check node. ₄ , v ₅ equation (7) check node operation to find. The message corresponding to the other branches is also obtained in the same manner.

In addition, the function Φ(x) of the formula (7) can also be expressed as Φ(x)=ln((e ^x +1)/(e ^x -1)), and Φ(x)=Φ when x>0 ^-1 (x). When the functions Φ(x) and Φ ^-1 (x) are mounted on a hardware, the LUT (Look Up Table) is used for mounting, but both are the same LUT.

Non-Patent Document 1: DVB-S. 2: ETSI EN 302 307 V1.1.2 (2006-06)

The LDPC code is used in the DVB-S.2 specification for satellite digital broadcasting or the DVB-T.2 specification for terrestrial digital broadcasting in the next generation. Moreover, the LDPC code is intended to be used in the next-generation CATV (Cable Television) digital broadcasting specification DVB-C.2.

For digital playback in accordance with DVB specifications such as DVB-S.2, the LDPC code is used as a symbol (symbol) of quadrature modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying). The symbol is mapped to a signal point and sent.

In the symbolization of the LDPC code, the replacement of the code bits of the LDPC code is performed in units of code bits of more than 2 bits, and the replaced code bit is used as the bit of the symbol.

The replacement of the code bits for the symbolization of the LDPC code is proposed in various ways, but the manner in which the proposal is tolerant to errors is improved in a manner that has been proposed.

Moreover, regarding the LDPC code itself, it is also required to propose an LDPC code which is improved in tolerance to errors than the LDPC code specified by the DVB specification such as DVB-S.2.

The present invention has been made in view of such a situation, and the tolerance to errors can be improved.

The data processing device or the data processing method according to the first aspect of the present invention includes a replacement mechanism or a replacement step of LDPC (Low Density Parity Check) having a memory code length of N bits in the horizontal direction and the longitudinal direction. The m-bit of the code bit of the LDPC code read in the preceding direction of the memory cell of the code bit is written as one symbol, and a specific positive integer Let b be, the memory means memorize mb bits in the horizontal direction, and store N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism. And then reading in the horizontal direction, and replacing the code bits of the mb bits in the case where the code bits of the mb bits read in the row direction of the memory mechanism are used as the b symbols. a symbol, the replaced code bit is used as a symbol bit representing the symbol; the code length N specified by the specification of the LDPC code system DVB-S.2 or DVB-T.2 is 64800 bits, and the coding rate is Is an LDPC code of 2/3; the aforementioned m bit is 8 bits, and the aforementioned integer b is 2, and the foregoing code bit is The 8-bit is mapped to one of the 256 signal points determined by 256QAM as one of the aforementioned symbols; the memory mechanism includes 16 vertical lines of 8×2 bits in the horizontal direction, and is stored in the longitudinal direction. 64800/(8×2) bit; the code bit of 8×2 bits read out in the direction of the memory mechanism is set to be the bit b from the highest order bit _i , and the symbol of the 8×2 bit of the preceding two symbols is set from the highest order bit to the i+1th bit as the bit y _i , and the following replacement is performed: bit b _{0 is} assigned to bit y ₁₅ , bit b _{1 is} assigned to bit y ₇ , bit b _{2 is} assigned to bit y ₁ , bit b _{3 is} assigned to bit y ₅ , bit b _{4 is} assigned The bit y _{6 is} assigned, the bit b _{5 is} assigned to the bit y ₁₃ , the bit b _{6 is} assigned to the bit y ₁₁ , the bit b _{7 is} assigned to the bit y ₉ , and the bit b _{8 is} assigned to the bit Element y ₈ , assigning bit b ₉ to bit y ₁₄ , assigning bit b ₁₀ to bit y ₁₂ , assigning bit b ₁₁ to bit y ₃ , and assigning bit b ₁₂ to bit y ₀ , bit b _{13 is} assigned to bit y ₁₀ , bit b _{14 is} assigned to bit y ₄ , bit b is _{15 is} assigned to bit y ₂ .

In the first aspect of the above, the LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 2/3 as defined by the specifications of DVB-S.2 or DVB-T.2, and the aforementioned m bits. The memory is 8 bits, and the integer b is 2, and the octet of the code bit is mapped as one of the 256 signal points determined by 256QAM as one of the symbols, and the memory mechanism is included in the horizontal row. The direction memory remembers 16 wales of 8×2 bits, and in the case of memory 64800/(8×2) bits in the wale direction, 8×2 bits read out in the course direction of the memory mechanism The iQ bit from the highest order bit is set to the bit b _i from the highest order bit, and the symbol bits of the 8×2 bits of the consecutive two preceding symbols are counted from the highest order bit. The i+1 bit is set to the bit y _i , and the following substitution is made: the bit b _{0 is} assigned to the bit y ₁₅ , the bit b _{1 is} assigned to the bit y ₇ , and the bit b _{2 is} assigned to the bit y ₁ , assigning bit b ₃ to bit y ₅ , assigning bit b ₄ to bit y ₆ , assigning bit b ₅ to bit y ₁₃ , and assigning bit b ₆ to bit y ₁₁ , bit b _{7 is} assigned to bit y ₉ , bit b _{8 is} assigned to bit y ₈ , bit will be Element b _{9 is} assigned to bit y ₁₄ , bit b _{10 is} assigned to bit y ₁₂ , bit b _{11 is} assigned to bit y ₃ , bit b _{12 is} assigned to bit y ₀ , bit b is assigned _{13 is} assigned to bit y ₁₀ , bit b _{14 is} assigned to bit y ₄ , and bit b _{15 is} assigned to bit y ₂ .

An encoding apparatus or a coding method according to a second aspect of the present invention includes an encoding unit or a step of performing encoding of an LDPC code having a code length of 64,800 bits and a coding rate of 2/3; and the inspection matrix of the LDPC code is The first element of the information matrix defined by the check matrix initial value table of the check matrix is arranged in the row direction every 360-row period, and the check matrix initial value table corresponds to the information length corresponding to the code length and the encoding rate. The position of the 1 element of the aforementioned information matrix is represented by every 360 rows; the foregoing check matrix initial value table includes:

In the second aspect as described above, encoding is performed by an LDPC code having a code length of 64,800 bits and a coding rate of 2/3. The inspection matrix of the LDPC code is configured by arranging one element of the information matrix defined by the check matrix initial value table of the check matrix in the row direction every 360-row period, and the check matrix initial value table and the code length and The position of the first element of the information matrix corresponding to the information length corresponding to the foregoing coding rate is represented by every 360 lines; the initial value table of the foregoing check matrix includes:

The data processing device or the data processing method according to the third aspect of the present invention includes a replacement mechanism or a replacement step of LDPC (Low Density Parity Check) having a memory code length of N bits in the horizontal direction and the longitudinal direction. The m-bit of the code bit of the LDPC code read in the preceding direction of the memory cell of the code bit is written as one symbol, and a specific positive integer Let b be, the memory means memorize mb bits in the horizontal direction, and store N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism. And then reading in the horizontal direction, and replacing the code bits of the mb bits in the case where the code bits of the mb bits read in the row direction of the memory mechanism are used as the b symbols. a symbol, the replaced code bit is used as a symbol bit representing the symbol; the LDPC code has a code length N of 64800 bits and an encoding rate of 2/3 LDPC code; the m bit is 8 bits. And the aforementioned integer b is 2; 8 bits of the aforementioned code bit are mapped as one of the aforementioned symbols One of 256 signal points determined by 256QAM; the memory mechanism contains 16 vertical lines of 8×2 bits in the horizontal direction and 64800/(8×2) bits in the longitudinal direction; The code bit of 8×2 bits read out in the row direction of the memory mechanism is set to the bit b _i from the highest order bit, and 2 consecutive symbols are consecutive The 8×2 bit symbol bit is set to the bit y _i from the highest order bit, and the following replacement is performed: the bit b _{0 is} allocated to the bit y ₇ , and the bit is allocated b _{1 is} assigned to bit y ₂ , bit b _{2 is} assigned to bit y ₉ , bit b _{3 is} assigned to bit y ₀ , bit b _{4 is} assigned to bit y ₄ , bit b _{5 is} assigned Assigned to bit y ₆ , bit b _{6 is} assigned to bit y ₁₃ , bit b _{7 is} assigned to bit y ₃ , bit b _{8 is} assigned to bit y ₁₄ , bit b _{9 is} assigned Bit y ₁₀ , assigning bit b ₁₀ to bit y ₁₅ , assigning bit b ₁₁ to bit y ₅ , assigning bit b ₁₂ to bit y ₈ , and assigning bit b ₁₃ to bit y ₁₂ , assigning bit b ₁₄ to bit y ₁₁ and bit b ₁₅ to bit y ₁ ; the aforementioned LDPC code The check matrix is formed by arranging one element of the information matrix defined by the check matrix initial value table of the check matrix in the row direction every 360 rows, and the check matrix initial value table is matched with the aforementioned code length N and the foregoing code. The position of the 1 element of the aforementioned information matrix corresponding to the information length corresponding to the information length is represented by 360 lines; the initial value matrix of the foregoing inspection matrix includes:

In the third aspect of the above, the foregoing LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3; the m-bit is 8 bits, and the integer b is 2; The octet of the element is mapped to one of the 256 signal points determined by 256QAM as one of the aforementioned symbols; the memory mechanism includes 16 vertical lines of 8×2 bits in the horizontal direction, in the wales The direction memory is 64800/(8×2) bits; the code bits of 8×2 bits read out in the direction of the memory mechanism are set to be the i+1th bit from the highest order bit. The element b _i , and the symbol bits of the 8×2 bits of the preceding two symbols are set from the highest order bit to the i+1th bit as the bit y _i , and the following replacement is performed: The element b _{0 is} assigned to the bit y ₇ , the bit b _{1 is} assigned to the bit y ₂ , the bit b _{2 is} assigned to the bit y ₉ , the bit b _{3 is} assigned to the bit y ₀ , and the bit b is assigned _{4 is} assigned to bit y ₄ , bit b _{5 is} assigned to bit y ₆ , bit b _{6 is} assigned to bit y ₁₃ , bit b _{7 is} assigned to bit y ₃ , bit b _{8 is} assigned Given bit y ₁₄ , assign bit b ₉ to bit y ₁₀ and assign bit b ₁₀ to Bit y ₁₅ , assigning bit b ₁₁ to bit y ₅ , assigning bit b ₁₂ to bit y ₈ , assigning bit b ₁₃ to bit y ₁₂ , and assigning bit b ₁₄ to bit y ₁₁ , the bit b _{15 is} assigned to the bit y ₁ . Further, the inspection matrix of the LDPC code is configured by arranging one element of the information matrix defined by the check matrix initial value table of the check matrix in the row direction every 360-row period, and the check matrix initial value table is the same as the code The position of the first element of the information matrix corresponding to the information length corresponding to the foregoing coding rate is represented by 360 lines; the initial value table of the foregoing check matrix includes:

In addition, the data processing device and the encoding device may each be an independent device, or may be an internal block constituting one device.

Effect of invention

According to the present invention, tolerance to errors can be improved.

Fig. 7 is a view showing an example of a configuration in which one embodiment of the transmission system to which the present invention is applied (the system refers to a logically aggregated plurality of devices, regardless of whether or not the devices of the respective structures are in the same casing).

In Fig. 7, the transmission system is composed of a transmitting device 11 and a receiving device 12.

The transmitting device 11 performs, for example, transmission (playback) (transmission) of a television broadcast program. In other words, the transmitting device 11 encodes, for example, an image data to be transmitted as an image data or a sound material of a television broadcast program, into an LDPC code via a network such as a satellite line or a ground wave, a CATV network, or an Internet. It is sent by the communication channel 13.

The receiving device 12 is, for example, a pacer or a television receiver that receives a television broadcast program, an STB (Set Top Box), and a PC that receives an IPTV (Internet Protocol Television) (Personal Computer: Personal Computer) And the like, the LDPC code transmitted from the transmitting device 11 via the communication channel 13 is received, decoded into the target data, and output.

Here, the LDPC code used in the transmission system of FIG. 7 is known to have an extremely high capability in the AWGN (Additive White Gaussian Noise) communication channel.

However, in the communication channel 13 of the ground wave or the like, a burst error or erasure may occur. For example, in an OFDM (Orthogonal Frequency Division Multiplexing) system, D/U (Desired to Undesired Ratio) is 0 dB (not required = echo power and required = main path) In a multipath environment with equal power, there is a delay in response to an echo (path other than the main path), and the power of a specific symbol becomes 0 (erased).

Moreover, even if it is a flutter (a delay is 0 and a communication channel with an echo of the Doppler frequency is added), a specific time is generated by the Edujl frequency when the D/U is 0 dB. The power of the entire OFDM symbol is 0 (erased).

Further, since the receiving device 12 side receives the wiring condition of the receiving unit (not shown) such as an antenna from the transmitting device 11 to the receiving device 12 or the power supply of the receiving device 12, the cluster may also occur. Make a mistake.

On the other hand, in the decoding of the LDPC code, in the row of the check matrix H, even the variable node corresponding to the code bit of the LDPC code, since the code bit associated with the LDPC code is performed as shown in the foregoing FIG. Since the variable node operation of the equation (1) is added to the received value u _0i , the accuracy of the obtained message is lowered if an error occurs in the code bit used for the variable node operation.

Then, in the decoding of the LDPC code, in the check node, since the check node operation of the equation (7) is performed by using the message obtained by the variable node connected to the check node, if the complex number is connected, When the number of check nodes of a variable node (corresponding LDPC code) becomes an error (including erasure), the performance of decoding deteriorates.

That is, for example, if the check node is connected to the variable node of the check node and becomes more than two erased at the same time, the correctness rate of the value 0 and the accuracy of 1 are returned to all the variable nodes. In this case, the check node that sends back the information of the equal rate does not contribute to the decoding process (the variable node operation and the check node operation of the 1 set). As a result, the number of repetitions of the decoding process is required, and the decoding is performed. The performance is deteriorated. Further, the power consumption of the receiving device 12 that performs decoding of the LDPC code increases.

Therefore, in the transmission system of Fig. 7, it is desirable to maintain the performance of the AWGN communication channel while improving the tolerance to burst errors or erasure.

Fig. 8 is a view showing an example of the configuration of the transmitting device 11 of Fig. 7.

In FIG. 8, the transmitting apparatus 11 is composed of an LDPC encoding unit 21, a bit interleaver 22, a mapping unit 26, and a quadrature modulation unit 27.

The target data is supplied to the LDPC encoding unit 21.

The LDPC encoding unit 21 performs LDPC encoding on the target data supplied to the location, corresponding to the parity bit of the LDPC code, that is, the check matrix in which the parity matrix is a ladder structure, and outputs the LDPC code which uses the target data as the information bit. .

In other words, the LDPC encoding unit 21 performs an LDPC code in which the target data is encoded into an LDPC code defined by, for example, the specifications of DVB-S.2 or DVB-T.2, and outputs the LDPC code obtained as a result.

Here, the specification of DVB-T.2 is intended to adopt the LDPC code specified in the specification of DVB-S.2. The LDPC code defined by the specification of DVB-S.2 is an IRA (Irregular Repeat Accumulate) code, and the parity matrix of the check matrix of the LDPC code becomes a ladder structure. The parity matrix and the step structure will be described later. Further, the IRA code system is described, for example, in "Irregular Repeat-Accumulate Codes", H. Jin, A. Khandekar, and RJ McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp 1-8, Sept. 2000.

The LDPC code output from the LDPC encoding unit 21 is supplied to the bit interleaver 22.

The bit interleaver 22 is a data processing device for interleaving data, and is composed of a parity interleaver 23, a column twist interleaver 24, and a demultiplexer (DEMUX) 25.

The parity interleaver 23 performs co-located interleaving, interleaving the parity bits of the LDPC code from the LDPC encoding section 21 to the positions of the other parity bits, and supplies the parity interleaved LDPC code to the vertical twist interleaver 24.

The whirch twist interleaver 24 performs wobble interleaving for the LDPC code from the co-located interleaver 23, and supplies the LDPC code obtained by twisting the wobble to the demultiplexer 25.

In other words, the LDPC code is mapped to the mapping unit 26, which will be described later, and the code bits of two or more bits of the LDPC code are mapped to signal points representing one symbol of the quadrature modulation and transmitted.

The vertical twist interleaver 24 is not included in one symbol for the complex digital bit of the LDPC code corresponding to any one of the check matrices used in the LDPC encoding unit 21, and is relocated from the same position. The rearrangement processing of the code bits of the LDPC code of the interleaver 23 is performed, for example, by the wobble interleave described later.

The demultiplexer 25 replaces the position of the code bit of 2 or more of the LDPC code of the symbol with respect to the LDPC code from the vertical twist interleaver 24, thereby obtaining the enhanced tolerance to AWGN. LDPC code. Then, the demultiplexer 25 supplies the code bits of 2 or more of the LDPC codes obtained by the replacement processing to the mapping unit 26 as symbols.

The mapping unit 26 maps the symbols from the demultiplexer 25 to the respective signal points determined by the modulation method of the quadrature modulation (multi-value modulation) by the orthogonal modulation unit 27.

That is, the mapping unit 26 maps the LDPC code from the demultiplexer 25 to an IQ plane defined by the I axis representing the I component in phase with the carrier and the Q axis representing the Q component orthogonal to the carrier. The signal point determined by modulation in the (IQ constellation).

Here, as a modulation method of the quadrature modulation performed by the quadrature modulation unit 27, there is, for example, a modulation method including a modulation method defined by a specification of DVB-T, that is, for example, QPSK (Quadrature Phase Shift Keying) : Quadrature phase key shift) or 16QAM (Quadrature Amplitude Modulation), 64QAM, 256QAM, 1024QAM, 4096QAM, etc. The quadrature modulation unit 27 preliminarily sets the orthogonal modulation by a certain modulation method in accordance with, for example, the operation of the operator of the transmission device 11. Further, in the quadrature modulation unit 27, for example, 4PAM (Pulse Amplitude Modulation) and other orthogonal modulation can be performed.

The symbols mapped to the signal points by the mapping unit 26 are supplied to the orthogonal modulation unit 27.

The quadrature modulation unit 27 performs orthogonal modulation of the carrier in accordance with a signal point (a symbol mapped to the signal point) from the mapping unit 26, and the resulting modulated signal is transmitted via the communication channel 13 (FIG. 7). )send.

Next, Fig. 9 shows an inspection matrix H for LDPC encoding by the LDPC encoding unit 21 of Fig. 8.

The check matrix H is an LDGM (Low-Density Generation Matrix) structure, and may be an information matrix H _A corresponding to a portion of the information bit in the code bit of the LDPC code, and a co-located corresponding to the parity bit The matrix H _T is expressed as the equation H=[H _A |H _T ] (the elements of the information matrix H _A are set to the left side element, and the elements of the parity matrix H _T are set to the matrix of the right side element).

Here, the number of bits of the information bit and the number of bits of the parity bit in the code bit of one LDPC code (1 code word) are called the information length K and the co-located length M, respectively, and one LDPC code. The number of bits of the code bit is called the code length N (= K + M).

The information length K and the co-located length M of the LDPC code of a code length N are determined by the coding rate. Moreover, the matrix of the matrix H series × behavior M × N is checked. Then, the information matrix H _A is a matrix of M×K, and the parity matrix H _T is a matrix of M×M.

Figure 10 is a diagram showing the parity matrix H _T of the check matrix H of the LDPC code defined by the specifications of DVB-S.2 (and DVB-T.2).

As shown in FIG. 10, the parity matrix H _T of the inspection matrix H of the LDPC code defined by the specification of DVB-S.2 is a step structure in which a factor of 1 is arranged in a so-called step shape. The column weight of the parity matrix H _T is 1 for the first column and 2 for the remaining columns. Moreover, the row weight is 1 for the last row and the remaining behavior is 2.

As described above, the LDPC code in which the parity matrix H _T is the check matrix H of the step structure can be easily generated by the inspection matrix H.

That is, the LDPC code (1 codeword) is represented by the column vector c, and the row vector obtained by transposing the column vector is represented as c ^T . Moreover, the column vector A represents the portion of the information bit in the column vector c of the LDPC code, and the column vector T represents the portion of the parity bit.

Here, in this case, the column vector c can be used as the column vector A of the information bit and the column vector T as the parity bit, with the formula c=[A|T] (the elements of the column vector A are set to the left side) The element, the element of the column vector T is set as the column vector of the right element).

Check matrix H and as an LDPC code of the column vector c = [A | T] must meet the formula Hc ^T = 0, as a constituent in line with the formula Hc ^T = 0 of the column vector c = [A | T] The nibble of the same column vector T, Keji since check matrix _{H = [H A | H T} ] of the parity matrix H _T become as shown in FIG. 10 the case of a stepped structure, the formula Hc ^T = 0 of the row vector Hc ^T 1 of the first The elements are sequentially obtained by sequentially making the elements of each column zero.

Figure 11 is a diagram showing the check matrix H and row weight of the LDPC code specified by the specifications of DVB-S.2 (and DVB-T.2).

That is, Fig. 11A shows the inspection matrix H of the LDPC code defined by the specifications of DVB-S.2.

Separately, regarding the check matrix H from the KX row of the first row, the row weight is X, and for the subsequent K3 row, the row weight is 3, and for the subsequent M-1 row, the row weight is 2, regarding the last 1 Line, the row weight is 1.

Here, KX+K3+M-1+1 is equal to the code length N.

In the specification of DVB-S.2, the number of lines KX, K3, and M (colocated length), and the row weight X are defined as shown in Fig. 11B.

That is, FIG. 11B shows the line numbers KX, K3, and M of the respective coding rates of the LDPC code prescribed by the specifications of DVB-S.2, and the row weight X.

In the specification of DVB-S.2, there are LDPC codes of 64800 bits and 16200 bits of code length N.

Then, as shown in FIG. 11B, with respect to the LDPC code having a code length N of 64,800 bits, 11 encoding rates (nominal rate) of 1/4, 1/3, 2/5, 1/2 are specified. 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, for an LDPC code with a code length N of 16,200 bits, 10 encoding rates of 1/4 are specified. 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6 and 8/9.

Regarding the LDPC code, it is known that the code bit corresponding to the row having the larger weight of the check matrix H has a lower error rate.

The inspection matrix H defined by the specification of DVB-S.2 shown in FIG. 11 has a larger row weight tendency as the row on the head side (left side), so the LDPC code corresponding to the inspection matrix H is more It is the beginning of the code bit, the stronger the error (tolerance to the error), the more the last bit of the code bit, the weaker the tendency toward error.

Next, Fig. 12 shows an arrangement on the IQ plane of 16 symbols (corresponding signal points) in the case where 16QAM is performed by the quadrature modulation unit 27 of Fig. 8.

That is, Fig. 12A shows the symbol of 16QAM.

In 16QAM, 1 symbol represents 4 bits, and there are 16 (= 2 ⁴ ) symbols. Then, the 16 symbols are arranged around the origin of the IQ plane, and are arranged in a square shape of 4 × 4 in the I direction × Q direction.

Now, if the bit string represented by the 1 symbol is counted from the highest order bit as the bit of the i+1th bit is represented as the bit y _i , then the 4 bit represented by the 1 symbol of 16QAM is The highest order bits can be represented as bits y ₀ , y ₁ , y ₂ , y _{3 in order} . In the case where the modulation method is 16QAM, the 4 bits of the code bit of the LDPC code are taken as (symbolized) symbols (symbol values) of 4 bits y ₀ to y ₃ .

Fig. 12B shows the bit boundary of the 4-bit (hereinafter also referred to as symbol bit) y ₀ to y ₃ respectively expressed with respect to the symbol of 16QAM.

Here, the bit boundary of the symbol bit y _i (i=0, 1, 2, 3 in FIG. 12) means that the symbol bit y _i becomes a symbol of 0 and a symbol of 1 Boundary.

As shown in FIG. 12B, with respect to the highest-order symbol bit y ₀ of the 4-symbol bits y ₀ to y ₃ represented by the symbol of 16QAM, only one of the Q-axis of the IQ plane becomes a bit boundary. on the second (from the highest-order bit of two) the symbol bit y _1, only the I-axis of the plane of the IQ become a bit line.

Further, regarding the third symbol bit y ₂ , _two of the 4 × 4 symbols from the left to the first line and the second line, and two points between the third line and the fourth line become the bit boundary.

Further, regarding the fourth symbol bit y ₃ , 4 × 4 symbols are counted from the top of the first column and the second column, and between the third column and the fourth column. Yuanjie line.

The symbolic element y _i represented by the symbol is more away from the bit boundary, the more difficult it is to make mistakes (low error rate), the more symbols near the boundary of the bit, the more error-prone (high error rate) .

Now, if the bit that is not easy to make mistakes (the strength of the error) is called the "strong bit", and the bit that is easy to make mistakes (for the weak side of the error) is called the "weak bit", then the 4 symbol of the symbol of 16QAM The meta-bit y ₀ to y ₃ , the highest-order symbol y ₀ and the second-character y ₁ become strong bits, the third symbol y ₂ and the fourth symbol bit y ₃ becomes a weak bit.

13 to 15 show the arrangement on the IQ plane of 64 symbols (corresponding signal points) in the case where 64QAM is performed by the quadrature modulation unit 27 of Fig. 8.

In 64QAM, 1 symbol represents 6 bits, and there are 64 (= 2 ⁶ ) symbols. Then, 64 symbols are arranged around the origin of the IQ plane, and are arranged in a square shape of 8 × 8 in the I direction × Q direction.

The symbolic unit of the symbol of 64QAM is the highest order bit, which can be expressed as bits y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ . In the case where the modulation mode is 64QAM, the 6-bit code bit of the LDPC code is used as the symbol of the 6-bit symbol bit y ₀ to y ₅ .

Here, FIG. 13 shows the bit boundary of the highest bit symbol y ₀ and the second symbol bit y ₁ of the symbol bits y ₀ to y ₅ of the symbol of 64QAM, respectively; 14 shows the bit boundaries for the third symbol bit y ₂ and the fourth symbol bit y ₃ respectively; FIG. 15 shows the fifth symbol bit y ₄ and the sixth symbol, respectively. The bit boundary of the bit y ₅ .

As shown in FIG. 13, the bit boundary of the highest-order symbol bit y ₀ and the second symbol bit y ₁ is one. Moreover, as shown in FIG. 14, the bit boundaries for the third symbol bit y ₂ and the fourth symbol bit y ₃ are respectively two; as shown in FIG. 15, respectively, regarding the fifth symbol The bit boundary of the bit y ₄ and the sixth symbol bit y ₅ is four.

Therefore, with respect to the symbol bits y ₀ to y ₅ of the symbol of 64QAM, the highest-order symbol y ₀ and the second symbol y ₁ become strong bits, and the third symbol y ₂ And the fourth symbol bit y ₃ becomes the second strongest bit. Then, the fifth symbol bit y ₄ and the sixth symbol bit y ₅ become weak bits.

From Fig. 12, it can be further seen from Fig. 13 to Fig. 15 that with respect to the symbol bit of the symbol of the quadrature modulation, there is a tendency that the high order bit becomes a strong bit and the low order bit becomes a weak bit.

Here, as illustrated in FIG. 11, regarding the LDPC code outputted by the LDPC encoding section 21 (FIG. 8), there are code bits which are strong against errors and code bits which are weak to error.

Further, as illustrated in FIGS. 12 to 15, the symbol bits of the symbols of the orthogonal modulation performed by the quadrature modulation unit 27 have strong bits and weak bits.

Therefore, if the error bit of the LDPC code is assigned to the weak symbol bit of the quadrature modulated symbol, the tolerance to the error as a whole is lowered.

Therefore, an interleaver is proposed which interleaves the code bits of the LDPC code by assigning the error bit of the LDPC code to the strong bit (symbol bit) of the quadrature modulated symbol. yuan.

The multiplexer 25 of Figure 8 can perform the processing of the interleaver.

Figure 16 is a diagram for explaining the processing of the multiplexer 25 of Figure 8.

That is, Fig. 16A shows an example of the functional configuration of the demultiplexer 25.

The multiplexer 25 is composed of a memory 31 and a replacement unit 32.

The LDPC code from the LDPC encoding unit 21 is supplied to the memory 31.

The memory 31 contains memory mb bits in the row (horizontal) direction, and memorizes the memory capacity of the N/(mb) bits in the column (longitudinal) direction, and is supplied to the LDPC there. The code bit of the code is written in the wale direction, read out in the course direction, and supplied to the replacement unit 32.

Here, N (= information length K + co-located length M) is the code length of the LDPC code as described above.

Further, m denotes the number of bits of the code bit which becomes the 1-element LDPC code; b is a specific positive integer which is used to make m a multiple of an integral multiple. As described above, the demultiplexer 25 sets the code bits of the LDPC code as symbols (symbols), and the multiple b indicates the number of symbols obtained by the demultiplexer 25 by the so-called one-time symbolization.

16A shows an example of the configuration of the demultiplexer 25 in the case where the modulation method is 64QAM. Therefore, the number of bits m of the code bit which becomes the 1-element LDPC code is 6 bits.

Further, in Fig. 16A, since the multiple b is 1, the memory 31 has a memory capacity in which the wale direction × the course direction is N/(6 × 1) × (6 × 1) bits.

Here, the course direction of the memory 31 is a 1-bit memory area extending in the wale direction, and is hereinafter referred to as a wales as appropriate. In Fig. 16A, the memory 31 is composed of 6 (= 6 × 1) wales.

In the demultiplexer 25, the code bits of the LDPC code are written from the top to the bottom (the wale direction) in the vertical direction of the memory 31, from the left to the right.

Then, if the code bit is written to the bottom of the rightmost vertical line, the first column of all the wales constituting the memory 31 is read out in units of 6 bits (mb bits) in the course direction. The code bit is supplied to the replacement unit 32.

The replacing unit 32 performs a replacement process of replacing the position of the 6-bit code bit from the memory 31, and the resulting 6-bit element is used as the 6-symbol bit y ₀ , y representing the symbol of 64QAM. ₁ , y ₂ , y ₃ , y ₄ , y ₅ and output.

That is, from the memory 31, the code bits of the mb bits (here, 6 bits) are read in the course direction, and if the code bits of the mb bits read from the memory 31 are from the highest order The i-th bit (i=0,1,‧‧‧, mb-1) from the bit is represented as the bit b _i , and the 6-bit code position read from the memory 31 in the course direction The meta-system is represented by the highest-order bits, which can be sequentially expressed as bits b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ .

With the relationship of the row weights illustrated in Fig. 11, the code bit in the direction of the bit b ₀ becomes the code bit of the error strong, and the code bit in the direction of the bit b ₅ becomes the code of the error weak. Bit.

In the replacing unit 32, in order to make the code bits of the 6-bit code bits b ₀ to b ₅ from the memory 31 to the error weak, assign the symbol bits y ₀ to y ₅ of the 1 symbol of 64QAM. In the strong bit, a replacement process for replacing the position of the 6-bit code bits b ₀ to b ₅ from the memory 31 can be performed.

Here, as an alternative to how to replace the 6-bit code bits b ₀ to b ₅ from the memory 31 and assign them to the 6-symbol bits y ₀ to y ₅ representing the 1 symbol of 64QAM, There are various ways to propose from various companies.

16B shows a first alternative, FIG. 16C shows a second alternative, and FIG. 16D shows a third alternative.

16B to 16D (the same applies to FIG. 17 described later), the line segment connecting the bits b _i and y _j means that the code bit b _{i is} assigned to the symbol bit y _j of the symbol (replaced to the symbol) The position of the bit y _j ).

As a first alternative, any one of the alternatives of the three types of FIG. 16B is adopted, and as an alternative to the second alternative, any of the alternatives of the type of FIG. 16C is adopted.

As an alternative to the third alternative, the alternative of the six types of FIG. 16D is sequentially selected.

17 is a diagram showing the multiplexing in the case where the modulation method is 64QAM (hence, the number of bits m of the code bit mapped to the 1-element LDPC code is 6 bits as in FIG. 16) and the multiple b is 2. The configuration example of the device 25 and the fourth alternative.

When the multiple b is 2, the memory 31 has a memory capacity in which the wale direction × the course direction is N/(6 × 2) × (6 × 2) bits, and 12 (= 6 × 2) vertical The composition of the line.

Fig. 17A shows the writing order of the LDPC code to the memory 31.

In the demultiplexer 25, as illustrated in FIG. 16, the code bits of the LDPC code are written in the vertical direction from the top to the bottom (the wale direction) in the vertical direction of the memory 31. .

Then, if the code bit is written to the bottom of the rightmost vertical line, the first column of all the wales constituting the memory 31 is read out in units of 12 bits (mb bits) in the course direction. The code bit is supplied to the replacement unit 32.

The replacing unit 32 performs a replacement process of replacing the position of the code bit from the 12-bit memory of the memory 31 with the fourth alternative, and the 12-bit obtained as a result is used as the 2-symbol representing 64QAM ( 12 bits of b symbols, that is, 6 symbolic elements y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ representing the 1 symbol of 64QAM and indicating the next symbol The 6-symbol bits y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ are output.

Here, FIG. 17B shows a fourth alternative of the replacement process performed by the replacement unit 32 of FIG. 17A.

Further, in the case where the multiple b is 2 (the same applies to the case of 3 or more), in the replacement processing, the code bits of the mb bits are allocated to the symbol bits of the mb bits of the consecutive b symbols. Including the FIG. 17, the i+1th bit from the highest order bit of the mb bits of the consecutive b symbols is represented as a bit (symbol bit) for convenience of explanation. y _i .

Moreover, what kind of replacement method is appropriate, that is, how to improve the error rate in the AWGN communication channel is different according to the coding rate or code length and modulation mode of the LDPC code.

Next, the co-interleaving by the parity interleaver 23 of Fig. 8 will be explained with reference to Figs. 18 to 20 .

Fig. 18 is a Tanner diagram (part) showing a check matrix of an LDPC code.

If the check node is as shown in FIG. 18, two or more of the variable nodes (corresponding code bits) connected to the check node are simultaneously erased and the like, and the pair is connected to the check node. For all variable nodes, the message returns the value of 0 and the accuracy of 1 is the same as the rate of accuracy. Therefore, if the complex variable nodes connected to the same check node are erased at the same time, the decoding performance is degraded.

However, the LDPC code defined by the specification of DVB-S.2 outputted by the LDPC encoding unit 21 of Fig. 8 is an IRA code, and the parity matrix H _T of the inspection matrix H has a stepped structure as shown in Fig. 10 .

Fig. 19 is a view showing a parity matrix H _{T which} is a stepped structure and a Tanner graph corresponding to the parity matrix H _T .

That is, Fig. 19A shows a parity matrix H _{T which} is a step structure; Fig. 19B shows a Tanner graph corresponding to the parity matrix H _T of Fig. 19A.

Parity matrix H _T be the case where the stepped configuration of, in the parity matrix H _T of the Tanner graph, with the corresponding LDPC code is to the same bit matrix adjacent code bit line of the elements of it. 1 H _T of values (parity bits) The variable nodes that find the message are connected to the same check node.

Therefore, if the adjacent parity bit becomes an error at the same time due to a cluster error or erasure, etc., it is connected to a complex variable node corresponding to the complex parity bit that becomes the error (using the parity bit to obtain a message) The check node of the variable node sends a message with a value of 0 and a rate of accuracy of 1 to the variable node connected to the check node, so the decoding performance is degraded. Then, when the length of the cluster (the number of bits that become the error due to the burst) is very large, the decoding performance is further deteriorated.

Therefore, the parity interleaver 23 (FIG. 8) performs the co-interleaving in which the parity bits of the LDPC code from the LDPC encoding unit 21 are interleaved to the positions of the other parity bits in order to prevent deterioration of the above decoding performance.

Figure 20 is a diagram showing the parity matrix H _T of the check matrix H of the LDPC code corresponding to the co-interleave 23 of the co-located interleaver 23 of Figure 8 .

Here, the information matrix H _A of the inspection matrix H corresponding to the LDPC code defined by the specification of DVB-S.2, which is output by the LDPC encoding unit 21, is a tour structure.

The tour structure refers to a structure in which a row is consistent with other rows after cyclic shift (rotation), and includes, for example, every P row, the position of each of the columns of the P row is the initial row of the P row, only A value proportional to the value q obtained by subtracting the same length M, and a position at which the position is cyclically shifted in the row direction. Hereinafter, the P row of the tour structure is appropriately referred to as the number of rows of the tour structure.

As shown in FIG. 11, the LDPC code defined by the specification of DVB-S.2 outputted by the LDPC encoding unit 21 has two types of LDPC codes of a code length N of 64,800 bits and 16,200 bits.

Now, if attention is paid to an LDPC code in which the code length N of the two types of LDPC codes of 64800 bits and 16200 bits is 64800 bits, the code length N is a coding rate of the LDPC code of 64800 bits. There are 11 as illustrated in FIG.

Regarding the 11 LDPC codes whose code length N is 64800 bits, respectively, in either of the specifications of DVB-S.2, the number of rows P of the unit of the tour structure is the divisor of the same length M. 360 of one of the divisors except 1 and M.

Further, regarding the LDPC codes in which the code length N of each of the 11 coding rates is 64,800 bits, the co-located length M is a prime value expressed by the formula M = q × P = q × 360 by using a value q different depending on the coding rate. A value other than that. Therefore, the value q is also the same as the number of rows P of the unit of the patency structure, and the other one of the divisors of the unit of the same length, M, and the number of the number of lines P of the unit of the tour structure is divided by the number of lines P of the unit of the tour structure. Obtain (the product of P and q of the divisor length M is the same bit length M).

As described above, the co-located interleaver 23 sets the information length to K, and sets an integer of 0 or more and less than P to x, and sets an integer of 0 or more and less than q to y. The K+qx+y+1 code bits in the same bit of the K+1 to K+M (=N) code bits of the LDPC code of the encoding unit 21 are interleaved to the K+Py+x +1 location of the code bit.

According to the co-located interleaving, since the variable nodes (corresponding co-located bits) connected to the same check node are only separated by the number of rows P of the unit of the tour structure, that is, only 360 bits apart, When the length is less than 360 bits, a plurality of variable nodes connected to the same check node can be prevented from becoming an error at the same time, and the result is improved tolerance to burst errors.

In addition, the LDPC code of the same bit interleaved with the K+qx+y+1 code bits interleaved to the position of the K+Py+x+1 code bits is performed with the original check matrix H. The +qx+y+1 row is replaced by the LDPC code of the check matrix (hereinafter also referred to as the conversion check matrix) obtained by the row replacement of the K+Py+x+1 row.

Moreover, in the parity matrix of the conversion check matrix, as shown in Fig. 20, a pseudo-tour structure in which P rows (360 rows in Fig. 20) are used as a unit appears.

Here, the pseudo-tour structure means that a part of the structure is a structure of the tour structure. For the check matrix of the LDPC code specified in the specification of DVB-S.2, the conversion check matrix obtained by the row replacement corresponding to the co-interlace is part of 360 columns × 360 lines in the right corner portion thereof (the shift described later) The bit matrix) is only one element of 1 (the element that becomes 0), so it is a non-(complete) tour structure and becomes a pseudo-tour structure.

Further, the conversion check matrix of FIG. 20 is a replacement (column replacement) for the original check matrix H, in addition to the row replacement corresponding to the co-interleaving, and the column for forming the matrix to be described later in the conversion check matrix. The matrix after.

Next, the whirling twist interleaving as the rearrangement processing by the whirling twist interleaver 24 of Fig. 8 will be described with reference to Figs. 21 to 24 .

In the transmission device 11 of FIG. 8, in order to increase the frequency utilization efficiency, two bits or more of the code bits of the LDPC code are transmitted as one symbol as described above. In other words, for example, when two bits of the code bit are used as one symbol, the modulation method is used as a modulation when, for example, QPSK is used, and four bits of the code bit are used as one symbol. The method utilizes, for example, 16QAM.

In this case, when two or more bits of the code bit are transmitted as one symbol, if the symbol is erased or the like, the symbol bits of the symbol (assigned to the symbol bit) are all errors. (erased).

Therefore, in order to improve the decoding performance, the plurality of variable nodes (corresponding code bits) connected to the same check node are reduced to become the erasure accuracy, and the code bit corresponding to one symbol must be avoided. The variable nodes are connected to the same check node.

On the other hand, as described above, inspection of the LDPC code prescribed in the output 21 of the DVB-S.2 LDPC encoding unit size of the matrix H, the information matrix H _A circuit configuration comprising, parity matrix H _T comprises a stepped configuration. Then, as illustrated in FIG. 20, the check matrix of the LDPC code after the co-interleave is the conversion check matrix, and the tour structure also appears in the parity matrix (correctly, as described above, the pseudo-tour structure).

Figure 21 shows a conversion check matrix.

That is, Fig. 21A shows a conversion check matrix of the check matrix H of the LDPC code having a code length N of 64,800 bits and a coding rate (r) of 3/4.

In Fig. 21A, in the conversion check matrix, the position of the element having a value of 1 is indicated by a dot (‧).

Fig. 21B shows the processing performed by the demultiplexer 25 (Fig. 8) with the LDPC code of the conversion check matrix of Fig. 21A, that is, the LDPC code of the co-located interleaving.

In Fig. 21B, the modulation method is set to 16QAM, and in the four vertical lines of the memory 31 constituting the demultiplexer 25, the code bits of the LDPC code which are co-interleaved are written in the wale direction.

In the four vertical lines constituting the memory 31, the code bits written in the wale direction are in the course direction, and are read in units of 4 bits to become one symbol.

In this case, the code bits B ₀ , B ₁ , B ₂ , B ₃ which become the 4-bits of the 1 symbol may become the code bits corresponding to 1 of any one of the columns of the conversion check matrix of FIG. 21A. In this case, the variable nodes respectively corresponding to the code bit B ₀ , B ₁ , B ₂ , B ₃ are connected to the same check node.

Therefore, in the case where the code bits B ₀ , B ₁ , B ₂ , and B ₃ of the 4-bit symbol of 1 symbol correspond to the code bit located in any one of the columns of the conversion check matrix, if the symbol If the element is erased, the same check node connected to the variable nodes corresponding to the code bits B ₀ , B ₁ , B ₂ , and B ₃ respectively cannot obtain an appropriate message, and as a result, the decoding performance deteriorates. .

Regarding the coding rate other than the coding rate of 3/4, the complex digital bit corresponding to the complex variable node connected to the same check node may also be used as one symbol of 16QAM.

Therefore, the whirling torsion interleaver 24 performs the interleaving and wobble interleaving of the code bits of the LDPC code interleaved from the co-located interleaver 23 so as to correspond to any one of the columns of the conversion check matrix. The complex digital bit is not included in one symbol.

Fig. 22 is a view showing the longitudinal twisting and interlacing.

That is, Fig. 22 shows the memory 31 of the multiplexer 25 (Figs. 16 and 17).

As shown in FIG. 16, the memory 31 has a memory capacity of mb bits in the vertical (longitudinal) direction and a memory capacity of N/(mb) bits in the horizontal (horizontal) direction, and is composed of mb vertical lines. . Then, the whirling twist interleaver 24 controls the memory 31 to perform the wagger interleaving by controlling the start of the write position when the code bits of the LDPC code are written in the wale direction and read in the course direction.

That is, in the vertical twist interleaver 24, the start write position of the start code bit is appropriately changed for the plurality of wales, so that the complex digital bit as the 1-symbol read in the course direction is read. , does not become corresponding to the code bit located in any one of the columns of the conversion check matrix (rearrangement of the code bits of the LDPC code, so that the complex digital bit corresponding to 1 of any one of the columns in the check matrix does not contain In the same symbol).

Here, FIG. 22 shows an example of the configuration of the memory 31 in the case where the modulation method is 16QAM and the multiple b described in FIG. 16 is 1. Therefore, the number of bits m of the code bit as the 1-symbol LDPC code is 4 bits, and the memory 31 is composed of 4 (= mb) wales.

The whirling torsion interleaver 24 (instead of the demultiplexer 25 of FIG. 16) is a wales from the left to the right direction, and the code bits of the LDPC code are moved from the top to the bottom of the four wales constituting the memory 31. (Writing direction) Write.

Then, if the writing of the code bit to the rightmost vertical line ends, the vertical twisting interleaver 24 is from the first column of all the wales constituting the memory 31, and is 4 bits in the horizontal direction (mb bits) The unit reads the code bit and outputs the LDPC code which is twisted and interleaved as a wales to the replacement unit 32 of the demultiplexer 25 (Figs. 16 and 17).

In the vertical twist interleaver 24, if the address of the position of the beginning (topmost) of each wales is set to 0, and the address of each position of the waling direction is represented by an integer in ascending order, then the leftmost vertical position is In the line, the write start position is set to the position where the address is 0. With respect to the (2nd vertical) (2nd vertical line), the start write position is set to the position where the address is 2, and regarding the 3rd vertical line, the write start position is set as The address is at the position of 4, and regarding the 4th rowth, the write position is set to the position where the address is 7.

In addition, regarding the trajectory where the start write position is a position other than the position where the address is 0, the code bit is written to the lowermost position, and the start is returned (the address is 0), and the write position is started immediately. Write to the previous position. Then, the writing from the next (right) wales is performed thereafter.

By performing the wobble interleaving as described above, the LDPC code of all coding rates with a code length N specified by the specification of DVB-S.2 of 64800 can avoid the complex variable nodes corresponding to the same check node. The complex digital bit is used as a symbol of 16QAM (contained in the same symbol), and the decoding performance of the erased communication channel can be improved.

23 is an LDPC code for 11 encoding rates of a code length N of 64800 specified by the specification of DVB-S.2, and the number of wales of the memory 31 necessary for the wobble interleaving according to each modulation mode and Start writing the address of the location.

Since the multiple b is 1, and QPSK is used as the modulation method, when the number m of the 1-bit is 2 bits, according to FIG. 23, the memory 31 contains 2 × 1 in the course direction. (= mb) 2 wales of bits, memory 64800 / (2 × 1) bits in the wales.

Then, in the two wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 2.

In addition, when the replacement of the demultiplexer 25 (FIG. 8) is used as an alternative to the first to third alternatives of FIG. 16, the multiple b becomes 1.

Since the multiple b is 2, and QPSK is used as the modulation method, for example, when the number m of the 1-bit is 2 bits, according to FIG. 23, the memory 31 contains 2×2 in the course direction. The four vertical lines of the bit store 64800/(2×2) bits in the wale direction.

Then, among the four wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address 2, the third vertical The start write position of the line is set to the position where the address is 4, and the start write position of the fourth vertical line is set to the position where the address is 7.

In addition, when the fourth alternative of FIG. 17 is used as an alternative to the replacement processing of the demultiplexer 25 (FIG. 8), the multiple b becomes 2.

Since the multiple b is 1, and the modulation method is, for example, 16QAM, when the number m of the 1-bit is 4 bits, according to FIG. 23, the memory 31 contains 4×1 in the course direction. The four vertical lines of the bit store 64800/(4×1) bits in the wale direction.

Then, among the four wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address 2, the third vertical The start write position of the line is set to the position where the address is 4, and the start write position of the fourth vertical line is set to the position where the address is 7.

Since the multiple b is 2, and the modulation method is, for example, 16QAM, if the number of bits of the 1-symbol m is 4 bits, according to FIG. 23, the memory 31 contains 4×2 in the horizontal direction. The 8 vertical lines of the bit store 64800/(4×2) bits in the wale direction.

Then, among the eight wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 0, and the third vertical The start write position of the line is set to the position where the address is 2, the start write position of the 4th vertical line is set to the position where the address is 4, and the start write position of the 5th vertical line is set to the position where the address is 4, the sixth position The start position of the wales is set to the position where the address is 5, the start write position of the 7th ordinate is set to the position of the address 7, and the start write position of the 8th ordinate is set to the position of the address 7.

Since the multiple b is 1, and the modulation method is, for example, 64QAM, if the number m of the 1-bit is 6 bits, the memory 31 is stored in the horizontal direction 6×1 according to FIG. The six vertical lines of the bit store 64800/(6×1) bits in the wale direction.

Then, among the six wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address 2, the third vertical The start write position of the line is set to the address of 5, the start write position of the 4th vertical line is set to the address of the address 9, and the start write position of the 5th vertical line is set to the position of the address of 10, the sixth The start position of the wales is set to the position of the address 13.

Since the multiple b is 2, and the modulation method is, for example, 64QAM, when the number of bits of the 1-symbol m is 6 bits, according to FIG. 23, the memory 31 is stored in the horizontal direction and is 6×2. The 12 vertical lines of the bit store 64800/(6×2) bits in the wale direction.

Then, among the 12 wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 0, and the third vertical The start write position of the line is set to the position where the address is 2, the start write position of the 4th vertical line is set to the position where the address is 2, and the start write position of the 5th vertical line is set to the position where the address is 3, the sixth position The write start position of the wales is set to the position where the address is 4, the start write position of the 7th ordinate is set to the address of 4, and the start write position of the 8th traverse is set to the position of the address of 5, The start position of the 9 wales is set to the position where the address is 5, the start write position of the 10th wales is set to the position of the address 7, and the start write position of the 11th ordinate is set to the position of the address of 8, The start write position of the 12th wales is set to the position of the address 9.

Since the multiple b is 1, and the modulation method is, for example, 256QAM, when the number m of the 1-bit is 8 bits, according to FIG. 23, the memory 31 is stored in the horizontal direction 8×1. The 8 vertical lines of the bit store 64800/(8×1) bits in the wale direction.

Then, among the eight wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 0, and the third vertical The start write position of the line is set to the position where the address is 2, the start write position of the 4th vertical line is set to the position where the address is 4, and the start write position of the 5th vertical line is set to the position where the address is 4, the sixth position The start position of the wales is set to the position where the address is 5, the start write position of the 7th ordinate is set to the position of the address 7, and the start write position of the 8th ordinate is set to the position of the address 7.

Since the multiple b is 2, and the modulation method is, for example, 256QAM, when the number m of the 1-bit is 8 bits, according to FIG. 23, the memory 31 is stored in the horizontal direction and is 8×2. The 16 vertical lines of the bit store 64800/(8×2) bits in the wale direction.

Then, among the 16 wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address 2, the third vertical The start write position of the line is set to the position where the address is 2, the start write position of the 4th vertical line is set to the position where the address is 2, and the start write position of the 5th vertical line is set to the position where the address is 2, the sixth position The write start position of the wales is set to the position where the address is 3, the start write position of the 7th ordinate is set to the position of the address 7, and the start write position of the 8th traverse is set to the position of the address of 15 The start position of the 9 wales is set to the address of 16, the write position of the 10th wales is set to the address of 20, and the write position of the 11th traverse is set to the address of 22. The start position of the 12th wales is set to the position of the address 22, the start write position of the 13th wales is set to the position of the address 27, and the start write position of the 14th waling is set to the position of the address of 27. The write position of the 15th vertical line is set to the position of the address 28, and the start write position of the 16th vertical line is set to the position of the address 32.

Since the multiple b is 1, and the modulation method is, for example, 1024QAM, when the number of bits of the 1-symbol m is 10 bits, according to FIG. 23, the memory 31 is stored in the horizontal direction to memorize 10×1. The 10 vertical lines of the bit store 64800/(10×1) bits in the wale direction.

Then, among the ten wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address of 3, the third vertical The start write position of the line is set to the address of the address 6, the start position of the fourth vertical line is set to the address of the address of 8, and the start write position of the fifth vertical line is set to the position of the address of 11, the sixth The start position of the wales is set to the address of 13, the start position of the 7th ordinate is set to the address of 15, and the write position of the 8th traverse is set to the position of the address of 17 The start position of the 9 wales is set to the position where the address is 18, and the start position of the 10th wales is set to the position where the address is 20.

Since the multiple b is 2, and the modulation method is, for example, 1024QAM, if the number of bits of the 1-symbol m is 10 bits, according to FIG. 23, the memory 31 contains 10×2 in the course direction. The 20 wales of the bit store 64800/(10×2) bits in the wale direction.

Then, among the 20 wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address of 1, the third vertical The start write position of the line is set to the position where the address is 3, the start write position of the 4th vertical line is set to the position where the address is 4, and the start write position of the 5th vertical line is set to the position where the address is 5, the sixth position The write start position of the wales is set to the position of the address 6, the start position of the seventh wales is set to the position of the address 6, and the start write position of the eighth traverse is set to the position of the address of 9, the first The start position of the 9 wales is set to the position of the address 13, the write position of the 10th wales is set to the address of 14, and the write position of the 11th traverse is set to the address of 14 The write position of the 12th wales is set to the address of 16, the start write position of the 13th traverse is set to the address of 21, and the start write position of the 14th traverse is set to the position of the address 21. The write position of the 15th vertical line is set to the address of 23, the start write position of the 16th vertical line is set to the address of 25, and the write position of the 17th vertical line is set as the address. At the position of 25, the write position of the 18th wales is set to the address of 26, the write position of the 19th traverse is set to the address of 28, and the write position of the 20th traverse is set as the address. It is the location of 30.

Since the multiple b is 1, and the modulation method is, for example, 4096QAM, when the number of bits of the one symbol is 12 bits, according to FIG. 23, the memory 31 contains 12×1 in the course direction. The 12 vertical lines of the bit store 64800/(12×1) bits in the wale direction.

Then, among the 12 wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 0, and the third vertical The start write position of the line is set to the position where the address is 2, the start write position of the 4th vertical line is set to the position where the address is 2, and the start write position of the 5th vertical line is set to the position where the address is 3, the sixth position The write start position of the wales is set to the position where the address is 4, the start write position of the 7th ordinate is set to the address of 4, and the start write position of the 8th traverse is set to the position of the address of 5, The start position of the 9 wales is set to the position where the address is 5, the start write position of the 10th wales is set to the position of the address 7, and the start write position of the 11th ordinate is set to the position of the address of 8, The start write position of the 12th wales is set to the position of the address 9.

Since the multiple b is 2, and the modulation method is, for example, 4096QAM, when the number m of the 1-bit is 12 bits, according to FIG. 23, the memory 31 contains 12×2 in the course direction. The 24 vertical lines of the bit store 64800/(12×2) bits in the wale direction.

Then, among the 24 wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address of 5, the third vertical The start write position of the line is set to the address of the address 8, the start position of the fourth vertical line is set to the address of the address of 8, and the start write position of the fifth vertical line is set to the position of the address of 8, the sixth The start position of the wales is set to the address of 8, the start position of the 7th ordinate is set to the address of 10, and the write position of the 8th traverse is set to the address of 10, The start position of the 9 wales is set to the position where the address is 10, the start write position of the 10th wales is set to the address of 12, and the start write position of the 11th ordinate is set to the position of the address 13. The write position of the 12th wales is set to the address of 16, the start write position of the 13th traverse is set to the address of the address 17, and the start write position of the 14th traverse is set to the position of the address of 19. The write position of the 15th vertical line is set to the position where the address is 21, the start write position of the 16th vertical line is set to the position where the address is 22, and the start write position of the 17th vertical line is set as the address. For the position of 23, the write position of the 18th wales is set to the position of the address 26, the start write position of the 19th traverse is set to the position of the address 37, and the write position of the 20th ordinate is set as the position. The address is 39, the start position of the 21st rowth is set to the address of 40, the start position of the 22nd traverse is set to the address of 41, and the write position of the 23rd wal is set as the start position. The address is at the position of 41, and the start position of the 24th rowth is set to the position where the address is 41.

Fig. 24 is an LDPC code for 10 coding rates of a code length N of 16200, which is defined by the specification of DVB-S.2, and shows the number of wales of the memory 31 necessary for the wobble interleaving according to each modulation mode. Start writing the address of the location.

Since the multiple b is 1, and QPSK is used as the modulation method, when the number m of the 1-bit is 2 bits, according to FIG. 24, the memory 31 contains 2 × 1 in the course direction. Two vertical lines of bits store 16200/(2×1) bits in the wale direction.

Then, in the two wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 0.

Since the multiple b is 2, and QPSK is used as the modulation method, for example, when the number of bits m of one symbol is two bits, according to FIG. 24, the memory 31 is stored in the horizontal direction and is 2×2. The four vertical lines of the bit store 16200/(2×2) bits in the wale direction.

Then, among the four wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address 2, the third vertical The start write position of the line is set to the position where the address is 3, and the start write position of the 4th vertical line is set to the position where the address is 3.

Since the multiple b is 1, and the modulation method is, for example, 16QAM, when the number m of the 1-bit is 4 bits, according to FIG. 24, the memory 31 is stored in the horizontal direction by 4×1. The four vertical lines of the bit store 16200/(4×1) bits in the wale direction.

Then, among the four wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address 2, the third vertical The start write position of the line is set to the position where the address is 3, and the start write position of the 4th vertical line is set to the position where the address is 3.

Since the multiple b is 2, and the modulation method is, for example, 16QAM, when the number of bits of the 1-symbol m is 4 bits, according to FIG. 24, the memory 31 is stored in the horizontal direction to store 4×2. The eight vertical lines of the bit store 16200/(4×2) bits in the wale direction.

Then, among the eight wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 0, and the third vertical The start write position of the line is set to the position where the address is 0, the start write position of the fourth vertical line is set to the position where the address is 1, and the start write position of the fifth vertical line is set to the position of the address of 7, the sixth The start position of the wales is set to the position where the address is 20, the start write position of the seventh wales is set to the address of 20, and the start write position of the eighth traverse is set to the position of the address 21.

Since the multiple b is 1, and the modulation method is, for example, 64QAM, if the number m of the 1-bit is 6 bits, the memory 31 is stored in the horizontal direction according to FIG. The six vertical lines of the bit store 16200/(6×1) bits in the wale direction.

Then, among the six wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 0, and the third vertical The start write position of the line is set to the position where the address is 2, the start write position of the 4th vertical line is set to the position where the address is 3, and the start write position of the 5th vertical line is set to the position of the address of 7, the sixth The start position of the wales is set to the position where the address is 7.

Since the multiple b is 2, and the modulation method is, for example, 64QAM, when the number of bits of the 1-symbol m is 6 bits, according to FIG. 24, the memory 31 is stored in the horizontal direction and is 6×2. The 12 vertical lines of the bit store 16200/(6×2) bits in the wale direction.

Then, among the 12 wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 0, and the third vertical The start write position of the line is set to the position where the address is 0, the start write position of the 4th vertical line is set to the position where the address is 2, and the start write position of the 5th vertical line is set to the position where the address is 2, the sixth position The write start position of the wales is set to the position where the address is 2, the start write position of the 7th wales is set to the position where the address is 3, and the start write position of the 8th ordinate is set to the position where the address is 3, The start position of the 9 wales is set to the position where the address is 3, the start write position of the 10th wales is set to the position of the address 6, and the start write position of the 11th ordinate is set to the position of the address of 7. The start write position of the 12th wales is set to the position where the address is 7.

Since the multiple b is 1, and the modulation method is, for example, 256QAM, when the number of bits of the one symbol is 8 bits, according to FIG. 24, the memory 31 is stored in the horizontal direction and is 8×1. The eight vertical lines of the bit store 16200/(8×1) bits in the wale direction.

Then, among the eight wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 0, and the third vertical The start write position of the line is set to the position where the address is 0, the start write position of the fourth vertical line is set to the position where the address is 1, and the start write position of the fifth vertical line is set to the position of the address of 7, the sixth The start position of the wales is set to the position where the address is 20, the start write position of the seventh wales is set to the address of 20, and the start write position of the eighth traverse is set to the position of the address 21.

Since the multiple b is 1, and the modulation method is, for example, 1024QAM, when the number m of the 1-bit is 10 bits, according to FIG. 24, the memory 31 contains 10×1 in the course direction. The 10 vertical lines of the bit store 16200/(10×1) bits in the wale direction.

Then, among the ten wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address 1, the third vertical The start write position of the line is set to the position where the address is 2, the start write position of the 4th vertical line is set to the position where the address is 2, and the start write position of the 5th vertical line is set to the position where the address is 3, the sixth position The start position of the wales is set to the position where the address is 3, the start write position of the 7th ordinate is set to the address of 4, and the write position of the 8th traverse is set to the position of the address of 4, The start position of the 9 wales is set to the position where the address is 5, and the start write position of the 10th wales is set to the position where the address is 7.

Since the multiple b is 2, and the modulation method is, for example, 1024QAM, when the number of bits of the 1-symbol m is 10 bits, according to FIG. 24, the memory 31 contains 10×2 in the course direction. The 20 wales of the bit store 16200/(10×2) bits in the wale direction.

Then, among the 20 wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 0, and the third vertical The start write position of the line is set to the position where the address is 0, the start write position of the 4th vertical line is set to the position where the address is 2, and the start write position of the 5th vertical line is set to the position where the address is 2, the sixth position The write start position of the wales is set to the position where the address is 2, the start write position of the 7th wales is set to the position where the address is 2, and the start write position of the 8th ordinate is set to the position where the address is 2, The start position of the 9 wales is set to the position where the address is 5, the start write position of the 10th wales is set to the position where the address is 5, and the start write position of the 11th ordinate is set to the position where the address is 5. The write position of the 12th wales is set to the position where the address is 5, the start write position of the 13th wales is set to the position where the address is 5, and the start write position of the 14th traverse is set to the position of the address of 7. The write position of the 15th vertical line is set to the position where the address is 7, the start write position of the 16th vertical line is set to the position where the address is 7, and the start write position of the 17th vertical line is set to the address of 7 Bit The write position of the 18th wales is set to the address of 8, the write position of the 19th traverse is set to the address of 8, and the write position of the 20th trajectory is set to the address of 10 The location.

Since the multiple b is 1, and the modulation method is, for example, 4096QAM, if the number of bits of the 1-symbol m is 12 bits, according to FIG. 24, the memory 31 is stored in the horizontal direction to memorize 12×1. The 12 vertical lines of the bit store 16200/(12×1) bits in the wale direction.

Then, among the 12 wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 0, and the third vertical The start write position of the line is set to the position where the address is 0, the start write position of the 4th vertical line is set to the position where the address is 2, and the start write position of the 5th vertical line is set to the position where the address is 2, the sixth position The write start position of the wales is set to the position where the address is 2, the start write position of the 7th wales is set to the position where the address is 3, and the start write position of the 8th ordinate is set to the position where the address is 3, The start position of the 9 wales is set to the position where the address is 3, the start write position of the 10th wales is set to the position of the address 6, and the start write position of the 11th ordinate is set to the position of the address of 7. The start write position of the 12th wales is set to the position where the address is 7.

Since the multiple b is 2, and the modulation method is, for example, 4096QAM, when the number of bits of the 1-symbol m is 12 bits, according to FIG. 24, the memory 31 is stored in the horizontal direction to memorize 12×2. The 24 vertical lines of the bit store 16200/(12×2) bits in the wale direction.

Then, among the 24 wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 0, and the third vertical The start write position of the line is set to the position where the address is 0, the start write position of the 4th vertical line is set to the position where the address is 0, and the write position of the 5th vertical line is set to the position where the address is 0, the sixth position The write start position of the wales is set to the position where the address is 0, the start write position of the 7th wales is set to the position where the address is 0, and the start write position of the 8th ordinate is set to the position where the address is 1, The start position of the 9 wales is set to the position where the address is 1, the start position of the 10th wales is set to the position where the address is 1, and the start write position of the 11th ordinate is set to the position where the address is 2. The write position of the 12th wales is set to the position where the address is 2, the start write position of the 13th wales is set to the position where the address is 2, and the start write position of the 14th ordinate is set to the position of the address 3. The write position of the 15th vertical line is set to the position where the address is 7, the start write position of the 16th vertical line is set to the position where the address is 9, and the start write position of the 17th vertical line is set to the address of 9 Bit The write position of the 18th wales is set to the address of 9, the write position of the 19th traverse is set to the address of 10, and the write position of the 20th trajectory is set to the address of 10 The position of the start of the 21st wales is set to the address of 10, the write position of the 22nd wales is set to the address of 10, and the write position of the 23rd traverse is set as the address. At the position of 10, the start position of the 24th wales is set to the position of the address 11.

Next, the transmission processing performed by the transmitting apparatus 11 of Fig. 8 will be described with reference to the flowchart of Fig. 25.

The LDPC encoding unit 21 waits for the supply of the target data, and in step S101, encodes the target data into an LDPC code, supplies the LDPC code to the bit interleaver 22, and the processing proceeds to step S102.

In step S102, the bit interleaver 22 performs bit interleaving on the LDPC code from the LDPC encoding unit 21, and supplies the symbolized symbol of the LDPC code interleaved to the mapping unit 26 for processing. The process proceeds to step S103.

That is, in step S102, in the bit interleaver 22, the parity interleaver 23 performs the co-located interleaving with the LDPC code from the LDPC encoding unit 21, and supplies the co-interleaved LDPC code to the whirling twist interleaver. twenty four.

The whirling torsion interleaver 24 takes the LDPC code from the co-located interleaver 23 as a target, performs wobble interleaving, and supplies it to the demultiplexer 25.

The demultiplexer 25 replaces the code bits of the LDPC code which are longitudinally twisted and interleaved by the wobble interleaver 24, and performs the symbol bit of the replaced code bit as a symbol (representing the symbol Replacement processing of bits).

Here, the replacement processing by the demultiplexer 25 may be performed in accordance with the first to fourth alternatives shown in FIGS. 16 and 17, and may be performed in accordance with an allocation rule. The allocation rule is a rule for assigning the code bit of the LDPC code to the symbol bit representing the symbol, which will be described later in detail.

The symbols obtained by the replacement processing of the demultiplexer 25 are supplied from the demultiplexer 25 to the mapping unit 26.

In step S103, the mapping unit 26 maps the symbols from the demultiplexer 25 to the signal points determined by the modulation method of the quadrature modulation by the quadrature modulation unit 27, and supplies them to the quadrature modulation. At step 27, the processing proceeds to step S104.

The quadrature modulation unit 27 performs orthogonal modulation of the carrier in accordance with the signal point from the mapping unit 26 in step S104, and the processing proceeds to step S105 to transmit the modulation signal obtained as a result of the quadrature modulation. Finished processing.

Further, the transmission processing of Fig. 25 is repeated in the pipeline.

As described above, by performing the co-located interleaving or the wobble interleaving, the tolerance for erasing or bursting errors in the case where the complex digital bit of the LDPC code is transmitted as one symbol can be improved.

Here, in FIG. 8, for convenience of explanation, the parity interleaver 23 which is a block which performs the co-interlacing, and the vertical twist interleaver 24 which is a block which performs the wagger interleaving are individually formed, but the parity interleaver 23 and the vertical The row twisting interleaver 24 can also be constructed integrally.

That is, any of the parity interleaving and the vertical twist interleaving can be performed by writing and reading the memory bit by the code bit, and the address at which the code bit is written can be written (address written) The conversion is represented by a matrix of addresses (read addresses) from which the code bits are read.

Therefore, if the matrix obtained by multiplying the matrix representing the co-located interlace and the matrix representing the wobble interleaving of the wales are obtained in advance, by using the matrix to convert the code bit, the co-located interleaving can be obtained, and the co-located interleaving is further performed. The LDPC code is the result of the twisted interleaving.

Further, the demultiplexer 25 may be integrally formed in addition to the co-interleaver 23 and the whirling interleaver 24.

That is, the replacement processing by the demultiplexer 25 can also be represented by converting the write address of the memory 31 of the memory LDPC code into a matrix of read addresses.

Therefore, if the matrix representing the co-located interlace, the matrix representing the wobble interleave, and the matrix obtained by the matrix representing the replacement process are obtained in advance, the matrix interleave, the wobble interleave, and the replacement process can be performed by the matrix. .

Further, regarding the co-interlacing and the whirling twisting, only one or both of them may not be performed.

Next, a simulation of the measurement error rate (bit error rate) performed with respect to the transmitting apparatus 11 of FIG. 8 will be described with reference to FIGS. 26 to 28.

The simulation is performed using a communication channel with a D/U of 0 dB and flutter.

Figure 26 is a diagram showing the model of the communication channel used for the simulation.

That is, Fig. 26A shows a model of the flutter used in the simulation.

Further, Fig. 26B shows a model of the communication channel having the flutter represented by the model of Fig. 26A.

Further, in Fig. 26B, H represents the model of the flutter of Fig. 26A. Further, in Fig. 26B, N represents ICI (Inter Carrier Interference), and in the simulation, the expected value E[N ² ] of its power is approximated by AWGN.

27 and 28 show the relationship between the error rate obtained by the simulation and the Doppler frequency f _d of the flutter.

In addition, FIG. 27 shows the relationship between the error rate and the Doppler frequency f _{d in} the case where the modulation method is 16QAM and the coding rate (r) is 3/4, and the alternative is the first alternative. Further, Fig. 28 shows the relationship between the error rate and the Doppler frequency f _{d in} the case where the modulation method is 64QAM and the coding rate (r) is 5/6, and the alternative is the first alternative.

Further, in FIGS. 27 and 28, the thick line indicates the relationship between the error rate and the Doppler frequency f _{d in} the case of performing the co-interleaving, the wobble interleave, and the replacement processing, and the thin line indicates that only the co-interlacing is performed. The relationship between the error rate in the case of the twisting interleaving and the replacement processing in the replacement processing and the Doppler frequency f _d .

As shown in any of Figs. 27 and 28, it can be seen that the case where all of the co-located interleaving, the whirling twist interleaving, and the replacement processing are performed is a case where only the replacement processing is performed, and the error rate is increased (smaller).

Next, the LDPC encoding unit 21 of Fig. 8 will be further explained.

As illustrated in Fig. 11, in the specification of DVB-S.2, there are two LDPC codes of code length N of 64800 bits and 16200 bits.

Then, regarding the LDPC code having a code length N of 64,800 bits, 11 coding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/ are specified. 5, 5/6, 8/9, and 9/10. For an LDPC code with a code length N of 16,200 bits, 10 encoding rates of 1/4, 1/3, 2/5, 1/2, 3/ are specified. 5, 2/3, 3/4, 4/5, 5/6 and 8/9 (Fig. 11B).

The LDPC encoding unit 21 encodes the LDPC code of each encoding rate of 64800 bits or 16200 bits according to the check matrix H prepared according to the code length N and the coding rate (error correction coding). ).

FIG. 29 shows an example of the configuration of the LDPC encoding unit 21 of FIG.

The LDPC encoding unit 21 is composed of an encoding processing unit 601 and a storage unit 602.

The encoding processing unit 601 is composed of a coding rate setting unit 611, an initial value table reading unit 612, a check matrix generating unit 613, an information bit reading unit 614, a coded parity calculating unit 615, and a control unit 616, and supplies them. The LDPC code of the target data to the LDPC encoding section 21 supplies the LDPC code obtained as a result to the bit interleaver 22 (Fig. 8).

In other words, the coding rate setting unit 611 sets the code length N and the coding rate of the LDPC code in response to, for example, the operation of the operator.

The initial value table reading unit 612 reads out the check matrix initial value table described later in accordance with the code length N and the coding rate set by the coding rate setting unit 611 from the storage unit 602.

The inspection matrix generation unit 613 is arranged in accordance with the inspection matrix initial value table read by the initial value table reading unit 612 in the row direction for every 360 lines (the number of rows P of the circuit structure). element setting unit 611 code length N and the set coding rate information length K (= code length N- parity length M) of the information matrix H _A of 1, parity check matrix H is generated and stored in the memory unit 602.

The information bit reading unit 614 reads (takes) the information bits of the information length K from the target data supplied to the LDPC encoding unit 21.

The coded parity calculating unit 615 reads the check matrix H generated by the check matrix generating unit 613 from the storage unit 602, and calculates a parity bit of the information bit read by the information bit reading unit 614 based on the specific expression to generate a code. Word (LDPC code).

The control unit 616 controls each block constituting the encoding processing unit 601.

The memory unit 602 stores a complex check matrix initial value table and the like corresponding to the complex coding rates shown in FIG. 11 for the two code lengths N of 64800 bits and 16200 bits, respectively. Further, the storage unit 602 temporarily stores the data necessary for the processing of the encoding processing unit 601.

Fig. 30 is a flow chart for explaining the processing of the LDPC encoding unit 21 of Fig. 29.

In step S201, the coding rate setting unit 611 determines (sets) the code length N and the coding rate r at which LDPC coding is performed.

In step S202, the initial value table reading unit 612 reads out a predetermined check matrix initial value table corresponding to the code length N and the coding rate r determined by the coding rate setting unit 611 from the storage unit 602.

In step S203, the check matrix generation unit 613 obtains (generates) the code length N determined by the coding rate setting unit 611 by using the check matrix initial value table read from the storage unit 602 by the initial value table reading unit 612. The inspection matrix H of the LDPC code of the coding rate r is supplied to the memory unit 602 and stored.

In step S204, the information bit reading unit 614 reads the information length K corresponding to the code length N and the coding rate r determined by the coding rate setting unit 611 from the target data supplied to the LDPC encoding unit 21. The information bit of N×r) is read from the storage unit 602 by the check matrix H obtained by the check matrix generation unit 613, and supplied to the coded parity calculation unit 615.

In step S205, the encoding parity calculating unit 615 sequentially calculates the parity bits of the codeword c conforming to the equation (8).

Hc ^T =0 ‧‧‧(8)

In equation (8), c denotes a column vector as a codeword (LDPC code), and c ^T denotes a transposition of the column vector c.

Here, as described above, in the column vector c of the LDPC code (1 code word), the column vector A indicates the portion of the information bit, and the column vector T indicates the portion of the parity bit, the column vector c may be It is represented by the column vector A as the information bit and the column vector T as the parity bit, and is expressed by the equation c=[A|T].

Check matrix H and as an LDPC code of the column vector c = [A | T] must meet the formula Hc ^T = 0, as a constituent in line with the formula Hc ^T = 0 of the column vector c = [A | T] The nibble of the same column Since the vector T Keji check matrix _{H = [H A | H T} ] of the parity matrix H _T become as shown in FIG. 10 the case of a stepped structure, from the formula H _c ^T = 0, column 1 of row vectors of H _c ^T The elements are sequentially zeroed out by making the elements of each column zero.

When the coded parity calculation unit 615 obtains the parity bit T for the information bit A, the code word c=[A|T] represented by the information bit A and the parity bit T is used as the information bit A. The LDPC encodes the result and outputs it.

In addition, the codeword c is 64800 bits or 16200 bits.

Thereafter, in step S206, the control unit 616 determines whether or not the LDPC encoding is ended. In the case where it is determined in step S206 that the LDPC encoding is not completed, that is, for example, if the target data to be LDPC-encoded is still present, the processing returns to step S201, and the processing of steps S201 to S206 is repeated below.

Further, in the case where it is determined in step S206 that the LDPC encoding is terminated, that is, for example, when there is no object data to be LDPC-encoded, the LDPC encoding unit 21 terminates the processing.

As described above, the check matrix initial value table corresponding to each code length N and each coding rate r is prepared, and the LDPC encoding unit 21 LDPC encodes the specific coding rate r of the specific code length N, and uses the corresponding code length corresponding to the specific code length. N and the check matrix H generated by the check matrix initial value table of the specific coding rate r are performed.

Check matrix initial value table system checks the corresponding matrix H is to the response to the LDPC code (LDPC code by parity check matrix H defined of) the code length N and the information length encoding rate r of the K of the information matrix H _A (FIG. 9) of the The position of the element of 1 is expressed in units of 360 lines (the number of rows P of the circuit structure), and is prepared one by one according to the code length N and the inspection matrix H of each coding rate r.

31 to 58 show a plurality of check matrix initial value tables defined by the specifications of DVB-S.2.

That is, Fig. 31 is a table showing an initial value of the check matrix of the check matrix H for which the code rate r of the code length N is 16200 bits is 2/3 as defined by the specification of DVB-S.2.

32 to 34 are diagrams showing an inspection matrix initial value table of the inspection matrix H for which the coding rate r of the code length N is 64,800 bits is 2/3 as defined by the specification of DVB-S.2.

In addition, FIG. 33 is a view subsequent to FIG. 32, and FIG. 34 is a view subsequent to FIG.

Fig. 35 is a table showing an initial value of the check matrix of the check matrix H for which the code rate r of 16200 bits is 3/4 as defined by the specification of DVB-S.2.

36 to 39 are diagrams showing an inspection matrix initial value table of the inspection matrix H for which the coding rate r of the code length N is 64,800 bits is 3/4 as defined by the specification of DVB-S.2.

In addition, FIG. 37 is a view continuing from FIG. 36, and FIG. 38 is a view continuing from FIG. Moreover, Fig. 39 is continued from Fig. 38.

Fig. 40 is a table showing an initial value of the check matrix of the check matrix H for which the code rate r of 16200 bits is 4/5 as defined by the specification of DVB-S.2.

41 to 44 are diagrams showing an inspection matrix initial value table of the inspection matrix H for which the coding rate r of the code length N is 64,800 bits is 4/5, which is defined by the specification of DVB-S.2.

In addition, FIG. 42 is a view continuing from FIG. 41, and FIG. 43 is a view continuing from FIG. Moreover, Fig. 44 is a view subsequent to Fig. 43.

Fig. 45 is a table showing an initial value of the check matrix of the check matrix H for which the code rate r of 16200 bits is 5/6 as defined by the specification of DVB-S.2.

Fig. 46 to Fig. 49 are diagrams showing an inspection matrix initial value table of the inspection matrix H for which the coding rate r of the code length N is 64,800 bits is 5/6 as defined by the specification of DVB-S.2.

In addition, FIG. 47 is a view continuing from FIG. 46, and FIG. 48 is a view continuing from FIG. Moreover, Fig. 49 is continued from Fig. 48.

Fig. 50 is a table showing the check matrix initial value of the check matrix H for which the code rate R of 16200 bits is 8/9 as defined by the specification of DVB-S.2.

Fig. 51 to Fig. 54 are diagrams showing an inspection matrix initial value table of the inspection matrix H having a coding rate r of 8/9 with a code length N of 64,800 bits as defined by the specification of DVB-S.2.

In addition, FIG. 52 is continued from FIG. 51, and FIG. 53 is continued from FIG. Moreover, Fig. 54 is continued from Fig. 53.

55 to 58 are diagrams showing an inspection matrix initial value table of the inspection matrix H for which the coding rate r of the code length N is 64,800 bits is 9/10, which is defined by the specification of DVB-S.2.

In addition, FIG. 56 is continued from FIG. 55, and FIG. 57 is continued from FIG. Moreover, Fig. 58 is continued from Fig. 57.

The inspection matrix generation unit 613 (FIG. 29) uses the inspection matrix initial value table to obtain the inspection matrix H as follows.

That is, Fig. 59 shows a method of obtaining the inspection matrix H from the inspection matrix initial value table.

In addition, the check matrix initial value table of FIG. 59 indicates the check matrix of the check matrix H whose code length N is 16200 bits and the code rate r is 2/3 as specified in the specification of DVB-S.2 shown in FIG. Initial value table.

The check matrix initial value table is as described above, and corresponds to the position of the element of the information matrix H _A ( FIG. 9 ) corresponding to the code length N of the LDPC code and the information length K of the coding rate r, for every 360 lines (tour structure) In the table of the number of rows of the unit P), in the i-th column, check the column number of the element of the 1+360×(i-1) row of the matrix H (check the column number of the first column of the matrix H) The number set to 0 is only the number of rows of the line of the 1+360×(i-1) line.

Here, since the parity matrix H _T ( FIG. 9 ) of the inspection matrix H corresponding to the co-located length M is determined as shown in FIG. 19 , if the inspection matrix initial value table is used, the inspection matrix H can be determined to correspond to the information length. K's information matrix H _A (Figure 9).

The number of columns k+1 of the check matrix initial value table differs depending on the information length K.

The relationship of the equation (9) holds between the information length K and the number k+1 of the check matrix initial value table.

K=(k+1)×360 ‧‧‧(9)

Here, 360 of the formula (9) is the number of rows P of the unit of the tour structure described in FIG.

In the check matrix initial value table of Fig. 59, 13 values are arranged from the 1st column to the 3rd column, and three values are arranged from the 4th column to the k+1th column (the 30th column in Fig. 59).

Therefore, the row weight of the check matrix H obtained from the check matrix initial value table of Fig. 59 is from the 1st line to the 1+360×(3-1)-1 behavior 13 from the 1+360×(3) -1) Go to the Kth act 3.

The first column of the check matrix initial value table of FIG. 59 is 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622, which is shown in the first row of the inspection matrix H. The elements whose column numbers are 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622 are 1 (and other elements are 0).

Further, the second column of the check matrix initial value table of FIG. 59 is 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, 3108, which is shown in the check matrix H. The 361 (=1+360×(2-1)) row has elements of column numbers 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, and 3108.

As described above, the check matrix initial value table indicates the position of the element of the information matrix H _A of the matrix H to be expressed every 360 lines.

Check the line other than the 1+360×(i-1) line of the matrix H, that is, the line from the 2+360×(i-1) line to the 360×i line will be checked by the matrix initial value table. The element of the 1st +360 × (i-1) line of the determination is cyclically shifted in the downward direction (the direction below the line) in the same direction length M.

That is, for example, the 2+360×(i-1) line only cyclically shifts the 1+360×(i-1) line downward by M/360 (=q), and then the 3+360× (i-1) The line is rotated by 2×M/360 (=2×q) in the downward direction of the 1+360×(i-1) line (the 2+360×(i-1) line will be Only rotate M/360 (=q) in the downward direction.

Now, if the value of the jth row (jth from the left) of the i-th column (the i-th from the top) of the check matrix initial value table is expressed as h _i,j , and the w of the matrix H will be checked. line of the j-th of the elements of the a number represented as H _wj, check the elements of the w-th row of the rows of the outside of the matrix H of the first 1 + 360 × (i-1 ) row a number H _WJ by Formula (10) is obtained.

H _wj = mod{h _i,j +mod((w-1),P)×q,M) ‧‧‧(10)

Here, mod(x, y) means the remainder after dividing y by x.

Further, P is the number of rows of the above-mentioned tour structure, and the specification of DVB-S. 2 is, for example, 360 as described above. Further, q is a value M/360 obtained by dividing the parity length M by the number of rows P (= 360) of the unit of the tour structure.

The inspection matrix generation unit 613 (FIG. 29) specifies the column number of the element of the 1+360×(i-1) row of the inspection matrix H by checking the matrix initial value table.

Further, the inspection matrix generation unit 613 (FIG. 29) obtains the column of the first w-th row of the row other than the first +360×(i-1) row of the inspection matrix H according to the equation (10). The number H _wj , and a check matrix H having the element of the column number obtained above as 1 is generated.

However, the LDPC code of 2/3 of the coding rate specified by the specification of DVB-S.2 is known to be the LDPC code difference (high) of other coding rates compared to the wrong floor.

Here, as S/N(E _s /N ₀ ) becomes higher, the failure rate (BER) is reduced and passivated, and the phenomenon that the error rate does not decrease (wrong floor phenomenon) occurs, and the error rate when the time is not lowered is the wrong floor. .

If the wrong floor is high, in general, the communication path 13 (Fig. 7) is less resistant to errors, and therefore countermeasures for improving tolerance to errors should be applied.

As a countermeasure for improving the tolerance to errors, for example, there is a replacement process performed by the demultiplexer 25 (Fig. 8).

In the replacement process, as an alternative to replacing the code bit of the LDPC code, for example, the above-described first to fourth alternatives are provided, but the proposal is required to be more resistant to errors than the first to fourth alternatives. The way to improve it.

Therefore, in the demultiplexer 25 (Fig. 8), as illustrated in Fig. 25, the replacement processing can be performed in accordance with the allocation rule.

Hereinafter, the replacement processing according to the allocation rule will be described, and the replacement processing by the alternative method (hereinafter also referred to as the current method) which has been proposed will be described before.

Referring to Fig. 60 and Fig. 61, the replacement processing in the case where the demultiplexer 25 is assumed to perform the replacement processing in the current manner will be described.

Fig. 60 is a diagram showing an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5.

That is, FIG. 60A shows an example in which the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and a further modulation method is 16QAM, and the multiple b is 2. .

When the modulation method is 16QAM, the 4 (=m) bits of the code bit are mapped as one symbol to any of the 16 signal points determined by 16QAM.

Further, when the code length N is 64,800 bits and the multiple b is 2, the memory 31 (FIG. 16, FIG. 17) of the demultiplexer 25 is stored in the horizontal direction memory 4×2 (=mb). The 8 vertical lines of the bit store 64800/(4×2) bits in the wale direction.

In the demultiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 31, and if the writing of the 64800 bit code bit (1 code word) is finished, it is written in the memory 31. The code bits are read in the horizontal direction, read in units of 4 × 2 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17).

The replacing unit 32 is for reading the code bits b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ of the 4 × 2 (= mb) bits from the memory 31, for example. Figure 60A shows the symbol bits y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ assigned to 4 × 2 (= mb) bits of consecutive 2 (= b) symbols. , in the manner of y ₇ , replacing the code bits b ₀ to b _{7 of} 4 × 2 (= mb) bits.

That is, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₇ , the code bit b ₁ to the symbol bit y ₁ , and the code bit b ₂ to the symbol bit . y ₄ , assigning the code bit b ₃ to the symbol bit y ₂ , assigning the code bit b ₄ to the symbol bit y ₅ , and assigning the code bit b ₅ to the symbol bit y ₃ , the code Bit b _{6 is} assigned to symbol bit y ₆ , and code bit b _{7 is} assigned to symbol bit y ₀ for replacement.

Fig. 60B shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and a further modulation method is 64QAM, and the multiple b is 2.

In the case where the modulation method is 64QAM, the 6 (=m) bits of the code bit are mapped as one symbol to any of the 64 signal points determined by 64QAM.

Further, when the code length N is 64800 bits and the multiple b is 2, the memory 31 (FIG. 16, FIG. 17) of the demultiplexer 25 is stored in the horizontal direction memory 6×2 (= mb). The 12 vertical lines of the bit store 64800/(6×2) bits in the wale direction.

In the demultiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 31, and if the writing of the 64800 bit code bit (1 code word) is finished, it is written in the memory 31. The code bits are read in the horizontal direction, read in units of 6 × 2 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17).

The replacing unit 32 is a code bit b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ , b which will be read from the 6×2 (= mb) bits of the memory 31. ₈ , b ₉ , b ₁₀ , b ₁₁ , for example, the symbol bits y ₀ , y ₁ , y ₂ assigned to 6 × 2 (= mb) bits of consecutive 2 (= b) symbols as shown in Fig. 60B , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , replacing the 6×2 (= mb) bit code bits b ₀ to b ₁₁ .

That is, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₁₁ , assigns the code bit b ₁ to the symbol bit y ₇ , and assigns the code bit b ₂ to the symbol bit y ₃ , assigning the code bit b ₃ to the symbol bit y ₁₀ , assigning the code bit b ₄ to the symbol bit y ₆ , and assigning the code bit b ₅ to the symbol bit y ₂ , the code Bit b _{6 is} assigned to symbol bit y ₉ , code bit b _{7 is} assigned to symbol bit y ₅ , code bit b _{8 is} assigned to symbol bit y ₁ , and bit bit b _{9 is} assigned The symbol bit y _{8 is} assigned, the code bit b _{10 is} assigned to the symbol bit y ₄ , and the code bit b _{11 is} assigned to the symbol bit y ₀ for replacement.

Fig. 60C shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and a further modulation method is 256QAM, and the multiple b is 2.

In the case where the modulation method is 256QAM, the 8 (=m) bits of the code bit are mapped as one symbol to one of the 256 signal points determined by 256QAM.

Further, when the code length N is 64,800 bits and the multiple b is 2, the memory 31 (FIG. 16, FIG. 17) of the demultiplexer 25 is stored in the horizontal direction memory 8×2 (=mb). The 16 vertical lines of the bit store 64800/(8×2) bits in the wale direction.

In the demultiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 31, and if the writing of the 64800 bit code bit (1 code word) is finished, it is written in the memory 31. The code bits are read in the horizontal direction, read in units of 8 × 2 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17).

The replacing unit 32 is a code bit b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ , b which will be read from the 8×2 (= mb) bits of the memory 31. ₈ , b ₉ , b ₁₀ , b ₁₁ , b ₁₂ , b ₁₃ , b ₁₄ , b ₁₅ , for example, as shown in Fig. 60C, assigned to 8 × 2 (= mb) bits of consecutive 2 (= b) symbols Symbol bits y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , y ₁₂ , y ₁₃ , y ₁₄ , y _In the manner of ₁₅ , the code bits b ₀ to b _{15 of} 8 × 2 (= mb) bits are replaced.

That is, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₁₅ , assigns the code bit b ₁ to the symbol bit y ₁ , and assigns the code bit b ₂ to the symbol bit . y ₁₃ , assigning the code bit b ₃ to the symbol bit y ₃ , assigning the code bit b ₄ to the symbol bit y ₈ , and assigning the code bit b ₅ to the symbol bit y ₁₁ , the code Bit b _{6 is} assigned to symbol bit y ₉ , code bit b _{7 is} assigned to symbol bit y ₅ , code bit b _{8 is} assigned to symbol bit y ₁₀ , and code bit b _{9 is} assigned For the symbol bit y ₆ , the code bit b _{10 is} assigned to the symbol bit y ₄ , the code bit b _{11 is} assigned to the symbol bit y ₇ , and the code bit b _{12 is} assigned to the symbol bit y ₁₂ , assigning the code bit b ₁₃ to the symbol bit y ₂ , assigning the code bit b ₁₄ to the symbol bit y ₁₄ , and assigning the code bit b ₁₅ to the symbol bit y ₀ , and performing replace.

Fig. 61 is a diagram showing an example of a replacement process of the current mode in the case where the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5.

That is, FIG. 61A shows an example in which the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5, and a further modulation method is 16QAM, and the multiple b is 2. .

When the modulation method is 16QAM, the 4 (=m) bits of the code bit are mapped as one symbol to any of the 16 signal points determined by 16QAM.

Further, when the code length N is 16200 bits and the multiple b is 2, the memory 31 (FIG. 16, FIG. 17) of the demultiplexer 25 is stored in the horizontal direction memory 4×2 (=mb). The eight vertical lines of the bit store 16200/(4×2) bits in the wale direction.

In the demultiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 31, and if the writing of the 16200 bit code bit (1 code word) is finished, it is written in the memory 31. The code bits are read in the horizontal direction, read in units of 4 × 2 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17).

The replacing unit 32 is for reading the code bits b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ of the 4 × 2 (= mb) bits from the memory 31, for example. Figure 6A shows the symbol bits y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ assigned to 4 × 2 (= mb) bits of consecutive 2 (= b) symbols. , in the manner of y ₇ , replacing the code bits b ₀ to b _{7 of} 4 × 2 (= mb) bits.

That is, the replacement unit 32 performs the replacement of the code bits b ₀ to b ₇ to the symbol bits y ₀ to y ₇ as in the case of the above-described FIG. 60A.

Fig. 61B shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5, and a further modulation method is 64QAM, and the multiple b is 2.

In the case where the modulation method is 64QAM, the 6 (=m) bits of the code bit are mapped as one symbol to any of the 64 signal points determined by 64QAM.

Further, when the code length N is 16,200 bits and the multiple b is 2, the memory 31 (FIG. 16, FIG. 17) of the demultiplexer 25 is stored in the horizontal direction memory 6×2 (=mb). The 12 vertical lines of the bit store 16200/(6×2) bits in the wale direction.

In the demultiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 31, and if the writing of the 16200 bit code bit (1 code word) is finished, it is written in the memory 31. The code bits are read in the horizontal direction, read in units of 6 × 2 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17).

The replacing unit 32 is a code bit b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ , b which will be read from the 6×2 (= mb) bits of the memory 31. ₈ , b ₉ , b ₁₀ , b ₁₁ , such as the symbol bits y ₀ , y ₁ , y ₂ assigned to 6 × 2 (= mb) bits of consecutive 2 (= b) symbols as shown in Fig. 61B , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ , y ₈ , y ₉ , y ₁₀ , y ₁₁ , replacing the 6×2 (= mb) bit code bits b ₀ to b ₁₁ .

That is, the replacement unit 32 performs the replacement of the code bits b ₀ to b ₁₁ to the symbol bits y ₀ to y ₁₁ as in the case of the above-described FIG. 60B.

Fig. 61C shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5, and a further modulation method is 256QAM, and the multiple b is 1.

In the case where the modulation method is 256QAM, the 8 (=m) bits of the code bit are mapped as one symbol to one of the 256 signal points determined by 256QAM.

Further, when the code length N is 16,200 bits and the multiple b is 1, the memory 31 of the multiplexer 25 (FIG. 16, FIG. 17) contains 8×1 (=mb) in the horizontal direction. The eight vertical lines of the bit store 16200/(8×1) bits in the wale direction.

In the demultiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 31, and if the writing of the 16200 bit code bit (1 code word) is finished, it is written in the memory 31. The code bits are read out in the horizontal direction, in units of 8 × 1 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17).

The replacing unit 32 is for reading the code bits b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ of the 8 × 1 (= mb) bits from the memory 31, for example. Figure 61C shows the symbol bits y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ of 8 × 1 (= mb) bits assigned to 1 (= b) symbols. In the manner of y ₇ , the code bits b ₀ to b _{7 of} 8 × 1 (= mb) bits are replaced.

That is, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₇ , assigns the code bit b ₁ to the symbol bit y ₃ , and assigns the code bit b ₂ to the symbol bit . y ₁ , the code bit b _{3 is} assigned to the symbol bit y ₅ , the code bit b _{4 is} assigned to the symbol bit y ₂ , and the code bit b _{5 is} assigned to the symbol bit y ₆ , the code is Bit b _{6 is} assigned to symbol bit y ₄ , and code bit b _{7 is} assigned to symbol bit y ₀ for replacement.

Next, the replacement processing according to the distribution rule (hereinafter also referred to as replacement processing of the new replacement method) will be described.

62 to 64 are diagrams illustrating a new alternative.

In the new alternative, the replacement unit 32 of the demultiplexer 25 performs the replacement of the mb bits of the mb bits in accordance with a predetermined allocation rule.

The allocation rule is a rule for assigning the code bits of the LDPC code to the symbol bits. The distribution rule defines: a combination of a code bit group of a code bit element and a symbol bit group of a symbol bit of a code bit element of the code bit group; that is, a group; The code bit group of the group set, and the bit number of the symbol bit group and the bit number of the symbol bit group (hereinafter also referred to as the group bit number).

Herein, the code bit is as described above, and there is a difference in the error rate, and the symbol bit also differs in the error rate. The code bit group is a group that distinguishes the code bit groups according to the error correction rate, and the symbol bit group is grouped according to the error rate to group the symbol bit groups.

62 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and a further modulation method is 256QAM, and a multiple of b is a code bit group and a symbol bit. Group.

In this case, the code bits b ₀ to b ₁₅ of the 8 × 2 (= mb) bits read from the memory 31 are grouped into 5 codes as shown in FIG. 62A in response to the difference in error correction rates. Bit groups Gb ₁ , Gb ₂ , Gb ₃ , Gb ₄ , Gb ₅ .

Here, the code bit group Gb _i is a group whose subscript i is smaller, and the error rate of the code bit belonging to the code bit group Gb _i is better (smaller).

In FIG. 62A, respectively, the code bit group Gb ₁ belongs to the code bit b ₀ , the code bit group Gb ₂ belongs to the code bit b ₁ , and the code bit group Gb ₃ is the code bit b ₂ to b ₉ belong to, the code bit group Gb _{4 is} associated with the code bit b ₁₀ , and the code bit group Gb ₅ is the code bit b ₁₁ to b ₁₅ belongs to.

When the modulation mode is 256QAM and the multiple b is 2, the symbol bits y ₀ to y ₁₅ of the 8×2 (= mb) bits are different according to the error correction rate, and can be grouped as shown in FIG. 62B. 4 symbol bit groups Gy ₁ , Gy ₂ , Gy ₃ , Gy ₄ .

Here, the symbol bit group Gy _i is the same as the code bit group, and the smaller the subscript i is, the group with the better error rate of the symbol bit belonging to the symbol bit group Gy _i .

In FIG. 62B, respectively, the symbol bit group Gy ₁ is a symbol bit y ₀ , y ₁ , y ₈ , y ₉ belongs to, and the symbol bit group Gy ₂ is a symbol bit y ₂ . y ₃ , y ₁₀ , y ₁₁ belong to, the symbol element group Gy ₃ is a symbol element y ₄ , y ₅ , y ₁₂ , y ₁₃ belongs to, the symbol element group Gy ₄ is a symbol element y ₆ , y ₇ , y ₁₄ , y ₁₅ belong.

63 is a diagram showing an LDPC code in which an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and a further modulation method of 256QAM and a multiple b of 2.

In the allocation rule of FIG. 63, the combination of the code bit group Gb ₁ and the symbol bit group Gy ₄ is a group set, which is defined first in the figure from the left. Then, the number of group bits of the group set is defined as 1 bit.

Herein, the group set and its group bit number are collectively referred to as group set information. Then, for example, a group set of the code bit group Gb ₁ and the symbol bit group Gy ₄ and a group bit number of the group set, that is, 1 bit, are described as group set information (Gb ₁ , Gy ₄ , 1).

In the allocation rule of FIG. 63, in addition to the group collection information (Gb ₁ , Gy ₄ , 1), group collection information (Gb ₂ , Gy ₄ , 1), (Gb ₃ , Gy ₁ , 3) is also specified. (Gb ₃ , Gy ₂ , 1), (Gb ₃ , Gy ₃ , 2), (Gb ₃ , Gy ₄ , 2), (Gb ₄ , Gy ₃ , 1), (Gb ₅ , Gy ₁ , 1), (Gb ₅ , Gy ₂ , 3), (Gb ₅ , Gy ₃ , 1).

For example, the group set information (Gb ₁ , Gy ₄ , 1) means that _one bit of the code bit belonging to the code bit group Gb ₁ is assigned to the symbol bit belonging to the symbol bit group Gy ₄ . 1 bit.

Therefore, the allocation rule in FIG. 63 is defined as follows: according to the group set information (Gb ₁ , Gy ₄ , 1), the error bit rate is 1 bit of the code bit of the first good code bit group Gb ₁ , Assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy ₄ of the error rate; according to the group set information (Gb ₂ , Gy ₄ , 1), the error rate is the 2nd good code point. 1 bit of the code bit of the meta-group Gb ₂ , assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy ₄ of the error rate; according to the group set information (Gb ₃ , Gy ₁ , 3), assigning the 3 bits of the code bit of the 3rd good code bit group Gb ₃ of the error rate to the symbol bit of the first good symbol bit group Gy ₁ of the error rate. 3-bit; according to the group set information (Gb ₃ , Gy ₂ , 1), the 1st bit of the code bit of the 3rd good code bit group Gb ₃ of the error rate is assigned to the second error of the error rate. 1 bit of the symbol bit of the symbol group Gy ₂ ; according to the group set information (Gb ₃ , Gy ₃ , 2), the code position of the third good code bit group Gb ₃ of the error rate is determined. 2 yuan of the yuan, assigned to the third good symbol of the error rate Groups of ₃ Gy membered symbol bits of two yuan; according to the group set information _{(Gb 3, Gy 4, 2} ), determining the error rate of 2 3 Good ₃ code bits of the code bit group Gb of Yuan, assigned to the 2nd bit of the symbol bit of the 4th good symbol group Gy ₄ of the error rate; according to the group set information (Gb ₄ , Gy ₃ , 1), the error rate is 4th. 1 bit of the code bit of the code bit group Gb ₄ , assigned to the 1st bit of the symbol bit of the 3rd good symbol bit group Gy ₃ of the error rate; according to the group set information (Gb ₅ , Gy ₁ , 1), assigning the 1st bit of the code bit of the 5th good code bit group Gb ₅ of the error rate to the symbol bit of the first good symbol bit group Gy ₁ of the error rate. 1 bit of the element; according to the group set information (Gb ₅ , Gy ₂ , 3), the 3rd bit of the code bit of the 5th good code bit group Gb ₅ of the error rate is assigned to the error correction rate 2 3 bits of the symbol element of the good symbol group Gy ₂ ; and according to the group collection information (Gb ₅ , Gy ₃ , 1), the error rate is the 5th good code group Gb ₅ One bit of the code bit is assigned to the third good symbol group of the error rate Membered bits of symbol ₃ Gy of 1 yuan.

As described above, the code bit group is grouped according to the error rate to group the code bit groups, and the symbol bit group is grouped according to the error rate to group the symbol bit groups. Therefore, the allocation rule may also be a combination of the error rate of the specified code bit and the error rate of the symbol bit to which the code bit is assigned.

Thus, the allocation rule that specifies the combination of the error rate of the code bit and the error rate of the symbol bit to which the code bit is assigned is determined by, for example, the simulation of the BER, to improve the tolerance to errors (for Tolerance of noise).

In addition, even if the allocation of the code bits of a certain code bit group is changed in the bit of the same symbol bit group, (almost) does not affect the tolerance to errors.

Therefore, in order to improve the tolerance to errors, the group set information that minimizes the BER (Bit Error Rate) of the wrong floor is defined, that is, the code bit group of the specified code bit is allocated and allocated. The combination of the symbol group of the symbol bit of the code bit group (group set), the code bit group of the group set, and the code bit of the symbol bit group respectively The number of bits and the number of bits of the symbol element (the number of group bits) is used as an allocation rule, and according to the allocation rule, the code bit is allocated to the symbol bit to replace the code bit.

Wherein, according to the allocation rule, the specific allocation method of which code bit is assigned to which symbol must be determined in advance between the transmitting device 11 and the receiving device 12 (FIG. 7).

Figure 64 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 63.

That is, FIG. 64A shows that the LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 2/3, and the further modulation method is 256QAM, and the multiple b is 2, according to the allocation rule of FIG. 63. The first example of the replacement of the code bit.

The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3. In the case where the modulation method is 256QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction × the traverse direction The code bits written in the memory 31 of the direction (64800/(8×2))×(8×2) bits are in the horizontal direction, and are read in units of 8×2 (=mb) bits, and It is supplied to the replacement unit 32 (Figs. 16 and 17).

The replacing unit 32 assigns the code bits b ₀ to b ₁₅ read from the 8 × 2 (= mb) bits of the memory 31 in accordance with the allocation rule of FIG. 63, for example, as shown in FIG. 64A to consecutive 2 (=b). The symbol bits y ₀ to y _{15 of the} 8 × 2 (= mb) bits of the symbols are replaced by the code bits b ₀ to b _{15 of the} 8 × 2 (= mb) bits.

That is, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₁₅ , assigns the code bit b ₁ to the symbol bit y ₇ , and assigns the code bit b ₂ to the symbol bit . y ₁ , the code bit b _{3 is} assigned to the symbol bit y ₅ , the code bit b _{4 is} assigned to the symbol bit y ₆ , and the code bit b _{5 is} assigned to the symbol bit y ₁₃ , the code is Bit b _{6 is} assigned to symbol bit y ₁₁ , code bit b _{7 is} assigned to symbol bit y ₉ , code bit b _{8 is} assigned to symbol bit y ₈ , and code bit b _{9 is} assigned To the symbol bit y ₁₄ , the code bit b _{10 is} assigned to the symbol bit y ₁₂ , the code bit b _{11 is} assigned to the symbol bit y ₃ , and the code bit b _{12 is} assigned to the symbol bit . y ₀ , the code bit b _{13 is} assigned to the symbol bit y ₁₀ , the code bit b _{14 is} assigned to the symbol bit y ₄ , and the code bit b _{15 is} assigned to the symbol bit y ₂ . replace.

64B is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and further modulation is 256QAM, and the multiple b is 2, and the code bit according to the allocation rule of FIG. 63 is used. The second example of replacement.

According to FIG. 64B, the replacing unit 32 performs the following replacement for the code bits b ₀ to b ₁₅ of the 8 × 2 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 63: The code bit b _{0 is} assigned to the symbol bit y ₁₅ , the code bit b _{1 is} assigned to the symbol bit y ₁₄ , and the code bit b _{2 is} assigned to the symbol bit y ₈ , and the code bit b is _{3 is} assigned to the symbol bit y ₅ , the code bit b _{4 is} assigned to the symbol bit y ₆ , the code bit b _{5 is} assigned to the symbol bit y ₄ , and the code bit b _{6 is} assigned to the symbol Bit y ₂ , assigning code bit b ₇ to symbol bit y ₁ , assigning code bit b ₈ to symbol bit y ₉ , and assigning code bit b ₉ to symbol bit y ₇ , The code bit b _{10 is} assigned to the symbol bit y ₁₂ , the code bit b _{11 is} assigned to the symbol bit y ₃ , and the code bit b _{12 is} assigned to the symbol bit y ₁₃ , and the code bit b is _{13 is} assigned to the symbol bit y ₁₀ , the code bit b _{14 is} assigned to the symbol bit y ₀ , and the code bit b _{15 is} assigned to the symbol bit y ₁₁ .

Here, the allocation manner of the code bit b _i shown in FIG. 64A and FIG. 64B to the symbol bit y _i is in accordance with the allocation rule of FIG. 63 (according to the allocation rule).

Figure 65 is a diagram showing the case where the replacement process of Figure 64A in the replacement process of the new alternative mode illustrated in Figures 62 to 64 has been performed, and the BER (Bit) in the case where the replacement process described in Figure 60C of the current mode has been performed. Error Rate: The result of the simulation of the bit error rate.

That is, FIG. 65 shows an LDPC code defined by the specification of DVB-S.2 having a code length N of 64800 and a coding rate of 2/3, 256QAM as a modulation method, and 2 as a multiple b. BER in case. .

Further, in Fig. 65, the horizontal axis represents E _s /N ₀ and the vertical axis represents BER. Moreover, the circle mark indicates the BER in the case where the replacement process of the new replacement mode has been performed, and the star mark (star mark) indicates the BER in the case where the replacement process of the current mode has been performed.

As can be seen from Fig. 65, in the replacement process of the new alternative, the replacement process of the current mode is compared, and the wrong floor is drastically lowered, and the tolerance to errors is improved.

Further, in the present embodiment, for convenience of explanation, in the multiplexer 25, the replacing unit 32 performs replacement processing on the code bits read from the memory 31, but the replacement processing can be performed by controlling the memory. The writing or reading of the code bits of 31 is performed.

That is, the replacement processing can be performed by, for example, controlling the address of the read code bit (read address) and reading out the code bits from the memory 31 in the order of the replaced code bits.

Next, as a countermeasure for improving the tolerance to errors, in addition to the replacement process of replacing the wrong floor, there is also a method of reducing the LDPC code of the wrong floor.

Therefore, in the LDPC encoding unit 21 (Fig. 8), the LDPC code having a code length R of 64,800 bits and a coding rate r of 2/3 is different from the check matrix initial value table defined by the specification of DVB-S.2. The inspection matrix initial value table of the appropriate inspection matrix H is obtained, and the inspection matrix H obtained from the inspection matrix initial value table can be encoded to obtain an LDPC code having good performance.

Here, the appropriate check matrix H is low E _s /N ₀ (signal power to noise power ratio per 1 symbol) or E _b /N ₀ (signal power to noise power ratio per 1 bit) When the modulation signal of the LDPC code obtained from the inspection matrix H is transmitted, the BER (Bit Error Rate) is made smaller to meet the check condition of the specific condition. Moreover, a good performance LDPC code is obtained from an LDPC code of the appropriate inspection matrix H.

A suitable inspection matrix H can be obtained by, for example, performing a simulation to transmit a BER simulation of a modulated signal of an LDPC code obtained from various inspection matrices satisfying a specific condition at a low E _s /N ₀ .

As a specific condition to be appropriate for the inspection matrix H, for example, an analytical result obtained by an analytical method called a code property called Density Evolution is good, and the inspection matrix H does not exist as a loop 4 The loop of the feature, the loop 6 does not exist, and so on.

Here, the density evolution and the actual system are described, for example, in "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit", SYChung, GD Forney, TJ Richardson, R. Urbanke, IEEE Communications Leggers. , VOL. 5, NO. 2, Feb 2001.

For example, on the AWGN channel, if the discrete value of the noise increases from 0, the expected value of the error correction rate of the LDPC code is initially 0, but if the discrete value of the noise is greater than a certain threshold (threshold), then No longer 0.

If the density is evolved, the performance of the LDPC code can be determined by comparing the threshold value of the discrete value of the noise whose expected value is no longer zero (hereinafter also referred to as the performance threshold). Sexuality. Here, as the performance threshold, E _b /N ₀ when the BER starts to decrease (small) is adopted.

If the LDPC code (hereinafter also referred to as the specification code) whose code length N is 64800 and the coding rate r is 2/3 as defined by the specification of DVB-S.2 is analyzed by density, the performance limit of the specification code is obtained. The value, expressed as V, is selected in the simulation, and the performance threshold is selected as the value of V + Δ after V plus a certain margin Δ, and the code length N is 64800, and the coding rate r is 2/3. (Check matrix), come as a good performance LDPC code.

66 to 68 show one check matrix in the LDPC code (the code length N is 64800 and the code rate r is 2/3 LDPC code) where the performance threshold E _b /N ₀ is V+Δ or less. Initial value table.

In addition, FIG. 67 is a view continuing from FIG. 66, and FIG. 68 is a view continuing from FIG. 67.

There is no loop 4 and loop 6 in the check matrix H obtained from the check matrix initial value table of Figs. 66 to 68.

Fig. 69 is a simulation result showing the BER of the LDPC code (hereinafter also referred to as a proposal code) of the inspection matrix H obtained from the inspection matrix initial value table of Figs. 66 to 68.

That is, FIG. 69 shows the BER of the E _s /N ₀ for the specification code (indicated by a circle in the figure) in the case where the modulation mode is 256QAM, and the BER of E _s /N ₀ for the proposal code (Fig. It is represented by a rectangle). Further, in Fig. 69, the replacement processing of the current mode of Fig. 60C is employed as an alternative processing.

It can be seen from Fig. 69 that the proposed code is better than the specification code, that is, the wrong floor is particularly improved.

Further, the specific condition that the appropriate inspection matrix H should conform to can be appropriately determined from the viewpoints of improvement in decoding performance of the LDPC code, or ease of decoding processing (simplification) of the LDPC code.

Next, Fig. 70 is a block diagram showing a configuration example of the receiving device 12 of Fig. 7.

In Fig. 70, the receiving device 12 receives the modulated signal from the transmitting device 11 (Fig. 7), and is composed of a quadrature demodulating unit 51, a demapping unit 52, a deinterleaver 53 and an LDPC decoding unit 56. .

The orthogonal demodulation unit 51 receives the modulated signal from the transmitting device 11, performs quadrature demodulation, and supplies the signal point (the value in the I and Q-axis directions) obtained as a result to the demapping unit 52.

The demapping unit 52 performs demapping of the symbol points from the orthogonal demodulation unit 51 into symbolized symbols of the LDPC code, and supplies them to the deinterleaver 53.

The deinterleaver 53 is composed of a multiplexer (MUX) 54 and a directional twist deinterleaver 55, and deinterleaves the symbol bits from the symbols of the demapping unit 52.

That is, the multiplexer 54 takes the symbol bit from the symbol of the demapping unit 52 as an object, and performs the inverse replacement processing corresponding to the replacement processing by the multiplexer 25 of Fig. 8 (reverse processing Processing), that is, performing an inverse replacement process of returning the position of the code bit (symbol bit) of the LDPC code replaced by the replacement process to the original position, and supplying the LDPC code obtained as a result to the directional twist Deinterleaver 55.

The vertical twist deinterleaver 55 takes the LDPC code from the multiplexer 54 as a target, and performs the longitudinal twist deinterlacing of the vertical twist interlace as the rearrangement processing performed by the vertical twist interleaver 24 of FIG. (Reverse processing of the whirling and twisting interleaving), that is, as a code bit which changes the aligned LDPC code by the wobble interleave as the rearranging process, and returns to the anti-rearrangement process of the original arrangement, for example, the wales Reverse the deinterlacing.

Specifically, the vertical twist deinterleaver 55 writes the code bits of the LDPC code and further reads them out by the memory for deinterleaving configured similarly to the memory 31 shown in FIG. 22 and the like. Perform longitudinal twist de-interlacing.

Wherein, in the vertical twist deinterleaver 55, the writing of the code bit uses the read address from the reading of the code bit of the memory 31 as the write address, and the memory for deinterleaving The direction of the body is in the direction of the column. Further, the reading of the code bit is performed by using the write address at the time of writing the code bit of the memory 31 as the read address, and in the wale direction of the memory for deinterleaving.

The LDPC code obtained as a result of the whirling de-interlacing is supplied from the vertical twist deinterleaver 55 to the LDPC decoding unit 56.

Here, in the LDPC code supplied from the demapping unit 52 to the deinterleaver 53, the parity interleaving, the walody interleaving, and the replacement processing are performed in this order, but in the deinterleaver 53, only the replacement processing is performed. The inverse replacement processing and the vertical twist deinterlacing corresponding to the longitudinal twist interleaving, so that the co-located deinterlacing corresponding to the co-located interleaving (the inverse processing of the co-located interleaving) is not performed, that is, the LDPC which is changed by the co-located interleaving is not performed. The code bits of the code return to the co-interlace of the original arrangement.

Therefore, from the deinterleaver 53 (the vertical twist deinterleaver 55), the LDPC decoding unit 56 is supplied with an LDPC code in which the inverse replacement processing and the vertical twist deinterleave are performed, and the co-located deinterleaving is not performed.

The LDPC decoding unit 56 performs the LDPC code from the deinterleaver 53 by performing at least the conversion check matrix obtained by the LDPC encoding of the LDPC encoding unit 21 of FIG. The LDPC decodes and outputs the data obtained as a result of the decoding of the target data.

Figure 71 is a flow chart showing the receiving process performed by the receiving device 12 of Figure 70.

The quadrature demodulation unit 51 receives the modulation signal from the transmission device 11 in step S111, and the processing proceeds to step S112 to perform orthogonal demodulation of the modulation signal. The orthogonal demodulation unit 51 supplies the signal point obtained as a result of the orthogonal demodulation to the demapping unit 52, and the processing proceeds from step S112 to step S113.

In step S113, the demapping unit 52 performs demapping of the signal point from the orthogonal demodulation unit 51 into a symbol, and supplies it to the deinterleaver 53, and the processing proceeds to step S114.

In step S114, the deinterleaver 53 performs deinterleaving of the symbol bits from the symbols of the demapping unit 52, and the processing proceeds to step S115.

That is, in step S114, in the deinterleaver 53, the multiplexer 54 takes the symbol bit from the symbol of the demapping section 52 as an object, performs inverse replacement processing, and obtains the LDPC code obtained as a result. The code bit is supplied to the wale twist deinterleaver 55.

The wales deinterleaver 55 takes the LDPC code from the multiplexer 54 as a target, performs directional twist deinterleaving, and supplies the LDPC code obtained as a result to the LDPC decoding unit 56.

In step S115, the LDPC decoding unit 56 performs at least a conversion check matrix obtained by performing row replacement for eccentric interleaving on the check matrix H for LDPC encoding by the LDPC encoding unit 21 of FIG. The LDPC code of the LDPC code of the interleaver 55 is decoded, and the data obtained as a result is output as the decoding result of the object data, and the processing ends.

Further, the reception processing of Fig. 71 is repeated.

Further, Fig. 70 is also the same as the case of Fig. 8. For convenience of explanation, the multiplexer 54 for performing the reverse replacement processing and the vertical twist deinterleaver 55 for performing the longitudinal twist deinterlacing are separately formed, but the multiplexer 54 and The wale twist deinterleaver 55 can also be constructed integrally.

Further, in the case where the transmitting device 11 of FIG. 8 does not perform the wobble interleaving, the receiving device 12 of FIG. 70 does not need to provide the whirling twist deinterleaver 55.

Next, the LDPC decoding performed by the LDPC decoding unit 56 of Fig. 70 will be further explained.

In the LDPC decoding unit 56 of FIG. 70, as described above, the check matrix H for LDPC encoding by the LDPC encoding unit 21 of FIG. 8 is subjected to at least a conversion check matrix obtained by row replacement of the co-located interleaving, and is performed from the vertical. The LDPC decoding of the LDPC code in which the row twist deinterleaver 55 performs the inverse replacement processing and the vertical twist deinterleave and does not perform the co-located deinterleaving.

Here, an LDPC decoding has been proposed, which performs LDPC decoding by using a conversion check matrix, and can suppress the circuit scale while suppressing the operating frequency to a sufficiently achievable range (refer to Japanese Laid-Open Patent Publication No. 2004-343170, for example). .

Therefore, first, referring to FIG. 72 to FIG. 75, the LDPC decoding regarding the utilization conversion check matrix which is proposed first will be explained.

Fig. 72 shows an example of the check matrix H of the LDPC code having a code length N of 90 and a coding rate of 2/3.

Further, in Fig. 72 (the same applies to Figs. 73 and 74 to be described later), 0 is represented by a period (.).

In the check matrix H of Fig. 72, the co-located matrix becomes a stepped structure.

Fig. 73 is a view showing the inspection matrix H' obtained by the row replacement of the equation (11) and the row replacement of the equation (12) in the inspection matrix H of Fig. 72.

Column permutation: 6s+t+1st column→5t+s+1st column ‧‧‧(11)

Line replacement: 6x+y+ line 61→5y+x+ line 61 ‧‧‧(12)

In the equations (11) and (12), s, t, x, and y are integers in the range of 0 ≦ s < 5, 0 ≦ t < 6, 0 ≦ x < 5, and 0 ≦ t < 6, respectively.

If it is replaced according to the formula (11), the substitution is performed by dividing the first, seventh, third, fourth, and fifth columns by the sixth, and the first, seventh, third, fourth, and fifth columns, respectively. The 2nd, 8th, 14th, 20th, and 26th columns with 6 remainders are replaced by the sixth, seventh, eighth, ninth, and tenth columns, respectively.

Further, if the row is replaced by the equation (12), the 61st row and the subsequent (colocated matrix) are replaced by the following cases: the 61st, 67th, 73rd, 79th, and 85th lines divided by the 6th remainder are replaced by the Lines 61, 62, 63, 64, and 65 are divided by lines 62, 68, 74, 80, and 86 of the remainder of 6 to be replaced by lines 66, 67, 68, 69, and 70, respectively.

Thus, the matrix obtained by performing column and row permutation on the inspection matrix H of FIG. 72 is the inspection matrix H' of FIG.

Here, even if the column replacement of the inspection matrix H is performed, the arrangement of the code bits of the LDPC code is not affected.

Moreover, the row permutation of the equation (12) is equivalent to the information length of the co-interleaving in which the K+qx+y+1 code bits are interleaved to the position of the K+Py+x+1 code bits. K is 60, and the number of rows P of the unit of the tour structure is 5 and the parity of the parity of the same length M (here, 30) is q (=M/P) is 6.

For the check matrix of FIG. 73 (hereinafter referred to as a replacement check matrix as appropriate) H', the LDPC code multiplied by the check matrix of FIG. 72 (hereinafter referred to as the original check matrix) H is the same as the equation (12). After the replacement matrix, a 0 vector is output. That is, if the column vector obtained by the row permutation of the equation (12) is expressed as c' in the column vector c of the LDPC code (1 codeword) of the original inspection matrix H, the nature of the matrix is checked. Look, Hc ^T becomes a 0 vector, so H'c' ^T also becomes a 0 vector.

According to the above, the conversion check matrix H' of FIG. 73 is based on the LDPC code c of the original inspection matrix H, and the inspection matrix of the LDPC code c' obtained by the row replacement of the equation (12) is performed.

Therefore, in the LDPC code c of the original inspection matrix H, the row substitution of the equation (12) is performed, and the LDPC code c' of the row replacement is decoded (LDPC decoding) by using the conversion check matrix H' of FIG. 73. The decoding result is subjected to the inverse permutation of the row substitution of the equation (12), whereby the decoding result in the case where the LDPC code of the original inspection matrix H is decoded by the inspection matrix H can be obtained.

Fig. 74 is a diagram showing the conversion check matrix H' of Fig. 73 with intervals of 5 × 5 matrix.

In FIG. 74, the conversion check matrix H' is represented by a combination of the following matrix: a 5×5 unit matrix; and one or more of the unit matrix 1 is a matrix of 0 (hereinafter referred to as a quasi-unit matrix as appropriate) a matrix of cyclic shifts (hereinafter suitably referred to as a shift matrix) of a unit matrix or a quasi-unit matrix; a sum of 2 or more of a unit matrix, a quasi-unit matrix, or a shift matrix (hereinafter suitably referred to as a And matrix); and 5 × 5 0 matrix.

The conversion check matrix H' of Fig. 74 can be composed of a 5 × 5 unit matrix, a quasi-unit matrix, a shift matrix, and a matrix and a 0 matrix. Therefore, the 5 × 5 matrix constituting the conversion check matrix H' is hereinafter referred to as a constituent matrix as appropriate.

For the decoding of the LDPC code represented by the check matrix represented by the constituent matrix of P×P, it is possible to use P architectures for performing check node operation and variable node operation at the same time.

Fig. 75 is a block diagram showing a configuration example of a decoding apparatus that performs such decoding.

That is, Fig. 75 shows the structure of a decoding apparatus for performing decoding of an LDPC code by using at least the conversion check matrix H' of Fig. 74 obtained by performing the row replacement of the equation (12) with respect to the original inspection matrix H of Fig. 72. example.

The decoding apparatus of FIG. 75 comprises: a branching data from 6 to 300 ₆ FIFO300 ₁ composed of a storage memory 300, the selector selecting FIFO300 ₁ of 301 to 300 _6, a check node calculation 302,2 cyclic shift unit circuit 303 and 308, the variable node information 18 composed of M. FIFO304 ₁ to _30,418 with a memory storage 304, a selector to select 305 FIFO304 ₁ to _30,418, the receiver receiving the data information storage memory 306 only, The calculation unit 307, the decoded word calculation unit 309, the received data rearrangement unit 310, and the decoded data rearrangement unit 311.

First, a method of storing data on the memory 300 and 304 for branch data storage will be described.

The branch data storage memory 300 is composed of six FIFOs 300 ₁ to 300 ₆ which are divided by the number of columns 30 of the conversion check matrix H' of FIG. 74 and which are divided by the number of columns 5 of the matrix. FIFO300 _y (y=1, 2..., 6) is composed of a plurality of segments of memory area, and the memory area of each segment can be simultaneously read or written to correspond to the number of columns and the number of rows constituting the matrix. Branched message. Moreover, the number of segments of the memory area of the FIFO 300 _y is the maximum number of the number of the column of the conversion check matrix of FIG. 74 (Hamming weight), that is, 9.

In the FIFO 300 ₁ , the data corresponding to the position of the first column to the fifth column of the conversion check matrix H′ of FIG. 74 (the message v _i from the variable node) is stored in a form in which the columns are horizontally packed ( In the form of neglecting 0). That is, if the i-th row of the j-th column is represented as (j, i), the first-stage memory area of the FIFO 300 ₁ is stored with the conversion check matrix H' from (1, 1) to (5, 5). ) The position of the position of the unit matrix of 5×5. In the second segment memory region, a shift matrix corresponding to the conversion check matrix H' from (1, 21) to (5, 25) is stored (after the 5×5 unit matrix is only cyclically shifted to the right by 3) The position of the position of the displacement matrix). The memory areas from the third to the eighth segments are also stored in association with the conversion check matrix H'. Then, the 9th segment memory region stores a shift matrix corresponding to the conversion check matrix H' from (1, 86) to (5, 90) (substituting 1 of the 1st column in the 5×5 unit matrix 0, and only shift to the left of the data of the position of 1 of the shift matrix).

In the FIFO 300 ₂ , the data corresponding to the position of the sixth column to the tenth column of the conversion check matrix H' of FIG. 74 is stored. That is, in the first segment memory area of the FIFO 300 _{2, a} sum matrix corresponding to the transition check matrix H' from (6, 1) to (10, 5) is stored (the 5 x 5 unit matrix is looped only to the right) A data of the position of the first shift matrix of one of the first shift matrix shifted by one and the sum of the two shift matrices that are cyclically shifted only to the right. Further, the second-stage memory area stores data corresponding to the position of the first shift matrix constituting the sum matrix of the transition check matrix H' from (6, 1) to (10, 5).

That is, with respect to a constituent matrix having a weight of 2 or more, a unit matrix of P×P having a weight of 1 and a quasi unit matrix of one or more of the elements 1 being 0 or a unit matrix or a quasi-unit matrix The sum of the complex sums in the shift matrix after cyclic shifting represents the position of the unit matrix, the quasi-unit matrix, or the position of the shift matrix 1 (corresponding to the unit matrix) when the constituent matrix is represented. The message of the branch of the quasi-unit matrix or the shift matrix is stored in the same address (the same FIFO in FIFOs 300 ₁ to 300 ₆ ).

Hereinafter, the data is stored in the memory areas from the third to the ninth segments in association with the conversion check matrix H'.

FIFO300 ₃ to 300 ₆ equally with the conversion parity check matrix H 'corresponding to the given data store.

The branch data storage memory 304 is composed of 18 FIFOs 304 ₁ to 304 ₁₈ divided by the number of rows constituting the matrix, which is divided by the number 90 of the conversion check matrix H'. FIFO304 _x (x=1, 2, ..., 18) is composed of a plurality of segments of memory area, and the number of columns corresponding to the conversion check matrix H' can be simultaneously read or written in the memory area of each segment and The message of 5 branches of the number of rows.

In the FIFO 304 ₁ , the data corresponding to the position of the 1st row to the 5th row of the conversion check matrix H′ of FIG. 74 (the message u _j from the check node) is stored in the form of vertical filling of each row ( Ignore the form of 0). That is, in the first-stage memory area of the FIFO 304 ₁ , data corresponding to the position of the unit matrix of 5 × 5 of (1, 1) to (5, 5) of the conversion check matrix H' is stored. In the second segment memory region, a sum matrix corresponding to the transition check matrix H' from (6, 1) to (10, 5) is stored (the fifth unit matrix of 5×5 is cyclically shifted by only one) 1) The position of the position of the 1st shift matrix of the shift matrix and the sum matrix of the sum of the 2nd shift matrices which are only cyclically shifted to the right. Further, the third-stage memory area stores data corresponding to the position of the first shift matrix constituting the sum matrix of the transition check matrix H' from (6, 1) to (10, 5).

That is, with respect to a constituent matrix having a weight of 2 or more, a unit matrix of P×P having a weight of 1 and a quasi unit matrix of one or more of the elements 1 being 0 or a unit matrix or a quasi-unit matrix The sum of the complex sums in the shift matrix after cyclic shifting represents the position of the unit matrix, the quasi-unit matrix, or the position of the shift matrix 1 (corresponding to the unit matrix) when the constituent matrix is represented. The message of the branch of the quasi-unit matrix or the shift matrix is stored in the same address (the same FIFO in FIFOs 304 ₁ to 304 ₁₈ ).

Hereinafter, data is stored from the fourth and fifth segment memory regions in association with the conversion check matrix H'. The number of segments of the memory area of the FIFO 304 ₁ is the maximum number of the number (1 Hamming weight) of the conversion check matrix H' from the first row to the fifth row, that is, 5.

Similarly, the FIFOs 304 ₂ and 304 ₃ are stored in correspondence with the conversion check matrix H', and the length (number of segments) is 5. The FIFOs 304 ₄ to 304 ₁₂ also store data in correspondence with the conversion check matrix H', respectively, and have a length of three. The FIFOs 304 ₁₃ to 304 ₁₈ also store data in correspondence with the conversion check matrix H', respectively, and have a length of two.

Next, the operation of the decoding apparatus of Fig. 75 will be described.

The branch data storage memory 300 is composed of six FIFOs 300 ₁ to 300 ₆ and belongs to the column of the conversion check matrix H' according to the five messages D311 supplied from the previous stage cyclic shift circuit 308 (Matrix data) D312, the FIFO storing the data is selected from the FIFOs 300 ₁ to 300 ₆ , and the five messages D311 are sequentially stored in the selected FIFO. Further, when the branch data storage memory 300 is for reading data, five messages D300 ₁ are sequentially read from the FIFO 300 ₁ and supplied to the selector 301 of the second stage, and the branch data storage memory 300 is attached to After the reading of the message from the FIFO 300 _{1 is completed,} the messages are sequentially read from the FIFOs 300 ₂ to 300 ₆ and supplied to the selector 301.

The selector 301 selects five messages from the FIFOs of the data to be read out of the FIFOs 300 ₁ to 300 ₆ in accordance with the selection signal D301, and supplies them to the check node calculation unit 302 as the message D302.

The check node calculation unit 302 is composed of five check node calculators 302 ₁ to 302 ₅ and uses the message D302 (D302 ₁ to D302 ₅ ) supplied by the selector 301 (the message v _{i of the} equation (7)). Performing a check node operation according to equation (7), and supplying five messages D303 (D303 ₁ to D303 ₅ ) (message u _{j of} equation (7)) obtained by the result of the check node operation to the cyclic shift Circuit 303.

The cyclic shift circuit 303 cyclically shifts the information of several original unit matrices in the conversion check matrix H' by the five messages D303 ₁ to D303 ₅ obtained by the check node calculating unit 302 (Matrix) The data is cyclically shifted based on D305, and the result is supplied to the branch data storage memory 304 as a message D304.

The branch data storage memory 304 is composed of 18 FIFOs 304 ₁ to 304 ₁₈ , and belongs to the information D305 of the column of the conversion check matrix H' according to the five messages D304 supplied from the loop shift circuit 303 of the previous stage. The FIFOs of the stored data are selected among the FIFOs 304 ₁ to 304 ₁₈ , and the five messages D304 are sequentially stored in the selected FIFO. Further, when the branch data storage memory 304 is for reading data, five messages D306 ₁ are sequentially read from the FIFO 304 ₁ and supplied to the selector 305 of the next stage. After the read data stored in the branch information from an end of the FIFO304 ₁ with 304-based memory, the message is also sequentially read out from the FIFO 304 ₂ to 304 ₁₈ and supplied to the selector 305.

The selector 305 selects five messages from the FIFOs of the FIFOs 304 ₁ to 304 ₁₈ that are currently reading data in accordance with the selection signal D307, and supplies them to the variable node calculation unit 307 and the decoded word calculation unit 309 as the message D308.

On the other hand, the received data rearrangement unit 310 rearranges the LDPC code D313 received through the communication channel by the line replacement of the equation (12), and supplies it to the received data memory 306 as the received data D314. . The received data memory 306 calculates and memorizes the received LLR (Logarithmic Probability Ratio) from the received data D314 supplied from the received data rearrangement unit 310, and supplies the received LLR to the received value D309 every five times. The variable node calculation unit 307 and the decoded word calculation unit 309.

The variable node calculation unit 307 is composed of five variable node calculators 307 ₁ to 307 ₅ and uses the message D308 (D308 ₁ to D308 ₅ ) supplied by the selector 305 (the message u _{j of the} equation (1)). And the five received values D309 (the received value u _{oi of the} equation (1)) supplied from the received data memory 306, the variable node operation is performed according to the equation (1), and the message D310 obtained as a result of the calculation is performed ( D310 ₁ to D310 ₅ ) (the message v _{i of the} equation (1)) is supplied to the cyclic shift circuit 308.

The cyclic shift circuit 308 cyclically shifts the information D310 ₁ to D310 ₅ calculated by the variable node calculation unit 307 based on the information of the corresponding unit matrix in which the corresponding branch is cyclically shifted by the conversion check matrix H'. The bit is supplied to the branch data storage memory 300 as the message D311.

By patrolling the above operation once, the LDPC code can be decoded once. The decoding apparatus of FIG. 75 decodes the LDPC code only a specific number of times, and obtains the final decoding result in the decoded word calculation unit 309 and the decoded data rearrangement unit 311, and outputs the result.

That is, the decoded word calculation unit 309 is composed of five decoded word calculators 309 ₁ to 309 ₅ and uses the five messages D308 (D308 ₁ to D308 ₅ ) output by the selector 305 (the message of the equation (5) u _j ) and five received values D309 (received value u _{oi of the} equation (5)) supplied from the received data memory 306 as the final segment of the plurality of decodings, and the decoding result (decoded word) is calculated according to the equation (5). The decoded data D315 obtained as a result is supplied to the decoded data rearrangement unit 311.

The decoded data rearrangement unit 311 performs the inverse permutation of the line replacement of the equation (12) by using the decoded data D315 supplied from the decoded word calculation unit 309, and rearranges the order, and as the final decoding result D316. Output.

As described above, by applying one or both of the column permutation and the row permutation to the inspection matrix (original inspection matrix), it is converted into a unit matrix of P × P, and one or more of the elements are zero. a quasi-unit matrix, a sum matrix of a shift matrix, a unit matrix, a quasi-unit matrix or a shift matrix of a unit matrix or a quasi-unit matrix, and a combination of a P matrix of P×P, That is, the inspection matrix (conversion check matrix) can be represented by a combination of the constituent matrices, and the decoding of the LDPC code can be performed by simultaneously performing an architecture of P check node operations and variable node operations, thereby simultaneously performing P node operations can reduce the operating frequency down to the achievable range and perform many repeated decodings.

The LDPC decoding unit 56 constituting the receiving device 12 of Fig. 70 is the same as the decoding device of Fig. 75, and performs LDPC decoding by simultaneously performing P check node operations and variable node operations.

In other words, the inspection matrix of the LDPC code outputted by the LDPC encoding unit 21 of the transmitting device 11 of Fig. 8 is set to, for example, the check matrix H in which the parity matrix shown in Fig. 72 is a stepped structure, for the sake of simplicity of explanation. The co-located interleaver 23 of the transmitting device 11 interleaves the K+qx+y+1 code bits to the position of the K+Py+x+1 code bits, and sets the information length K to 60 respectively. The number of rows P of the unit of the tour structure is set to 5, and the number q of the same length M (=M/P) is set to 6.

Since the co-located interleaving is replaced by the line corresponding to the above equation (12), the LDPC decoding unit 56 does not need to perform the line replacement of the equation (12).

Therefore, in the receiving apparatus 12 of Fig. 70, the LDPC decoding unit 56 supplies the LDPC code which is not equally deinterleaved to the LDPC decoding unit 56 as described above, that is, the line replacement of the equation (12) is supplied. In the LDPC decoding unit 56, the LDPC decoding unit 56 performs the same processing as the decoding apparatus of Fig. 75 except that the line replacement of the equation (12) is not performed.

That is, Fig. 76 shows an example of the configuration of the LDPC decoding unit 56 of Fig. 70.

In FIG. 76, the LDPC decoding unit 56 is configured similarly to the decoding device of FIG. 75 except that the received data rearrangement unit 310 of FIG. 75 is not provided, and the row replacement is performed without the equation (12), and FIG. 75 Since the decoding apparatus performs the same processing, the description thereof will be omitted.

As described above, since the LDPC decoding unit 56 is not provided with the received data rearrangement unit 310, the decoding apparatus of FIG. 75 can be reduced in size.

In addition, in FIGS. 72 to 76, in order to simplify the description, the code length N of the LDPC code is set to 90, the information length K is set to 60, and the number of rows of the tour structure (the number of columns and the number of rows of the matrix) P. Let 5 be the same as the number q (=M/P) of the same-length length M, but the code length N, the information length K, the number of rows of the unit of the tour structure P, and the number q (=M/P) are not limited. Above the above values.

That is, in the transmitting apparatus 11 of Fig. 8, the LDPC encoding unit 21 outputs, for example, the number of lines in which the code length N is set to 64800 or 16200, the information length K is set to N-Pq (=NM), and the tour structure is respectively. P is set to 360 and the divisor q is set as the M/P LDPC code, but the LDPC decoding unit 56 of FIG. 76 takes the LDPC code as the object and performs P check node operations and variable node operations simultaneously. It can also be applied in the case of LDPC decoding.

Then, the series of processes described above may be performed by hardware or by software. When a series of processing is performed by software, the program constituting the software is installed in a general-purpose computer or the like.

Therefore, Fig. 77 is a view showing an example of a configuration in which one of the computers having the program for executing the above-described series of processes is installed.

The program can be recorded in advance on a hard disk 705 or a ROM 703 which is built in a computer as a recording medium.

Alternatively, the program can be temporarily or permanently stored (recorded) on a floppy disk, CD-ROM (Compact Disc Read Only Memory), MO (Magneto Optical) disc, and DVD (Digital). Versatile Disc: Digital versatile disc), magnetic disc, semiconductor memory and other portable recording media 711. This type of portable recording medium 711 can be provided as a so-called packaged software.

In addition, the program is installed on the portable recording medium 711 as described above, and can be wirelessly transmitted to the computer via the LAN (Local Area Network) from the download page via the artificial satellite for digital satellite broadcasting. The network of the Internet is transmitted to the computer by wire, and the program transmitted by the communication unit 708 is received by the computer 708 and installed on the built-in hard disk 705.

A CPU (Central Processing Unit) 702 is built in the computer system. In the CPU 702, an input/output interface 710 is connected via the bus bar 701, and when the input/output interface 710 is used by the user, the input unit 707 composed of a keyboard, a mouse, a microphone, or the like is operated by the user to input an instruction. The CPU 702 executes a program stored in a ROM (Read Only Memory) 703 in accordance therewith. Alternatively, the CPU 702 reads a program stored in the hard disk 705, a program transmitted from the satellite or the network, received by the communication unit 708, and mounted on the hard disk 705, or read from the portable recording medium 711 loaded on the disk drive 709. The program that is installed and installed on the hard disk 705 is loaded into a RAM (Random Access Memory) 704 and executed. Thereby, the CPU 702 performs the processing according to the above-described flowchart or the processing performed by the configuration of the above-described block map. Then, the CPU 702 outputs the processing result to the output unit 706 including an LCD (Liquid Crystal Display), a speaker, or the like via the input/output interface 710 as necessary, or transmits it from the communication unit 708, and further causes it to Recorded on hard disk 705, etc.

Here, the processing steps of the program for causing the computer to perform various processes are described in the present specification, and it is not necessary to process them in time series according to the sequence described in the flowchart, and also includes processing performed in parallel or individually (for example, juxtaposition Handling or handling by object).

Moreover, the program can be processed by one computer or distributed by a plurality of computers. Further, the program can also be transferred to a remote computer for execution.

Next, the processing of LDPC encoding by the LDPC encoding unit 21 of the transmitting device 11 will be further described.

For example, in the specification of DVB-S.2, there are two LDPC codes of code length N of 64800 bits and 16200 bits.

Then, regarding the LDPC code having a code length N of 64,800 bits, 11 coding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/ are specified. 5, 5/6, 8/9, and 9/10. For an LDPC code with a code length N of 16,200 bits, 10 encoding rates of 1/4, 1/3, 2/5, 1/2, 3/ are specified. 5, 2/3, 3/4, 4/5, 5/6 and 8/9.

The LDPC encoding unit 21 encodes the LDPC code of each encoding rate of 64800 bits or 16200 bits according to the check matrix H prepared according to the code length N and the coding rate (error correction coding). ).

In other words, the LDPC encoding unit 21 stores an inspection matrix initial value table to be described later for generating the inspection matrix H for each code length N and coding rate.

Here, in the specification of DVB-S.2, as described above, there are two LDPC codes of code length N of 64800 bits and 16200 bits, and 11 codes are respectively specified for the LDPC code of code length N of 64800 bits. The rate is about 10 encoding rates for an LDPC code having a code length N of 16,200 bits.

Therefore, when the transmitting apparatus 11 processes the apparatus according to the specifications of DVB-S.2, the LDPC encoding unit 21 stores an inspection matrix corresponding to 11 encoding rates for the LDPC codes having a code length N of 64,800 bits. The initial value table and the LDPC code having a code length N of 16,200 bits respectively correspond to a check matrix initial value table of 10 coding rates.

The LDPC encoding unit 21 sets the code length N and the encoding rate r of the LDPC code in response to, for example, an operator's operation. Here, the code length N and the coding rate r set by the LDPC encoding unit 21 are also referred to as a set code length N and a set coding rate r, respectively.

The LDPC encoding unit 21 sets the information length K corresponding to the set code length N and the set coding rate r according to the check matrix initial value table corresponding to the set code length N and the set coding rate r (=Nr=code length N-co-location The element of the information matrix H _A of the length M) is arranged in the row direction every cycle of 360 lines (the number of rows P of the circuit structure) to generate the inspection matrix H.

Then, the LDPC encoding unit 21 extracts information bits of the information length K from the target data to be transmitted, such as image data or audio data supplied to the transmitting device 11. Further, the LDPC encoding unit 21 calculates a codeword (LDPC code) of one code length for the parity bit of the information bit based on the inspection matrix H.

That is, the LDPC encoding unit 21 sequentially calculates the parity bits of the code word c conforming to the following equation.

Hc ^T =0

Here, in the above formula, c represents a column vector as a codeword (LDPC code), and c ^T represents a transposition of the column vector c.

In the column vector c of the LDPC code (1 codeword), the column vector A represents a portion of the information bit, and in the case where the column vector T represents a portion of the parity bit, the column vector c can be used as the information bit. The column vector A and the column vector T which is a parity bit are expressed by the equation c=[A|T].

Moreover, the check matrix H can be represented by the information matrix H _A corresponding to the information bit in the code bit of the LDPC code, and the parity matrix H _T corresponding to the co-located bit, as the formula H=[H _A | H _T ] (The elements of the information matrix H _A are set to the left side element, and the elements of the parity matrix H _T are set to the matrix of the right side element).

Further, for example, in the specification of DVB-S.2, the parity matrix H _T of the check matrix H = [H _A | H _T ] is a stepped structure.

Check matrix H and as an LDPC code of the column vector c = [A | T] must meet the formula Hc ^T = 0, as a constituent in line with the formula Hc ^T = 0 of the column vector c = [A | T] The nibble of the same column vector T, Keji since check matrix _{H = [H A | H T} ] of the parity matrix H _T be the case where the stepped structure, the row vector Hc ^T = 0 of formula Hc ^T from the elements of the first column, by sequentially The elements of each column are zero and can be obtained sequentially.

When the LDPC encoding unit 21 finds the parity bit T for the information bit A, the code word c=[A|T] represented by the information bit A and the parity bit T is used as the LDPC of the information bit A. The result is encoded and output.

As described above, the LDPC encoding unit 21 stores the code length N and the check matrix initial value table corresponding to each code rate r, and sets the LDPC code of the set code rate r of the code length N from the set code length N and corresponds to The inspection matrix H generated by the inspection matrix initial value table of the coding rate r is set.

Check matrix initial value table system checks the corresponding matrix H is to the response to the LDPC code (LDPC code by parity check matrix H as defined in the) of the code elements of a length N and information length encoding rate r of the K of the information matrix H _A of the The position is expressed in a table of every 360 lines (the number of rows P of the circuit structure), and is prepared one by one according to the code length N and the inspection matrix H of each coding rate r.

78 to 123 show an inspection matrix initial value table for generating various inspection matrices H including the inspection matrix initial value table defined by the specifications of DVB-S.2.

That is, Fig. 78 shows an inspection matrix initial value table of the inspection matrix H for which the coding rate r of the code length N is 16,200 bits is 2/3 as defined by the specification of DVB-S.2.

79 to 81 show the check matrix initial value table of the check matrix H for which the code rate r of 64800 bits is 2/3 as defined by the specification of DVB-S.2.

In addition, FIG. 80 is continued from FIG. 79, and FIG. 81 is continued from FIG.

Fig. 82 is a table showing an initial value of the check matrix of the check matrix H for which the code rate R of 16200 bits is 3/4 as defined by the specification of DVB-S.2.

83 to 86 show the check matrix initial value table of the check matrix H for which the code rate R of 64800 bits is 3/4 as defined by the specification of DVB-S.2.

In addition, FIG. 84 is continued from FIG. 83, and FIG. 85 is continued from FIG. Moreover, Fig. 86 is continued from Fig. 85.

Fig. 87 is a table showing an initial value of the check matrix of the check matrix H for which the code rate r of 16200 bits is 4/5 as defined by the specification of DVB-S.2.

88 to 91 show the check matrix initial value table of the check matrix H for which the code rate R of 64800 bits is 4/5 as defined by the specification of DVB-S.2.

In addition, FIG. 89 is continued from FIG. 88, and FIG. 90 is continued from FIG. Further, Fig. 91 is continued from Fig. 90.

Fig. 92 is a table showing the check matrix initial value of the check matrix H for which the code rate n of the code length r is 5/6, which is defined by the specification of DVB-S.2, is 5/200.

Fig. 93 to Fig. 96 are diagrams showing the check matrix initial value table of the check matrix H for which the code rate R of 64800 bits is 5/6 as defined by the specification of DVB-S.2.

In addition, FIG. 94 is continued from FIG. 93, and FIG. 95 is continued from FIG. Moreover, Fig. 96 is continued from Fig. 95.

Fig. 97 is a table showing the check matrix initial value of the check matrix H for which the code rate N of 16200 bits is 8/9 as defined by the specification of DVB-S.2.

98 to 101 show the check matrix initial value table of the check matrix H for which the code rate R of 64800 bits is 8/9 as defined by the specification of DVB-S.2.

In addition, FIG. 99 is continued from FIG. 98, and FIG. 100 is continued from FIG. Moreover, Fig. 101 is continued from the diagram of Fig. 100.

Fig. 102 to Fig. 105 are diagrams showing an inspection matrix initial value table of the inspection matrix H for which the coding rate r of the code length N is 64,800 bits is 9/10, which is defined by the specification of DVB-S.2.

In addition, FIG. 103 is continued from the diagram of FIG. 102, and FIG. 104 is continued from FIG. Moreover, Fig. 105 is continued from the diagram of Fig. 104.

Fig. 106 and Fig. 107 show the check matrix initial value table of the check matrix H for which the code rate r of 64800 bits is 1/4 as defined by the specification of DVB-S.2.

In addition, FIG. 107 is continued from the diagram of FIG.

Fig. 108 and Fig. 109 are diagrams showing an inspection matrix initial value table of the inspection matrix H for which the coding rate r of the code length N is 64,800 bits is 1/3, which is defined by the specification of DVB-S.2.

Moreover, Fig. 109 is continued from the diagram of Fig. 108.

Fig. 110 and Fig. 111 are diagrams showing an inspection matrix initial value table of the inspection matrix H for which the coding rate r of the code length N is 64,800 bits is 2/5, which is defined by the specification of DVB-S.2.

In addition, FIG. 111 is continued from the diagram of FIG.

Fig. 112 to Fig. 114 are diagrams showing an inspection matrix initial value table of the inspection matrix H for which the coding rate r of the code length N is 64,800 bits is 1/2, which is defined by the specification of DVB-S.2.

In addition, FIG. 113 is continued from FIG. 112, and FIG. 114 is continued from FIG.

Fig. 115 to Fig. 117 are diagrams showing an inspection matrix initial value table of the inspection matrix H for which the coding rate r of the code length N is 64,800 bits is 3/5, which is defined by the specification of DVB-S.2.

In addition, FIG. 116 is continued from FIG. 115, and FIG. 117 is continued from FIG.

Fig. 118 is a table showing an initial value of the check matrix of the check matrix H for which the code rate r of the code length N is 16,200 bits is 1/4 as defined by the specification of DVB-S.2.

Figure 119 is a table showing an initial value of the check matrix of the check matrix H for which the code rate r of the code length N is 16,200 bits is 1/3 as defined by the specification of DVB-S.2.

Fig. 120 is a table showing an initial value of the check matrix of the check matrix H for which the code rate r of the code length N is 16,200 bits is 2/5 as defined by the specification of DVB-S.2.

Fig. 121 is a table showing an initial value of the check matrix of the check matrix H for which the code rate r of the code length N is 16,200 bits is 1/2 as defined by the specification of DVB-S.2.

Fig. 122 is a table showing an initial value of the check matrix of the check matrix H for which the code rate R of the code length N is 16,200 bits is 3/5 as defined in the specification of DVB-S.2.

Fig. 123 is a table showing the check matrix initial value of the check matrix H for which the code rate r is 3/5, which can be used in place of the check matrix initial value table of Fig. 122.

The LDPC encoding unit 21 of the transmitting device 11 uses the inspection matrix initial value table to obtain the inspection matrix H as follows.

That is, Fig. 124 shows a method of obtaining the inspection matrix H from the inspection matrix initial value table.

Further, the check matrix initial value table of FIG. 124 indicates a check matrix of the check matrix H having a code length N of 16200 bits as specified in the specification of DVB-S.2 shown in FIG. 78 of 2/3. Initial value table.

The check matrix initial value table is as described above, and corresponds to the position of the element of the information matrix H _A corresponding to the code length N of the LDPC code and the information length K of the coding rate r, for every 360 lines (the row of the tour structure unit) In the table of the number P), in the i-th column, check the column number of the element of the 1+360×(i-1) row of the matrix H (the column number of the first column of the check matrix H is set to 0) The column number is only the number of row weights that the row of the 1+360×(i-1) row has.

Here, the parity matrix H _T corresponding to the co-located length M of the check matrix H is a stepped structure, which is determined in advance. According to the inspection matrix initial value table, the information matrix HA corresponding to the information length K in the inspection matrix H can be obtained.

The number of columns k+1 of the check matrix initial value table differs depending on the information length K.

Between the information length K and the number k+1 of the check matrix initial value table, the relationship of the following formula holds.

K=(k+1)×360

Here, 360 of the above formula is the number of rows P of the unit of the tour structure.

In the check matrix initial value table of Fig. 124, 13 values are arranged from the 1st column to the 3rd column, and three values are arranged from the 4th column to the k+1th column (the 30th column in Fig. 124).

Therefore, the row weight of the check matrix H obtained from the check matrix initial value table of Fig. 124 is from the 1st line to the 1+360×(3-1)-1 behavior 13 from the 1+360×(3) -1) Go to the Kth act 3.

The first column of the check matrix initial value table of FIG. 124 is 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622, which is shown in the first row of the inspection matrix H. The elements whose column numbers are 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622 are 1 (and other elements are 0).

Moreover, the second column of the check matrix initial value table of FIG. 124 is 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, 3108, which is shown in the check matrix H. The 361 (=1+360×(2-1)) row has elements of column numbers 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, and 3108.

As described above, the check matrix initial value table indicates the position of the element of the information matrix H _A of the matrix H to be expressed every 360 lines.

Checking the lines other than the 1+360×(i-1) line of the matrix H, that is, the lines from the 2+360×(i-1) line to the 360×i line will be checked by the matrix initial value table. The element 1 of the 1st + 360 × (i-1) line determined is periodically cyclically shifted in accordance with the same length M (downward direction).

That is, for example, the 2+360×(i-1) line only cyclically shifts the 1+360×(i-1) line downward by M/360 (=q), and then the 3+360× (i-1) The line is rotated by 2×M/360 (=2×q) in the downward direction of the 1+360×(i-1) line (the 2+360×(i-1) line will be Only rotate M/360 (=q) in the downward direction.

Now, if the value of the jth row (jth from the left) of the i-th column (the i-th from the top) of the check matrix initial value table is expressed as h _i,j , and the w of the matrix H will be checked. line of the j-th of the elements of the a number represented as H _wj, check the elements of the w-th row of the rows of the outside of the matrix H of the first 1 + 360 × (i-1 ) row a number H _WJ by The following formula is obtained.

H _wj = mod{h _i,j +mod((w-1),P)×q,M)

Here, mod(x, y) means the remainder after dividing y by x.

Further, P is the number of rows of the above-mentioned tour structure, for example, the specification of DVB-S.2 is 360. Further, q is a value M/360 obtained by dividing the parity length M by the number of rows P (= 360) of the unit of the tour structure.

The LDPC encoding unit 21 specifies the column number of the element of the first +360 × (i-1) line of the inspection matrix H by checking the matrix initial value table.

Further, the LDPC encoding unit 21 obtains the column number H _wj of the element of the w-th row of the row other than the 1+360×(i-1) row of the inspection matrix H, and generates the obtained by the above. The element of the column number is set as the inspection matrix H of 1.

Next, a description will be given of an alternative manner of the code bit of the LDPC code by the replacement unit 32 of the demultiplexer 25 of the transmitting device 11, that is, the code bit of the LDPC code and the symbol representing the symbol. The change of the bit allocation mode (hereinafter also referred to as the bit allocation mode).

In the demultiplexer 25, the code bits of the LDPC code are written in the wale direction of the memory 31 in the wale direction x column direction (N/(mb))×(mb) bits, and thereafter The mb bit unit is read in the horizontal direction. Further, in the demultiplexer 25, the replacement bit 32 is replaced with the code bit of the mb bit read in the course direction of the memory 31, and the replaced code bit becomes (continuous) b symbols. The oct bit of the mb bit.

That is, the replacing unit 32 counts the i+1th bit from the highest order bit of the code bit of the mb bit read from the course direction of the memory 31 as the code bit b _i , and will Continuously) the highest order bit of the mb bit of the b-bit symbol, the i+1th bit is used as the symbol bit y _i , and the code of the mb bit is replaced according to the specific bit allocation pattern. Bits b ₀ to b _mb-1 .

Figure 125 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6 or 9/10. The bit modulation can be used in the case where the modulation mode is 4096QAM and the multiple b is 1. An example of a pattern.

The LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 5/6 or 9/10. In the case where the modulation mode is 4096QAM and the multiple b is 1, the multiplexer 25 is used in the traversing. The memory bit written by the memory 31 whose direction × course direction is (64800/(12 × 1)) × (12 × 1) bits is in the course direction, in units of 12 × 1 (= mb) bits It is read out and supplied to the replacement unit 32.

The replacing unit 32 assigns the code bits b ₀ to b ₁₁ read from the 12 × 1 (= mb) bits of the memory 31 to 12 × 1 of 1 (= b) symbols as shown in FIG. The (= mb) bit symbols y ₀ to y ₁₁ are replaced by the code bits b ₀ to b _{11 of} 12 × 1 (= mb) bits.

That is, according to FIG. 125, the replacing unit 32 is an LDPC code having an encoding rate of 5/6 and an LDPC code having a coding rate of 9/10 in an LDPC code having a code length N of 64,800 bits. An LDPC code is respectively assigned: a code bit b _{0 is} assigned to a symbol bit y ₈ , a code bit b _{1 is} assigned to a symbol bit y ₀ , and a code bit b _{2 is} assigned to a symbol bit y ₆ , the code bit b _{3 is} assigned to the symbol bit y ₁ , the code bit b _{4 is} assigned to the symbol bit y ₄ , and the code bit b _{5 is} assigned to the symbol bit y ₅ , and the code bit is b _{6 is} assigned to the symbol bit y ₂ , the code bit b _{7 is} assigned to the symbol bit y ₃ , the code bit b _{8 is} assigned to the symbol bit y ₇ , and the code bit b _{9 is} assigned to the symbol The meta-bit y ₁₀ assigns the code bit b ₁₀ to the symbol bit y ₁₁ and assigns the code bit b ₁₁ to the symbol bit y ₉ for replacement.

Figure 126 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6 or 9/10. The bit modulation can be used in the case where the modulation mode is 4096QAM and the multiple b is 2. An example of a pattern.

The LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 5/6 or 9/10. In the case where the modulation mode is 4096QAM and the multiple b is 2, the multiplexer 25 is used in the traversing. The memory bit written by the memory 31 whose direction × course direction is (64800/(12 × 2)) × (12 × 2) bits is in the course direction, in units of 12 × 2 (= mb) bits It is read out and supplied to the replacement unit 32.

The replacing unit 32 is configured to assign the code bits b ₀ to b ₂₃ read from the 12 × 2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. The code bits p ₀ to b _{23 of} 12 × 2 (= mb) bits are replaced by the manner of the symbol bits y ₀ to y ₂₃ of × 2 (= mb) bits.

That is, according to FIG. 126, the replacing unit 32 is an LDPC code having an encoding rate of 5/6 in an LDPC code having a code length N of 64,800 bits, and an LDPC code having a coding rate of 9/10. An LDPC code is respectively assigned: a code bit b _{0 is} assigned to the symbol bit y ₈ , a code bit b _{2 is} assigned to the symbol bit y ₀ , and a code bit b _{4 is} assigned to the symbol bit y ₆ , the code bit b _{6 is} assigned to the symbol bit y ₁ , the code bit b _{8 is} assigned to the symbol bit y ₄ , and the code bit b _{10 is} assigned to the symbol bit y ₅ , and the code bit is assigned b _{12 is} assigned to the symbol bit y ₂ , the code bit b _{14 is} assigned to the symbol bit y ₃ , the code bit b _{16 is} assigned to the symbol bit y ₇ , and the code bit b _{18 is} assigned to the symbol The meta-bit y ₁₀ assigns the code bit b ₂₀ to the symbol bit y ₁₁ , assigns the code bit b ₂₂ to the symbol bit y ₉ , and assigns the code bit b ₁ to the symbol bit y ₂₀ , the code bit b _{3 is} assigned to the symbol bit y ₁₂ , the code bit b _{5 is} assigned to the symbol bit y ₁₈ , and the code bit b _{7 is} assigned to the symbol bit y ₁₃ , and the code bit is assigned b ₉ to the symbol bit y _16, the code bit b ₁₁ to the symbol bit y _17, the code bit b ₁₃ to the symbol Yuan y _14, the code bit b ₁₅ to the symbol bit y _15, the code bit b ₁₇ to the symbol bit y _19, the code bit b ₁₉ to the symbol bit y _22, the The code bit b _{21 is} assigned to the symbol bit y ₂₃ , and the code bit b _{23 is} assigned to the symbol bit y ₂₁ for replacement.

Here, the bit allocation pattern of FIG. 126 is a bit allocation pattern of FIG. 125 in the case where the multiple b is directly used. That is, in FIG. 126, the allocation manner of the code bit b ₀ , b ₂ , . . . , b ₂₂ to the symbol bit y ₁ and the parity of the code bit b ₁ , b ₃ , . . . , b ₂₃ bit allocation element y _i of the b ₀ to b ₁₁ are both identical to the symbol bit y _i assigned the code bits of the embodiment 125 of FIG.

127 is a diagram showing that the modulation mode is 1024QAM, and the LDPC code is an LDPC code having a code length N of 16,200 bits, a coding rate of 3/4, 5/6, or 8/9, and a multiple b is 2, and an LDPC code. It is an example of a bit allocation pattern that can be used in the case where the code length N is 64,800 bits, the coding rate is 3/4, 5/6, or 9/10, and the multiple b is 2.

The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/4, 5/6 or 8/9. In the case where the modulation mode is 1024QAM and the multiple b is 2, the multiplexer 25 is used. The code bit written in the memory direction 31 in the wale direction × course direction is (16200 / (10 × 2)) × (10 × 2) bits in the course direction, at 10 × 2 (= mb The bit unit is read out and supplied to the replacement unit 32.

Moreover, the LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 3/4, 5/6 or 9/10, and further modulating the mode to 1024QAM and the multiple b to 2, The memory element written in the memory 31 in the wale direction × the horizontal direction is (64800/(10×2))×(10×2) bits is in the course direction, at 10×2 ( The =mb) bit unit is read out and supplied to the replacement unit 32.

The replacing unit 32 is configured to assign the code bits b ₀ to b ₁₉ read from the 10 × 2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. The code bits p ₀ to b _{19 of} 10 × 2 (= mb) bits are replaced by the manner of the symbol bits y ₀ to y ₁₉ of × 2 (= mb) bits.

That is, according to FIG. 127, the replacing unit 32 is an LDPC code having an encoding rate of 3/4 in an LDPC code having a code length N of 16,200 bits, an LDPC code having a coding rate of 5/6, and a coding rate of 8/. An LDPC code of 9 and an LDPC code having a coding rate of 3/4 in an LDPC code having a code length N of 64,800 bits, an LDPC code having a coding rate of 5/6, and an LDPC code having a coding rate of 9/10, Regarding any of the LDPC codes, respectively, the code bit b _{0 is} assigned to the symbol bit y ₈ , the code bit b _{1 is} assigned to the symbol bit y ₃ , and the code bit b _{2 is} assigned to the symbol bit y ₇ , assigning the code bit b ₃ to the symbol bit y ₁₀ , assigning the code bit b ₄ to the symbol bit y ₁₉ , and assigning the code bit b ₅ to the symbol bit y ₄ , the code Bit b _{6 is} assigned to symbol bit y ₉ , code bit b _{7 is} assigned to symbol bit y ₅ , code bit b _{8 is} assigned to symbol bit y ₁₇ , and bit bit b _{9 is} assigned For the symbol bit y ₆ , the code bit b _{10 is} assigned to the symbol bit y ₁₄ , the code bit b _{11 is} assigned to the symbol bit y ₁₁ , and the code bit b _{12 is} assigned to the symbol bit y ₂ , the code bit b _{13 is} assigned to the symbol bit y ₁₈ , the code bit b _{14 is} assigned to the symbol bit y ₁₆ , and the code bit b is _{15 is} assigned to the symbol bit y ₁₅ , the code bit b _{16 is} assigned to the symbol bit y ₀ , the code bit b _{17 is} assigned to the symbol bit y ₁ , and the code bit b _{18 is} assigned to the symbol The bit y ₁₃ assigns the code bit b ₁₉ to the symbol bit y ₁₂ and replaces it.

Figure 128 is a diagram showing that the modulation mode is 4096QAM, and the LDPC code is an LDPC code having a code length N of 16,200 bits, a coding rate of 5/6 or 8/9, a multiple b is 2, and an LDPC code is a code length N. An example of a bit allocation pattern that can be used in the case of a 64800-bit LDPC code having a coding rate of 5/6 or 9/10 and a multiple b of 2.

The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6 or 8/9. In the case where the modulation method is 4096QAM and the multiple b is 2, the multiplexer 25 is used in the traversing. The code bits written by the memory 31 whose direction × course direction is (16200/(12×2))×(12×2) bits are in the course direction, in units of 12×2 (= mb) bits. It is read out and supplied to the replacement unit 32.

Moreover, the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6 or 9/10. In the case where the modulation method is 4096QAM and the multiple b is 2, the multiplexer 25 is The code direction written by the memory 31 in the wale direction × course direction is (64800/(12 × 2)) × (12 × 2) bits is in the course direction, with 12 × 2 (= mb) bits The unit is read out and supplied to the replacement unit 32.

The replacing unit 32 is configured to assign the code bits b ₀ to b ₂₃ read from the 12 × 2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. The code bits p ₀ to b _{23 of} 12 × 2 (= mb) bits are replaced by the manner of the symbol bits y ₀ to y ₂₃ of × 2 (= mb) bits.

That is, according to FIG. 128, the replacing unit 32 is an LDPC code having an encoding rate of 5/6 and an LDPC code having an encoding rate of 8/9 in an LDPC code having a code length N of 16,200 bits, and a code length N being For an LDPC code with a coding rate of 5/6 and an LDPC code with a coding rate of 9/10 in an LDPC code of 64,800 bits, for any LDPC code, respectively, the code bit b _{0 is} assigned to the symbol bit. y ₁₀ , assigning the code bit b ₁ to the symbol bit y ₁₅ , assigning the code bit b ₂ to the symbol bit y ₄ , and assigning the code bit b ₃ to the symbol bit y ₁₉ , the code Bit b _{4 is} assigned to symbol bit y ₂₁ , code bit b _{5 is} assigned to symbol bit y ₁₆ , code bit b _{6 is} assigned to symbol bit y ₂₃ , and bit bit b _{7 is} assigned To the symbol bit y ₁₈ , the code bit b _{8 is} assigned to the symbol bit y ₁₁ , the code bit b _{9 is} assigned to the symbol bit y ₁₄ , and the code bit b _{10 is} assigned to the symbol bit . y ₂₂ , assigning the code bit b ₁₁ to the symbol bit y ₅ , assigning the code bit b ₁₂ to the symbol bit y ₆ , and assigning the code bit b ₁₃ to the symbol bit y ₁₇ , the code Bit b _{14 is} assigned to symbol bit y ₁₃ , code bit b _{15 is} assigned to symbol bit y ₂₀ , and code bit b _{16 is} divided Assigning the symbol bit y ₁ , assigning the code bit b ₁₇ to the symbol bit y ₃ , assigning the code bit b ₁₈ to the symbol bit y ₉ , and assigning the code bit b ₁₉ to the symbol bit y ₂ , the code bit b _{20 is} assigned to the symbol bit y ₇ , the code bit b _{21 is} assigned to the symbol bit y ₈ , and the code bit b _{22 is} assigned to the symbol bit y ₁₂ , the code is Bit b _{23 is} assigned to the symbol bit y ₀ and is replaced.

According to the bit allocation pattern shown in FIG. 125 to FIG. 128, the LDPC code of the plural type can adopt the same bit allocation mode, and any one of the LDPC codes of the plural type can make tolerance to errors. Sex becomes the required performance.

That is, FIGS. 129 to 132 show simulation results of BER (Bit Error Rate) in the case where replacement processing is performed in accordance with the bit allocation pattern of FIGS. 125 to 128.

Further, in FIGS. 129 to 132, the horizontal axis represents E _s /N ₀ (signal power to noise power ratio per symbol), and the vertical axis represents BER.

Further, the solid line indicates the BER in the case where the replacement processing has been performed, and the one-dot chain indicates the BER in the case where the replacement processing is not performed.

129 is an LDPC code for which the code length N is 64800 and the coding rates are 5/6 and 9/10, respectively, and 4096QAM is used as the modulation method, and the multiple b is set to 1, and the replacement processing is performed according to the bit allocation pattern of FIG. The BER in the case.

Figure 130 shows an LDPC code with a code length N of 64800 and a coding rate of 5/6 and 9/10, respectively. 4096QAM is used as the modulation method, and the multiple b is set to 2, and the replacement processing is performed according to the bit allocation pattern of Fig. 126. The BER in the case.

Further, in FIGS. 129 and 130, a graph with a triangular mark indicates a BER with respect to an LDPC code having a coding rate of 5/6, and a graph with a star mark (star mark) indicates that the coding rate is 9/10. The BER of the LDPC code.

Figure 131 shows an LDPC code and a code length N of 64800 for a code length N of 16200 and a coding rate of 3/4, 5/6, and 8/9, respectively, and encoding rates of 3/4, 5/6, and 9/, respectively. The LDPC code of 10 uses 1024QAM as the modulation method, and the multiple b is set to 2, and the BER in the case of performing the replacement processing according to the bit allocation pattern of FIG.

Further, in Fig. 131, a graph attached with a star indicates a BER with respect to an LDPC code having a code length N of 64800 and a coding rate of 9/10, and a graph with an upward triangular mark indicates that the code length N is 64,800. The BER of the LDPC code with a coding rate of 5/6. Moreover, the graph with square marks indicates the BER of the LDPC code with a code length N of 64800 and a coding rate of 3/4.

Further, in FIG. 131, a graph with a circle mark indicates a BER with respect to an LDPC code having a code length N of 16200 and an encoding rate of 8/9, and a graph with a downward triangular mark indicating a code length N. It is 16200, and the BER of the LDPC code with a coding rate of 5/6. Moreover, the graph with the positive sign indicates the BER of the LDPC code with a code length N of 16200 and a coding rate of 3/4.

Figure 132 is a diagram showing an LDPC code having a code length N of 16200, a coding rate of 5/6 and 8/9, and an LDPC code having a code length N of 64800 and a coding rate of 5/6 and 9/10, respectively. The mode adopts 4096QAM, and the multiple b is set to 2, and the BER in the case of performing the replacement processing according to the bit allocation mode of FIG.

Further, in FIG. 132, a graph attached with a star indicates a BER with respect to an LDPC code having a code length N of 64800 and a coding rate of 9/10, and a graph with an upward triangular mark indicates that the code length N is 64,800. The BER of the LDPC code with a coding rate of 5/6.

Further, in Fig. 132, a graph with a circle mark indicates a BER with respect to an LDPC code having a code length N of 16200 and a coding rate of 8/9, and a graph with a downward triangular mark indicates that the code length N is 16,200. The BER of the LDPC code with a coding rate of 5/6.

As can be seen from FIG. 129 to FIG. 132, the same bit allocation mode can be used for the plural types of LDPC codes, and tolerance to errors can be made with respect to any of the plural types of LDPC codes using the same bit allocation pattern. Become the required performance.

In other words, when a plurality of types of LDPC codes having different code lengths or coding rates are used in the bit allocation mode dedicated to the LDPC code, the tolerance to errors is extremely high, but it must be different. The LDPC code of the type changes the bit allocation mode one by one.

On the other hand, according to the bit allocation pattern of FIG. 125 to FIG. 128, the same bit allocation mode can be adopted for each of the plural types of LDPC codes having different code lengths or encoding rates, and it is not necessary to adopt the respective types of LDPC codes. In the case of the bit allocation mode dedicated to the LDPC code, the bit allocation pattern is changed one by one for different types of LDPC codes.

Further, according to the bit allocation pattern of FIG. 125 to FIG. 128, for each of the plural types of LDPC codes, even if the bit allocation mode dedicated to the LDPC code is slightly used, even if this is still possible, the error can be made. The tolerance is high performance.

That is, for example, in the case where the modulation mode is 4096QAM, for an LDPC code having a code length N of 64800 and a coding rate of 5/6 and 9/10, respectively, any LDPC code can be used as shown in FIG. 125 or FIG. The same bit allocation mode. Then, even if the same bit allocation mode is employed, the tolerance to errors can be made high performance.

Further, for example, in the case where the modulation mode is 1024QAM, the LDPC code having a code length N of 16200 and a coding rate of 3/4, 5/6, and 8/9, respectively, and a code length N of 64800, respectively, are respectively encoded. For the LDPC codes of 3/4, 5/6 and 9/10, the same bit allocation pattern of Fig. 127 can be used for any LDPC code. Then, even if the same bit allocation mode is employed, the tolerance to errors can be made high performance.

Moreover, for example, in the case where the modulation mode is 4096QAM, the LDPC code having a code length N of 16200 and a coding rate of 5/6 and 8/9, respectively, and a code length N of 64800 and a coding rate of 5/6 and 9 respectively. For the LDPC code of /10, the same bit allocation pattern of FIG. 128 can be used for any LDPC code. Then, even if the same bit allocation mode is employed, the tolerance to errors can be made high performance.

Further explanation of the change in the bit allocation pattern.

Figure 133 is a diagram showing the coding rate of an LDPC code whose code length N is 16200 or 64800 bits and whose code rate is determined by, for example, the check matrix H generated from the check matrix initial value table shown in Figs. 78 to 123, in the LDPC code. An example of a bit allocation pattern that can be used in the case where the LDPC code other than 3/5 is further modulated by QPSK and the multiple b is 1.

The LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and a coding rate of 3/5. In the case where the modulation method is QPSK and the multiple b is 1, the multiplexer 25 is in the traverse direction. × The code bits written in the memory 31 of the (N/(2 × 1)) × (2 × 1) bits in the course direction are in the course direction, and are read in 2 × 1 (= mb) bit units. It is supplied to the replacement unit 32.

The replacing unit 32 assigns the code bits b ₀ and b ₁ read from the 2 × 1 (= mb) bits of the memory 31 to 2 × 1 of 1 (= b) symbols as shown in FIG. (= mb) The symbol bits y ₀ and y ₁ of the bit are replaced by the code bits b ₀ and b _{1 of the} 2 × 1 (= mb) bits.

That is, according to Fig. 133, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₀ and assigns the code bit b ₁ to the symbol bit y ₁ , respectively.

Further, in this case, it is also possible to consider not to replace, and the code bits b ₀ and b ₁ are directly used as the symbol bits y ₀ and y _{1 , respectively} .

Figure 134 is a diagram showing that the LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and an encoding rate of 3/5. The bit allocation mode can be adopted when the modulation mode is 16QAM and the multiple b is 2. An example.

The LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 16QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction. × The code bit written in the memory 31 of the (N/(4 × 2)) × (4 × 2) bit direction is in the course direction, and is read in units of 4 × 2 (= mb) bits. It is supplied to the replacement unit 32.

The replacing unit 32 is configured to assign the code bits b ₀ to b ₇ read from the 4 × 2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. The code bits p ₀ to b _{7 of} 4 × 2 (= mb) bits are replaced by the manner of the symbol bits y ₀ to y ₇ of × 2 (= mb) bits.

That is, according to FIG. 134, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₇ and the code bit b ₁ to the symbol bit y ₁ , and the code bit b ₂ Assigned to the symbol bit y ₄ , the code bit b _{3 is} assigned to the symbol bit y ₂ , the code bit b _{4 is} assigned to the symbol bit y ₅ , and the code bit b _{5 is} assigned to the symbol bit The element y ₃ assigns the code bit b ₆ to the symbol bit y ₆ and assigns the code bit b ₇ to the symbol bit y ₀ for replacement.

135 is a diagram showing that the modulation mode is 64QAM, and the LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and a coding rate of 3/5, and the bit allocation mode can be used when the multiple b is 2. example.

The LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 64QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction. × The code bits written in the memory 31 of the (N/(6 × 2)) × (6 × 2) bits in the course direction are in the course direction, and are read in units of 6 × 2 (= mb) bits. It is supplied to the replacement unit 32.

The replacing unit 32 assigns the code bits b ₀ to b ₁₁ read from the 6 × 2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. The code bits p ₀ to b _{11 of} 6 × 2 (= mb) bits are replaced by the manner of the symbol bits y ₀ to y ₁₁ of × 2 (= mb) bits.

That is, according to FIG. 135, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₁₁ and the code bit b ₁ to the symbol bit y ₇ , and the code bit b ₂ Assigned to the symbol bit y ₃ , the code bit b _{3 is} assigned to the symbol bit y ₁₀ , the code bit b _{4 is} assigned to the symbol bit y ₆ , and the code bit b _{5 is} assigned to the symbol bit Element y ₂ , assigning code bit b ₆ to symbol bit y ₉ , assigning code bit b ₇ to symbol bit y ₅ , and assigning code bit b ₈ to symbol bit y ₁ , The code bit b _{9 is} assigned to the symbol bit y ₈ , the code bit b _{10 is} assigned to the symbol bit y ₄ , and the code bit b _{11 is} assigned to the symbol bit y ₀ for replacement.

FIG. 136 shows an example in which the modulation mode is 256QAM, and the LDPC code is an LDPC code having a code length N of 64,800 bits and an encoding rate of 3/5, and a multiple of b can be used.

The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 256QAM and the multiple b is 2, the multiplexer 25 is in the traversing direction. The code bits written in the memory 31 whose column direction is (64800/(8×2))×(8×2) bits are in the horizontal direction and are read in units of 8×2 (= mb) bits. And supplied to the replacement unit 32.

The replacing unit 32 is configured to assign the code bits b ₀ to b ₁₅ read from the 8 × 2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. The code bits p ₀ to b _{15 of} 8 × 2 (= mb) bits are replaced by the manner of the symbol bits y ₀ to y ₁₅ of × 2 (= mb) bits.

That is, according to FIG. 136, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₁₅ and the code bit b ₁ to the symbol bit y ₁ , and the code bit b ₂ Assigned to the symbol bit y ₁₃ , the code bit b _{3 is} assigned to the symbol y ₃ , the code bit b _{4 is} assigned to the symbol y ₈ , and the code bit b _{5 is} assigned to the symbol bit Element y ₁₁ , assigning code bit b ₆ to symbol bit y ₉ , assigning code bit b ₇ to symbol bit y ₅ , and assigning code bit b ₈ to symbol bit y ₁₀ , The code bit b _{9 is} assigned to the symbol bit y ₆ , the code bit b _{10 is} assigned to the symbol bit y ₄ , the code bit b _{11 is} assigned to the symbol bit y ₇ , and the code bit b _{12 is} assigned Assigned to the symbol bit y ₁₂ , the code bit b _{13 is} assigned to the symbol bit y ₂ , the code bit b _{14 is} assigned to the symbol bit y ₁₄ , and the code bit b _{15 is} assigned to the symbol bit The element y ₀ is replaced.

137 is a diagram showing an example in which the modulation mode is 256QAM, and the LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 3/5, and the multiple b is 1.

The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5. In the case where the modulation method is 256QAM and the multiple b is 1, the multiplexer 25 is in the traverse direction. The code bits written in the memory 31 whose column direction is (16200/(8×1))×(8×1) bits are in the horizontal direction and are read in units of 8×1 (= mb) bits. And supplied to the replacement unit 32.

The replacing unit 32 is configured to assign the code bits b ₀ to b ₇ read from the 8 × 1 (= mb) bits of the memory 31 to 8 × 1 of 1 (= b) symbols as shown in FIG. (= mb) The bit y ₀ to y ₇ of the bit are replaced by the code bits b ₀ to b _{7 of} 8 × 1 (= mb) bits.

That is, according to FIG. 137, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₇ and the code bit b ₁ to the symbol bit y ₃ , and the code bit b ₂ Assigned to the symbol bit y ₁ , the code bit b _{3 is} assigned to the symbol bit y ₅ , the code bit b _{4 is} assigned to the symbol bit y ₂ , and the code bit b _{5 is} assigned to the symbol bit The element y ₆ assigns the code bit b ₆ to the symbol bit y ₄ and assigns the code bit b ₇ to the symbol bit y ₀ for replacement.

Figure 138 is a diagram showing that the LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and a coding rate of 3/5. Further modulation mode is QPSK, and the multiple b is 1. example.

The LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and a coding rate of 3/5. When the modulation method is QPSK and the multiple b is 1, the multiplexer 25 is in the traverse direction. The code bits written in the memory 31 of the (N/(2×1))×(2×1) bit row are in the course direction, and are read out in 2×1 (=mb) bit units. And supplied to the replacement unit 32.

The replacing unit 32 assigns the code bits b ₀ and b ₁ read from the 2 × 1 (= mb) bits of the memory 31 to 2 × 1 of 1 (= b) symbols as shown in FIG. (= mb) The symbol bits y ₀ and y ₁ of the bit are replaced by the code bits b ₀ and b _{1 of the} 2 × 1 (= mb) bits.

That is, according to FIG. 138, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₀ and assigns the code bit b ₁ to the symbol bit y ₁ , respectively.

Further, in this case, it is also possible to consider not to replace, and the code bits b ₀ and b ₁ are directly used as the symbol bits y ₀ and y _{1 , respectively} .

Figure 139 is a diagram showing an example in which the LDPC code is an LDPC code having a code length N of 64,800 bits and an encoding rate of 3/5, and a bit allocation mode can be employed in the case where the modulation method is 16QAM and the multiple b is 2.

The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 16QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction × the traverse direction The code bits written in the memory 31 of the direction (64800/(4×2))×(4×2) bits are in the horizontal direction, and are read in units of 4×2 (=mb) bits, and It is supplied to the replacement unit 32.

The replacing unit 32 is configured to assign the code bits b ₀ to b ₇ read from the 4 × 2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. The code bits p ₀ to b _{7 of} 4 × 2 (= mb) bits are replaced by the manner of the symbol bits y ₀ to y ₇ of × 2 (= mb) bits.

That is, according to FIG. 139, the replacing unit 32 respectively assigns the code bit b ₀ to the symbol bit y ₀ , assigns the code bit b ₁ to the symbol bit y ₅ , and sets the code bit b ₂ Assigned to the symbol bit y ₁ , the code bit b _{3 is} assigned to the symbol bit y ₂ , the code bit b _{4 is} assigned to the symbol bit y ₄ , and the code bit b _{5 is} assigned to the symbol bit The element y ₇ assigns the code bit b ₆ to the symbol bit y ₃ and assigns the code bit b ₇ to the symbol bit y ₆ for replacement.

Fig. 140 is a diagram showing an example in which the LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 3/5, and a bit allocation pattern which can be employed in the case where the modulation method is 16QAM and the multiple b is 2.

The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5. In the case where the modulation method is 16QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction × the traverse direction The code bits written in the memory 31 of the direction (16200/(4×2))×(4×2) bits are in the course direction, and are read in units of 4×2 (=mb) bits, and It is supplied to the replacement unit 32.

The replacing unit 32 is configured to assign the code bits b ₀ to b ₇ read from the 4 × 2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. The code bits p ₀ to b _{7 of} 4 × 2 (= mb) bits are replaced by the manner of the symbol bits y ₀ to y ₇ of × 2 (= mb) bits.

That is, according to FIG. 140, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₇ and the code bit b ₁ to the symbol bit y ₁ , and the code bit b ₂ Assigned to the symbol bit y ₄ , the code bit b _{3 is} assigned to the symbol bit y ₂ , the code bit b _{4 is} assigned to the symbol bit y ₅ , and the code bit b _{5 is} assigned to the symbol bit The element y ₃ assigns the code bit b ₆ to the symbol bit y ₆ and assigns the code bit b ₇ to the symbol bit y ₀ for replacement.

Figure 141 shows an example in which the modulation mode is 64QAM, and the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and a multiple of the bit allocation mode.

The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 64QAM and the multiple b is 2, the multiplexer 25 is in the traversing direction. The code bits written in the memory 31 of the direction (64800/(6×2))×(6×2) bits are in the horizontal direction, and are read in units of 6×2 (=mb) bits, and It is supplied to the replacement unit 32.

The replacing unit 32 assigns the code bits b ₀ to b ₁₁ read from the 6 × 2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. The code bits p ₀ to b _{11 of} 6 × 2 (= mb) bits are replaced by the manner of the symbol bits y ₀ to y ₁₁ of × 2 (= mb) bits.

That is, according to FIG. 141, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₂ and the code bit b ₁ to the symbol bit y ₇ , and the code bit b ₂ Assigned to the symbol bit y ₆ , the code bit b _{3 is} assigned to the symbol bit y ₉ , the code bit b _{4 is} assigned to the symbol bit y ₀ , and the code bit b _{5 is} assigned to the symbol bit Element y ₃ , assigning code bit b ₆ to symbol bit y ₁ , assigning code bit b ₇ to symbol bit y ₈ , and assigning code bit b ₈ to symbol bit y ₄ , The code bit b _{9 is} assigned to the symbol bit y ₁₁ , the code bit b _{10 is} assigned to the symbol bit y ₅ , and the code bit b _{11 is} assigned to the symbol bit y ₁₀ for replacement.

142 is a diagram showing an example in which the modulation mode is 64QAM, and the LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 3/5, and a multiple of the bit allocation mode.

The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5. In the case where the modulation method is 64QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction. The code bits written in the memory 31 of the direction (16200/(6×2))×(6×2) bits are in the horizontal direction, and are read in units of 6×2 (=mb) bits, and It is supplied to the replacement unit 32.

The replacing unit 32 assigns the code bits b ₀ to b ₁₁ read from the 6 × 2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. The code bits p ₀ to b _{11 of} 6 × 2 (= mb) bits are replaced by the manner of the symbol bits y ₀ to y ₁₁ of × 2 (= mb) bits.

That is, according to FIG. 142, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₁₁ and the code bit b ₁ to the symbol bit y ₇ , and the code bit b ₂ Assigned to the symbol bit y ₃ , the code bit b _{3 is} assigned to the symbol bit y ₁₀ , the code bit b _{4 is} assigned to the symbol bit y ₆ , and the code bit b _{5 is} assigned to the symbol bit Element y ₂ , assigning code bit b ₆ to symbol bit y ₉ , assigning code bit b ₇ to symbol bit y ₅ , and assigning code bit b ₈ to symbol bit y ₁ , The code bit b _{9 is} assigned to the symbol bit y ₈ , the code bit b _{10 is} assigned to the symbol bit y ₄ , and the code bit b _{11 is} assigned to the symbol bit y ₀ for replacement.

Figure 143 shows an example in which the modulation mode is 256QAM, and the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and a multiple of the bit allocation mode.

The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 256QAM and the multiple b is 2, the multiplexer 25 is in the traversing direction. The code bits written in the memory 31 of the direction (64800/(8×2))×(8×2) bits are in the horizontal direction, and are read in units of 8×2 (=mb) bits, and It is supplied to the replacement unit 32.

The replacing unit 32 assigns the code bits b ₀ to b ₁₅ read from the 8 × 2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. The code bits p ₀ to b _{15 of} 8 × 2 (= mb) bits are replaced by the manner of the symbol bits y ₀ to y ₁₅ of × 2 (= mb) bits.

That is, according to FIG. 143, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₂ and the code bit b ₁ to the symbol bit y ₁₁ , and the code bit b ₂ Assigned to the symbol bit y ₃ , the code bit b _{3 is} assigned to the symbol bit y ₄ , the code bit b _{4 is} assigned to the symbol bit y ₀ , and the code bit b _{5 is} assigned to the symbol bit Element y ₉ , assigning code bit b ₆ to symbol bit y ₁ , assigning code bit b ₇ to symbol bit y ₈ , and assigning code bit b ₈ to symbol bit y ₁₀ , The code bit b _{9 is} assigned to the symbol bit y ₁₃ , the code bit b _{10 is} assigned to the symbol bit y ₇ , the code bit b _{11 is} assigned to the symbol bit y ₁₄ , and the code bit b _{12 is} assigned Assigned to symbol bit y ₆ , assign code bit b ₁₃ to symbol bit y ₁₅ ' assign code bit b ₁₄ to symbol bit y ₅ ' assign code bit b ₁₅ to symbol bit Yuan y ₁₂ and replace it.

Figure 144 shows an example in which the modulation mode is 256QAM, and the LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 3/5, and a multiple of the bit allocation mode.

The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5. In the case where the modulation method is 256QAM and the multiple b is 1, the multiplexer 25 is in the traverse direction × the traverse direction The code bits written in the memory 31 of the direction (16200/(8×1))×(8×1) bits are in the horizontal direction, and are read in units of 8×1 (= mb) bits, and It is supplied to the replacement unit 32.

The replacing unit 32 assigns the code bits b ₀ to b ₇ read from the 8 × 1 (= mb) bits of the memory 31 to 8 × 1 of 1 (= b) symbols as shown in FIG. (= mb) The bit y ₀ to y ₇ of the bit are replaced by the code bits b ₀ to b _{7 of} 8 × 1 (= mb) bits.

That is, according to FIG. 144, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₇ and the code bit b ₁ to the symbol bit y ₃ , and the code bit b ₂ Assigned to the symbol bit y ₁ , the code bit b _{3 is} assigned to the symbol bit y ₅ , the code bit b _{4 is} assigned to the symbol bit y ₂ , and the code bit b _{5 is} assigned to the symbol bit The element y ₆ assigns the code bit b ₆ to the symbol bit y ₄ and assigns the code bit b ₇ to the symbol bit y ₀ for replacement.

Next, the deinterleaver 53 constituting the receiving device 12 will be described.

Figure 145 is a diagram for explaining the processing of the multiplexer 54 constituting the deinterleaver 53.

That is, FIG. 145A shows an example of the functional configuration of the multiplexer 54.

The multiplexer 54 is composed of a reverse replacement unit 1001 and a memory 1002.

The multiplexer 54 performs the inverse replacement processing (replacement processing) of the replacement processing performed by the demultiplexer 25 of the transmitting apparatus 11 with the symbol bit supplied from the symbol of the demapping section 52 of the preceding stage as a target. Reverse processing), that is, performing an inverse replacement process of returning the position of the code bit (symbol bit) of the LDPC code replaced by the replacement process to the original position, and supplying the LDPC code obtained as a result to the subsequent stage The whirling twist deinterleaver 55.

That is, in the multiplexer 54, the inverse replacement unit 1001 supplies the symbol bits y ₀ , y ₁ , mb of the mb bits of the b symbols in units of (continuous) b symbols. , y _mb-1 .

The inverse replacement unit 1001 performs an arrangement in which the symbol bits y ₀ to y _mb-1 of the mb bit are returned to the original mb bits of the code bits b ₀ , b ₁ , . . . , b _mb-1 ( The replacement of the replacement unit 32 of the demultiplexer 25 constituting the transmitting device 11 side is replaced by the replacement of the preceding code bits b ₀ to b _mb-1 , and the result of the mb bit obtained by the result is output. Bits b ₀ to b _mb-1 .

The memory 1002 is the same as the memory 31 constituting the demultiplexer 25 on the side of the transmitting device 11, and stores memory mb bits in the row (horizontal) direction and memorizes in the column (longitudinal) direction. Memory capacity of N/(mb) bits. That is, the memory 1002 is composed of mb wales of memory N/(mb) bits.

In the memory 1002, the code bit of the LDPC code outputted by the inverse replacement unit 1001 is written in the direction in which the memory 31 of the demultiplexer 25 of the transmitting device 11 reads the code bit. The writing of the code bit written in the memory 1002 is performed in the direction in which the memory 31 is written.

That is, the multiplexer 54 of the receiving device 12, as shown in FIG. 145A, writes the code bits of the LDPC code outputted by the inverse replacement unit 1001 in the mb bit unit in the course direction, from the memory. The first column of 1002 proceeds in the following order.

Then, if the writing of the code bit of 1 code long is finished, the multiplexer 54 reads the code bit from the wale direction from the memory 1002 and supplies it to the slanting twist deinterleaver of the subsequent stage. 55.

Here, FIG. 145B shows a view of reading from the code bit of the memory 1002.

In the multiplexer 54, the reading of the code bits of the LDPC code from the top to the bottom (the wale direction) of the wales constituting the memory 1002 is performed from the leftward to the rightward wales.

Next, the processing of the vertical twist deinterleaver 55 constituting the deinterleaver 53 of the receiving device 12 will be described with reference to FIG.

146 is a diagram showing an example of the structure of the memory 1002 of the multiplexer 54.

The memory 1002 has a memory capacity of mb bits in the wale (longitudinal) direction and a memory capacity of N/(mb) bits in the horizontal (horizontal) direction, and is composed of mb wales.

The vertical twist deinterleaver 55 controls the memory 1002 to perform the wagger de-interlacing by controlling the start of the reading position when the code bits of the LDPC code are written in the course direction and read in the wale direction.

In other words, the vertical twist deinterleaver 55 appropriately changes the start reading position of the start code bit for each of the plurality of wales, thereby performing the arrangement of the code bits rearranged by the wobble interleave. Go back to the original rearrangement processing.

Here, FIG. 146 shows a configuration example of the memory 1002 in the case where the modulation method is 16QAM and the multiple b is 1. Therefore, the number of bits m of one symbol is 4 bits, and the memory 1002 is composed of 4 (= mb) vertical lines.

The vertical twist deinterleaver 55 (instead of the multiplexer 54) sequentially writes the code bits of the LDPC code output from the replacement unit 1001 in the course direction from the first column to the lower side of the memory 1002.

Then, if the writing of the code bit of 1 code long is finished, the wale twist deinterleaver 55 is a wales from the left to the right direction, and the code bit is turned from above the memory 1002 (the waling direction) ) read out.

Here, the vertical twist deinterleaver 55 writes the vertical twist interleaver 24 on the transmitting device 11 side to the start writing position of the code bit, as the start reading position of the code bit, and performs the code bit from the memory 1002. Read it out.

That is, if the address of the position of the beginning (topmost) of each wales is set to 0, and the address of each position of the waling direction is represented by an integer in ascending order, the modulation mode is 16QAM and the multiple b is 1. In the case of the vertical twist deinterleaver 55, the start read position is set to the position where the address is 0 for the leftmost vertical line, and the read position is set for the second vertical line (from the left). The address is a position of 2, and regarding the 3rd ordinate, the read position is set to the position where the address is 4, and with respect to the 4th ordinate, the start read position is set to the position where the address is 7.

Further, regarding the wales in which the start reading position is a position other than the position of the address 0, the reading of the code bit is performed to the lowermost position, and then the head is returned (the address is 0), and the traverse is performed. Readout before reading the position before the position is read. Then, the reading from the next (right) wales is performed thereafter.

By performing the longitudinal twist deinterlacing as above, the arrangement of the code bits rearranged by the wobble interleaving will return to the original arrangement.

Next, Fig. 147 is a block diagram showing another configuration example of the receiving device 12.

In FIG. 147, the receiving device 12 is a data processing device that receives a modulated signal from the transmitting device 11, and is composed of a quadrature demodulating unit 51, a demapping unit 52, a deinterleaver 53 and an LDPC decoding unit 1021.

The orthogonal demodulation unit 51 receives the modulated signal from the transmitting device 11, performs quadrature demodulation, and supplies the obtained symbols (values in the I and Q-axis directions) to the demapping unit 52.

The demapping unit 52 performs demapping of the symbols from the orthogonal demodulation unit 51 into code bits of the LDPC code, and supplies them to the deinterleaver 53.

The deinterleaver 53 is composed of a multiplexer (MUX) 54, a vertical twist deinterleaver 55, and a parity deinterleaver 1011, and performs deinterleaving of code bits from the LDPC code of the demapping section 52.

In other words, the multiplexer 54 performs the inverse replacement processing (reverse processing of the replacement processing) corresponding to the replacement processing performed by the demultiplexer 25 of the transmitting device 11 with the LDPC code from the demapping unit 52 as an object. That is, the reverse replacement processing of returning the position of the code bit replaced by the replacement processing to the original position is performed, and the LDPC code obtained as a result is supplied to the vertical twist deinterleaver 55.

The vertical twist deinterleaver 55 takes the LDPC code from the multiplexer 54 as a target, and performs a longitudinal twisting solution of the longitudinal twist interleaving performed as the rearrangement processing by the vertical twist interleaver 24 of the transmitting device 11. staggered.

The LDPC code obtained as a result of the whirth twist deinterlacing is supplied from the wale twist deinterleaver 55 to the parity deinterleaver 1011.

The parity deinterleaver 1011 performs the co-located deinterleaving (co-location) of the co-interleaving performed by the co-interleaver 23 of the transmitting device 11 with the code bit elements deinterlaced by the wobble deinterlacing of the wander twist deinterleaver 55 as a target. The inverse processing of the interleaving), that is, the parity bit of the LDPC code arranged by the co-located interleaving change is returned to the co-located deinterlacing of the original arrangement.

The LDPC code obtained as a result of the co-deinterlacing is supplied from the parity deinterleaver 1011 to the LDPC decoding unit 1021.

Therefore, in the receiving apparatus 12 of FIG. 147, the LDPC decoding unit 1021 is supplied with the LDPC code which has undergone the inverse replacement processing, the vertical twist deinterleave, and the colocated deinterleaving, that is, the LDPC code which is supplied by the inspection matrix H. Obtained LDPC code.

The LDPC decoding unit 1021 performs the LDPC encoding unit 21 of the transmitting device 11 for the LDPC-encoded inspection matrix H itself or the conversion check matrix obtained by performing at least the interleave-interlaced row replacement for the inspection matrix H. The LDPC code of the LDPC code of the interleaver 53 is decoded, and the data obtained as a result is output as a decoding result of the object data.

Here, in the receiving apparatus 12 of FIG. 147, since the deinterleaver 53 (the parity deinterleaver 1011) supplies the LDPC code obtained by the LDPC encoding according to the inspection matrix H to the LDPC decoding section 1021, it is transmitted. When the LDPC encoding unit 21 of the device 11 performs LDPC decoding of the LDPC code by using the check matrix H itself used for LDPC encoding, the LDPC decoding unit 1021 can sequentially perform a message (check node information, for example, by one node). A decoding device that performs LDPC decoding in a full serial decoding manner of a variable node message, or a full parallel decoding by simultaneously (parallel) performing information operations on all nodes. The method is configured by a decoding device that performs LDPC decoding.

Further, the LDPC decoding unit 1021 performs LDPC decoding of the LDPC code by performing at least the conversion check matrix obtained by the row interleave replacement for the parity check matrix H for the LDPC encoding by the LDPC encoding unit 21 of the transmitting device 11. In the case of a decoding device that performs an architecture of a check node operation and a variable node operation simultaneously with P (or a submultiple of P), and includes the conversion by using the LDPC code to obtain a conversion. The row of the check matrix is replaced by the same row permutation, and is configured by rearranging the decoding means of the received data rearrangement unit 310 of the code bit of the LDPC code.

In addition, in FIG. 147, for convenience of explanation, the multiplexer 54 for performing the inverse replacement processing, the vertical twist deinterleaver 55 for performing the wandering deinterlacing, and the colocated deinterleaver 1011 for performing the co-located deinterleaving are separately configured. However, two or more of the multiplexer 54, the vertical twist deinterleaver 55, and the in-position deinterleaver 1011 can be integrally formed in the same manner as the parity interleaver 23, the vertical twist interleaver 24, and the demultiplexer 25 of the transmitting device 11. .

Next, FIG. 148 is a block diagram showing a first configuration example of a receiving system applicable to the receiving device 12.

In FIG. 148, the receiving system is composed of an obtaining unit 1101, a channel decoding processing unit 1102, and an information source decoding processing unit 1103.

The acquisition unit 1101 obtains, by means of, for example, terrestrial digital broadcasting, satellite digital broadcasting, CATV network, Internet, and other networks, a transmission path including at least LDPC encoding of image data such as image data or audio data of the program. The signal of the obtained LDPC code is supplied to the transmission channel decoding processing unit 1102.

Here, when the signal acquired by the acquisition unit 1101 is played back from the broadcast station via a ground wave, a satellite wave, a CATV (Cable Television) network, or the like, the acquisition unit 1101 is a level adjuster or an STB ( Set Top Box: Set-top box). In the case where the signal acquired by the acquisition unit 1101 is transmitted by multicast from a web server such as IPTV (Internet Protocol Television), the acquisition unit 1101 is, for example, an NIC (Network Interface Card: Network interface card) and other network I / F (Inter face: interface).

The channel decoding processing unit 1102 applies a channel decoding process including at least a process of making a mistake in the transmission path to the signal acquired by the acquisition unit 1101 via the transmission channel, and supplies the signal obtained as a result to the information source. The decoding processing unit 1103.

In other words, the signal obtained by the acquisition unit 1101 via the transmission channel is a signal obtained by at least performing error correction coding for correcting the error generated by the transmission path, and the transmission channel decoding processing unit 1102 applies the signal to the signal. The channel decoding processing is performed by, for example, a mistake correction process.

Here, as the error correction code, for example, LDPC code or Reed Solomon code or the like is used. Here, at least LDPC encoding is performed as the error correction code.

Moreover, the transmission channel decoding process may include demodulation of a modulated signal or the like.

The information source decoding processing unit 1103 applies an information source decoding process including at least a process of extending the compressed information into the original information for the signal subjected to the channel decoding processing.

In other words, the signal acquired by the acquisition unit 1101 via the transmission path may be subjected to compression coding of compressed information in order to reduce the amount of data such as images or sounds of information. In this case, the information source decoding processing unit 1103 is The information source decoding processing such as the processing (stretching processing) of stretching the information into the original information is performed by applying the signal of the channel decoding processing.

Further, when the signal acquired by the acquisition unit 1101 via the transmission path is not subjected to compression coding, the information source decoding processing unit 1103 does not perform the process of extending the compressed information into the original information.

Here, as the stretching processing, for example, MPEG decoding or the like is used. Moreover, the transmission channel decoding process may include a de-mixing code or the like in addition to the stretching process.

In the receiving system configured as described above, the acquisition unit 1101 performs compression encoding such as MPEG encoding on data such as images and sounds, and further acquires a signal subjected to error correction coding such as LDPC encoding via a transmission path, and supplies the signal to the receiving unit 1101. To the channel decoding processing unit 1102.

The channel decoding processing unit 1102 applies, for example, to the orthogonal demodulation unit 51 or the demapping unit 52, the deinterleaver 53, and the LDPC decoding unit 56 (or LDPC) as the channel decoding processing for the signal from the acquisition unit 1101. The decoding unit 1021) performs the same processing, and the signal obtained as a result is supplied to the information source decoding processing unit 1103.

The information source decoding processing unit 1103 performs information source decoding processing such as MPEG decoding on the signal from the channel decoding processing unit 1102, and outputs the image or sound obtained as a result.

The receiving system as shown in FIG. 148 above can be applied to, for example, a television level adjuster that receives television broadcast as digital playback.

Further, the acquisition unit 1101, the transmission channel decoding processing unit 1102, and the information source decoding processing unit 1103 can be configured as one independent device (hardware (integrated circuit) or the like) or a software module.

Further, the acquisition unit 1101, the channel decoding processing unit 1102, and the information source decoding processing unit 1103 can aggregate the acquisition unit 1101 and the channel decoding processing unit 1102, or the channel decoding processing unit 1102 and the information source decoding processing unit 1103. The set of the acquisition unit 1101, the channel decoding processing unit 1102, and the information source decoding processing unit 1103 is configured as one independent device.

Figure 149 is a block diagram showing a second configuration example of a receiving system applicable to the receiving device 12.

In the drawings, the same reference numerals are given to the portions corresponding to those in the case of FIG. 148, and the description thereof will be omitted as appropriate.

The receiving system of FIG. 149 is the same as the case of FIG. 148 in the case where the acquisition unit 1101, the channel decoding processing unit 1102, and the information source decoding processing unit 1103 are included, and the point where the output unit 1111 is newly provided is compared with the case of FIG. different.

The output unit 1111 is, for example, a display device that displays an image or a speaker that outputs sound, and outputs an image, a sound, or the like as a signal output from the information source decoding processing unit 1103. That is, the output unit 1111 displays an image or outputs a sound.

The receiving system as shown in Fig. 149 above can be applied to, for example, a TV (television receiver) that receives television broadcast as digital broadcast, or a broadcast receiver that receives broadcast broadcast, and the like.

Further, when the signal acquired by the acquisition unit 1101 is not subjected to compression coding, the signal output from the transmission channel decoding processing unit 1102 is supplied to the output unit 1111.

Figure 150 is a block diagram showing a third configuration example of a receiving system applicable to the receiving device 12.

In the drawings, the same reference numerals are given to the portions corresponding to those in the case of FIG. 148, and the description thereof will be omitted as appropriate.

The receiving system of Fig. 150 is the same as the case of Fig. 148 except that the acquisition unit 1101 and the channel decoding processing unit 1102 are included.

The receiving system of FIG. 150 is different from the case of FIG. 148 in that the recording unit 1121 is newly provided without the information source decoding processing unit 1103.

The recording unit 1121 records (storing, for example, a TS packet of the MPEG TS) recorded in the transmission channel decoding processing unit 1102 on a disc, a hard disk (magnetic disk), a flash memory, or the like. (memory) media.

The receiving system as shown in Fig. 150 above can be applied to a video recorder or the like for recording a television broadcast.

Further, in FIG. 150, the reception system is configured by providing the information source decoding processing unit 1103, and the information source decoding processing unit 1103 can record the signal subjected to the information source decoding processing by the recording unit 1121, that is, by decoding. The image or sound obtained.

However, if the replacement processing of the new replacement method of replacing the code bit as shown in FIG. 64 is performed according to the allocation rule according to FIG. 63, the replacement processing of the current mode of replacing the code bit as shown in FIG. 60C may be performed, so that the error is Increased tolerance (Figure 65).

Further, according to the LDPC code (proposal code) of the inspection matrix H obtained from the inspection matrix initial value table of Figs. 66 to 68, as shown in Fig. 69, the tolerance to errors can be improved compared with the specification code.

As mentioned above, only the new replacement method or the proposal code can be used, and the tolerance for errors can be improved, but by adopting the proposal code and adopting the replacement of the code bits according to the allocation rule appropriate for the proposal code. The replacement treatment (hereinafter also referred to as the appropriate method) can further improve the tolerance to errors.

151 to 155 are diagrams illustrating a suitable mode.

That is, FIG. 151 is a diagram showing that the LDPC code is an LDPC code of the inspection matrix H obtained from the check matrix initial value table of FIGS. 66 to 68 with a code length N of 64,800 bits and a coding rate of 2/3. Further, the modulation mode is 256QAM, and the multiple of the code bit group and the symbol bit group in the case where the multiple b is 2.

In this case, the memory 31 is read out in units of code bits b ₀ to b ₁₅ of 8 × 2 (= mb) bits, and the code bits b _{0 of} the 8 × 2 (= mb) bits To b ₁₅ is the difference between the error correction rates, as shown in FIG. 151A, the group can be divided into 5 code bit groups Gb ₁ , Gb ₂ , Gb ₃ , Gb ₄ , Gb ₅ .

151A, respectively, the code bit group Gb ₁ belongs to the code bit b ₀ , the code bit group Gb ₂ belongs to the code bit b ₁ , and the code bit group Gb ₃ is the code bit b ₂ to b ₉ belong to, the code bit group Gb _{4 is} associated with the code bit b ₁₀ , and the code bit group Gb ₅ is the code bit b ₁₁ to b ₁₅ belongs to.

When the modulation mode is 256QAM and the multiple b is 2, the symbol bits y ₀ to y ₁₅ of the 8×2 (= mb) bits are different according to the error correction rate, and can be grouped as shown in FIG. 151B. 4 symbol bit groups Gy ₁ , Gy ₂ , Gy ₃ , Gy ₄ .

In FIG. 151B, respectively, the symbol bit group Gy ₁ is a symbol bit y ₀ , y ₁ , y ₈ , y ₉ belongs to, and the symbol bit group Gy ₂ is a symbol bit y ₂ . y ₃ , y ₁₀ , y ₁₁ belong to, the symbol element group Gy ₃ is a symbol element y ₄ , y ₅ , y ₁₂ , y ₁₃ belongs to, the symbol element group Gy ₄ is a symbol element y ₆ , y ₇ , y ₁₄ , y ₁₅ belong.

Figure 152 is a diagram showing an allocation rule of a suitable mode in the case where the LDPC code is a proposal code and the modulation method is 256QAM and the multiple b is 2.

In the allocation rule of FIG. 152, group aggregation information (Gb ₁ , Gy ₄ , 1), (Gb ₂ , Gy ₂ , 1), (Gb ₃ , Gy ₁ , 2), (Gb ₃ , Gy ₂ , 2), (Gb ₃ , Gy ₃ , 2), (Gb ₃ , Gy ₄ , 2), (Gb ₄ , Gy ₄ , 1), (Gb ₅ , Gy ₁ , 2), (Gb ₅ , Gy ₂ , 1), (Gb ₅ , Gy ₃ , 2).

Therefore, the allocation rule in FIG. 152 is defined as follows: according to the group set information (Gb ₁ , Gy ₄ , 1), the error bit rate is 1 bit of the code bit of the first good code bit group Gb ₁ , Assigned to the 1st bit of the symbol bit of the 4th good symbol group Gy ₄ of the error rate; according to the group set information (Gb ₂ , Gy ₂ , 1), the error rate is the 2nd good code point. One bit of the code bit of the meta-group Gb ₂ is assigned to the 1-bit of the symbol bit of the second good symbol bit group Gy ₂ of the error rate; according to the group set information (Gb ₃ , Gy ₁ , 2), assigning the 2 bits of the code bit of the 3rd good code bit group Gb ₃ of the error rate to the symbol bit of the first good symbol bit group Gy ₁ of the error rate. 2 bits; according to the group set information (Gb ₃ , Gy ₂ , 2), the 2 bits of the code bit of the 3rd good code bit group Gb ₃ of the error rate are assigned to the second correct error rate. ₂ bits of the symbol bit of the symbol group Gy ₂ ; according to the group set information (Gb ₃ , Gy ₃ , 2), the code position of the third good code bit group Gb ₃ of the error rate is determined. 2 yuan of the yuan, assigned to the third good symbol of the error rate 2 bits of the symbol group of the meta group Gy ₃ ; according to the group set information (Gb ₃ , Gy ₄ , 2), the code bit of the 3rd good code bit group Gb ₃ of the error rate is 2 The bit is allocated to the 2-bit of the symbol bit of the 4th good symbol group Gy ₄ of the error rate; according to the group set information (Gb ₄ , Gy ₄ , 1), the error rate is 4th. 1 bit of the code bit of the code bit group Gb ₄ , assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy ₄ of the error rate; according to the group set information (Gb ₅ , Gy ₁ , 2), assigning the 2 bits of the code bit of the 5th good code bit group Gb ₅ of the error rate to the symbol of the first good symbol bit group Gy ₁ of the error rate. 2 bits of the bit; according to the group set information (Gb ₅ , Gy ₂ , 1), the 1st bit of the code bit of the 5th good code bit group Gb ₅ of the error rate is assigned to the error correction rate 2 1 bit of the symbol element Gy ₂ of the good symbol group; and according to the group set information (Gb ₅ , Gy ₃ , 2), the error rate is the 5th good code bit group Gb 2 of ₅ bits of the code bits allocated to determine the error rate of the third symbol bit group good The _3-bit symbol Gy element 2 of bits.

Figure 153 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 152.

That is, FIG. 153A shows that the LDPC code is a proposal code having a code length N of 64800 bits and a coding rate of 2/3, and further modulation mode is 256QAM, and the multiple b is 2, and the allocation rule according to FIG. 152 is used. The first example of the replacement of the code bit °

The LDPC code is a proposed code having a code length N of 64,800 bits and a coding rate of 2/3. In the case where the modulation method is 256QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction. The code bits written in the memory 31 of the direction (64800/(8×2))×(8×2) bits are in the horizontal direction, and are read in units of 8×2 (=mb) bits, and It is supplied to the replacement unit 32 (Figs. 16 and 17).

The replacing unit 32 assigns the code bits b ₀ to b ₁₅ read from the 8 × 2 (= mb) bits of the memory 31 in accordance with the allocation rule of FIG. 152, for example, as shown in FIG. 153A to consecutive 2 (=b). The symbol bits y ₀ to y _{15 of the} 8 × 2 (= mb) bits of the symbols are replaced by the code bits b ₀ to b _{15 of the} 8 × 2 (= mb) bits.

That is, the replacing unit 32 assigns the code bit b ₀ to the symbol bit y ₇ , assigns the code bit b ₁ to the symbol bit y ₂ , and assigns the code bit b ₂ to the symbol bit y ₉ , assigning the code bit b ₃ to the symbol bit y ₀ , assigning the code bit b ₄ to the symbol bit y ₄ , and assigning the code bit b ₅ to the symbol bit y ₆ , the code Bit b _{6 is} assigned to symbol bit y ₁₃ , code bit b _{7 is} assigned to symbol bit y ₃ , code bit b _{8 is} assigned to symbol bit y ₁₄ , and bit bit b _{9 is} assigned For the symbol bit y ₁₀ , the code bit b _{10 is} assigned to the symbol bit y ₁₅ , the code bit b _{11 is} assigned to the symbol bit y ₅ , and the code bit b _{12 is} assigned to the symbol bit y ₈ , the code bit b _{13 is} assigned to the symbol bit y ₁₂ , the code bit b _{14 is} assigned to the symbol bit y ₁₁ , and the code bit b _{15 is} assigned to the symbol bit y ₁ . replace.

153B shows that the LDPC code is a coded code having a code length N of 64,800 bits and a coding rate of 2/3. Further modulation is 256QAM, and the multiple b is 2, and the code bit according to the allocation rule of FIG. The second example of replacement.

According to FIG. 153B, the replacing unit 32 performs the following replacement for the code bits b ₀ to b ₁₅ of the 8×2 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 152: The code bit b _{0 is} assigned to the symbol bit y ₇ , the code bit b _{1 is} assigned to the symbol bit y ₂ , and the code bit b _{2 is} assigned to the symbol bit y ₁ , and the code bit b is _{3 is} assigned to the symbol bit y ₀ , the code bit b _{4 is} assigned to the symbol bit y ₁₃ , the code bit b _{5 is} assigned to the symbol bit y ₁₂ , and the code bit b _{6 is} assigned to the symbol Bit y ₆ , assigning code bit b ₇ to symbol bit y ₃ , assigning code bit b ₈ to symbol bit y ₁₅ , and assigning code bit b ₉ to symbol bit y ₁₁ , The code bit b _{10 is} assigned to the symbol bit y ₁₄ , the code bit b _{11 is} assigned to the symbol bit y ₅ , and the code bit b _{12 is} assigned to the symbol bit y ₈ , and the code bit b is _{13 is} assigned to the symbol bit y ₄ , the code bit b _{14 is} assigned to the symbol bit y ₁₀ , and the code bit b _{15 is} assigned to the symbol bit y ₉ .

Here, the manner in which the code bit b _i shown in FIGS. 153A and 153B is assigned to the symbol bit y _i is in accordance with the allocation rule of FIG. 152 (according to the allocation rule).

FIGS. 154 and 155 show simulation results of the BER in the case where the replacement processing of the appropriate mode described in FIGS. 151 to 153 has been performed.

Further, in FIGS. 154 and 155, the horizontal axis represents E _s /N ₀ and the vertical axis represents BER. Further, in FIGS. 154 and 155, the modulation method is 256QAM, and the multiple b is 2.

Figure 154 is a diagram showing the BER (indicated by a circle mark) in the case of the replacement processing of Figure 153A in the applicable mode illustrated in Figures 151 to 153 for the proposed code, and the code length N is 64800, and the coding rate is The LDP (code) of the DVB-S.2 specification specified in 2/3 carries out the BER (indicated by a star in the figure) in the case of the replacement processing (the replacement processing of the current mode) described in FIG. 60C.

As can be seen from FIG. 154, by performing the replacement processing for the proposed code, the replacement process of the current mode can be performed more than the specification code, and the wrong floor is drastically lowered, and the tolerance to errors is improved.

155 is a diagram showing a BER (indicated by a circle mark) in the case where the proposal code is subjected to the replacement process of the appropriate mode, and a case where the replacement process (the replacement process of the current mode) described in FIG. 60C is performed on the proposal code. BER (indicated by a star in the figure).

As can be seen from Fig. 155, by adopting the appropriate replacement processing for the proposed code, the BER can be lowered and the tolerance to errors can be improved as compared with the case of the replacement processing in the current mode.

The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the invention.

11. . . Transmitting device

12. . . Receiving device

twenty one. . . LDPC coding department

twenty two. . . Bit interleaver

twenty three. . . Parity interleaver

twenty four. . . Longitudinal twisting interleaver

25. . . Demultiplexer

26. . . Mapping department

27. . . Orthogonal modulation

31. . . Memory

32. . . Replacement department

51. . . Quadrature demodulation unit

52. . . Demapping section

53. . . Deinterleaver

54. . . Multiplexer

55. . . Longitudinal twist deinterleaver

56. . . LDPC decoding unit

300. . . Branch data storage memory

301. . . Selector

302. . . Check node calculation unit

303. . . Cyclic shift circuit

304. . . Branch data storage memory

305. . . Selector

306. . . Receiving data memory

307. . . Variable node calculation department

308. . . Cyclic shift circuit

309. . . Decoded word calculation unit

310. . . Receiving data rearrangement department

311. . . Decoding data rearrangement

601. . . Coding processing unit

602. . . Memory department

611. . . Code rate setting unit

612. . . Initial value table reading unit

613. . . Check matrix generation

614. . . Information bit reading unit

615. . . Coding unit

616. . . Control department

701. . . Busbar

702. . . CPU

703. . . ROM

704. . . RAM

705. . . Hard disk

706. . . Output department

707. . . Input section

708. . . Ministry of Communications

709. . . Disk drive

710. . . Output interface

711. . . Portable recording medium

1001. . . Anti-replacement department

1002. . . Memory

1011. . . Parole deinterleaver

1021. . . LDPC decoding unit

1101. . . Acquisition department

1102. . . Transport channel decoding processing unit

1103. . . Information source decoding processing unit

1111. . . Output department

1121. . . Recording department

Figure 1 is a diagram illustrating a check matrix H of an LDPC code.

Figure 2 is a flow chart showing the decoding procedure of the LDPC code.

Fig. 3 is a view showing an example of a check matrix of an LDPC code.

Figure 4 is a diagram showing the Tanner graph of the inspection matrix.

Figure 5 is a diagram showing a variable node.

Figure 6 is a diagram showing a check node.

Fig. 7 is a view showing a configuration example of an embodiment of a transport system to which the present invention is applied.

FIG. 8 is a block diagram showing a configuration example of the transmitting device 11.

Figure 9 is a diagram showing an inspection matrix.

Fig. 10 is a view showing a parity matrix.

Figure 11 is a diagram showing the check matrix and row weight of the LDPC code defined by the specifications of DVB-S.2.

12A and 12B are diagrams showing the signal point arrangement of 16QAM.

Figure 13 is a diagram showing the signal point configuration of 64QAM.

Figure 14 is a diagram showing the signal point configuration of 64QAM.

Figure 15 is a diagram showing the signal point configuration of 64QAM.

16A to 16D are diagrams illustrating the processing of the multiplexer 25.

17A and 17B are diagrams for explaining the processing of the multiplexer 25.

Figure 18 is a diagram showing a Tanner graph for decoding of an LDPC code.

19A and 19B are views showing a parity matrix H _{T which} is a step structure and a Tanner graph corresponding to the parity matrix H _T .

Figure 20 is a diagram showing the parity matrix H _T of the check matrix H corresponding to the LDPC code of the co-located interleaving.

21A and 21B are views showing a conversion check matrix.

Fig. 22 is a view showing the processing of the whirling twist interleaver 24.

Fig. 23 is a view showing the number of wales of the memory 31 and the address at which the writing position is started, which are necessary for the whirling of the wales.

Fig. 24 is a view showing the number of wales of the memory 31 and the address at which the writing position is started, which are necessary for the whirling of the wales.

Fig. 25 is a flow chart showing the transmission processing.

26A and 26B are views showing a model of a communication channel used in the simulation.

Fig. 27 is a graph showing the relationship between the error rate obtained by the simulation and the Bucher frequency f _d of the chatter.

Fig. 28 is a graph showing the relationship between the error rate obtained by the simulation and the Bucher frequency f _d of the flutter.

FIG. 29 is a block diagram showing a configuration example of the LDPC encoding unit 21.

Fig. 30 is a flow chart for explaining the processing of the LDPC encoding unit 21.

Fig. 31 is a view showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 16200.

Fig. 32 is a view showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 64,800.

Fig. 33 is a view showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 64,800.

Fig. 34 is a view showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 64,800.

Fig. 35 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 16200.

Fig. 36 is a view showing a table of initial values of inspection matrices of a coding rate of 3/4 and a code length of 64,800.

Fig. 37 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800.

38 is a diagram showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800.

Fig. 39 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800.

Fig. 40 is a diagram showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 16200.

41 is a diagram showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800.

Fig. 42 is a view showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800.

Fig. 43 is a view showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800.

Fig. 44 is a diagram showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800.

Fig. 45 is a view showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 16200.

Fig. 46 is a view showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800.

Fig. 47 is a view showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800.

Fig. 48 is a view showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800.

Fig. 49 is a view showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800.

Fig. 50 is a view showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 16200.

Fig. 51 is a view showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800.

Figure 52 is a diagram showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800.

Fig. 53 is a view showing a table of initial values of inspection matrices of a coding rate of 8/9 and a code length of 64,800.

Fig. 54 is a view showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800.

Fig. 55 is a diagram showing an inspection matrix initial value table of a coding rate of 9/10 and a code length of 64,800.

Fig. 56 is a diagram showing an inspection matrix initial value table of a coding rate of 9/10 and a code length of 64,800.

Fig. 57 is a diagram showing an inspection matrix initial value table of a coding rate of 9/10 and a code length of 64,800.

Fig. 58 is a diagram showing an inspection matrix initial value table of a coding rate of 9/10 and a code length of 64,800.

Fig. 59 is a view for explaining a method of obtaining the inspection matrix H from the inspection matrix initial value table.

Figures 60A-C are diagrams showing the replacement process of the current mode.

Figures 61A-C are diagrams showing the replacement process of the current mode.

62A and 62B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 256QAM and the multiple b is 2.

Fig. 63 is a diagram showing an allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 256QAM and the multiple b is 2.

64A and 64B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 2/3 is modulated by 256QAM and the multiple b is 2.

Fig. 65 is a view showing a case where the replacement processing of the new replacement mode has been performed and the BER of the case where the replacement processing of the current mode has been performed.

Fig. 66 is a view showing an example of an inspection matrix initial value table of an LDPC code which is a good performance _Eb /N ₀ ratio specification code.

Fig. 67 is a view showing an example of an inspection matrix initial value table of an LDPC code which is a good performance _Eb /N ₀ ratio specification code.

Fig. 68 is a view showing an example of an inspection matrix initial value table of an LDPC code which is a good performance _Eb /N ₀ ratio specification code.

Fig. 69 is a view showing the relationship between E _s /N ₀ and BER of the specification code and the proposal code.

Fig. 70 is a block diagram showing a configuration example of the receiving device 12.

Figure 71 is a flow chart illustrating the receiving process.

Fig. 72 is a view showing an example of a check matrix of an LDPC code.

Fig. 73 is a view showing a matrix (conversion check matrix) after column replacement and row replacement are performed on the inspection matrix.

Fig. 74 is a view showing a conversion check matrix divided into 5 × 5 units.

Fig. 75 is a block diagram showing a configuration example of a plurality of decoding apparatuses for performing node calculation.

Fig. 76 is a block diagram showing a configuration example of the LDPC decoding unit 56.

Fig. 77 is a block diagram showing a configuration example of an embodiment of a computer to which the present invention is applied.

Fig. 78 is a view showing an example of a check matrix initial value table of a coding rate of 2/3 and a code length of 16200.

Fig. 79 is a view showing an example of a check matrix initial value table of a coding rate of 2/3 and a code length of 64,800.

Fig. 80 is a view showing an example of a check matrix initial value table of a coding rate of 2/3 and a code length of 64,800.

Fig. 81 is a view showing an example of a check matrix initial value table of a coding rate of 2/3 and a code length of 64,800.

Fig. 82 is a view showing an example of an inspection matrix initial value table of a coding rate of 3/4 and a code length of 16200.

Fig. 83 is a view showing an example of a check matrix initial value table of a coding rate of 3/4 and a code length of 64,800.

Fig. 84 is a view showing an example of a check matrix initial value table of a coding rate of 3/4 and a code length of 64,800.

Fig. 85 is a view showing an example of an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800.

Fig. 86 is a view showing an example of an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800.

Fig. 87 is a view showing an example of a check matrix initial value table of a coding rate of 4/5 and a code length of 16200.

Fig. 88 is a view showing an example of a check matrix initial value table of a coding rate of 4/5 and a code length of 64,800.

Fig. 89 is a view showing an example of a check matrix initial value table of a coding rate of 4/5 and a code length of 64,800.

Fig. 90 is a view showing an example of a check matrix initial value table of a coding rate of 4/5 and a code length of 64,800.

Fig. 91 is a view showing an example of an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800.

Fig. 92 is a view showing an example of an inspection matrix initial value table of a coding rate of 5/6 and a code length of 16200.

Fig. 93 is a view showing an example of a check matrix initial value table of a coding rate of 5/6 and a code length of 64,800.

Fig. 94 is a view showing an example of a check matrix initial value table of a coding rate of 5/6 and a code length of 64,800.

Fig. 95 is a view showing an example of an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800.

Fig. 96 is a view showing an example of a check matrix initial value table of a coding rate of 5/6 and a code length of 64,800.

Fig. 97 is a diagram showing an example of an inspection matrix initial value table of a coding rate of 8/9 and a code length of 16200.

Fig. 98 is a view showing an example of an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800.

Fig. 99 is a view showing an example of an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800.

Fig. 100 is a view showing an example of a check matrix initial value table of a coding rate of 8/9 and a code length of 64,800.

Fig. 101 is a diagram showing an example of an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800.

Fig. 102 is a view showing an example of an inspection matrix initial value table of a coding rate of 9/10 and a code length of 64,800.

Fig. 103 is a view showing an example of an inspection matrix initial value table of a coding rate of 9/10 and a code length of 64,800.

Fig. 104 is a view showing an example of a check matrix initial value table of a coding rate of 9/10 and a code length of 64,800.

Fig. 105 is a view showing an example of a check matrix initial value table of a coding rate of 9/10 and a code length of 64,800.

Fig. 106 is a diagram showing an example of a check matrix initial value table of a coding rate of 1/4 and a code length of 64,800.

Fig. 107 is a view showing an example of a check matrix initial value table of a coding rate of 1/4 and a code length of 64,800.

Fig. 108 is a diagram showing an example of a check matrix initial value table of a coding rate of 1/3 and a code length of 64,800.

Fig. 109 is a diagram showing an example of a check matrix initial value table of a coding rate of 1/3 and a code length of 64,800.

Fig. 110 is a diagram showing an example of an inspection matrix initial value table of a coding rate of 2/5 and a code length of 64,800.

Fig. 111 is a view showing an example of a check matrix initial value table of a coding rate of 2/5 and a code length of 64,800.

Fig. 112 is a view showing an example of a check matrix initial value table of a coding rate of 1/2 and a code length of 64,800.

Fig. 113 is a view showing an example of a check matrix initial value table of a coding rate of 1/2 and a code length of 64,800.

Fig. 114 is a view showing an example of a check matrix initial value table of a coding rate of 1/2 and a code length of 64,800.

Fig. 115 is a diagram showing an example of a check matrix initial value table of a coding rate of 3/5 and a code length of 64,800.

Fig. 116 is a diagram showing an example of a check matrix initial value table of a coding rate of 3/5 and a code length of 64,800.

Figure 117 is a diagram showing an example of a check matrix initial value table of a coding rate of 3/5 and a code length of 64,800.

Fig. 118 is a diagram showing an example of an inspection matrix initial value table of a coding rate of 1/4 and a code length of 16200.

Figure 119 is a diagram showing an example of an inspection matrix initial value table of a coding rate of 1/3 and a code length of 16200.

Fig. 120 is a diagram showing an example of an inspection matrix initial value table of a coding rate of 2/5 and a code length of 16200.

Fig. 121 is a diagram showing an example of a check matrix initial value table of a coding rate of 1/2 and a code length of 16200.

Fig. 122 is a diagram showing an example of a check matrix initial value table of a coding rate of 3/5 and a code length of 16200.

Fig. 123 is a view showing another example of the check matrix initial value table of the coding rate 3/5 and the code length 16200.

Fig. 124 is a view for explaining a method of obtaining the inspection matrix H from the inspection matrix initial value table.

Figure 125 is a diagram showing an alternative of a code bit.

Figure 126 is a diagram showing an alternative of a code bit.

Figure 127 is a diagram showing an alternative of a code bit.

Figure 128 is a diagram showing an alternative of a code bit.

Figure 129 is a diagram showing the simulation result of BER.

Figure 130 is a diagram showing the simulation result of BER.

Fig. 131 is a view showing the simulation result of the BER.

Figure 132 is a diagram showing the simulation result of BER.

Figure 133 is a diagram showing an alternative of a code bit.

Figure 134 is a diagram showing an alternative of a code bit.

Figure 135 is a diagram showing an alternative of a code bit.

Figure 136 is a diagram showing an alternative of a code bit.

Figure 137 is a diagram showing an alternative of a code bit.

Figure 138 is a diagram showing an alternative of a code bit.

Figure 139 is a diagram showing an alternative of a code bit.

Figure 140 is a diagram showing an alternative of a code bit.

Figure 141 is a diagram showing an alternative of the code bits.

Figure 142 is a diagram showing an alternative of a code bit.

Figure 143 is a diagram showing an alternative of a code bit.

Figure 144 is a diagram showing an alternative of a code bit.

145A and 145B are views for explaining the processing of the multiplexer 54 constituting the deinterleaver 53.

Figure 146 is a diagram illustrating the processing of the wobble twist deinterleaver 55.

Figure 147 is a block diagram showing another configuration example of the receiving device 12.

Figure 148 is a block diagram showing a first configuration example of a receiving system applicable to the receiving device 12.

Figure 149 is a block diagram showing a second configuration example of a receiving system applicable to the receiving device 12.

Figure 150 is a block diagram showing a third configuration example of a receiving system applicable to the receiving device 12.

151A and 151B are diagrams showing a code bit group and a symbol bit group in the case where the 256QAM modulation code length 64800 and the coding rate 2/3 are proposed codes, and the multiple b is 2.

Figure 152 is a diagram showing an allocation rule in the case where the 256QAM modulation code length is 64800 and the coding rate is 2/3, and the multiple b is 2.

FIGS. 153A and 153B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the 256QAM modulation code length 64800 and the coding rate 2/3 are proposed codes, and the multiple b is 2.

Fig. 154 is a diagram showing a case where the replacement processing of the proposed code is performed in a suitable manner, and a BER in the case where the replacement processing of the current mode is performed on the specification code.

Fig. 155 is a diagram showing a case where the replacement processing of the proposal code is performed in a suitable manner, and a BER in the case where the replacement processing of the current mode is performed.

(no component symbol description)

Claims (2)

A data processing device comprising: a replacement mechanism for memorizing the code bits of an LDPC (Low Density Parity Check) code having a code length of N bits in the horizontal direction and the longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written in the row direction of the mechanism is defined as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and stores N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the preceding direction In the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are used as the b symbols, the code bits of the mb bits are replaced, and the replaced code bits are replaced. The LDPC code indicating the symbol element of the symbol; and the LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, wherein the m bit is 8 bits, and the integer b is 2, The octet of the aforementioned code bit is mapped as one of the aforementioned symbols to 256 signal points determined by 256QAM. In any one of the foregoing, the memory mechanism has 16 vertical lines of 8×2 bits in the horizontal direction and 64800/(8×2) bits in the longitudinal direction; the replacement mechanism is in the course of the foregoing memory mechanism. The code bit of the 8×2 bit read from the direction is set to the bit b _i from the highest order bit, and the 8×2 bit of the preceding two symbols will be consecutively The meta-bit is set to the bit y _i from the highest-order bit, and the bit b _{0 is} assigned to the bit y ₇ and the bit b _{1 is} assigned to the bit y ₂ . Bit b _{2 is} assigned to bit y ₉ , bit b _{3 is} assigned to bit y ₀ , bit b _{4 is} assigned to bit y ₄ , bit b _{5 is} assigned to bit y ₆ , bit is allocated b _{6 is} assigned to bit y ₁₃ , bit b _{7 is} assigned to bit y ₃ , bit b _{8 is} assigned to bit y ₁₄ , bit b _{9 is} assigned to bit y ₁₀ , bit b _{10 is} assigned Assigned to bit y ₁₅ , bit b _{11 is} assigned to bit y ₅ , bit b _{12 is} assigned to bit y ₈ , bit b _{13 is} assigned to bit y ₁₂ , bit b _{14 is} assigned to bit y _11, the bit b ₁₅ to the bit y _1, each of the alternative allocation; check LDPC code of the The matrix is configured by arranging one element of the information matrix defined by the check matrix initial value table of the check matrix in the row direction every 360-row period, and the check matrix initial value table is corresponding to the code length and the foregoing coding rate. The position of the 1 element of the aforementioned information matrix corresponding to the information length is represented by every 360 rows; the foregoing check matrix initial value table includes 317 2255 2324 2723 3538 3576 6194 6700 9101 10057 12739 17407 21039 1958 2007 3294 4394 12762 14505 14593 14692 16522 17737 19245 21272 21379 127 860 5001 5633 8644 9282 12690 14644 17553 19511 19681 20954 21002 2514 2822 5781 6297 8063 9469 9551 11407 11837 12985 15710 20236 20393 1565 3106 4659 4926 6495 6872 7343 8720 15785 16434 16727 19884 21325 706 3220 8568 10896 12486 13663 16398 16599 19475 19781 20625 20961 21335 4257 10449 12406 14561 16049 16522 17214 18029 18033 18802 19062 19526 20748 412 433 558 2614 2978 4157 6584 9320 11683 11819 13024 14486 16860 777 5906 7403 8550 8717 8770 11436 12846 13629 14755 15688 16392 16419 4093 5045 6037 7248 8633 9771 10260 10809 11326 12072 17516 19344 19938 2120 2648 3155 3852 6888 12258 14821 15359 16378 16437 17791 20614 21025 1085 2434 5816 7151 8050 9422 10884 12728 15353 17733 18140 18729 20920 856 1690 12787 6532 7357 9151 4210 16615 18152 11494 14036 17470 2474 10291 10323 1778 6973 10739 4347 9570 18748 2189 11942 20666 3868 7526 17706 8780 14796 18268 160 16232 17399 1285 2003 18922 4658 17331 20361 2765 4862 5875 4565 5521 8759 3484 7305 15829 5024 17730 17879 7031 12346 15024 179 6365 11352 2490 3143 5098 2643 3101 21259 4315 4724 13130 594 17365 18322 5983 8597 9627 10837 15102 20876 10448 20418 21478 3848 12029 15228 708 5652 13146 5998 7534 16117 2098 13201 18317 9186 14548 17776 5246 10398 18597 3083 4944 21021 13726 18495 19921 6736 10811 17545 10084 12411 14432 1064 13555 17033 679 9878 13547 3422 9910 20194 3640 3701 10046 5862 10134 11498 5923 9580 15060 1073 3012 16427 5527 20113 20883 7058 12924 15151 9764 12230 17375 772 7711 12723 555 13816 15376 10574 11268 17932 1544 2 17266 20482 390 3371 8781 10512 12216 17180 4309 14068 15783 3971 11673 20009 9259 14270 17199 2947 5852 20101 3965 9722 15363 1429 5689 16771 6101 6849 12781 3676 9347 18761 350 11659 18342 5961 14803 16123 2113 9163 13443 2155 9808 12885 2861 7988 11031 7309 9220 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 6297 16262 2792 3513 17031 14846 20893 21563 17220 20436 21337 275 4107 10497 3536 7520 10027 14089 14943 19455 1965 3931 21104 2439 11565 17932 154 15279 21414 10017 11269 16546 7169 10161 16928 10284 16791 20655 36 3175 8475 2605 16269 19290 8947 9178 15420 5687 9156 12408 8096 9738 14711 4935 8093 19266 2667 10062 15972 6389 11318 14417 8800 18137 18434 5824 5927 15314 6056 13168 15179 3284 13138 18919 13115 17259 17332. A data processing method includes the following steps: a replacement step of memorizing a code bit of an LDPC (Low Density Parity Check) code having a code length of N bits in a horizontal direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the preceding direction in the memory direction of the memory device is taken as one symbol, and the specific positive integer is b, and the memory mechanism is Storing mb bits in the horizontal direction and storing N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row Direction reading, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are used as b symbols, the code bits of the mb bits are replaced, and the replaced code is replaced. The bit element is used as a symbol bit indicating the symbol; and the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, wherein the m bit is 8 bits, and the aforementioned integer b is 2. The octet of the aforementioned code bit is mapped to 256 of 256QAM as one of the aforementioned symbols. Any one of the points, wherein the memory mechanism includes 16 vertical lines of 8×2 bits in the horizontal direction and 64800/(8×2) bits in the longitudinal direction; in the foregoing replacement step, the foregoing The code bit of the 8×2 bit read out from the row direction of the memory mechanism is set to the bit b _i from the highest order bit, and the 8 symbols of the preceding two symbols are 8× The 2-bit symbol bit is set to the bit y _i from the highest-order bit, and the bit b _{0 is} assigned to the bit y ₇ , and the bit b _{1 is} assigned to the bit Element y ₂ , assigning bit b ₂ to bit y ₉ , assigning bit b ₃ to bit y ₀ , assigning bit b ₄ to bit y ₄ , and assigning bit b ₅ to bit y ₆ , assigning bit b ₆ to bit y ₁₃ , assigning bit b ₇ to bit y ₃ , assigning bit b ₈ to bit y ₁₄ , and assigning bit b ₉ to bit y ₁₀ , Bit b _{10 is} assigned to bit y ₁₅ , bit b _{11 is} assigned to bit y ₅ , bit b _{12 is} assigned to bit y ₈ , bit b _{13 is} assigned to bit y ₁₂ , bit is placed Element b _{14 is} assigned to bit y ₁₁ , bit b _{15 is} assigned to bit y ₁ , and each of the allocations is replaced; The inspection matrix of the LDPC code is formed by arranging one element of the information matrix defined by the check matrix initial value table of the check matrix in the row direction every 360-row period, and the check matrix initial value table will be the same as the aforementioned code length N and The position of the 1 element of the information matrix corresponding to the information length corresponding to the foregoing coding rate is represented by 360 lines; the foregoing check matrix initial value table includes 317 2255 2324 2723 3538 3576 6194 6700 9101 10057 12739 17407 21039 1958 2007 3294 4394 12762 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 10896 12486 13663 16398 16599 19475 19781 20625 20961 21335 4257 10449 12406 14561 16049 16522 17214 18029 18033 18802 19062 19526 20748 412 433 558 2614 2978 4157 6584 9320 11683 11819 13024 14486 16860 777 5906 7403 8550 8717 8770 11436 12846 13629 14755 15688 16392 16419 4093 5 045 6037 7248 8633 9771 10260 10809 11326 12072 17516 19344 19938 2120 2648 3155 3852 6888 12258 14821 15359 16378 16437 17791 20614 21025 1085 2434 5816 7151 8050 9422 10884 12728 15353 17733 18140 18729 20920 856 1690 12787 6532 7357 9151 4210 16615 18152 11494 14036 17470 2474 10291 10323 1778 6973 10739 4347 9570 18748 2189 11942 20666 3868 7526 17706 8780 14796 18268 160 16232 17399 1285 2003 18922 4658 17331 20361 2765 4862 5875 4565 5521 8759 3484 7305 15829 5024 17730 17879 7031 12346 15024 179 6365 11352 2490 3143 5098 2643 3101 21259 4315 4724 13130 594 17365 18322 5983 8597 9627 10837 15102 20876 10448 20418 21478 3848 12029 15228 708 5652 13146 5998 7534 16117 2098 13201 18317 9186 14548 17776 5246 10398 18597 3083 4944 21021 13726 18495 19921 6736 10811 17545 10084 12411 14432 1064 13555 17033 679 9878 13547 3422 9910 20194 3640 3701 10046 5862 10134 11498 5923 9580 15060 1073 3012 16427 5527 20113 20883 7058 12924 15151 9764 12230 17375 772 7711 12723 555 13816 15376 1057 4 11268 17932 15442 17266 20482 390 3371 8781 10512 12216 17180 4309 14068 15783 3971 11673 20009 9259 14270 17199 2947 5852 20101 3965 9722 15363 1429 5689 16771 6101 6849 12781 3676 9347 18761 350 11659 18342 5961 14803 16123 2113 9163 13443 2155 9808 12885 2861 7988 11031 7309 9220 20745 6834 8742 11977 2133 12908 14704 10170 13809 18153 13464 14787 14975 799 1107 3789 3571 8176 10165 5433 13446 15481 3351 6767 12840 8950 8974 11650 1430 4250 21332 6283 10628 15050 8632 14404 16916 6509 10702 16278 15900 16395 17995 8031 18420 19733 3747 4634 17087 4453 6297 16262 2792 3513 17031 14846 20893 21563 17220 20436 21337 275 4107 10497 3536 7520 10027 14089 14943 19455 1965 3931 21104 2439 11565 17932 154 15279 21414 10017 11269 16546 7169 10161 16928 10284 16791 20655 36 3175 8475 2605 16269 19290 8947 9178 15420 5687 9156 12408 8096 9738 14711 4935 8093 19266 2667 10062 15972 6389 11318 14417 8800 18137 18434 5824 5927 15314 6056 13168 15179 3284 13138 18919 13115 17259 17332.