TW200943737A - Data processing device and data processing method - Google Patents

Data processing device and data processing method

Info

Publication number
TW200943737A
TW200943737A TW97147861A TW97147861A TW200943737A TW 200943737 A TW200943737 A TW 200943737A TW 97147861 A TW97147861 A TW 97147861A TW 97147861 A TW97147861 A TW 97147861A TW 200943737 A TW200943737 A TW 200943737A
Authority
TW
Taiwan
Prior art keywords
bits
code
data processing
symbol
bit group
Prior art date
Application number
TW97147861A
Other languages
Chinese (zh)
Inventor
Satoshi Okada
Lui Sakai
Takashi Yokokawa
Makiko Yamamoto
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of TW200943737A publication Critical patent/TW200943737A/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6552—DVB-T2
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/3405—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power
    • H04L27/3416—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power in which the information is carried by both the individual signal points and the subset to which the individual points belong, e.g. using coset coding, lattice coding, or related schemes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/3488—Multiresolution systems

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Error Detection And Correction (AREA)

Abstract

A data processing device and method in which resistance to an error of data can be improved. A demultiplexer (25) rearranges mb bits of code bits and defines the rearranged code bits as b pieces of symbols of symbol bits according to an assignment rule to assign the code bits of an LDPC code to symbol bits representing symbols. The assignment rule defines groups for grouping the code bits and the symbol bits according to error probability as a code bit group and a symbol bit group, respectively, a combination of the code bit group and the symbol bit group of symbol bits to assign the code bits of the code bit group, and the number of bits of code bits and symbol bits. The data processing device and method can be applied to, e.g., a transmission system or the like to transmit an LDPC code.
TW97147861A 2008-03-18 2008-12-09 Data processing device and data processing method TW200943737A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008070467 2008-03-18

Publications (1)

Publication Number Publication Date
TW200943737A true TW200943737A (en) 2009-10-16

Family

ID=41090621

Family Applications (3)

Application Number Title Priority Date Filing Date
TW97147861A TW200943737A (en) 2008-03-18 2008-12-09 Data processing device and data processing method
TW098103711A TW201034392A (en) 2008-03-18 2009-02-05 Data process device, data process method, coding device, coding method
TW098103754A TWI389460B (en) 2008-03-18 2009-02-05 Data processing device and data processing method

Family Applications After (2)

Application Number Title Priority Date Filing Date
TW098103711A TW201034392A (en) 2008-03-18 2009-02-05 Data process device, data process method, coding device, coding method
TW098103754A TWI389460B (en) 2008-03-18 2009-02-05 Data processing device and data processing method

Country Status (2)

Country Link
TW (3) TW200943737A (en)
WO (1) WO2009116204A1 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8799735B2 (en) * 2008-12-31 2014-08-05 Mediatek Inc. Channel interleaver having a constellation-based unit-wise permuation module
JP5630278B2 (en) 2010-12-28 2014-11-26 ソニー株式会社 Data processing apparatus and data processing method
JP5630282B2 (en) * 2011-01-19 2014-11-26 ソニー株式会社 Data processing apparatus and data processing method
JP5630283B2 (en) * 2011-01-19 2014-11-26 ソニー株式会社 Data processing apparatus and data processing method
JP2012151656A (en) * 2011-01-19 2012-08-09 Sony Corp Data processing device and data processing method
JP2012151655A (en) * 2011-01-19 2012-08-09 Sony Corp Data processing device and data processing method
JP5637393B2 (en) * 2011-04-28 2014-12-10 ソニー株式会社 Data processing apparatus and data processing method
EP2525498A1 (en) 2011-05-18 2012-11-21 Panasonic Corporation Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes
EP2525496A1 (en) 2011-05-18 2012-11-21 Panasonic Corporation Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes
EP2525497A1 (en) 2011-05-18 2012-11-21 Panasonic Corporation Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes
EP2525495A1 (en) * 2011-05-18 2012-11-21 Panasonic Corporation Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes
JP5648852B2 (en) * 2011-05-27 2015-01-07 ソニー株式会社 Data processing apparatus and data processing method
JP5664919B2 (en) 2011-06-15 2015-02-04 ソニー株式会社 Data processing apparatus and data processing method
EP2536030A1 (en) * 2011-06-16 2012-12-19 Panasonic Corporation Bit permutation patterns for BICM with LDPC codes and QAM constellations
EP2552043A1 (en) * 2011-07-25 2013-01-30 Panasonic Corporation Spatial multiplexing for bit-interleaved coding and modulation with quasi-cyclic LDPC codes
EP2560311A1 (en) 2011-08-17 2013-02-20 Panasonic Corporation Cyclic-block permutations for spatial multiplexing with quasi-cyclic LDPC codes

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060097503A (en) * 2005-03-11 2006-09-14 삼성전자주식회사 Channel interleaving/de-interleaving apparatus in a communication system using a low density parity check code and control method thereof
JP2007214783A (en) * 2006-02-08 2007-08-23 Kddi Corp Transmission device, reception device, and transmitting method

Also Published As

Publication number Publication date
TWI389460B (en) 2013-03-11
TW200952349A (en) 2009-12-16
TW201034392A (en) 2010-09-16
WO2009116204A1 (en) 2009-09-24

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