Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/709—Circuitry for control of the power supply
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
  • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
  • H04N25/767—Horizontal readout lines, multiplexers or registers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
  • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/12—Image sensors
  • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors

Definitions

• the present invention relates to an image sensing device and imaging system.
• driving signals are supplied to respective pixels via a plurality of row control lines extending in the row direction, and signals are read out from respective pixels via a plurality of column signal lines extending in the column direction.
• Accumulation capacitances are connected to one end and the other end of each column signal line, respectively.
• a signal output from a pixel is accumulated in the other accumulation capacitance (see Fig. 21) .
• two accumulation capacitances are parallel-connected to one end of each column signal line.
• a signal output from a pixel is accumulated in the other accumulation capacitance (see Fig. 22).
• the blanking period (during which no sensor output is obtained) is shortened to thereby shorten the total readout period.
• two accumulation capacitances and two amplifiers are alternately connected to respective column signal lines.
• a signal accumulated in one of the two accumulation capacitances is amplified by one of the two amplifiers, and the amplified signal is accumulated in the other accumulation capacitance.
• the signal accumulated in the other accumulation capacitance is amplified by the other amplifier, and read out to a subsequent output line.
• an image sensing device characterized by comprising: a pixel array in which a plurality of pixels are two-dimensionally arrayed and output signals to a plurality of signal lines; a plurality of first holding capacitances which hold a first signals transferred via the plurality of signal lines; a plurality of second holding capacitances which hold a second signals transferred at different timing from the first signals via the plurality of signal lines; a first reference power supply pattern for the plurality of first holding capacitances; and a second reference power supply pattern for the plurality of second holding capacitances, wherein at least part of the first reference power supply pattern is arranged in a first region where reference power supply electrodes of the plurality of first holding capacitances are arrayed, at least part - of the second reference power supply pattern is arranged in a second region where reference power supply electrodes of the plurality of second holding capacitances are arrayed, and the first reference power supply pattern and the second reference power
• an imaging system characterized by comprising: an image sensing device according to the first aspect of the present invention; an optical system which forms an image on an image sensing surface of the image sensing device; and a signal processing unit which processes a signal output from the image sensing device to generate image data.
• an imaging system characterized by comprising: an image sensing device according to the first aspect of the present invention; an optical system which forms an image on an image sensing surface of the image sensing device; and a signal processing unit which processes a signal output from the image sensing device to generate image data.
• Fig. 1 is a diagram showing the schematic arrangement of an image sensing device 1 according to the first embodiment of the present invention
• Fig. 2 is a circuit diagram showing an example of the circuit arrangement of the image sensing device 1 according to the first embodiment of the present invention
• Fig. 3 is a circuit diagram showing a simple arrangement in Fig. 2;
• Fig. 4 is a timing chart showing the operation of the image sensing device 1 according to the first embodiment of the present invention
• Fig. 5 is a diagram showing, the schematic arrangement of an image sensing device Ia according to a modification to the first embodiment of the present invention
• FIG. 6 is a diagram showing the schematic arrangement of an image sensing device Ib according to another modification to the first embodiment of the present invention.
• Fig. 7 is a sectional view showing an example of the sectional structure of the first and second holding capacitances (modification) ;
• Fig. 8 is a plan view showing an example of the layout of the first and second holding capacitances
• Fig. 9 is a sectional view showing a holding capacitance (modification) ;
• Fig. 10 is a sectional view showing a holding capacitance (modification) ;
• FIG. 11 is a block diagram showing the configuration of an imaging system to which the image sensing device according to the first embodiment is applied;
• Fig. 12 is a plan view showing an example of the layout of an image sensing device according to the second embodiment of the present invention.
• Fig. 13 is a plan view showing an example of the layout of a holding capacitance (modification) ;
• Fig. 14 is a diagram showing the arrangement of an image sensing device according to the third embodiment of the present invention.
• Fig. 15 is a circuit diagram showing an example of the circuit arrangement of the image sensing device according to the third embodiment of the present invention.
• Fig. 16 is a timing chart showing the operation of the image sensing device according to the third embodiment of the present invention.
• FIG. 17 is a diagram showing the arrangement of an image sensing device according to the fourth embodiment of the present invention.
• Fig. 18 is a circuit diagram showing an example of the circuit arrangement of the image sensing device according to the fourth embodiment of the present invention.
• FIG. 19 is a diagram showing the arrangement of an image sensing device according to a modification to the fourth embodiment of the present invention.
• Fig. 20 is a view for explaining a problem to be solved by the present invention.
• Fig. 21 is a diagram for explaining a conventional technique.
• Fig. 22 is a diagram for explaining a conventional technique. BEST MODE FOR CARRYING OUT THE INVENTION
• Fig. 1 is a diagram showing the schematic arrangement of the image sensing device 1 according to the first embodiment of the present invention.
• the image sensing device 1 includes a pixel array PA, a vertical scanning circuit (VSR) 102, a plurality of first holding capacitances 103, a plurality of second holding capacitances 104, a horizontal scanning circuit (HSR) 106, a first reference power supply pattern 107, a second reference power supply pattern 108, and a common reference power supply pattern 120.
• VSR vertical scanning circuit
• HSR horizontal scanning circuit
• a plurality of pixels All to B2n are arrayed two-dimensionally .
• a plurality of pixels All to B2n are arrayed in the row and column directions.
• the row direction is defined as a direction along a row or defined as a direction across the signal line 100.
• the column direction is defined as a direction along a column or defined as a direction along the signal line 100.
• Each of the pixels All to B2n includes a photoelectric conversion unit PD, transfer unit Ml, charge-voltage converter FD, and output unit M2 (see Fig. 3) .
• the photoelectric conversion unit PD accumulates charges generated in accordance with incident light.
• the photoelectric conversion unit PD is, for example, a photodiode.
• the transfer unit Ml Upon receiving an active-level transfer signal ⁇ TX from the vertical scanning circuit 102, the transfer unit Ml transfers charges generated in the photoelectric conversion unit PD to the charge-voltage converter FD.
• the transfer unit Ml is, for example, a transfer MOS transistor.
• the charge-voltage converter FD converts transferred charges into a voltage, and inputs the converted voltage to the output unit M2.
• the charge-voltage converter FD is, for example, a floating diffusion.
• the output unit M2 outputs a signal corresponding to the input voltage to a column signal line 100.
• the output unit M2 is, for example, an amplification MOS transistor which forms a source follower circuit together with a constant current source CS connected to the column signal line 100.
• a plurality of column signal lines 100 extend in the column direction, and transfer signals output from pixels in respective columns.
• the vertical scanning circuit 102 scans the pixel array PA in the vertical direction (column direction) to drive the pixels All to B2n so as to output signals to the column signal lines 100.
• the plurality of first holding capacitances 103 are connected to pixels in a plurality of columns via the plurality of column signal lines 100.
• the plurality of first holding capacitances 103 hold signals transferred via the plurality of column signal lines 100.
• Each first holding capacitance includes a signal electrode (first electrode) for receiving a signal, and a reference power supply electrode for receiving a reference power, which will be described later. In each first holding capacitance, the signal electrode and reference power supply electrode are arranged to form a capacitance.
• the signal electrode and reference power supply electrode are arranged to face each other.
• the first holding capacitances 103 are arranged in a first region Rl.
• the plurality of second holding capacitances 104 are connected to pixels in a plurality of columns via the plurality of column signal lines 100.
• the plurality of second holding capacitances 104 hold other signals transferred via the plurality of column signal lines 100.
• Each second holding capacitance includes a signal electrode (second electrode) for receiving a signal, and a reference power supply electrode for receiving a reference power, which will be described later.
• the signal electrode and reference power supply electrode are arranged to form a capacitance.
• the signal electrode and reference power supply electrode are arranged to face each other.
• the second holding capacitances 104 are arranged in a second region R2.
• the horizontal scanning circuit 106 scans the plurality of first holding capacitances 103 and the plurality of second holding capacitances 104 in the horizontal direction (row direction) . Signals held in the plurality of first holding capacitances and other signals held in the plurality of second holding capacitances are sequentially read out to common output lines 105.
• the first reference power supply pattern 107 is a pattern for the plurality of first holding capacitances, and part of it is arranged in the first region Rl.
• the first reference power supply pattern is a pattern which is obtained by patterning a conductor.
• the first reference power supply pattern is, for example, a metal wiring.
• the second reference power supply pattern 108 is a pattern for the plurality of second holding capacitances, and part of it is arranged in the second region R2.
• the second reference power supply pattern 108 is electrically connected to the reference power supply electrode of each second holding capacitance.
• the second reference power supply pattern is a pattern which is obtained by patterning a conductor.
• the second reference power supply pattern is, for example, a metal wiring.
• the common reference power supply pattern 120 electrically connects the first reference power supply pattern 107 and second reference power supply pattern 108 outside a region CR.
• the region CR includes the first region Rl and second region R2.
• the common reference power supply pattern 120 is electrically connected to reference power supply pads 109.
• a width W120 of the common reference power supply pattern 120 is larger than a width W107 of the first reference power supply pattern 107 and a width W108 of the second reference power supply pattern 108.
• the wiring resistance of the common reference power supply pattern 120 is lower than that of the first reference power supply pattern 107 and that of the second reference power supply pattern 108.
• the first reference power supply pattern 107 and second reference power supply pattern 108 are isolated between at least the first region Rl and the second region R2 in the region CR including the first region Rl and second region R2. Even if the potential of the reference power supply electrode of the first holding capacitance fluctuates when transferring a signal from a pixel to the first holding capacitance, the fluctuations of the potential are hardly directly transferred from the first reference power supply pattern 107 to the second reference power supply pattern 108. Hence, the potential of the reference power supply electrode of the second holding capacitance hardly fluctuates. That is, when transferring a signal from a pixel to one of two holding capacitances for holding signals transferred at different timings via a column signal line, fluctuations of the potential of the reference power supply electrode of the other holding capacitance can be suppressed.
• an insulator arranged between the first reference power supply pattern 107 and second reference power supply pattern 108 to isolate the both reference power supply patterns 107, 108.
• the insulator includes, for example, a silicon oxide or a silicon nitride as a main component.
• Fig. 2 is a circuit diagram showing an example of the circuit arrangement of the image sensing device 1 according to the first embodiment of the present invention.
• Fig. 3 is a circuit diagram showing a simple arrangement in Fig. 2.
• holding capacitances of each column in the plurality of first holding capacitances 103 are indicated as first holding capacitances 1031.
• the first holding capacitance 1031 includes a capacitance Ctnl and Ctsl.
• the capacitance Ctnl holds a reference signal component (noise-level N signal) output from the first pixel (e.g., the pixel All).
• the capacitance Ctsl holds a pixel signal component (optical signal-level S signal) output from the first pixel.
• the capacitances Ctnl and Ctsl are arranged in the first region Rl.
• the reference power supply- electrodes of the capacitances Ctnl and Ctsl are connected to the first reference power supply pattern 107.
• a switching element TnI Upon receiving an active-level control pulse ⁇ Tnl, a switching element TnI is turned on to connect the column signal line 100 to the capacitance Ctnl. The capacitance Ctnl accumulates an N signal transferred from the first pixel via the column signal line 100. Upon receiving a nonactive-level control pulse ⁇ Tnl, the switching element TnI is turned off to disconnect the column signal line 100 from the capacitance Ctnl . The capacitance Ctnl holds an N signal .
• a switching element TsI Upon receiving an active-level control pulse ⁇ Tsl, a switching element TsI is turned on to connect the column signal line 100 to the capacitance Ctsl. The capacitance Ctsl accumulates an S signal transferred from the first pixel via the column signal line 100. Upon receiving a nonactive-level control pulse ⁇ Tsl, the switching element TsI is turned off to disconnect the column signal line 100 from the capacitance Ctsl. The capacitance Ctsl holds an S signal .
• holding capacitances of each column in the second holding capacitances 104 are indicated as second holding capacitances 1041.
• the second holding capacitance 1041 includes a capacitance Ctn2 and Cts2.
• the capacitance Ctn2 holds a reference signal component (noise-level N signal) output from the second pixel (e.g., the pixel BIl) .
• the capacitance Cts2 holds a pixel signal component (optical signal- level S signal) output from the second pixel.
• the capacitances Ctn2 and Cts2 are arranged in the second region R2.
• the reference power supply electrodes of the capacitances Ctn2 and Cts2 are connected to the second reference power supply pattern 108.
• a switching element Tn2 Upon receiving an active-level control pulse ⁇ Tn2, a switching element Tn2 is turned on to connect the column signal line 100 to the capacitance Ctn2.
• the capacitance Ctn2 accumulates an N signal transferred from the second pixel via the column signal line 100.
• the switching element Tn2 is turned off to disconnect the column signal line 100 from the capacitance Ctn2.
• the capacitance Ctn2 holds an N signal.
• a switching element Ts2 Upon receiving an active-level control pulse ⁇ Ts2, a switching element Ts2 is turned on to connect the column signal line 100 to the capacitance Cts2. The capacitance Cts2 accumulates an S signal transferred from the second pixel via the column signal line 100. Upon receiving a nonactive-level control pulse ⁇ Ts2, the switching element Ts2 is turned off to disconnect the column signal line 100 from the capacitance Cts2. The capacitance Cts2 holds an S signal .
• a switching element Hl is turned on in the first period in which the horizontal scanning circuit 106 selects a certain column (e.g., a column of the pixels All to B21) and a control signal ⁇ Sl is active.
• a certain column e.g., a column of the pixels All to B21
• a control signal ⁇ Sl is active.
• the N signal of the first pixel held in the capacitance Ctnl and the S signal of the first pixel held in the capacitance Ctsl are read out to the common output lines 105, and supplied to a differential amplifier 201.
• the differential amplifier 201 calculates the difference between the N and S signals of the first pixel (performs CDS processing) , and thereby outputs an image signal of the first pixel free from the noise component .
• a switching element H2 is turned on in the second period in which the horizontal scanning circuit 106 selects the certain column and a control signal ⁇ S2 is active.
• the N signal of the second pixel held in the capacitance Ctn2 and the S signal of the second pixel held in the capacitance Cts2 are read out to the common output lines 105, and supplied to the differential amplifier 201.
• the differential amplifier 201 calculates the difference between the N and S signals of the second pixel (performs CDS processing) , and thereby outputs an image signal of the second pixel free from the noise component.
• FIG. 4 is a timing chart showing the operation of the image sensing device 1 according to the first embodiment of the present invention.
• a control signal ⁇ Tx shown in Fig. 4 is supplied from the vertical scanning circuit 102 to the transfer unit Ml (see Fig. 3) of each pixel of the pixel array PA.
• Control signals ⁇ Hl and ⁇ H2 are supplied from the horizontal scanning circuit 106 via the switching elements Sl and S2 to the switching elements Hl and H2, respectively.
• the remaining control signals are supplied from the vertical scanning circuit 102, the horizontal scanning circuit 106, or a timing generator 98 (see Fig. 11) .
• control signal ⁇ Tnl changes to an active level to turn on the switching elements TnI and transfer the N signals of pixels in the (k+l)th row to the capacitances Ctnl.
• the control signal ⁇ Tsl changes to an active level to turn on the switching elements TsI.
• the control signal ⁇ Tx changes to an active level to turn on the transfer units (transfer MOS transistors) Ml of pixels in the (k+l)th row and transfer the S signals of the pixels in the (k+l)th row to the capacitances Ctsl.
• the operation to read out the signals of pixels in the (k)th row to the common output lines and the operation to transfer the signals of pixels in the (k+l)th row to the holding capacitances are parallel-executed in the horizontal transferring period HTk.
• the horizontal transferring period HTk for the signals of pixels in the (k)th row and a horizontal blanking period (BLK period) BLKk+1 for the signals of pixels in the (k+l)th row overlap each other.
• the vertical scanning circuit 102 is driven.
• a horizontal transferring period HTk+1 which starts at timing t5
• the control signals ⁇ Hl of respective columns sequentially changes to an active level to sequentially turn on the switching elements Hl of the respective columns.
• the N and S signals of pixels in the (k+l)th row are read out from the capacitances Ctnl and Ctsl of the respective columns to the common output lines 105.
• control signal ⁇ Tn2 changes to an active level to turn on the switching elements Tn2 and transfer the N signals of pixels in the (k+2)th row to the capacitances Ctn2.
• the control signal ⁇ Ts2 changes to an active level to turn on the switching elements Ts2.
• the control signal ⁇ Tx changes to an active level to turn on the transfer units (transfer MOS transistors) Ml of pixels in the (k+2)th row and transfer the S signals of the pixels in the (k+2)th to the capacitances Cts2.
• the operation to read out the signals of pixels in the (k+l)th row to the common output lines and the operation to transfer the signals of pixels in the (k+2)th row to the holding capacitances are parallel-executed in the horizontal transferring period HTk+1.
• the horizontal transferring period HTk+1 for the signals of pixels in the (k+l)th row and the horizontal blanking period BLKk+2 for the signals of pixels in the (k+2)th row overlap each other.
• the BLK period overlaps the horizontal transferring period of a preceding row, as described above, the readout time is shortened to increase the number of shooting frames (shooting count) per unit time.
• the switching element Ts2 is turned on, and the transfer unit (transfer MOS transistor) Ml of the predetermined pixel is subsequently turned on to transfer the pixel signal to the capacitance Cts2.
• the capacitance Cts2 holds a large signal component in a preceding frame especially upon light irradiation, charges move at the timing when the switching element Ts2 is turned on.
• the reference power supply pattern has a resistance component (wiring resistance) , a reference power supply potential transferred by the reference power supply pattern fluctuates upon movement of charges .
• FIG. 20 is a view showing fluctuations of the potential of the reference power supply electrode of the capacitance Ctn2 or Cts2 upon turning on the switching element TsI when the first and second holding capacitances are connected to one reference power supply pattern.
• the potential of the reference power supply electrode of the second holding capacitance fluctuates at the timing when the switching element Ts is turned on. A long time is taken to stabilize a signal held in the second holding capacitance. Further, the amount of charges held in the holding capacitance is different between low- and high-luminance signals of an object, so the level of mixed noise changes. It is difficult to correct noise whose level fluctuates over a predetermined period and changes depending on the luminance .
• the reference power supply electrodes of the first holding capacitance 1031 (Ctnl and Ctsl) and second holding capacitance 1041 (Ctn2 and Cts2) are connected to the first reference power supply pattern - 2A -
• the reference power supply electrodes of the first holding capacitance 1031 (Ctnl and Ctsl) and second holding capacitance 1041 (Ctn2 and Cts2) are electrically isolated from each other in the region CR (see Fig. 1) including the first region Rl and second region R2. Hence, even if the potential of the reference power supply electrode of Cts2 fluctuates, the potentials of the reference power supply electrodes of Ctnl and Ctsl hardly fluctuate (for example, the amplitude of noise is about 1/10 of that shown in Fig. 20) .
• the reference power supply electrodes of holding capacitances in an region where the holding capacitances are arranged. It is relatively easy to increase the width of the reference power supply pattern and the influence on the reference power supply electrode of the reference power supply pattern is limited outside an region where pixels are arrayed and outside an region where holding capacitances are arranged. In this region, the reference power supply patterns of the first and second holding capacitances need not always be isolated. In the first embodiment, as shown in Fig.
• the first reference power supply pattern 107 of the first holding capacitance 103 and the second reference power supply pattern 108 of the second holding capacitance 104 are electrically isolated in the region CR including the first region Rl and second region R2. Since a large- area wiring pattern can be formed outside the region CR, the first reference power supply pattern 107 and second reference power supply pattern 108 are connected to the wide common reference power supply pattern 120, preventing an increase in the number of pads. If an increase in the number of pads is permitted, an image sensing device Ia may also be configured as shown in Fig. 5. More specifically, the first reference power supply pattern 107 and second reference power supply pattern 108 are electrically isolated till pads by connecting them to first reference power supply pads 110 and second reference power supply pads 111, respectively.
• a reference power supply voltage applied from the reference power supply pattern to the reference power supply electrode of a holding capacitance Ct may be a ground voltage or another fixed voltage serving as a reference.
• the circuit arrangement is not limited to one in the first embodiment as long as the first and second holding capacitances are arranged and the BLK operation can be executed during the horizontal transferring period.
• amplifiers may be arranged between the pixels in respective columns and the first holding capacitances.
• an N signal of each column may include an offset of the amplifier.
• the amplifier performs a clamp operation to generate a difference signal between the above-described noise- level signal and the above-described optical signal- level signal.
• An S signal of each column may include the difference signal in addition to the offset.
• the first and second holding capacitances are arranged on only one side of the pixel array PA, but an image sensing device Ib may also be configured as shown in Fig. 6. More specifically, the first and second holding capacitances, common output lines, and a horizontal scanning circuit may be arranged on the other side of the pixel array PA as well. In this case, pixel signals can be read out to the upper or lower part for each column, further increasing the readout speed (further shortening the total readout period) .
• Fig. 7 is a sectional view showing an example of the sectional structure of the first and second holding capacitances.
• a well 702 of the p type (second conductivity type) opposite to the n type (first conductivity type) is formed in an n-type semiconductor region 701 in a semiconductor substrate SB.
• a first n-type semiconductor region 703 as the reference power supply electrode of the first holding capacitance 1031 is formed in the well 702 (in the well) .
• a polysilicon layer 705 is deposited on an oxide film 704 on the first semiconductor region 703.
• a first holding capacitance 1031 is formed using the polysilicon layer 705 as a signal electrode and the first semiconductor region 703 as a reference power supply electrode.
• the potential of the p-type well 702 formed in the n-type semiconductor region 701 (in the semiconductor region) is the reference power supply potential.
• the first semiconductor region 703 formed in the well 702 is connected to the reference power supply potential via the reference power supply pattern.
• a signal is written in the top polysilicon layer 705.
• a second n-type semiconductor region 706 serving as the reference power supply electrode of the second holding capacitance 1041 is formed.
• a polysilicon layer 708 is deposited on an oxide film 707 on the second semiconductor region 706.
• the polysilicon layer 708 functions as the signal electrode of the second holding capacitance 1041, and the second semiconductor region 706 functions as the reference power supply electrode of the second holding capacitance 1041.
• the potential of the p-type well 702 formed in the n-type semiconductor region 701 is the reference power supply potential.
• the second semiconductor region 706 formed in the well 702 is connected to the reference power supply potential via the reference power supply pattern.
• a signal is written in the polysilicon layer 708.
• the second semiconductor region 706 is electrically isolated from the first semiconductor region 703 in the well 702. This structure prevents fluctuations of the potential of the reference power supply electrode of the first holding capacitance from transferring to the reference power supply electrode of the second holding capacitance.
• Fig. 8 is a plan view showing an example of the layout of the first and second holding capacitances .
• the polysilicon layer 705, and the first semiconductor region 703 in the well 702 form the first holding capacitance 1031.
• the polysilicon layer 708, and the second semiconductor region 706 in the well 702 form the second holding capacitance 1041.
• the layout shown in Fig. 8 can easily implement a circuit arrangement (see Fig. 2) in which the first and second holding capacitances are configured to receive signals of pixels in parallel between the column signal lines and the common output lines .
• the layout shown in Fig. 8 may also be used to implement a circuit arrangement (see Fig. 15) in which the first and second holding capacitances are configured to receive a signal of a pixel in series between the column signal lines and the common output lines .
• the holding capacitance may not always have a MOS capacitor structure.
• the holding capacitance may also have a "metal/insulation film/metal” structure shown in Fig. 9 or a "polysilicon/insulation film/polysilicon” structure shown in Fig. 10 as long as at least the reference power supply electrodes of the first and second holding capacitances are electrically isolated from each other.
• FIG. 11 shows an example of an imaging system to which the image sensing device according to the present invention is applied.
• an imaging system 90 mainly includes an optical system, the image sensing device 1, and a signal processing unit.
• the optical system mainly includes a shutter 91, lens 92, and stop 93.
• the signal processing unit mainly includes a sensed signal processing circuit 95, an A/D converter 96, an image signal processor 97, a memory 87, an external I/F 89, the timing generator 98, an overall control/arithmetic unit 99, a recording medium 88, and a. recording medium control I/F 94.
• the signal processing unit may not include the recording medium 88.
• the shutter 91 is arranged in front of the lens 92 on the optical path to control the exposure.
• the lens 92 refracts incident- light to form an object image on the pixel array (image sensing surface) of the image sensing device 1.
• the stop 93 is interposed between the lens 92 and the image sensing device 1 on the optical path. The stop 93 adjusts the quantity of light guided to the image sensing device 1 after passing through the lens 92.
• the image sensing device 1 converts an object image formed on the pixel array into an image signal.
• the image sensing device 1 reads out the image signal from the pixel array, and outputs it.
• the sensed signal processing circuit 95 is connected to the image sensing device 1, and processes an image signal output from the image sensing device 1.
• the A/D converter 96 is connected to the sensed signal processing circuit 95.
• the A/D converter 96 converts a processed image signal (analog signal) output from the sensed signal processing circuit 95 into an image signal (digital signal) .
• the image signal processor 97 is connected to the A/D converter 96.
• the image signal processor 97 performs various arithmetic processes such as correction for an image signal (digital signal) output from the A/D converter 96, generating image data.
• the image signal processor 97 supplies the image data to the memory 87, external I/F 89, overall control/arithmetic unit 99, recording medium control
• the memory 87 is connected to the image signal processor 97, and stores image data output from the image signal processor 97.
• the external I/F 89 is connected to the image signal processor 97.
• Image data output from the image signal processor 97 is transferred to an external device (e.g., a personal computer) via the external I/F
• the timing generator 98 is connected to the image sensing device 1, sensed signal processing circuit 95, A/D converter 96, and image signal processor 97.
• the timing generator 98 supplies timing signals to the image sensing device 1, sensed signal processing circuit 95, A/D converter 96, and image signal processor 97.
• the image sensing device 1, sensed signal processing circuit 95, A/D converter 96, and image signal processor 97 operate in synchronism with the timing signals.
• the overall control/arithmetic unit 99 is connected to the timing generator 98, image signal processor 97, and recording medium control I/F 94, and controls all of them.
• the recording medium 88 is detachably connected to the recording medium control I/F 94.
• Image data output from the image signal processor 97 is recorded on the recording medium 88 via the recording medium control I/F 94.
• the image sensing device 1 can provide a high-quality image (image data) as long as it can obtain a high-quality image signal.
• An image sensing device according to the second embodiment of the present invention will be explained with reference to Fig. 12.
• Fig. 12 is a plan view showing an example of the layout of the image sensing device according to the second embodiment of the present invention.
• the arrangement of the image sensing device according to the second embodiment is different from the first embodiment in the following point. Pairs each formed by arranging a first holding capacitance 1031 and second holding capacitance 1041 in the vertical direction (column direction) are repetitively arrayed in the horizontal direction (row direction) . More specifically, a plurality of first holding capacitances 103 and a plurality of second holding capacitances 104 are arranged to be aligned in the column direction in an region CR including a first region Rl and second region R2.
• the layout shown in Fig. 12 can easily implement a circuit arrangement (see Fig. 15) in which the first and second holding capacitances are configured to receive a signal of a pixel in series between the column signal lines and common output lines.
• the layout shown in Fig. 12 may also be used to implement a circuit arrangement (see Fig. 2) in which the first and second holding capacitances are configured to receive signals of pixels in parallel between the column signal lines and common output lines.
• a first well 702a and second well 702b may also be formed instead of the well 702.
• the first well 702a is a p-type region arranged in a n-type semiconductor region 701 in the first region Rl.
• the second well 702b is a p-type region arranged in the n- type semiconductor region 701 in the second region R2 to be isolated from the first well 702a, because the n- type semiconductor region 701 exists between the first p-type well 702a and the second p-type well 702b.
• a first semiconductor region 703 serving as the reference power supply electrode of the first holding capacitance 1031 is arranged in the first well 702a.
• a second semiconductor region 706 serving as the reference power supply electrode of the second holding capacitance 1041 is arranged in the second well 702b.
• This structure prevents fluctuations of the potential of the reference power supply electrode of the first holding capacitance 1031 from transferring to the reference power supply electrode of the second holding capacitance 1041.
• this structure prevents fluctuations of the potential of the reference power supply electrode of the second holding capacitance 1031 from transferring to the reference power supply electrode of the first holding capacitance 1041.
• FIG. 14 is a diagram showing the arrangement of the image sensing device according to the third embodiment of the present invention.
• Fig. 15 is a circuit diagram showing an example of the circuit arrangement of the image sensing device according to the third embodiment of the present invention.
• the arrangement of the image sensing device according to the third embodiment is different from the first embodiment in the following point.
• the first holding capacitances 1031 and second holding capacitances 1041 are configured to receive a signal of a pixel in series between a column signal line 100 and common output lines 105.
• Amplifiers 1121 and switches 1141 are interposed between the first holding capacitances 1031 and the second holding capacitances 1041.
• the amplifiers 1121 include, for example, buffer amplifiers BAn and BAs.
• the switches 1141 include, for example, switching elements Tn3 and Ts3.
• amplifiers of each column in a plurality of amplifiers (a plurality of first amplifiers) 112 are indicated as the amplifiers 1121, and switches of each column in a plurality of switches 114 are indicated as the switches 1141.
• the plurality of amplifiers 112 is interposed between a plurality of first holding capacitances 103 and a plurality of second holding capacitances 104.
• the plurality of amplifiers 112 correspond to the plurality of first holding capacitances 103 and also correspond to the plurality of second holding capacitances 104.
• Signals held in the first holding capacitances 103 are output to the corresponding amplifiers 112.
• the amplifiers 112 amplify signals held in the corresponding first holding capacitances 103.
• the second holding capacitances 104 hold, as other signals, signals amplified by the corresponding amplifiers 112. Then, the other signals held in the second holding capacitances 104 are read out to common output lines 105.
• An output unit 130 outputs a signal transferred via the common output lines 105. Because the amplifier 1121 interposed between the first and second holding capacitances can amplify a signal, the capacitance value of each first holding capacitance 103 may be smaller than that of each second holding capacitance 104. This enable the layout area of the the first and second holding capacitances to be reduced. [0110] Other signals held in the second holding capacitances are read out to the output unit 130 by capacitive division based on the capacitance value of the second holding capacitance 1041 and that of the common output line 105.
• each second holding capacitance 104 is larger than that of each first holding capacitance 103, so other signals can be read out to the common output lines without decreasing the gain.
• the capacitance values can be compared based on the electrode area as long as holding capacitances have, for example, the similar structure (structure having the same electrode interval, insulation film dielectric constant, and the like) .
• control signals ⁇ Hl of respective columns sequentially change to an active level to sequentially turn on switching elements Hl of the respective columns .
• control signals ⁇ Tn3 and ⁇ Ts3 change to an active level to turn on the switching elements Tn3 and Ts3.
• the N signals of pixels in the (k+l)th row are transferred from the capacitances Ctnl via the buffer amplifiers BAn to the capacitances Ctn2 on respective columns, and the S signals are transferred from the capacitances Ctsl via the buffer amplifiers BAs to the capacitances Cts2 on the respective columns.
• Fig. 17 is a diagram showing the arrangement of the image sensing device according to the fourth embodiment of the present invention.
• FIG. 18 is a circuit diagram showing an example of the circuit arrangement of the image sensing device according to the fourth embodiment of the present invention.
• the arrangement of the image sensing device according ' to the fourth embodiment is different from the first embodiment in the following point.
• a plurality of amplifiers (a plurality of second amplifiers) 113 is interposed between column signal lines 100 and first holding capacitances 103.
• a switch VL is interposed between each column signal line 100 and each amplifier 1131 to connect or disconnect the column signal line 100 and a capacitance CO.
• a switch COR for the clamping operation, and a plural sets of switches SWl to SW3 & capacitances CfI to Cf3 are parallel-connected between the input and output terminals of the amplifier 1131.
• the switch COR turns on/off to connect/disconnect the feed back path of the amplifier and thereby performs the clamping operation.
• the switches SWl to SW3 turns on/off to activate/deactivate the corresponding capacitance CfI to Cf3 and thereby change a value of feed back capacitances of the amplifier.
• the amplifier 1131 can apply a gain at a ratio of CO/ (sum of selected ones of CfI to Cf3) .
• CfI to Cf3 are selected by turning on the switches SWl to SW3 series-connected to them. That is, the gain of the amplifier 1131 can be changed by changing the feedback capacitance of the amplifier 1131.
• Each of the plurality of amplifiers 112 and a second reference power supply pattern 108 are electrically connected in a second region R2, as shown in Fig. 17.
• Each of the amplifiers 113 and a third reference power supply pattern 114 are electrically connected in a third region R3.
• the third region R3 is defined between a pixel array PA and a first region Rl.
• each of the amplifiers 113 and a first reference power supply pattern 107 may also be electrically connected in the first region Rl.
• an N signal of each column may include the above-described noise-level signal and an offset of the amplifier 1131 and that an S signal of each column may include the above-described optical signal-level signal and the offset.
• an N signal of each column ' may include an offset of the amplifier 1131.
• the amplifier performs a clamp operation to generate a difference signal between the above-described noise-level signal and the above- described optical signal-level signal.
• An S signal of each column may include the difference signal in addition to the offset.

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• Engineering & Computer Science (AREA)
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• Solid State Image Pick-Up Elements (AREA)
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