WO2009096338A1 - 固体撮像装置及びそれを含むx線ct装置 - Google Patents
固体撮像装置及びそれを含むx線ct装置 Download PDFInfo
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- WO2009096338A1 WO2009096338A1 PCT/JP2009/051105 JP2009051105W WO2009096338A1 WO 2009096338 A1 WO2009096338 A1 WO 2009096338A1 JP 2009051105 W JP2009051105 W JP 2009051105W WO 2009096338 A1 WO2009096338 A1 WO 2009096338A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
- G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
- G01T1/16—Measuring radiation intensity
- G01T1/24—Measuring radiation intensity with semiconductor detectors
- G01T1/247—Detector read-out circuitry
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
- G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
- G01T1/16—Measuring radiation intensity
- G01T1/24—Measuring radiation intensity with semiconductor detectors
- G01T1/249—Measuring radiation intensity with semiconductor detectors specially adapted for use in SPECT or PET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14654—Blooming suppression
- H01L27/14656—Overflow drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/30—Circuitry of solid-state image sensors [SSIS]; Control thereof for transforming X-rays into image signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
- H04N25/621—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
- H04N25/622—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming by controlling anti-blooming drains
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/30—Transforming light or analogous information into electric information
- H04N5/32—Transforming X-rays
Definitions
- the present invention relates to a solid-state imaging device including a plurality of light receiving units arranged two-dimensionally, and an X-ray CT apparatus including the same.
- PPS Passive Pixel Sensor
- the PPS solid-state imaging device has a structure in which PPS pixel portions including photodiodes that generate an amount of electric charge corresponding to incident light intensity are two-dimensionally arranged in M rows and N columns. In each pixel portion, the charge generated by the photodiode in response to light incidence is stored in the capacitor element of the integration circuit, and a voltage value corresponding to the amount of stored charge is output.
- the output ends of each of the M pixel units belonging to each column are connected to the input ends of the integration circuits provided corresponding to the columns via readout wirings provided corresponding to the columns. It is connected. Then, in order from the first row to the M-th row, the charges generated in the photodiodes of the pixel portion are input to the corresponding integration circuit via the corresponding readout wiring, and the voltage value corresponding to the charge amount from the integration circuit. Is output.
- each of the N pixel units belonging to each row is connected to the control unit via a row selection wiring provided corresponding to the row.
- each pixel unit outputs charges generated in the photodiode to the readout wiring.
- a PPS solid-state imaging device is used in various applications.
- a PPS solid-state imaging device is combined with a scintillator panel and used as an X-ray flat panel sensor in medical applications and industrial applications.
- the PPS solid-state imaging device is specifically used in an X-ray CT apparatus, a microfocus X-ray inspection apparatus, and the like.
- a solid-state imaging device used for such an application includes a large-area light-receiving unit in which M ⁇ N pixel units are two-dimensionally arranged, and the light-receiving unit has a side length exceeding 10 cm. In some cases, it is integrated on a semiconductor substrate. Therefore, only one solid-state imaging device may be manufactured from one semiconductor wafer. JP 2006-234557 A JP 2001-027673 A
- the inventors have found the following problems. That is, in the conventional solid-state imaging device, when the readout wiring corresponding to any column is disconnected during manufacture, the M pixel units belonging to that column are positioned closer to the integration circuit than the disconnection position. The pixel portion to be connected is connected to the integration circuit by the readout wiring, but the pixel portion located far from the disconnection position with respect to the integration circuit is not connected to the integration circuit.
- the charge generated in the photodiode in response to light incidence in the pixel portion located far from the disconnection position with respect to the integration circuit is not read out to the integration circuit, and the photodiode It is being accumulated in the junction capacitance part.
- the row selection wiring corresponding to any one of the rows is disconnected in the middle of manufacturing, among the N pixel portions belonging to the row, the pixel portion located closer to the row selection portion than the disconnection position is Although connected to the row selection unit through the row selection wiring, the pixel unit located farther from the disconnection position than the row selection unit is not connected to the row selection unit.
- the charge generated in the photodiode in response to the light incidence in the pixel portion located far from the disconnection position with respect to the row selection portion is not read out to the integration circuit and accumulated in the junction capacitance portion of the photodiode.
- the amount of charge accumulated in the junction capacitance portion of the photodiode exceeds the saturation level, the charge exceeding the saturation level overflows to the adjacent pixel portion.
- the influence when one readout wiring is disconnected, the influence not only affects the pixel portion of the column connected to the readout wiring, but also extends to the pixel portions of both adjacent columns. Eventually, a defective line occurs in the pixel portions of three consecutive columns. Similarly, when one row selection wiring is disconnected, the influence extends not only to the pixel portion of the row connected to the row selection wiring, but also to the pixel portions of both adjacent rows. A defective line is generated in the pixel portions of the three rows.
- the defective lines are not continuous and if both sides of one defective line are normal lines, it is possible to interpolate the pixel data of the defective lines using the pixel data of the normal lines on both sides.
- the probability of occurrence of disconnection is increased because the readout wiring and the row selection wiring are long.
- Patent Document 1 proposes a technique intended to eliminate the problems of such a conventional solid-state imaging device.
- this conventional technique an average value of all pixel data of adjacent lines adjacent to the defective line is obtained, and an average value of all pixel data of several normal lines adjacent to the defect line is also obtained. If the difference is equal to or greater than a certain value, it is determined that the adjacent line is also defective, the pixel data of the adjacent line is corrected, and the pixel data of the defective line is further corrected based on the corrected value of the pixel data of the adjacent line. Correct.
- Patent Document 2 proposes a technique intended to solve the problems of the above-described conventional solid-state imaging device.
- a dummy photodiode is formed in the region between the pixel portions, Charges saturated in the pixel portion on the defective line are caught by a dummy photodiode and discharged.
- the present invention has been made to solve the above-described problems, and is capable of obtaining a high-resolution image even when any of the readout wirings or row selection wirings is disconnected.
- An object of the present invention is to provide a solid-state imaging device having a structure and an X-ray CT apparatus including the same.
- each of the pixel portions P 1,1 to P M, N includes a photodiode that generates an amount of charge corresponding to the intensity of incident light, and a readout switch connected to the photodiode.
- the photodiodes included in the pixel portion P m, n (m is an integer from 1 to M and n is an integer from 1 to N) in the light receiving unit have the first conductivity type.
- the light receiving unit includes channel stoppers provided in regions sandwiched between the pixel units P 1,1 to P M, N.
- the channel stopper is formed of a first conductivity type third semiconductor region having an impurity concentration higher than that of the first semiconductor region.
- the light receiving portion is a region surrounded by any 2 ⁇ 2 pixel portions adjacent to each other among the pixel portions P 1,1 to P M, N (specifically, corner portions of the arbitrary pixel portions).
- the first dummy photodiode provided in a state surrounded by the channel stopper.
- the first dummy photodiode includes a common first semiconductor region and a second conductivity type fourth semiconductor region formed on the first semiconductor region.
- One of the first conductivity type and the second conductivity type is P-type, and the other is N-type.
- the light receiving unit is surrounded by a channel stopper in a region surrounded by any two adjacent pixel units among the pixel units P 1,1 to P M, N
- the second dummy photodiode may be further included.
- the second dummy photodiode is constituted by a common first semiconductor region and a second conductivity type fifth semiconductor region formed on the first semiconductor region.
- the pixel portion on the defective line responds to light incidence.
- the charges generated in the photodiode are not read out and are stored in the junction capacitance portion of the photodiode.
- the amount of charge accumulated in the junction capacitance portion of the photodiode exceeds the saturation level, the charge exceeding the saturation level overflows outside the pixel portion.
- the dummy area is surrounded by the channel stopper in the area between the pixel parts (the area around the corner of each pixel part or the area between the two pixel parts) in the light receiving part.
- a photodiode is provided.
- the solid-state imaging device can obtain a high-resolution image even when any one of the readout wirings or the row selection wiring is disconnected.
- each pixel portion occupies a substantially square area.
- Most of the substantially square region is a photodiode region, and a field effect transistor as a read switch is formed at one corner of the approximately square region. Since the electric field strength is high at the corners of the substantially square region of the photodiode, the electric charge tends to overflow. Further, unnecessary charges are likely to be generated in the vicinity of the region where the read switch is provided. Therefore, in the present invention, at least a region surrounded by any 2 ⁇ 2 pixel portions adjacent to each other out of the M ⁇ N pixel portions P 1,1 to P M, N (each of the arbitrary pixel portions). Since the dummy photodiode is formed in the common corner portion), the charge generated at the corner of the substantially square region of the photodiode can be efficiently discharged by the dummy photodiode.
- the X-ray CT apparatus includes an X-ray output unit, a solid-state imaging device having the above-described structure (solid-state imaging device according to the present invention), moving means, and an image analysis unit.
- the X-ray output unit outputs X-rays toward the subject.
- the solid-state imaging device receives and captures X-rays that are output from the X-ray output unit and arrive through the subject.
- the moving means moves the X-ray output unit and the solid-state imaging device relative to the subject.
- the image analysis unit receives frame data output from the solid-state imaging device, and generates a tomographic image of the subject based on the frame data.
- a high-resolution image can be obtained even when any row selection wiring is disconnected.
- FIG. 4 is a circuit diagram of each of a pixel unit P m, n , an integration circuit Sn, and a holding circuit H n included in the solid-state imaging device 1 illustrated in FIG. 1. These are timing charts explaining the operation of the solid-state imaging device shown in FIG. These are top views which show the structural example of the light-receiving part in the solid-state imaging device shown by FIG. These are top views which show the other structural example of the light-receiving part in the solid-state imaging device shown by FIG.
- FIG. 6 is a cross-sectional view of a region located between pixel portions along line AA in FIG. 5.
- FIG. 6 is a cross-sectional view of a region located between pixel portions along the line BB in FIG. 5.
- SYMBOLS 1 Solid-state imaging device 10, 10A, 10B ... Light-receiving part, 20, 20A, 20B ... Signal reading part, 30 ... Control part, 201 ... P-type semiconductor area, 202 ... N + type semiconductor area, 203 ... Depletion layer, 204 ... P + type semiconductor region, 205 ... insulating layer, 206 ... contact hole, 207 ... metal wiring, 212 ... N + type semiconductor region, 213 ... depletion layer, 216 ... contact hole, P 1,1 to P M, N ... Pixel part, PD ... Photodiode, SW 1 ... Reading switch, S 1 to S N ... Integration circuit, C 2 ... Integration capacitor element, SW 2 ...
- Discharge switch A 2 ... Amplifier, H 1 to H N ... holding circuit, C 3 ... holding capacitor, SW 31 ... input switch, SW 32 ... output switch, L V, m ... m-th row selection wiring, L H, n ... n-th column selection wiring, L O, n ... n-th column readout arrangement Line, L R ... discharge controlling wiring, L H ... hold controlling wiring, L out ... voltage output wiring, CS ... channel stopper, PD1, PD2 ... photodiode dummy.
- FIG. 1 is a diagram showing a configuration of an embodiment of a solid-state imaging device according to the present invention.
- the solid-state imaging device 1 shown in FIG. 1 includes a light receiving unit 10, a signal reading unit 20, and a control unit 30.
- a scintillator panel is overlaid on the light receiving surface 10 of the solid-state imaging device 1.
- the light receiving unit 10 includes M ⁇ N pixel units P 1,1 to P M, N two-dimensionally arranged in a matrix in M rows and N columns.
- the pixel unit P m, n means a pixel unit located in the m-th row and the n-th column.
- M and N are each an integer of 2 or more
- m is an integer of 1 to M
- n is an integer of 1 to N.
- the pixel unit P m, n in the light receiving unit 10 is a PPS pixel unit and has a common configuration.
- Each of the N pixel portions P m, 1 to P m, N belonging to the m-th row is connected to the control unit 30 via the m-th row selection wiring L V, m .
- the output ends of the M pixel units P 1, n to P M, n belonging to the n-th column are connected to the integration circuit S n included in the signal readout unit 20 via the n-th column readout wiring L O, n. It is connected to the.
- the signal reading unit 20 includes N integration circuits S 1 to S N and N holding circuits H 1 to H N. Each integrating circuit Sn has a common configuration. Moreover, the holding circuits H n have a common configuration.
- Each integrating circuit Sn has an input terminal connected to the readout wiring L O, n .
- Each integrating circuit S n accumulates the charge input through the input terminal, and outputs a voltage value corresponding to the accumulated charge amount from the output terminal to the holding circuit H n .
- the N integrating circuits S 1 ⁇ S N respectively connected to the control unit 30 via the discharge control wiring L R.
- Each holding circuit H n has an input terminal connected to the output terminal of the integrating circuit S n. Each holding circuit H n holds the voltage value input via this input terminal, and outputs the held voltage value from the output terminal to the output wiring L out .
- Each of the N holding circuits H 1 to H N is connected to the control unit 30 via a holding control wiring L H. Moreover, each holding circuit H n is connected to the control unit 30 first n column selecting wiring L H, through n.
- the control unit 30 outputs the m-th row selection control signal Vsel (m) to the m-th row selection wiring LV , m, and outputs the m-th row selection control signal Vsel (m) to N pixels in the m-th row.
- Each of the parts P m, 1 to P m, N is given.
- the M row selection control signals Vsel (1) to Vsel (M) sequentially become significant values.
- the control unit 30 includes a shift register in order to sequentially output M row selection control signals Vsel (1) to Vsel (M) as significant values.
- Control unit 30 the n-th column selecting control signal Hsel (n) and outputs the n-th column selecting wiring L H, the n, giving the n-th column selecting control signal Hsel (n) to the holding circuit H n.
- N column selection control signals Hsel (1) to Hsel (N) also sequentially become significant values.
- the control unit 30 includes a shift register for sequentially outputting N column selection control signals Hsel (1) to Hsel (N) as significant values.
- the control unit 30 outputs a discharging control signal Reset to the discharge controlling wiring L R, provide the discharge control signal Reset to the N integrating circuits S 1 ⁇ S N, respectively.
- Control unit 30 outputs a holding control signal Hold to the hold controlling wiring L H, it gives the holding control signal Hold to the N holding circuits H 1 ⁇ H N, respectively.
- control unit 30 controls the opening / closing operation of the readout switch SW 1 included in each of the N pixel units P m, 1 to P m, N belonging to the m-th row in the light receiving unit 10, and The voltage reading holding operation and the output operation in the signal reading unit 20 are controlled.
- the control unit 30 uses the voltage value corresponding to the amount of charge generated in the photodiode PD included in each of the M ⁇ N pixel units P 1,1 to P M, N in the light receiving unit 10 as frame data.
- the signal reading unit 20 repeatedly outputs the signal.
- FIG. 2 is a circuit diagram of each of the pixel unit P m, n , the integration circuit Sn, and the holding circuit H n included in the solid-state imaging device illustrated in FIG.
- the circuit diagram of the pixel portion P m, n is representative of M ⁇ N pixel portions P 1,1 to P M, N
- the integration circuit S is representative of N integration circuits S 1 to S N.
- a circuit diagram of n and a circuit diagram of the holding circuit H n are shown as a representative of the N holding circuits H 1 to H N. That is, FIG. 2 shows circuit portions related to the pixel portion P m, n of the m- th row and the n-th column and the n-th column readout wiring L O, n .
- Pixel unit P m, n includes a photodiode PD and the readout switch SW 1.
- the anode terminal of the photodiode PD is grounded, the cathode terminal of the photodiode PD is connected to the n-th column readout wiring L O via the readout switch SW 1, to n.
- the photodiode PD generates an amount of charge corresponding to the incident light intensity, and accumulates the generated charge in the junction capacitor.
- the read switch SW 1 is supplied with an m-th row selection control signal from the control unit 30 via the m-th row selection wiring LV , m .
- the m-th row selection control signal is an electric signal for instructing the opening / closing operation of the read switch SW 1 included in each of the N pixel portions P m, 1 to P m, N belonging to the m-th row in the light receiving unit 10. .
- the pixel portion P m, the n when the m-th row selecting control signal Vsel (m) is at low level, opens readout switch SW 1. At this time, the electric charge generated in the photodiode PD is accumulated in the junction capacitance portion without being output to the n-th column readout wiring L O, n .
- the readout switch SW 1 when the m-th row selecting control signal Vsel (m) is at high level, the readout switch SW 1 in close. In this case, charges accumulated in the junction capacitance portion is generated in the photodiode PD until it passes through the readout switch SW 1, and output the n-th column readout wiring L O, to n.
- the n-th column readout wiring L O, n is connected to a readout switch SW 1 included in each of the M pixel units P 1, n to P M, n belonging to the n-th column in the light receiving unit 10.
- the n-th column readout wiring L O, n receives charges generated in the photodiode PD included in any one of the M pixel portions P 1, n to P M, n in the pixel portion. read out via the readout switch SW 1 included in, and transfers to the integrating circuit S n.
- the integrating circuit Sn includes an amplifier A 2 , an integrating capacitive element C 2, and a discharging switch SW 2 . Integrating capacitive element C 2 and the discharge switch SW 2 are connected in parallel to each other, and provided between an input terminal of the amplifier A 2 and the output terminal. The input terminal of the amplifier A 2 is connected to the n-th column readout wiring L O, to n. Discharge switch SW 2 are given the discharge control signal Reset passed through the discharge controlling wiring L R from the controlling section 30.
- the discharge control signal Reset is an electric signal instructing the opening / closing operation of the discharge switch SW 2 included in each of the N integration circuits S 1 to S N.
- the holding circuit H n includes an input switch SW 31 , an output switch SW 32, and a holding capacitive element C 3 .
- One end of the holding capacitive element C 3 is grounded.
- the other end of the holding capacitive element C 3 is connected via an input switch SW 31 is connected to the output terminal of the integrating circuit S n, and is connected to the voltage output wiring L out via the output switch SW 32.
- Input switch SW 31 is supplied with a holding control signal Hold through the wiring L H for holding control from the control unit 30.
- the holding control signal Hold is an electric signal that instructs the opening / closing operation of the input switch SW 31 included in each of the N holding circuits H 1 to H N.
- the output switch SW 32 is supplied with the n-th column selection control signal Hsel (n) from the control unit 30 via the n-th column selection wiring L H, n .
- N-th column selecting control signal Hsel (n) is an electrical signal for instructing opening and closing operations of the output switch SW 32 included in the holding circuit H n.
- the control unit 30 uses the discharge control signal Reset to output N pixels.
- the discharging switch SW 2 included in each of the integrating circuits S 1 to S N is instructed to be closed and then opened. Thereafter, the readout switch SW 1 included in each of the N pixel portions P m, 1 to P m, N belonging to the m-th row in the light receiving unit 10 is set to a predetermined period by the m-th row selection control signal Vsel (m). Instruct to close.
- the control unit 30 instructs the input switch SW 31 included in each of the N holding circuits H 1 to H N to change from the closed state to the open state by the holding control signal Hold during the predetermined period. Then, after the predetermined period, the control unit 30 sequentially sets the output switches SW 32 included in each of the N holding circuits H 1 to H N by the column selection control signals Hsel (1) to Hsel (N). Instruct to close only for a period. The control unit 30 sequentially performs the above control for each row.
- FIG. 1 the operation of one embodiment (FIG. 1) of the solid-state imaging device according to the present invention will be described.
- the solid-state imaging device under the control of the control unit 30, M row selection control signals Vsel (1) to Vsel (M), N column selection control signals Hsel (1) to Hsel (N), By changing the level of each of the discharge control signal Reset and the hold control signal Hold at a predetermined timing, it is possible to obtain frame data by capturing an image of light incident on the light receiving surface 10.
- FIG. 3 is a timing chart for explaining the operation of the solid-state imaging device 1.
- FIG. 3 shows (a) a discharge control signal Reset for instructing the opening / closing operation of the discharge switch SW 2 included in each of the N integration circuits S 1 to S N , and (b) the first row in the light receiving unit 10.
- First row selection control signal Vsel (1) for instructing opening / closing operation of the readout switch SW 1 included in each of the N pixel portions P 1,1 to P 1, N
- Second row in the light receiving unit 10 the N pixel portions P 2,1 ⁇ P 2, N second row selecting control signal Vsel for instructing opening and closing operations of the readout switches SW 1 included in each of (2)
- the N holding A hold control signal Hold that indicates an opening / closing operation of the input switch SW 31 included in each of the circuits H 1 to H N is shown.
- Reading of charges generated in the photodiode PD included in each of the N pixel portions P 1,1 to P 1, N belonging to the first row and accumulated in the junction capacitance portion is performed as follows.
- the readout switch SW 1 included in each of the N pixel portions P 1,1 to P 1, N belonging to the first row in the light receiving unit 10 is closed.
- the holding control signal Hold output from the control unit 30 to the holding control wiring L H becomes high level during the period from time t 13 to time t 14 .
- the input switch SW 31 is closed in each of the N holding circuits H 1 to H N.
- the holding control signal Hold switches from high level to low level, in the N holding circuits H 1 ⁇ H N, the input switch SW 31 closed To open state. Then, a voltage value being input to the input terminal of the holding circuit H n are output from the output terminal of the integrating circuit S n is held in the holding capacitive element C 3.
- the column selection control signals Hsel (1) to Hsel (N) output from the control unit 30 to the column selection wirings L H, 1 to L H, N are sequentially constant. High level only for the period.
- the output switches SW 32 included in each of the N holding circuits H 1 to H N are sequentially closed for a certain period. Thereby, the voltage value held in the holding capacitive element C 3 of the holding circuits H n are sequentially outputted through the output switches SW 32 to the voltage output wiring L out.
- the voltage value V out output to the voltage output wiring L out represents the received light intensity in the photodiode PD included in each of the N pixel portions P 1,1 to P 1, N in the first row.
- the discharge control signal Reset is at the high level output from the control unit 30 to the discharge controlling wiring L R.
- the discharge switch SW 2 is closed.
- the integrating capacitive element C 2 is discharged.
- the second row selection control signal Vsel (2) a high level output from the control unit 30 to the second row selecting wiring L V, 2 It becomes.
- the readout switch SW 1 included in each of the N pixel portions P 2,1 to P 2, N belonging to the second row in the light receiving unit 10 is closed.
- the holding control signal Hold that is output from the control unit 30 to the holding control wiring L H is at a high level during the period from time t 23 to time t 24 .
- the input switch SW 31 is closed in each of the N holding circuits H 1 to H N.
- the column selection control signals Hsel (1) to Hsel (N) output from the control unit 30 to the column selection wirings L H, 1 to L H, N are sequentially constant. High level only during the period. As a result, the output switches SW 32 included in each of the N holding circuits H 1 to H N are sequentially closed for a certain period.
- the voltage value V out indicating the light reception intensity in the photodiode PD included in each of the N pixel portions P 2,1 to P 2, N belonging to the second row is output to the voltage output wiring L out . Is done.
- each pixel portion P m, n belonging to the m-th row is closed.
- the charge generated in the photodiode PD and accumulated in the junction capacitance portion passes through the readout switch SW 1 and the n-th column readout wiring L O, n of the pixel portion P m, n , and passes through the integration circuit Sn . It is transferred to the integrating capacitive element C 2.
- the accumulated charge in the junction capacitance portion of the photodiode PD of each pixel portion P m, n belonging to the m-th row is initialized.
- the solid-state imaging device 1 shown in FIG. 1 (one embodiment of the solid-state imaging device according to the present invention) is described below with reference to FIGS. ,Operate. That is, in the solid-state imaging device 1, the light receiving unit 10 is a region surrounded by any 2 ⁇ 2 pixel units adjacent to each other among the M ⁇ N pixel units P 1,1 to P M, N ( A corner portion common to each pixel portion) includes a dummy photodiode PD1 (first dummy photodiode) provided in a state surrounded by a channel stopper CS.
- PD1 first dummy photodiode
- FIGS. 4 and 5 each show a configuration example (plan view) of the light receiving unit 10 in the solid-state imaging device 1.
- one pixel portion P m in the photodetecting section 10, around the n, the pixel portion P m, is shown also a part of the neighboring pixel portions of n.
- the layout of the semiconductor region is mainly shown, but the metal wiring (row selection wiring, readout wiring) and the insulating layer on the semiconductor region are not shown. .
- the pixel portion P m, n occupies a substantially square area. As most of the substantially square region is a region of the photodiode PD, The field effect transistor as the read switch SW 1 in is formed on one corner of the substantially square region.
- the source terminal of the field effect transistor as the readout switch SW 1 of the pixel portion P m, n is connected to the cathode terminal of the photodiode PD, and the drain terminal of this field effect transistor is connected to the readout wiring L O, n .
- the gate terminal of this field effect transistor is connected to the row selection wiring LV , m .
- channel stoppers CS are continuously formed in the region between the pixel portions.
- a dummy photodiode PD1 is formed in a region surrounded by 2 ⁇ 2 arbitrary pixel portions adjacent to each other. This dummy photodiode PD1 is surrounded by a channel stopper CS.
- the dummy photodiode PD1 is formed only in a region surrounded by arbitrary 2 ⁇ 2 pixel portions adjacent to each other.
- the layout example shown in FIG. 5 in addition to the dummy photodiode PD1 being formed in a region surrounded by any mutually adjacent 2 ⁇ 2 pixel portions, any two adjacent pixels A dummy photodiode PD2 is also formed in a region sandwiched between the portions.
- FIG. 6 is a cross-sectional view of the peripheral area of the pixel portion P m, n along the line AA in FIG.
- FIG. 7 is a cross-sectional view of the peripheral region of the pixel portion Pm , n along the line BB in FIG.
- a cross section is shown for a part of the pixel portions adjacent to each other with the region between the pixel portions as the center.
- FIG. 6 shows a cross section of a region where the dummy photodiodes PD1 and PD2 are not formed.
- FIG. 7 shows a cross section of a portion where the dummy photodiode PD2 is formed.
- the semiconductor region 201 is a semiconductor region to which a P-type impurity is added, and includes a substrate and an epitaxial layer formed on the substrate.
- the photodiode PD included in the pixel portion P m, n is composed of a P-type semiconductor region 201 and an N + -type semiconductor region 202 provided on the P-type semiconductor region 201.
- a depletion layer 203 is formed in a region including the boundary between the P-type semiconductor region 201 and the N + -type semiconductor region 202.
- a channel stopper CS made of a P + type semiconductor region 204 having a P type impurity concentration higher than that of the P semiconductor region 201 is formed in a region between the pixel portions (a region between the N + type semiconductor regions 202). This P + type semiconductor region 204 is connected to a metal wiring 207 through a contact hole 206 formed in the insulating layer 205.
- Each of the dummy photodiodes PD1 and PD2 includes a P-type semiconductor region 201 and an N + -type semiconductor region 212 provided on the P-type semiconductor region 201.
- a depletion layer 213 is formed in a region including a boundary between the P-type semiconductor region 201 and the N + -type semiconductor region 212.
- the N + type semiconductor region 212 is connected to the metal wiring 207 through a contact hole 216 formed in the insulating layer 205.
- the N + type semiconductor region 212 is surrounded by a P + type semiconductor region 204, and each of the dummy photodiodes PD1 and PD2 is surrounded by a channel stopper CS.
- the thickness of the semiconductor region 201 including the substrate is 750 ⁇ m.
- Each of the N + type semiconductor region 202, the P + type semiconductor region 204, and the N + type semiconductor region 212 has a thickness of 1 ⁇ m.
- Each of the P + type semiconductor region 204 and the N + type semiconductor region 212 has a width of 1.4 ⁇ m.
- the interval between two adjacent N + type semiconductor regions 202 is 3.6 ⁇ m, and the width of the metal wiring 207 is 4.8 ⁇ m.
- the distance between the N + type semiconductor region 202 and the N + type semiconductor region 212 is 3.6 ⁇ m, and the width of the metal wiring 207 is as follows. 9.8 ⁇ m.
- the solid-state imaging device 1 having the above structure (one embodiment of the solid-state imaging device according to the present invention)
- dummy photodiodes PD1 and PD2 are formed surrounded by the channel stopper CS in the region between the pixel portions.
- the charges overflowing from the pixel portion are caught and discharged by the dummy photodiodes PD1 and PD2.
- this solid-state imaging device 1 it is suppressed that an electric charge flows into the pixel part adjacent to a pixel part, and the fall of S / N ratio is suppressed. Therefore, according to the solid-state imaging device 1, a high-resolution image can be obtained even when any one of the readout wirings or the row selection wiring is disconnected.
- the voltage value corresponding to the pixel part on the defective line in the frame data is set to the pixel part on the adjacent normal line. Can be determined based on the voltage value corresponding to. In this determination, it is preferable to perform an interpolation calculation based on a voltage value corresponding to a pixel portion on both adjacent lines.
- the dummy photodiodes PD1 and PD2 are intended to discharge charges overflowing from the pixel portion, and are not intended to actively collect so-called crosstalk carriers. Therefore, it is not preferable that the depletion layer 213 expands too much when no disconnection occurs. This is because when the solid-state imaging device 1 is used as an X-ray flat panel sensor in combination with a scintillator panel, scintillator light is generated isotropically from the scintillator panel. For this reason, a certain amount of charge is generated also in the region between the pixel portions, but if this charge is discharged by the dummy photodiodes PD1 and PD2, the output may be reduced.
- the dummy photodiodes PD1 and PD2 are not provided so as to extend continuously in the region between the pixel portions, but are provided discretely (dot-like). Moreover, the dummy photodiodes PD1 and PD2 are both surrounded by the channel stopper CS. With this configuration, it is possible to achieve an appropriate balance between suppression of output decrease and suppression of S / N ratio decrease.
- the pixel portion P m, n occupies a substantially square region, and most of the substantially square region is the region of the photodiode PD, and at one corner of the substantially square region.
- field effect transistor as the read switch SW 1 in is formed. Since the electric field strength is high at the corners of the substantially square region of the photodiode PD, the electric charge tends to overflow. Further, in the vicinity of the region where the read switch SW 1 in is provided, apt unnecessary charge is generated.
- a dummy photodiode PD1 is formed in the solid-state imaging device 1. Therefore, the charges generated at the corners of the substantially square region of the photodiode PD can be efficiently discharged by the dummy photodiode PD1.
- the dummy photodiode PD2 is not provided in a region sandwiched between two adjacent pixel portions. Since only the dummy photodiode PD1 is provided in the region surrounded by the adjacent 2 ⁇ 2 pixel portions, the photosensitive region of the photodiode PD in each pixel portion can be widened and the aperture ratio is increased. be able to.
- the solid-state imaging device 1 having the above-described structure can be suitably used for an X-ray CT apparatus.
- An embodiment of an X-ray CT apparatus (X-ray CT apparatus according to the present invention) provided with the solid-state imaging apparatus 1 (an embodiment of the solid-state imaging apparatus according to the present invention) will be described below.
- FIG. 8 is a diagram showing the configuration of an embodiment of the X-ray CT apparatus according to the present invention.
- the X-ray source 106 generates X-rays toward the subject.
- the irradiation field of X-rays generated from the X-ray source 106 is controlled by the primary slit plate 106b.
- the X-ray source 106 includes an X-ray tube, and the amount of X-ray irradiation to the subject is controlled by adjusting conditions such as tube voltage, tube current, and energization time of the X-ray tube.
- the X-ray imager 107 incorporates a CMOS solid-state image pickup device having a plurality of two-dimensionally arranged pixel units, and detects an X-ray image that has passed through the subject.
- a secondary slit plate 107a for limiting the X-ray incident area is provided.
- the swivel arm 104 turns the X-ray source 106 and the X-ray imager 107 around the subject during panoramic tomography while holding the X-ray source 106 and the X-ray imager 107 facing each other.
- a slide mechanism 113 for linearly displacing the X-ray imager 107 with respect to the subject is provided during linear tomography.
- the turning arm 104 is driven by an arm motor 110 constituting a rotary table, and the rotation angle is detected by an angle sensor 112.
- the arm motor 110 is mounted on a movable part of the XY table 114, and the center of rotation is arbitrarily adjusted within a horizontal plane.
- a CRT cathode ray tube
- a work memory 123 necessary for signal processing is connected to the CPU 121, and an operation panel 119 provided with a panel switch, an X-ray irradiation switch, and the like is further connected.
- the CPU 121 also includes a motor drive circuit 111 that drives the arm motor 110, slit control circuits 115 and 116 that control the opening ranges of the primary slit plate 106b and the secondary slit plate 107a, and an X-ray control circuit that controls the X-ray source 106. 118, and a clock signal for driving the X-ray imager 107 is output.
- the X-ray control circuit 118 can feedback-control the X-ray irradiation amount to the subject based on the signal imaged by the X-ray imager 107.
- the X-ray imager 107 corresponds to the light receiving unit 10, the signal reading unit 20, and the control unit 30 in the solid-state imaging device 1.
- a scintillator panel is provided.
- the X-ray CT apparatus 100 includes the solid-state imaging apparatus 1, a high-resolution tomographic image can be obtained even near the defect line.
- a large number (for example, 300) of frame data is continuously acquired in a short time, and the amount of light incident on the light receiving unit 10 in the solid-state imaging device 1 varies from frame to frame.
- the amount of charge that overflows from the pixel portion on the defective line to the pixel portion on the adjacent line varies from frame to frame. Since such an X-ray CT apparatus includes the solid-state imaging device 1 having the above-described structure, the X-ray CT apparatus can be used when any readout wiring or row selection wiring is disconnected. Even high resolution images can be obtained.
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Abstract
Description
Claims (3)
- M(2以上の整数)行N(2以上の整数)列のマトリックスを構成するよう二次元配列されたM×N個の画素部P1,1~PM,Nを有する受光部であって、前記画素部P1,1~PM,Nのそれぞれが入射光強度に応じた量の電荷を発生するフォトダイオードと、該フォトダイオードと接続された読出用スイッチを含んでいる受光部を備えた固体撮像装置であって、
前記受光部における画素部Pm,n(mは1以上M以下の整数、nは1以上N以下の整数)に含まれるフォトダイオードは、第1導電型の第1半導体領域と、該第1半導体領域上に形成された第2導電型の第2半導体領域により構成され、
前記受光部は、前記画素部P1,1~PM,Nそれぞれに挟まれた領域に設けられたチャネルストッパであって、前記第1半導体領域より不純物濃度が高い第1導電型の第3半導体領域からなるチャネルストッパを有し、そして、
前記受光部は、前記画素部P1,1~PM,Nのうち互いに隣接する任意の2×2個の画素部により囲まれた領域に、前記チャネルストッパにより取り囲まれた状態で設けられた第1ダミー用フォトダイオードであって、前記第1半導体領域と、該第1半導体領域上に形成された第2導電型の第4半導体領域により構成された第1ダミー用フォトダイオードを含む、固体撮像装置。 - 請求項1記載の固体撮像装置において、
前記受光部は、前記画素部P1,1~PM,Nのうち互いに隣接する任意の2個の画素部により囲まれた領域に、前記チャネルストッパにより取り囲まれた状態で設けられた第2ダミー用フォトダイオードであって、前記第1半導体領域と、該第1半導体領域上に形成された第2導電型の第5半導体領域により構成された第2ダミー用フォトダイオードをさらに含む。 - 被写体に向けてX線を出力するX線出力部と、
前記X線出力部から出力されて前記被写体を経て到達したX線を受光し撮像する請求項1又は2記載の固体撮像装置と、
前記X線出力部及び前記固体撮像装置を前記被写体に対して相対移動させる移動手段と、
前記固体撮像装置から出力されるフレームデータを入力し、そのフレームデータに基づいて前記被写体の断層画像を生成する画像解析部と、を備えることを特徴とするX線CT装置。
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EP09705131.2A EP2237317B1 (en) | 2008-01-30 | 2009-01-23 | Solid-state imager and x-ray ct apparatus including same |
US12/864,575 US8488735B2 (en) | 2008-01-30 | 2009-01-23 | Solid-state imager and X-ray CT apparatus including same |
CN200980103667.1A CN101933143B (zh) | 2008-01-30 | 2009-01-23 | 固体摄像装置以及包括其的x射线ct装置 |
US13/921,565 US8675813B2 (en) | 2008-01-30 | 2013-06-19 | Solid-state imager and X-ray CT apparatus including same |
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US13/921,565 Continuation US8675813B2 (en) | 2008-01-30 | 2013-06-19 | Solid-state imager and X-ray CT apparatus including same |
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JP5150283B2 (ja) * | 2008-01-30 | 2013-02-20 | 浜松ホトニクス株式会社 | 固体撮像装置 |
FR2972295B1 (fr) * | 2011-03-04 | 2013-07-19 | Soc Fr Detecteurs Infrarouges Sofradir | Matrice de detection a conditions de polarisation ameliorees et procede de fabrication |
EP2495764B1 (fr) | 2011-03-04 | 2017-10-04 | Société Française de Détecteurs Infrarouges - SOFRADIR | Matrice de détection à conditions de polarisation améliorées et procédé de fabrication |
JP5199497B2 (ja) | 2011-08-31 | 2013-05-15 | 富士フイルム株式会社 | 放射線画像撮影装置、放射線画像撮影システム、放射線画像撮影装置の制御プログラム、及び放射線画像撮影装置の制御方法 |
FR2983640B1 (fr) * | 2011-12-02 | 2014-06-20 | Soc Fr Detecteurs Infrarouges Sofradir | Matrice de detection compacte a conditions de polarisation ameliorees |
JP5926634B2 (ja) * | 2012-07-03 | 2016-05-25 | キヤノン株式会社 | 固体撮像装置及びカメラ |
JP6188433B2 (ja) * | 2013-06-07 | 2017-08-30 | 浜松ホトニクス株式会社 | 固体撮像装置 |
DE102015213911B4 (de) * | 2015-07-23 | 2019-03-07 | Siemens Healthcare Gmbh | Verfahren zum Erzeugen eines Röntgenbildes und Datenverarbeitungseinrichtung zum Ausführen des Verfahrens |
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KR102595513B1 (ko) * | 2018-12-28 | 2023-10-27 | 엘지디스플레이 주식회사 | 디지털 엑스레이 검출장치 및 그의 구동방법 |
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