WO2009057691A1 - 接続端子及びこれを用いたパッケージ並びに電子装置 - Google Patents

接続端子及びこれを用いたパッケージ並びに電子装置 Download PDF

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Publication number
WO2009057691A1
WO2009057691A1 PCT/JP2008/069749 JP2008069749W WO2009057691A1 WO 2009057691 A1 WO2009057691 A1 WO 2009057691A1 JP 2008069749 W JP2008069749 W JP 2008069749W WO 2009057691 A1 WO2009057691 A1 WO 2009057691A1
Authority
WO
WIPO (PCT)
Prior art keywords
line conductor
connection terminal
package
same
electronic device
Prior art date
Application number
PCT/JP2008/069749
Other languages
English (en)
French (fr)
Inventor
Mahiro Tsujino
Original Assignee
Kyocera Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corporation filed Critical Kyocera Corporation
Priority to US12/739,937 priority Critical patent/US8344259B2/en
Priority to JP2009539102A priority patent/JP5189597B2/ja
Priority to EP08845868.2A priority patent/EP2221867B1/en
Publication of WO2009057691A1 publication Critical patent/WO2009057691A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6638—Differential pair signal lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Waveguides (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

　接続端子１０において、第１誘電体層１上面に、第１線路導体１１とこの第１線路導体１１の両側に隣り合わせて設けられた第１接地用線路導体１２とを有し、第３誘電体層３上面に、第３線路導体３１とこの第３線路導体３１の両側に隣り合わせて設けられた第３接地用線路導体３２とを有する。これらが第２誘電体層２上面に設けられた第２線路導体２１とこの第２線路導体２１の両側に隣り合わせて設けられた第２接地用線路導体２２とにそれぞれ接続されている。高周波信号に対応可能で小形な接続端子１０を実現できる。
PCT/JP2008/069749 2007-10-30 2008-10-30 接続端子及びこれを用いたパッケージ並びに電子装置 WO2009057691A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/739,937 US8344259B2 (en) 2007-10-30 2008-10-30 Connection terminal, package using the same, and electronic apparatus
JP2009539102A JP5189597B2 (ja) 2007-10-30 2008-10-30 接続端子及びこれを用いたパッケージ並びに電子装置
EP08845868.2A EP2221867B1 (en) 2007-10-30 2008-10-30 Connection terminal, package using the same, and electronic device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007-281069 2007-10-30
JP2007281069 2007-10-30
JP2007308272 2007-11-29
JP2007-308272 2007-11-29

Publications (1)

Publication Number Publication Date
WO2009057691A1 true WO2009057691A1 (ja) 2009-05-07

Family

ID=40591075

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/069749 WO2009057691A1 (ja) 2007-10-30 2008-10-30 接続端子及びこれを用いたパッケージ並びに電子装置

Country Status (4)

Country Link
US (1) US8344259B2 (ja)
EP (1) EP2221867B1 (ja)
JP (1) JP5189597B2 (ja)
WO (1) WO2009057691A1 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013015216A1 (ja) * 2011-07-26 2013-01-31 京セラ株式会社 半導体素子収納用パッケージ、これを備えた半導体装置および電子装置
WO2013141013A1 (ja) * 2012-03-22 2013-09-26 京セラ株式会社 素子収納用パッケージ
WO2015012405A1 (ja) * 2013-07-26 2015-01-29 京セラ株式会社 素子収納用パッケージおよび実装構造体
WO2022230883A1 (ja) * 2021-04-27 2022-11-03 京セラ株式会社 半導体パッケージ及び半導体電子装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102473686B (zh) * 2009-09-29 2014-07-30 京瓷株式会社 元件收纳用封装及安装结构体
CN104364897B (zh) * 2012-10-29 2017-07-25 京瓷株式会社 元件收纳用封装件以及安装结构体
WO2014069123A1 (ja) * 2012-10-30 2014-05-08 京セラ株式会社 電子部品収納用容器および電子装置
CN105144370B (zh) * 2013-09-25 2017-11-14 京瓷株式会社 电子部件收纳用封装件以及电子装置
JP7279527B2 (ja) * 2019-05-31 2023-05-23 株式会社オートネットワーク技術研究所 配線部材
TWI720898B (zh) * 2020-05-28 2021-03-01 欣興電子股份有限公司 具有增加芯層走線面積的載板結構及其製作方法
GB2600918B (en) * 2020-10-30 2022-11-23 Npl Management Ltd Ion microtrap assembly and method of making of making such an assembly

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004356391A (ja) 2003-05-29 2004-12-16 Kyocera Corp 半導体素子収納用パッケージおよび半導体装置
JP2005108891A (ja) * 2003-09-26 2005-04-21 Kyocera Corp 入出力端子および半導体素子収納用パッケージならびに半導体装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6197954A (ja) * 1984-10-19 1986-05-16 Hitachi Ltd 半導体装置
US7020958B1 (en) * 1998-09-15 2006-04-04 Intel Corporation Methods forming an integrated circuit package with a split cavity wall
US6936921B2 (en) * 2002-11-11 2005-08-30 Kyocera Corporation High-frequency package
JP2004349476A (ja) * 2003-05-22 2004-12-09 Toshiba Corp 半導体装置
EP3358670A1 (en) * 2004-06-28 2018-08-08 Mitsubishi Electric Corporation Multilayer dielectric substrate and semiconductor package
US7947908B2 (en) * 2007-10-19 2011-05-24 Advantest Corporation Electronic device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004356391A (ja) 2003-05-29 2004-12-16 Kyocera Corp 半導体素子収納用パッケージおよび半導体装置
JP2005108891A (ja) * 2003-09-26 2005-04-21 Kyocera Corp 入出力端子および半導体素子収納用パッケージならびに半導体装置

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013015216A1 (ja) * 2011-07-26 2013-01-31 京セラ株式会社 半導体素子収納用パッケージ、これを備えた半導体装置および電子装置
JP5537736B2 (ja) * 2011-07-26 2014-07-02 京セラ株式会社 半導体素子収納用パッケージ、これを備えた半導体装置および電子装置
US8952518B2 (en) 2011-07-26 2015-02-10 Kyocera Corporation Semiconductor device housing package, and semiconductor apparatus and electronic apparatus including the same
WO2013141013A1 (ja) * 2012-03-22 2013-09-26 京セラ株式会社 素子収納用パッケージ
US9408307B2 (en) 2012-03-22 2016-08-02 Kyocera Corporation Device housing package
WO2015012405A1 (ja) * 2013-07-26 2015-01-29 京セラ株式会社 素子収納用パッケージおよび実装構造体
JP6082114B2 (ja) * 2013-07-26 2017-02-15 京セラ株式会社 素子収納用パッケージおよび実装構造体
JPWO2015012405A1 (ja) * 2013-07-26 2017-03-02 京セラ株式会社 素子収納用パッケージおよび実装構造体
WO2022230883A1 (ja) * 2021-04-27 2022-11-03 京セラ株式会社 半導体パッケージ及び半導体電子装置

Also Published As

Publication number Publication date
EP2221867B1 (en) 2017-08-02
JP5189597B2 (ja) 2013-04-24
US20100252313A1 (en) 2010-10-07
EP2221867A1 (en) 2010-08-25
US8344259B2 (en) 2013-01-01
EP2221867A4 (en) 2013-02-13
JPWO2009057691A1 (ja) 2011-03-10

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