WO2009014017A1 - 多層セラミック基板およびその製造方法 - Google Patents

多層セラミック基板およびその製造方法 Download PDF

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Publication number
WO2009014017A1
WO2009014017A1 PCT/JP2008/062574 JP2008062574W WO2009014017A1 WO 2009014017 A1 WO2009014017 A1 WO 2009014017A1 JP 2008062574 W JP2008062574 W JP 2008062574W WO 2009014017 A1 WO2009014017 A1 WO 2009014017A1
Authority
WO
WIPO (PCT)
Prior art keywords
layers
laminate
powder
manufacturing
base material
Prior art date
Application number
PCT/JP2008/062574
Other languages
English (en)
French (fr)
Inventor
Yuichi Iida
Osamu Chikagawa
Original Assignee
Murata Manufacturing Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co., Ltd. filed Critical Murata Manufacturing Co., Ltd.
Priority to CN2008801004055A priority Critical patent/CN101772994B/zh
Priority to JP2009524446A priority patent/JP5012899B2/ja
Priority to DE112008001956T priority patent/DE112008001956T5/de
Priority to KR1020107001445A priority patent/KR101124277B1/ko
Publication of WO2009014017A1 publication Critical patent/WO2009014017A1/ja
Priority to US12/691,782 priority patent/US7911801B2/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/091—Locally and permanently deformed areas including dielectric material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1002—Methods of surface bonding and/or assembly therefor with permanent bending or reshaping or surface deformation of self sustaining lamina
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y10T428/24322—Composite web or sheet
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
    • Y10T428/24612—Composite web or sheet
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

　たとえば積層セラミックコンデンサのような素子を未焼結状態の生の積層体の内部に配置し、その状態で生の積層体を焼成することによって、多層セラミック基板を製造しようとするとき、内蔵された素子にクラックが生じ、また、積層体側にもクラックが生じることがある。 　積層体（６）を基材層（２）とその間に配置された層間拘束層（３～５）とをもって構成する。基材層はガラス材料および第１のセラミック材料を含む第１の粉体の焼結体からなり、層間拘束層は、上記ガラス材料を溶融させ得る温度では焼結しない第２のセラミック材料を含む第２の粉体を含むとともに、基材層に含まれていたガラス材料を含む第１の粉体の一部が焼成時に拡散あるいは流動することによって、第２の粉体が固着した状態にある。内蔵素子（７）は、その全周囲が層間拘束層（３，４）によって覆われた状態とされる。
PCT/JP2008/062574 2007-07-26 2008-07-11 多層セラミック基板およびその製造方法 WO2009014017A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN2008801004055A CN101772994B (zh) 2007-07-26 2008-07-11 多层陶瓷基板及其制造方法
JP2009524446A JP5012899B2 (ja) 2007-07-26 2008-07-11 多層セラミック基板およびその製造方法
DE112008001956T DE112008001956T5 (de) 2007-07-26 2008-07-11 Mehrschichtkeramiksubstrat und Verfahren zum Herstellen desselben
KR1020107001445A KR101124277B1 (ko) 2007-07-26 2008-07-11 다층 세라믹 기판 및 그 제조 방법
US12/691,782 US7911801B2 (en) 2007-07-26 2010-01-22 Multilayer ceramic substrate and method for manufacturing the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007194329 2007-07-26
JP2007-194329 2007-07-26
JP2007-329930 2007-12-21
JP2007329930 2007-12-21

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/691,782 Continuation US7911801B2 (en) 2007-07-26 2010-01-22 Multilayer ceramic substrate and method for manufacturing the same

Publications (1)

Publication Number Publication Date
WO2009014017A1 true WO2009014017A1 (ja) 2009-01-29

Family

ID=40281274

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/062574 WO2009014017A1 (ja) 2007-07-26 2008-07-11 多層セラミック基板およびその製造方法

Country Status (6)

Country Link
US (1) US7911801B2 (ja)
JP (1) JP5012899B2 (ja)
KR (1) KR101124277B1 (ja)
CN (1) CN101772994B (ja)
DE (1) DE112008001956T5 (ja)
WO (1) WO2009014017A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011152544A1 (ja) * 2010-05-31 2011-12-08 パナソニック株式会社 セラミック基板およびその製造方法
JP2014222698A (ja) * 2013-05-13 2014-11-27 コバレントマテリアル株式会社 電極埋め込み石英部材及びその製造方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
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WO2012014692A1 (ja) * 2010-07-29 2012-02-02 株式会社村田製作所 セラミック多層基板およびその製造方法
JP5598452B2 (ja) 2011-10-14 2014-10-01 株式会社村田製作所 電子部品及びその製造方法
JP2017183653A (ja) * 2016-03-31 2017-10-05 スナップトラック・インコーポレーテッド 高周波用多層配線基板とその製造方法
DE102018102144A1 (de) * 2018-01-31 2019-08-01 Tdk Electronics Ag Elektronisches Bauelement
KR102102311B1 (ko) * 2018-12-18 2020-04-21 주식회사 와이컴 프로브카드 공간변환기 제조방법 및 프로브카드 공간변환기용 세라믹 플레이트 가공장치
CN109688699A (zh) * 2018-12-31 2019-04-26 深圳硅基仿生科技有限公司 陶瓷电路板及其制造方法
JP6883059B2 (ja) * 2019-04-18 2021-06-09 株式会社フジクラ アンテナ
US11217542B2 (en) 2019-07-10 2022-01-04 Southern University Of Science And Technology Three-dimensional module with integrated passive components
WO2023272647A1 (zh) * 2021-06-30 2023-01-05 深南电路股份有限公司 埋入式电子元件及其制作方法、电压调节模块

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JP2005191316A (ja) * 2003-12-25 2005-07-14 Kyocera Corp 多層回路基板及びその製造方法
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011152544A1 (ja) * 2010-05-31 2011-12-08 パナソニック株式会社 セラミック基板およびその製造方法
JP2014222698A (ja) * 2013-05-13 2014-11-27 コバレントマテリアル株式会社 電極埋め込み石英部材及びその製造方法

Also Published As

Publication number Publication date
JPWO2009014017A1 (ja) 2010-09-30
CN101772994A (zh) 2010-07-07
CN101772994B (zh) 2011-07-20
KR101124277B1 (ko) 2012-03-27
KR20100022119A (ko) 2010-02-26
DE112008001956T5 (de) 2010-06-17
US20100112284A1 (en) 2010-05-06
US7911801B2 (en) 2011-03-22
JP5012899B2 (ja) 2012-08-29

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