WO2023272647A1 - 埋入式电子元件及其制作方法、电压调节模块 - Google Patents

埋入式电子元件及其制作方法、电压调节模块 Download PDF

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Publication number
WO2023272647A1
WO2023272647A1 PCT/CN2021/103816 CN2021103816W WO2023272647A1 WO 2023272647 A1 WO2023272647 A1 WO 2023272647A1 CN 2021103816 W CN2021103816 W CN 2021103816W WO 2023272647 A1 WO2023272647 A1 WO 2023272647A1
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WIPO (PCT)
Prior art keywords
conductive
hole
layer
substrate
electronic component
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PCT/CN2021/103816
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English (en)
French (fr)
Inventor
黄立湘
缪桦
董晋
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深南电路股份有限公司
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Priority to PCT/CN2021/103816 priority Critical patent/WO2023272647A1/zh
Publication of WO2023272647A1 publication Critical patent/WO2023272647A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present application relates to the technical field of embedding electronic components, in particular to an embedded electronic component, a manufacturing method thereof, and a voltage regulating module.
  • the electronic components occupy a large surface area of the circuit board, which is not conducive to the realization of high-density miniaturization. If the electronic components can be embedded inside the circuit board, it can save board space, enhance the ability of wiring layout, and realize high-density miniaturization.
  • An embodiment of the present application provides an embedded electronic component, wherein the embedded electronic component includes a substrate and an electronic component; an accommodating groove and a conductive hole are provided in the substrate, and a conductive layer is provided on the surface of the substrate , the electronic component is arranged in the accommodating groove, and the electronic component is provided with a first connection terminal and a second connection terminal extending laterally to the conductive hole; wherein, the first connection terminal and the The second connection terminal is electrically connected to the conductive layer through the conductive hole.
  • the embodiment of the present application also provides a method for manufacturing an embedded electronic component, wherein the method includes: providing a substrate and electronic components, and disposing the electronic components in the substrate; A conductive hole is opened on the substrate, and the conductive hole is subjected to conductive treatment; a conductive layer is formed on the surface of the substrate, and the conductive layer is electrically connected to the conductive hole; wherein, the electronic component is provided with A first connection terminal and a second connection terminal extending laterally to the conductive hole, the first connection terminal and the second connection terminal are electrically connected to the conductive layer through the conductive hole.
  • the embodiment of the present application also provides a voltage regulation module, wherein the voltage regulation module includes a MOS transistor and embedded electronic components, and the embedded electronic components include a substrate and electronic components; the substrate An accommodating groove and a conductive hole are provided inside, and a conductive layer is provided on the surface of the substrate; the electronic component is arranged in the accommodating groove, and the electronic component is provided with a first connection extending laterally to the conductive hole terminal and a second connection terminal; wherein, the first connection terminal and the second connection terminal are electrically connected to the conductive layer through the conductive hole; the MOS transistor is stacked on the substrate.
  • the voltage regulation module includes a MOS transistor and embedded electronic components
  • the embedded electronic components include a substrate and electronic components; the substrate An accommodating groove and a conductive hole are provided inside, and a conductive layer is provided on the surface of the substrate; the electronic component is arranged in the accommodating groove, and the electronic component is provided with a first connection extending laterally to the conductive hole terminal and a second connection terminal; wherein, the
  • the embedded electronic component, its manufacturing method, and voltage regulation module provided in the embodiments of the present application can be installed on the side of the electronic component by providing connection terminals and electrically connecting the connection terminals to the conductive layer on the surface of the substrate through conductive holes. Reduce the overall thickness of embedded electronic components during the packaging of electronic components.
  • FIG. 1 is a schematic structural view of the first embodiment of the embedded electronic component of the present application
  • Fig. 2 is another structural schematic diagram of the embedded electronic component in the embodiment of Fig. 1;
  • Fig. 3 is a schematic structural view of the application of embedded electronic components in the embodiment of Fig. 1;
  • Fig. 4 is a schematic diagram of the layout effect when the embedded electronic component is applied in the embodiment of Fig. 3;
  • Fig. 5 is a schematic diagram of layout effect when electronic components are applied in general technology
  • FIG. 6 is a schematic structural view of the second embodiment of the embedded electronic component of the present application.
  • Fig. 7 is another structural schematic diagram of the second embodiment of the embedded electronic component of the present application.
  • Fig. 8 is a schematic flowchart of a method for manufacturing an embedded electronic component in the second embodiment
  • Fig. 8a-Fig. 8c are schematic structural diagrams corresponding to the manufacturing method in Fig. 8 embodiment
  • Fig. 9 is a schematic flowchart of another manufacturing method of embedded electronic components in the second embodiment.
  • Fig. 9a is a schematic structural diagram corresponding to the manufacturing method in the embodiment of Fig. 9;
  • FIG. 10 is a schematic structural view of a third embodiment of the embedded electronic component of the present application.
  • Fig. 11 is another structural schematic diagram of the third embodiment of the embedded electronic component of the present application.
  • Fig. 12 is a schematic flowchart of a method for manufacturing an embedded electronic component in the third embodiment
  • Fig. 12a-Fig. 12h are schematic structural diagrams corresponding to the manufacturing method in Fig. 12 embodiment
  • FIG. 13 is a schematic structural view of a fourth embodiment of the embedded electronic component of the present application.
  • Fig. 14 is another structural schematic diagram of the fourth embodiment of the embedded electronic component of the present application.
  • Fig. 15 is a schematic flowchart of a method for manufacturing an embedded electronic component in the fourth embodiment
  • Fig. 15a-Fig. 15f are schematic structural diagrams corresponding to the manufacturing method in Fig. 15 embodiment
  • FIG. 16 is a schematic structural view of a fifth embodiment of the embedded electronic component of the present application.
  • Fig. 17 is another structural schematic diagram of the embedded electronic component in the embodiment of Fig. 16;
  • Fig. 18 is another structural schematic diagram of the fifth embodiment of the embedded electronic component of the present application.
  • Fig. 19 is a schematic flowchart of a method for manufacturing an embedded electronic component in the fifth embodiment
  • 19a-19d are schematic structural diagrams corresponding to the manufacturing method in the embodiment of FIG. 19 .
  • an embodiment of the present application provides an embedded electronic component on the one hand, wherein the embedded electronic component includes a substrate and an electronic component; the substrate is provided with accommodating grooves and conductive holes, and the surface of the substrate is provided with Conductive layer; the electronic component is arranged in the accommodating groove, and the electronic component is provided with a first connection terminal and a second connection terminal extending laterally to the conductive hole; wherein, the first connection terminal and the second connection terminal The second connecting terminal is electrically connected to the conductive layer through the conductive hole.
  • the substrate surface includes a first surface and a second surface opposite to each other, and the conductive layer is disposed on the first surface and/or the second surface.
  • the conductive hole includes an opposite conduction end and a cut-off end, the conduction end is connected to one of the first surface and the second surface, and the cut-off end is adjacent to the first surface and the second surface.
  • an insulation groove is provided between the cut-off end and the surface of the substrate adjacent to the cut-off end.
  • the bottom wall of the insulating groove is in contact with the cut-off end of the conductive hole, and the diameter of the insulating groove is larger than the cut-off end of the conductive hole.
  • the insulating groove is filled with insulating material.
  • the substrate surface includes a first surface and a second surface opposite to each other, and the conductive layer includes a first conductive layer disposed on the first surface and a second conductive layer disposed on the second surface , the conductive hole includes a first conductive hole connected to the first conductive layer and a second conductive hole connected to the second conductive layer; the first connecting terminal is connected to the first conductive hole through the first conductive hole The first conductive layer, the second connection terminal is connected to the second conductive layer through the second conductive hole.
  • the first conductive hole is pierced through the first connection terminal, and the second conductive hole is pierced through the second connection terminal.
  • the inner sidewall of the conductive hole is covered with a conductive substance, or the conductive hole is filled with a conductive substance, so as to realize the electrical connection between the conductive hole and the conductive layer.
  • the substrate is an insulating substrate
  • the electronic components are passive electronic components.
  • the embedded electronic component further includes an insulating layer, the insulating layer is disposed on the surface of the substrate and covers one end of the conductive hole, and the other end of the conductive hole is electrically connected to the conductive layer.
  • a pad is provided on the surface of the substrate, the pad is in contact with one end of the conductive hole, and the insulating layer completely covers the pad.
  • the embedded electronic component further includes an insulating layer
  • the conductive layer includes a first conductive layer and a second conductive layer
  • the first conductive layer is arranged on the surface of the substrate and covers the conductive hole The end portion
  • the insulating layer covers the side of the first conductive layer away from the substrate, and the insulating layer is provided with a conductive blind hole, and the conductive blind hole is electrically connected to the first conductive layer
  • the second conductive layer covers a side of the insulating layer away from the substrate, and the second conductive layer is electrically connected to the conductive blind hole.
  • the conductive blind hole is arranged corresponding to one end of the conductive hole, and is electrically connected with the conductive hole, and the first connection terminal and the second connection terminal pass through the conductive hole and the second The conductive layer is electrically connected.
  • the substrate surface includes a first surface and a second surface opposite to each other, and the first conductive layer includes a first conductive I layer on the first surface and a first conductive I layer on the second surface.
  • the conductive blind hole includes a first conductive blind hole and a second conductive blind hole
  • the first conductive blind hole is arranged in the first insulating layer and is electrically connected with the first conductive I layer
  • the The second conductive blind hole is arranged in the second insulating layer and is electrically connected with the first conductive II layer
  • the second conductive layer includes a second conductive I layer and a device arranged on the first insulating layer.
  • the second conductive II layer on the second insulating layer; the first conductive blind hole is electrically connected to the second conductive I layer, and the second conductive blind hole is electrically connected to the second conductive II layer sexual connection.
  • the conductive hole includes a first conductive hole and a second conductive hole arranged at intervals, and the conduction end of the first conductive hole is electrically connected to the first conductive blind hole through the first conductive I layer, The conducting end of the second conductive hole is electrically connected through the first conductive II layer and the second conductive blind hole; the first connection terminal is connected through the first conductive hole and the first conductive blind hole.
  • the hole is electrically connected to the second conductive layer I, and the second connection terminal is electrically connected to the second conductive layer II through the second conductive hole and the second conductive blind hole.
  • the conductive hole includes a first conductive blind hole and a second conductive blind hole
  • the first connecting terminal is electrically connected to the conductive layer through the first conductive blind hole
  • the second connecting terminal is electrically connected to the conductive layer through the first conductive blind hole.
  • the second conductive blind hole is electrically connected to the conductive layer.
  • the embodiments of the present application also provide a method for manufacturing an embedded electronic component, wherein the method includes: providing a substrate and electronic components, and disposing the electronic components in the substrate; A conductive hole is opened on the substrate, and the conductive hole is subjected to conductive treatment; a conductive layer is formed on the surface of the substrate, and the conductive layer is electrically connected to the conductive hole; wherein, the electronic component is provided with a side To the first connection terminal and the second connection terminal extending to the conductive hole, the first connection terminal and the second connection terminal are electrically connected to the conductive layer through the conductive hole.
  • the step of opening a conductive hole on the substrate further includes: processing one end of the conductive hole to form an insulating groove; wherein, the conductive hole includes opposite conduction ends and stop ends, and the conduction The through end is in contact with one surface of the substrate, and the cut-off end is disposed adjacent to the other surface of the substrate; the insulating groove is located between the cut-off end and the surface of the substrate adjacent to the cut-off end.
  • Still another aspect of the embodiment of the present application provides a voltage regulation module, wherein the voltage regulation module includes a MOS transistor and embedded electronic components, and the embedded electronic components include a substrate and electronic components; An accommodating groove and a conductive hole are provided, and a conductive layer is provided on the surface of the substrate; the electronic component is arranged in the accommodating groove, and the electronic component is provided with a first connection terminal extending laterally to the conductive hole and a second connection terminal; wherein, the first connection terminal and the second connection terminal are electrically connected to the conductive layer through the conductive hole; the MOS tube is stacked on the substrate
  • FIG. 1 is a schematic structural diagram of a first embodiment of an embedded electronic component of the present application.
  • the electronic component may be a passive electronic component, such as an inductance element, a capacitance element, a resistance element, and the like.
  • the electronic components in the embodiments of the present application are illustrated by taking an inductance component as an example.
  • the embedded electronic component 100 of this embodiment may include: a substrate 10 and an electronic component 12.
  • the substrate 10 is provided with at least one accommodating groove 111
  • at least one electronic component 12 is provided, and each accommodating groove 111 is provided with at least one electronic component 12 .
  • the substrate 10 is made of an insulating material, and the substrate 10 of this embodiment may use the same kind of insulating material.
  • the substrate 10 includes a frame 110 and a filling layer 120 integrally formed.
  • the frame 110 defines a receiving slot 111 .
  • the height of the frame 110 can be greater than or equal to the height of the electronic component 12 placed in the accommodating groove 111, so that when filling or pressing the filling layer 120, the frame 110 can play a supporting role, so as to prevent the electronic component 12 from being too stressed. Big and damaged.
  • the accommodating slot 111 of the frame 110 also serves as a position for positioning the electronic component 12 .
  • the filling layer 120 is filled in the receiving groove 111 to cover and/or wrap the electronic component 12 .
  • the material of filling layer 120 can adopt thermoplastic resin, such as polypropylene (PP), is used for encapsulating electronic component 12;
  • the material of frame 110 can adopt thermosetting resin, such as epoxy resin, and frame 110 is arranged around electronic component 12, The epoxy resin is molded after being cured, and will not soften or dissolve when heated, and is used to form the protective frame 110 to avoid damage to the electronic components 12 during the encapsulation process.
  • the substrate 10 has a first surface 101 and a second surface 102 opposite to each other. Back set on both surfaces. That is, the surface of the substrate 10 may include the above-mentioned first surface 101 and second surface 102 .
  • the filling layer 120 covers a side of the frame 110 close to the first surface 101 .
  • the electronic component 12 is disposed in the accommodating groove 111 , and the electronic component 12 is provided with a connecting terminal 121 extending laterally, that is, the extending direction of the connecting terminal 121 intersects with the Z direction.
  • the electronic component 12 has a top surface 122 , a bottom surface 124 disposed opposite to each other, and a side surface 126 connecting the top surface 122 and the bottom surface 124 , and the connection terminal 121 is disposed on the side surface 126 .
  • the top surface 122 and the bottom surface 124 are disposed opposite to each other along the thickness direction of the substrate 10 (Z direction as shown in FIG. 1 ).
  • the top surface 122 is disposed close to the first surface 101
  • the bottom surface 124 is disposed close to the second surface 102
  • the side surface 126 is located between the top surface 122 and the bottom surface 124 .
  • the top surface 122 and the bottom surface 124 of the electronic component 12 are substantially parallel, and the plane where the two are located is substantially parallel to the plane where the first surface 101 and the second surface 102 of the substrate 10 are located.
  • the lateral extension direction of the electronic component 12 can be regarded as a direction substantially parallel to the plane where the top surface 122 or the bottom surface 124 of the electronic component 12 is located.
  • the substrate 10 is provided with a conductive hole 130 , and the axis extending direction of the conductive hole 130 intersects both the first surface 101 and the second surface 102 of the substrate 10 .
  • the axial extension direction of the conductive hole 130 is substantially the same as the thickness direction of the substrate 10, or the axial extension direction of the conductive hole 130 is substantially the same as the Z direction shown in FIG.
  • the two surfaces 102 are substantially parallel to each other.
  • the first surface 101 and the second surface 102 are arranged in parallel, and both ends of the conductive hole 130 are parallel to the first surface 101 .
  • the connecting terminal 121 extends from the side of the electronic component 12 to the conductive hole 130 , that is, the lateral extending direction of the connecting terminal 121 is roughly the extending direction of the plane where the first surface 101 or the second surface 102 of the substrate 10 is located.
  • the conductive hole 130 is connected to the connecting terminal 121 or the conductive hole 130 passes through the connecting terminal 121 so that the connecting terminal 121 and the conductive hole 130 are electrically connected.
  • a conductive layer 14 is disposed on the surface of the substrate 10 .
  • the conductive layer 14 may be disposed on the first surface 101 or the second surface 102 of the substrate 10 .
  • the conductive hole 130 is connected to the conductive layer 14 and is electrically connected to the conductive layer 14
  • the connecting terminal 121 is electrically connected to the conductive layer 14 through the conductive hole 130 , that is, the electronic component 12 can realize conduction on one side of the substrate 10 .
  • the conductive layer 14 is disposed on the first surface 101 of the substrate 10 .
  • a plurality of conductive holes 130 and connecting terminals 121 can be provided respectively, and the conductive holes 130 and the connecting terminals 121 are correspondingly arranged, and each connecting terminal 121 is electrically connected to the conductive layer 14 provided on the first surface 101 through a conductive hole 130 . connect.
  • the conductive layer 14 can also be disposed on the second surface 102 of the substrate 10 .
  • Each connection terminal 121 is electrically connected to the conductive layer 14 on the second surface 102 through a conductive hole 130 , so that the electronic components 12 can be electrically connected on one side of the substrate 10 .
  • the conductive layer 14 can be respectively disposed on the first surface 101 and the second surface 102 of the substrate 10 .
  • FIG. 2 is another structural schematic diagram of the embedded electronic component in the embodiment of FIG. 1 .
  • the conductive layer 14 may include a first conductive layer 141 and a second conductive layer 142 .
  • the first conductive layer 141 is disposed on the first surface 101
  • the second conductive layer 142 is disposed on the second surface 102 .
  • first”, “second”, and “third” in this application are only used for descriptive purposes, and should not be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. quantity. Thus, features defined as “first”, “second”, and “third” may explicitly or implicitly include at least one of these features.
  • the conductive hole 130 may include a first conductive hole 131 and a second conductive hole 132, and the connection terminal 121 may include a first connection terminal 121a and a second connection terminal 121b.
  • the first conductive hole 131 is connected to the first conductive layer 141
  • the second conductive hole 132 is connected to the second conductive layer 142 .
  • the first connection terminal 121 a is connected to the first conductive layer 141 through the first conductive hole 131
  • the second connection terminal 121 b is connected to the second conductive layer 142 through the second conductive hole 132 .
  • the electronic component 12 can be conducted on both sides of the first surface 101 and the second surface 102 of the substrate 10 .
  • the embedded electronic component provided by the embodiment of the present application realizes conduction of the electronic component on one or both sides of the substrate by providing connection terminals on the side of the electronic component and connecting to the conductive layer on the surface of the substrate through the conductive hole.
  • the embodiment of the present application arranges the connection terminal on the side of the electronic component, which can reduce the thickness of the overall structure when the electronic component is packaged, and when the electronic component is embedded In the process in the substrate, the environmental requirements are relatively lower compared with the electronic component mounting process.
  • the electronic components in the embodiment of the present application are embedded inside the substrate, which can increase the mounting area of other components or chips on the surface of the substrate.
  • the electronic component 12 may have multiple connection terminals 121 , and the above-mentioned embodiments of the present application illustrate an embodiment in which the electronic component 12 has two connection terminals 121 .
  • two conductive holes 130 are provided, and are provided correspondingly to the two connecting terminals 121 , that is, each conductive hole 130 passes through each connecting terminal 121 .
  • the electronic component 12 may have three connection terminals, for example, an inductance component with a three-pin structure has three pins.
  • three conductive holes 130 may be provided, which are respectively arranged corresponding to the three connecting terminals, that is, each connecting terminal 121 is electrically connected to each conductive hole 130 .
  • some of the plurality of connection terminals 121 can be connected to the conductive layer provided on the first surface 101 or the second surface 102 through the conductive hole 130, and another part of the plurality of connection terminals 121 can be connected to the conductive layer through the conductive hole 130.
  • 130 is connected to the conductive layer disposed on the first surface 101 or the second surface 102, so as to realize conduction of electronic components on one or both sides of the substrate.
  • the inner wall of the conductive hole 130 is covered with a conductive material, so as to realize the electrical connection between the conductive hole 130 and the conductive layer on the surface of the substrate.
  • a conductive material such as a copper layer, a copper-nickel alloy layer, and a copper-nickel-gold alloy layer can be covered on the inner sidewall of the conductive hole 130 by electroplating.
  • the conductive hole 130 is filled with conductive substances, so as to realize the electrical connection between the conductive hole 130 and the conductive layer on the surface of the substrate.
  • metal column structures such as copper columns and alloy columns may be formed in the conductive holes 130 .
  • FIG. 3 is a schematic structural diagram of the application of embedded electronic components in the embodiment of Figure 1
  • Figure 4 is a schematic diagram of the layout effect of the application of embedded electronic components in the embodiment of Figure 3
  • Figure 5 It is a schematic diagram of the layout effect of the application of electronic components in general technology.
  • the voltage regulation module is generally used to provide a stable working voltage for the CPU.
  • the voltage regulation module 1000 roughly includes an embedded electronic component 100 and a MOS transistor 800 (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide-Semiconductor Field-Effect Transistor).
  • MOS transistor 800 Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide-Semiconductor Field-Effect Transistor.
  • the MOS transistor 800 and the substrate 10 and electronic components 12 in the embedded electronic component 100 are usually flattened on the PCB motherboard 900 and electrically connected to
  • the CPU is powered, and usually a CPU needs roughly 10 voltage regulation modules 1000 to provide a stable power supply voltage for it. Based on this, the above-mentioned tiling scheme will occupy a large mounting area, which is not conducive to miniaturized layout.
  • the electronic components 12 are embedded in the substrate 10, and the MOS transistors 800 are stacked on the substrate 10 to form a voltage regulation module 1000, and then the voltage regulation module 1000 is placed on the PCB motherboard 900 to serve as The CPU provides a stable supply voltage.
  • the mounting area occupied by the voltage regulation module formed by stacking embedded electronic components on the PCB motherboard is greatly reduced, which has a good promotion effect for miniaturization layout.
  • devices such as ICs, capacitors, and inductors can also be stacked on embedded electronic components to reduce the mounting area of the circuit board.
  • FIG. 6 is a schematic structural diagram of a second embodiment of the embedded electronic component of the present application. Wherein, the difference between the second embodiment and the first embodiment lies in that: the connection mode between the conductive hole and the conductive layer is different.
  • the embedded electronic component 200 of this embodiment may include: a substrate 20 and an electronic component 22 , and the electronic component 22 is disposed in the substrate 20 .
  • the electronic component 22 is provided with a connecting terminal 221 extending laterally.
  • the substrate 20 has a first surface 201 and a second surface 202 opposite to each other, and a conductive hole 230 is disposed in the substrate 20 .
  • the connection terminal 221 extends from the side of the electronic component 22 to the conductive hole 230 .
  • the conductive hole 230 may include a conduction end 2301 and a cut-off end 2302 oppositely arranged, and the conduction end 2301 and the cut-off end 2302 are respectively arranged corresponding to the first surface 201 and the second surface 202 . That is, one of the conduction end 2301 and the cut-off end 2302 is disposed corresponding to the first surface 201 , and the other is disposed corresponding to the second surface 202 .
  • the conducting end 2301 is used to realize the electrical connection between the conductive hole 230 and the conductive layer on the surface of the substrate
  • the cut-off end 2302 is used to realize the insulation between the conductive hole 230 and the conductive layer on the surface of the substrate.
  • the conduction end 2301 and the first surface 201 are arranged correspondingly, that is, adjacent to each other, and the conduction end 2301 is electrically connected to the conductive layer on the first surface 201 .
  • the cut-off end 2302 and the second surface 202 are arranged correspondingly, that is, adjacent to each other, and the cut-off end 2302 is insulated from the conductive layer on the second surface 202 to realize the single-end conduction of the conductive hole 230 .
  • an insulating groove 250 is provided between the cut-off end 2302 and the surface of the substrate 20 adjacent to the cut-off end 2302, the bottom wall of the insulation groove 250 is in contact with the cut-off end 2302 of the conductive hole 230, and the aperture of the insulating groove 250 is larger than the cut-off end.
  • the insulating groove 250 is filled with insulating material to isolate the cut-off end 2302 of the conductive hole 230 from the conductive layer on the surface of the substrate, so that one end of the conductive hole 230 can be conducted, and the other end is cut off and conducted, so that the electronic component 22
  • the connecting terminal 221 is connected to the conductive layer through the conductive hole 230 and is electrically connected at one end of the conductive hole 230 .
  • the electronic component 22 is provided with two connection terminals, that is, the first connection terminal 221a and the second connection terminal 221b.
  • the conductive layer includes a first conductive layer 241 disposed on the first surface 201 and a second conductive layer 242 disposed on the second surface 202
  • the conductive hole 230 includes a first conductive hole 231 connected to the first conductive layer 241 and the second conductive hole 232 connected to the first conductive layer 241 .
  • the first connection terminal 221 a is connected to the first conductive layer 241 through the first conductive hole 231
  • the second connection terminal 221 b is connected to the first conductive layer 241 through the second conductive hole 232 .
  • the first conductive hole 231 may include a first conduction end 2311 and a first cut-off end 2312 oppositely arranged
  • the second conduction hole 232 may include a second conduction end 2321 and a second cut-off end 2322 oppositely arranged.
  • the first conducting end 2311 and the second conducting end 2321 may be electrically connected to the conductive layer on the first surface 201 , that is, the first conductive layer 241 .
  • a first insulating groove 251 is disposed between the first cut-off end 2312 and the second surface 202
  • a second insulating groove 252 is disposed between the second cut-off end 2322 and the second surface 202 .
  • an insulating groove 250 is provided between the cut-off end 2302 of the conductive hole 230 and the second conductive layer 242 of the second surface 202, so that the first conductive hole 231 and the second conductive hole 232 are respectively connected to the second conductive layer 242 of the first surface 201.
  • a conductive layer 241 is electrically connected, so that the first connection terminal 221a of the electronic component 22 is connected to the first conductive layer 241 through the first conductive hole 231, and the second connection terminal 221b is connected to the first conductive layer through the second conductive hole 232 241, so as to realize the conduction of electronic components on one side of the substrate, that is, the first surface.
  • a technical solution for the conduction of electronic components on the second surface of the substrate can also be derived, which will not be described in the embodiments of the present application.
  • FIG. 7 is another structural schematic diagram of the second embodiment of the embedded electronic component of the present application. Wherein, the difference between the embodiment in FIG. 7 and the embodiment in FIG. 6 lies in that the electronic components are conducted on both sides of the substrate.
  • the electronic component 22 is provided with two connection terminals, that is, a first connection terminal 221a and a second connection terminal 221b.
  • the conductive layer 24 includes a first conductive layer 241 disposed on the first surface 201 and a second conductive layer 242 disposed on the second surface 202
  • the conductive hole 230 includes a first conductive hole connected to the second conductive layer 242 231 and the second conductive hole 232 connected to the first conductive layer 241 .
  • the first connection terminal 221 a is connected to the second conductive layer 242 through the first conductive hole 231
  • the second connection terminal 221 b is connected to the first conductive layer 241 through the second conductive hole 232 .
  • the first conductive hole 231 may include a first conduction end 2311 and a first cut-off end 2312 oppositely arranged
  • the second conduction hole 232 may include a second conduction end 2321 and a second cut-off end 2322 oppositely arranged.
  • the first conduction end 2311 is electrically connected to the conductive layer on the second surface 202, that is, the second conduction layer 242
  • the second conduction end 2321 is electrically connected to the conduction layer on the first surface 201, that is, the first conduction layer 241. connect.
  • a first insulating groove 251 is disposed between the first cut-off end 2312 and the first surface 201
  • a second insulating groove 252 is disposed between the second cut-off end 2322 and the second surface 202 .
  • the first insulating groove 251 is provided between the cut-off end of the first conductive hole 231 and the first conductive layer of the first surface 201
  • the second insulation groove 251 is provided between the cut-off end of the second conductive hole 232 and the second end of the second surface 202
  • a second insulating groove 252 is provided between the conductive layers, so that the first conductive hole 231 is electrically connected to the second conductive layer 242 of the second surface 202, and the second conductive hole 232 is electrically connected to the first conductive layer 241 of the first surface 201. connect.
  • first connection terminal 221a of the electronic component 22 is connected to the second conductive layer 242 through the first conductive hole 231, and the second connection terminal 221b is connected to the first conductive layer 241 through the second conductive hole 232, so that the electronic component is connected to the second conductive layer 242 through the second conductive hole 232.
  • Both sides of the substrate, that is, the first surface and the second surface are simultaneously conducted.
  • the first connection terminal 221 a of the electronic component 22 can be connected to the first conductive layer 241 through the first conductive hole 231
  • the second connection terminal 221 b can be connected to the second conductive layer 242 through the second conductive hole 232 .
  • FIG. 8 is a schematic flowchart of a method for manufacturing an embedded electronic component in the second embodiment of the present application.
  • the manufacturing method can be used to manufacture the embedded electronic component in the second embodiment.
  • the preparation method generally includes the following steps:
  • FIG. 8a-FIG. 8c are schematic structural diagrams corresponding to the manufacturing method in the embodiment of FIG. 8 .
  • the substrate 20 has a first surface 201 and a second surface 202 disposed opposite to each other, and the electronic component 22 is provided with connecting terminals 221 extending laterally.
  • the specific structural features of the substrate 20 and the electronic components 22 reference may be made to the specific descriptions of the foregoing embodiments, which will not be repeated here.
  • the specific process of embedding electronic components into the substrate can be as follows: first place the electronic components in the accommodating slots of the frame, then fill the accommodating slots and the frame with insulating materials, and press the insulating materials to form a Frame integrally formed padding.
  • the conductive hole may be treated by electroplating. That is, the inner wall of the conductive hole is covered with a layer of conductive material by copper sinking, electroplating and other processes, so as to realize the electrical connection between the conductive hole and the connecting terminal.
  • conductive substances can be filled in the conductive holes by copper sinking, electroplating and other processes, that is, a metal columnar structure can be formed in the conductive holes to realize the electrical connection between the conductive holes and the connecting terminals.
  • the conductive holes opened on the substrate generally penetrate the first surface and the second surface of the substrate, that is, through holes can be formed on the substrate by drilling, and then through copper deposition, electroplating, etc.
  • the process forms conductive holes on top of vias.
  • the conductive layer 24 may be formed on the first surface 201 and/or the second surface 202 of the substrate by copper sinking, electroplating and other processes. As shown in FIG. 8 c , a conductive layer 24 is formed on the first surface 201 of the substrate through processes such as copper sinking and electroplating. It can be understood that in the embodiment shown in FIG. 2 , the first conductive layer 241 and the second conductive layer 242 can be formed on the first surface 201 and the second surface 202 of the substrate respectively by copper sinking, electroplating and other processes. Regarding the specific structural features of the conductive layer 24 that are not described in detail, reference may be made to the specific descriptions in the foregoing embodiments.
  • a conductive hole penetrating through the substrate can be firstly drilled on the substrate, and then the inner wall of the conductive hole is covered with a conductive substance by copper sinking, electroplating and other processes. Or fill conductive substances in the conductive holes.
  • a conductive layer can be formed on the surface of the substrate simultaneously, and then the conductive layer can be patterned to obtain the desired circuit.
  • the conductive material in the conductive hole and the conductive layer on the surface of the substrate can be formed simultaneously through the same process, which can improve production efficiency.
  • the manufacturing method of the embedded electronic component is to embed the electronic component in the substrate, and open a conductive hole on the substrate to be electrically connected to the connecting terminal extending laterally of the electronic component, and provide a conductive layer on the surface of the substrate.
  • the conductive layer is electrically connected to the conductive hole, so that the connection terminal of the electronic component can be connected to the conductive layer through the conductive hole, thereby realizing conduction of the electronic component on one or both sides of the substrate.
  • the manufacturing method provided in this embodiment can reduce the thickness of the overall structure when packaging electronic components, and can increase the mounting area of other components or chips on the surface of the substrate.
  • each connection terminal is generally led to conduction from one surface of the substrate, which requires the conduction hole to achieve single-end conduction.
  • the embodiment of the present application needs to further process the conductive hole before step S803, so that the conductive hole can realize single-ended conduction.
  • FIG. 9 is a schematic flowchart of another manufacturing method of embedded electronic components in the second embodiment of the present application. This manufacturing method can be used to manufacture embedded electronic components in the second embodiment. Electronic component.
  • the preparation method generally includes the following steps:
  • step S901 Provide a substrate and electronic components, and arrange the electronic components in the substrate.
  • step S801 in the foregoing embodiments, so details are not repeated here.
  • FIG. 9a is a schematic structural diagram corresponding to the manufacturing method in the embodiment of FIG. 9 .
  • the conductive hole 230 may include a conduction end 2301 and a cut-off end 2302 which are oppositely arranged.
  • the conduction end 2301 is connected to one surface of the substrate 20, the cut-off end 2302 is arranged adjacent to the other surface of the substrate 20, and the insulating groove 250 is located at the cut-off end. Between the cut-off end 2302 and the surface of the substrate 20 adjacent to the cut-off end 2302.
  • the conduction end 2301 is in contact with the first surface 201
  • the cut-off end 2302 is disposed adjacent to the second surface 202
  • the insulation groove 250 is located between the cut-off end 2302 and the second surface 202 .
  • the substrate 20 is provided with a through hole penetrating through the first surface 201 and the second surface 202 of the substrate 20, and then the conductive hole 230 is formed on the basis of the through hole by copper sinking, electroplating and other processes. . Further, a stop end 2302 and an insulating groove 250 are formed at one end of the conductive hole 230 by back drilling.
  • the bottom wall of the insulating groove 250 is in contact with the cut-off end 2302 of the conductive hole 230 , and the diameter of the insulating groove 250 is larger than that of the cut-off end 2302 .
  • the insulating groove 250 is filled with an insulating material to isolate the cut-off end 2302 of the conductive hole 230 from the conductive layer 24 on the surface of the substrate, so that one end of the conductive hole 230 can be turned on, and the other end is cut off and turned on, and then the connection of the electronic component 22
  • the terminal 221 is electrically led out and electrically connected at one end of the conductive hole 230 .
  • a conductive hole penetrating through the substrate can be first drilled on the substrate, and then one end of the conductive hole can be processed by back drilling to form an insulating groove and then insulated.
  • the slot is filled with insulating material; next, the inner wall of the conductive hole is covered with a conductive substance or the conductive hole is filled with a conductive substance through processes such as copper sinking and electroplating.
  • a conductive layer can be formed on the surface of the substrate simultaneously, and then the conductive layer can be patterned to obtain the desired circuit.
  • the conductive material in the conductive hole and the conductive layer on the surface of the substrate can be formed simultaneously through the same process, which can improve production efficiency.
  • a conductive hole penetrating through the substrate can be drilled on the substrate, and then the inner sidewall of the conductive hole can be covered with a conductive material or placed in the conductive hole through copper sinking, electroplating and other processes. Fill the conductive substance and form a conductive layer on the surface of the substrate simultaneously.
  • one end of the conductive hole is processed by back drilling to form an insulating groove and an insulating material is filled in the insulating groove; then the conductive layer is patterned to obtain the required circuit.
  • an insulating groove is provided between one end of the conductive hole and the surface of the substrate to realize single-ended conduction of the conductive hole, and then the connecting terminal of the electronic component can be electrically connected to the substrate through the conductive hole conductive layer on the first or second surface of the
  • FIG. 10 is a schematic structural diagram of a third embodiment of the embedded electronic component of the present application. Wherein, the difference between the third embodiment and the first and second embodiments lies in: the connection mode between the conductive hole and the conductive layer is different.
  • the embedded electronic component 300 of this embodiment may include: a substrate 30 and an electronic component 32 , and the electronic component 32 is disposed in the substrate 30 .
  • the electronic component 32 is provided with a connecting terminal 321 extending laterally.
  • the substrate 30 has a first surface 301 and a second surface 302 opposite to each other, and a conductive hole 330 is disposed in the substrate 30 .
  • the connection terminal 321 extends from the side of the electronic component 32 to the conductive hole 330 .
  • the conductive hole 330 may include a conduction end 3301 and a cut-off end 3302 oppositely disposed, and the conduction end 3301 and the cut-off end 3302 are respectively arranged corresponding to the first surface 301 and the second surface 302 . That is, one of the conduction end 3301 and the cut-off end 3302 is disposed corresponding to the first surface 301 , and the other is disposed corresponding to the second surface 302 .
  • the conducting end 3301 is used to realize the electrical connection between the conductive hole 330 and the conductive layer on the surface of the substrate
  • the cut-off end 3302 is used to realize the insulation between the conductive hole 330 and the conductive layer on the surface of the substrate.
  • the conduction end 3301 is connected to the first surface 301 , and the conduction end 3301 is electrically connected to the conductive layer on the first surface 301 .
  • the cut-off end 3302 is connected to the second surface 302 , and the cut-off end 3302 is insulated from the conductive layer on the second surface 302 , so as to realize the single-end conduction of the conductive hole 330 .
  • an insulating layer 360 is disposed on the surface of the substrate 30 , and the insulating layer 360 completely covers the cut-off end 3302 of the conductive hole 330 .
  • the insulating layer 360 is covered on the cut-off end 3302 of the conductive hole 330 to isolate the cut-off end 3302 of the conductive hole 330 from the conductive layer on the surface of the substrate, so that one end of the conductive hole 330 can be turned on, and the other end is turned off. , and then connect the connecting terminal 321 of the electronic component 32 to the conductive hole 330 and realize an electrical connection at one end of the conductive hole 330 .
  • the insulating layer 360 is made of insulating materials, such as resin materials such as polypropylene and epoxy resin.
  • the electronic component 32 is provided with two connection terminals, that is, a first connection terminal 321a and a second connection terminal 321b.
  • the conductive layer may include a first conductive layer 341 disposed on the first surface 301 and a second conductive layer 342 disposed on the second surface 302, and the conductive hole 330 includes a first conductive hole connected to the first conductive layer 341 331 and the second conductive hole 332 connected to the first conductive layer 341 .
  • the first connection terminal 321 a is connected to the first conductive layer 341 through the first conductive hole 331
  • the second connection terminal 321 b is connected to the first conductive layer 341 through the second conductive hole 332 .
  • the first conductive hole 331 may include a first conduction end 3311 and a first cut-off end 3312 oppositely arranged
  • the second conduction hole 332 may include a second conduction end 3321 and a second cut-off end 3322 oppositely arranged.
  • the first conducting end 3311 and the second conducting end 3321 can be electrically connected to the conductive layer on the first surface 301 , that is, the first conductive layer 341 .
  • a first insulating layer 361 is disposed between the first cut-off end 3312 and the second conductive layer 342
  • a second insulating layer 362 is disposed between the second cut-off end 3322 and the second conductive layer 342 .
  • the first insulating layer 361 is disposed on the second surface 302 and covers the first cut-off end 3312 .
  • the second insulating layer 362 is disposed on the second surface 302 and covers the second cut-off end 3322 .
  • the second conductive layer 342 on the second surface 302 covers the first insulating layer 361 , the second insulating layer 362 and the second surface 302 at the same time.
  • an insulating layer 360 is provided between the cut-off end 3302 of the conductive hole 330 and the second conductive layer 342 of the second surface 302, so that the first conductive hole 331 and the second conductive hole 332 are respectively connected to the second conductive layer 342 of the first surface 301.
  • a conductive layer 341 is electrically connected, so that the first connection terminal 321a of the electronic component 32 is connected to the first conductive layer 341 through the first conductive hole 331, and the second connection terminal 321b is connected to the first conductive layer through the second conductive hole 332 341, so as to realize the conduction of electronic components on one side of the substrate, that is, the first surface.
  • a technical solution for the conduction of electronic components on the second surface of the substrate can also be derived, which will not be described in the embodiments of the present application.
  • FIG. 11 is another structural schematic diagram of the third embodiment of the embedded electronic component of the present application. Wherein, the difference between the embodiment in FIG. 11 and the embodiment in FIG. 10 lies in that the electronic components are conducted on both sides of the substrate.
  • the electronic component 32 is provided with two connection terminals, that is, a first connection terminal 321a and a second connection terminal 321b.
  • the conductive layer may include a first conductive layer 341 disposed on the first surface 301 and a second conductive layer 342 disposed on the second surface 302, and the conductive hole 330 includes a first conductive hole connected to the second conductive layer 342 331 and the second conductive hole 332 connected to the first conductive layer 341 .
  • the first connection terminal 321 a is connected to the second conductive layer 342 through the first conductive hole 331
  • the second connection terminal 321 b is connected to the first conductive layer 341 through the second conductive hole 332 .
  • the first conductive hole 331 may include a first conduction end 3311 and a first cut-off end 3312 oppositely arranged
  • the second conduction hole 332 may include a second conduction end 3321 and a second cut-off end 3322 oppositely arranged.
  • the first conductive layer 3311 is electrically connected to the conductive layer on the second surface 302, that is, the second conductive layer 342
  • the second conductive layer 3321 is electrically connected to the conductive layer on the first surface 301, that is, the first conductive layer 341. connect.
  • a first insulating layer 361 is disposed between the first cut-off end 3312 and the first conductive layer 341
  • a second insulating layer 362 is disposed between the second cut-off end 3322 and the second conductive layer 342 .
  • the first insulating layer 361 is disposed on the first surface 301 and covers the first stop end 3312 .
  • the second insulating layer 362 is disposed on the second surface 302 and covers the second cut-off end 3322 .
  • the first conductive layer 341 on the first surface 301 covers the first insulating layer 361 and the first surface 301 at the same time.
  • the second conductive layer 342 on the second surface 302 covers the second insulating layer 362 and the second surface 302 at the same time.
  • the first insulating layer 361 is provided between the cut-off end of the first conductive hole 331 and the first conductive layer on the first surface 301 , and the cut-off end of the second conductive hole 332 and the first conductive layer on the second surface 302
  • the second insulating layer 362 is arranged between the second conductive layer, so that the first conductive hole 331 and the second conductive layer 342 of the second surface 302 are electrically connected, and the second conductive hole 332 and the first conductive layer 341 of the first surface 301 electrical connection.
  • first connection terminal 321a of the electronic component 32 is connected to the second conductive layer 342 through the first conductive hole 331, and the second connection terminal 321b is connected to the first conductive layer 341 through the second conductive hole 332, so that the electronic component is connected to the second conductive layer 342 through the second conductive hole 332.
  • Both sides of the substrate, that is, the first surface and the second surface are simultaneously conducted.
  • the first connection terminal 321 a of the electronic component 32 can be connected to the first conductive layer 341 through the first conductive hole 331
  • the second connection terminal 321 b can be connected to the second conductive layer 342 through the second conductive hole 332 .
  • a pad 370 is provided on the surface of the substrate 30, the pad 370 is in contact with the cut-off end 3302 of the conductive hole 330, and the size of the pad 370 is not smaller than the cut-off end of the conductive hole 330 3302.
  • the pad 370 is located between the insulating layer 360 and the cut-off end 3302 , and the insulating layer 360 completely covers the pad 370 to avoid the risk of communication between the cut-off end 3302 and the conductive layer on the corresponding surface of the substrate.
  • a first bonding pad 371 and a second bonding pad 372 are respectively provided on the surface of the substrate 30 .
  • the first pad 371 is in contact with the first cut-off end 3312 and is located between the first cut-off end 3312 and the first insulating layer 361 .
  • the second pad 372 is in contact with the second cut-off end 3322 and is located between the second cut-off end 3322 and the second insulating layer 362 .
  • the first insulating layer 361 completely covers the first pad 371 , and the size of the first pad 371 is not smaller than the first cut-off end 3312 .
  • the second insulating layer 362 completely covers the second pad 372 , and the size of the second pad 372 is not smaller than the second cut-off end 3322 .
  • FIG. 12 is a schematic flowchart of a method for manufacturing an embedded electronic component in the third embodiment of the present application.
  • the manufacturing method can be used to manufacture the embedded electronic component in the third embodiment.
  • the preparation method generally includes the following steps:
  • FIG. 12a-FIG. 12h are schematic structural diagrams corresponding to the manufacturing method in the embodiment of FIG. 12 .
  • the substrate 30 has a first surface 301 and a second surface 302 disposed opposite to each other, and the electronic component 32 is provided with a connecting terminal 321 extending laterally.
  • the specific structural features of the substrate 30 and the electronic components 32 reference may be made to the specific descriptions in the foregoing embodiments, which will not be repeated here.
  • a conductive hole penetrating through the substrate can be opened on the substrate first by drilling, and then the inner wall of the conductive hole is covered with conductive material or filled with conductive material through copper sinking, electroplating and other processes.
  • a conductive layer can be formed on the surface of the substrate simultaneously, and then the conductive layer can be patterned to obtain the desired circuit.
  • the conductive material in the conductive hole and the conductive layer on the surface of the substrate can be formed simultaneously through the same process, which can improve production efficiency.
  • the conductive layer may include a first conductive layer 341 disposed on the first surface 301 and a second conductive layer 342 disposed on the second surface 302 . At this time, two ends of the conductive hole 330 are electrically connected to the first conductive layer 341 and the second conductive layer 342 respectively.
  • part of the conductive substance may be reserved on the exposed surface of the substrate to form a pad, the pad completely covers the cut-off end of the conductive hole, and the pad is spaced apart from the conductive layer.
  • the conductive hole 330 includes a first conductive hole 331 connected to the second conductive layer 342 and a second conductive hole 332 connected to the first conductive layer 341 .
  • the first connection terminal 321 a is connected to the second conductive layer 342 through the first conductive hole 331
  • the second connection terminal 321 b is connected to the first conductive layer 341 through the second conductive hole 332 .
  • the first conductive hole 331 may include a first conduction end 3311 and a first cut-off end 3312 oppositely disposed
  • the second conduction hole 332 may include a second conduction end 3321 and a second cut-off end 3322 oppositely disposed.
  • the first conduction end 3311 is electrically connected to the second conductive layer 342
  • the second conduction end 3321 is electrically connected to the first conduction layer 341
  • the first cut-off end 3312 is connected to the first surface 301
  • the second cut-off end 3322 is connected to the second surface 302 .
  • Partial processing is performed on the area of the first conductive layer 341 corresponding to the first cut-off end 3312 to expose part of the first surface 301 , so that the first cut-off end 3312 and the first conductive layer 341 are spaced and insulated. Partial processing is performed on the area of the second conductive layer 342 corresponding to the second cut-off end 3322 to expose part of the second surface 302 , so that the second cut-off end 3322 and the second conductive layer 342 are insulated from each other.
  • the conductive layers may be partially treated by a copper reduction process to expose part of the surface of the substrate.
  • the conductive layer may also be processed by other processes such as drilling to expose part of the surface of the substrate.
  • the first pad 371 is formed by local processing in the area of the first conductive layer 341 corresponding to the first cut-off end 3312, and the first pad 371 covers part of the first surface 301 and completely covers the first surface 301. cut-off end 3312.
  • the second pad 372 is partially processed on the area of the second conductive layer 342 corresponding to the second cut-off end 3322 , and the second pad 372 covers part of the second surface 302 and completely covers the second cut-off end 3322 .
  • the first pad 371 is insulated from the first conductive layer 341
  • the second pad 372 is insulated from the second conductive layer 342 .
  • no conductive substance may be reserved on the partially exposed surface of the substrate, that is, no pad structure will be formed.
  • the substrate surface is exposed, and a groove 380 structure with the substrate surface as the bottom wall is formed, and the groove 380 structure completely covers the cut-off end of the conductive hole, so that the conductive hole
  • the cut-off end and the conductive layer are insulated. For example, removing part of the first conductive layer 341 forms a first groove 381 with the first surface 301 as the bottom wall, and removing part of the second conductive layer 342 forms a second groove 382 with the second surface 302 as the bottom wall.
  • the bottom wall of the first groove 381 is in contact with the first end 3312 , and the diameter of the first groove 381 is larger than that of the first end 3312 , so that the first end 3312 is insulated from the first conductive layer 341 .
  • the bottom wall of the second groove 382 is in contact with the second cut-off end 3322 , and the aperture of the second groove 382 is larger than the second cut-off end 3322 , thereby insulating the second cut-off end 3322 from the second conductive layer 342 .
  • pad structures are formed on the exposed surface of the substrate, and the insulating layer completely covers the above pad structures.
  • the pad structure is in contact with the conductive hole and completely covers one end of the conductive hole, and the pad structure is insulated from the conductive layer, so that one end of the conductive hole is insulated from the conductive layer.
  • the first pad 371 completely covers the first cut-off end 3312
  • a first insulating layer 361 is formed on the first pad 371
  • the first insulating layer 361 completely covers the first pad 371 .
  • the second pad 372 completely covers the second cut-off end 3322
  • a second insulating layer 362 is formed on the second pad 372
  • the second insulating layer 362 completely covers the second pad 372 .
  • the insulating material is filled in the first groove 381 to form the first insulating layer 361 , and the first insulating layer 361 completely covers the bottom wall of the first groove 381 and the first stop end 3312 .
  • the insulating material is filled in the second groove 382 to form the second insulating layer 362 , and the second insulating layer 362 completely covers the bottom wall of the second groove 382 and the second stop end 3322 .
  • part of the conductive layer is removed to expose part of the substrate surface, and an insulating layer is formed on the exposed substrate surface, and the insulating layer is completely covered on one end of the conductive hole, so that one end of the conductive hole and The conductive layer is insulated, and the other end is electrically connected to the conductive layer, so that the connection terminal of the electronic component can be connected to the conductive layer through the conductive hole.
  • the insulating layer is usually filled with conductive substances to form a complete surface with the conductive layer. Specifically, please continue to refer to FIG. 12h.
  • a step S1206 is also included, that is, to fill the insulating layer with a conductive substance, so that the surface of the conductive layer facing away from the substrate is even, so as to maintain the appearance consistency of the overall structure and It is convenient for subsequent production lines.
  • conductive substances can be covered on the insulating layer by copper sinking, electroplating and other processes to fill up the removed part of the conductive layer, so that the surface of the conductive layer facing away from the substrate is even.
  • the first insulating layer 361 is covered and filled with a conductive substance so that the first conductive layer 341 is flush on the side away from the first surface 301
  • the second insulating layer 362 is covered and filled with a conductive substance so that the second conductive layer 342 is facing away from the first surface 301.
  • One side of the second surface 302 is flush.
  • FIG. 13 is a schematic structural diagram of a fourth embodiment of the embedded electronic component of the present application.
  • the difference between the fourth embodiment and the first to third embodiments lies in that: the connection mode between the conductive hole and the conductive layer is different.
  • the embedded electronic component 400 of this embodiment may include: a substrate 40 and an electronic component 42 , and the electronic component 42 is disposed in the substrate 40 .
  • the electronic component 42 is provided with a connecting terminal 421 extending laterally.
  • the substrate 40 has a first surface 401 and a second surface 402 opposite to each other, and a conductive hole 430 is disposed in the substrate 40 .
  • the connecting terminal 421 extends from the side of the electronic component 42 to the conductive hole 430 .
  • the conductive hole 430 may include a conduction end 4301 and a cut-off end 4302 oppositely disposed, and the conduction end 4301 and the cut-off end 4302 are respectively arranged corresponding to the first surface 401 and the second surface 402 . That is, one of the conduction end 4301 and the cut-off end 4302 is disposed corresponding to the first surface 401 , and the other is disposed corresponding to the second surface 402 .
  • the conduction end 4301 is used to realize the electrical connection of the conductive hole 430
  • the cut-off end 4302 is used to realize the insulation of the conductive hole 430 , so as to realize the single-end conduction of the conductive hole 430 .
  • the conduction end 4301 is connected to the first surface 401
  • the cut-off end 4302 is connected to the second surface 402 to realize single-end conduction of the conductive hole 430 .
  • a first conductive layer 44 is disposed on the surface of the substrate 40 , and the first conductive layer 44 may be disposed on the first surface 401 and/or the second surface 402 of the substrate.
  • the first conductive layer 44 covers the end of the conductive hole 430 and is electrically connected to the conductive hole 430 .
  • the first conductive layer 44 can be provided in two layers, one is provided on the first surface 401 , and the other is provided on the second surface 402 .
  • the first conductive layer 44 on the first surface 401 completely covers one end of the conductive hole 430
  • the first conductive layer 44 on the second surface 402 completely covers the other end of the conductive hole 430 .
  • the area of the first conductive layer 44 on the first surface 401 not covering the conductive hole 430 exposes the first surface 401
  • the area of the first conductive layer 44 on the second surface 402 not covering the conductive hole 430 exposes the second surface 402 .
  • the first conductive layer 44 opens a window to expose part of the surface of the substrate, and the unopened area of the first conductive layer 44 covers the end of the conductive hole 430 .
  • the side of the first conductive layer 44 facing away from the substrate 40 is provided with an insulating layer 46 , that is, the insulating layer 46 covers the side of the first conductive layer 44 facing away from the substrate 40 .
  • the orthographic projection of the insulating layer 46 projected on the surface of the substrate can completely cover the surface of the substrate, that is, the insulating layer 46 covers the first conductive layer 44 and the surface of the substrate 40 at the same time, and the side of the insulating layer 46 facing away from the substrate 40 is in contact with the surface of the substrate.
  • the surfaces of the substrate 40 are substantially parallel.
  • the insulating layer 46 defines a conductive blind hole 450 , and the conductive blind hole 450 is electrically connected to the first conductive layer 44 , so that the conductive blind hole 450 is electrically connected to the conductive hole 430 .
  • the inner sidewall of the conductive blind hole 450 is covered with a conductive material, so as to realize the electrical connection between the conductive blind hole 450 and the conductive layer.
  • metal layers such as a copper layer, a copper-nickel alloy layer, and a copper-nickel-gold alloy layer can be covered on the inner sidewall of the conductive blind hole 450 by electroplating.
  • the conductive blind hole 450 is filled with a conductive material, so as to realize the electrical connection between the conductive blind hole 450 and the conductive layer.
  • a conductive material such as copper columns and alloy columns may be formed in the conductive blind holes 450 .
  • the side of the insulating layer 46 facing away from the substrate 40 is provided with a second conductive layer 47 , that is, the second conductive layer 47 covers the side of the insulating layer 46 facing away from the substrate 40 .
  • the second conductive layer 47 is electrically connected to the conductive blind hole 450 , so that the second conductive layer 47 is electrically connected to the conductive hole 430 .
  • the conductive blind hole 450 is disposed corresponding to one end of the conductive hole 430 , so that the conductive hole 430 forms a single-ended connection. That is, the conduction blind hole 450 corresponds to the arrangement of the conduction end 4301 of the conduction hole 430 and is electrically connected to the conduction end 4301 .
  • the connection terminal 421 of the electronic component 42 is electrically connected to the second conductive layer 47 through the conductive hole 430 .
  • the electronic component 42 is provided with two connection terminals, that is, a first connection terminal 421a and a second connection terminal 421b.
  • the first conductive layer 44 may include a first conductive I layer 441 disposed on the first surface 401 and a first conductive II layer 442 disposed on the second surface 402 .
  • the conductive hole 430 may include a first conductive hole 431 and a second conductive hole 432 arranged at intervals. The two ends of are connected to the first conductive I layer 441 and the first conductive II layer 442 respectively.
  • the first conductive hole 431 may include a first conduction end 4311 and a first cut-off end 4312 oppositely arranged
  • the second conduction hole 432 may include a second conduction end 4321 and a second cut-off end 4322 oppositely arranged.
  • the first conducting end 4311 and the second conducting end 4321 can be electrically connected to the first conductive I-layer 441 on the first surface 401 respectively.
  • the first stop end 4312 and the second stop end 4322 can be electrically connected to the first conductive II layer 442 on the second surface 402 respectively.
  • the first conductive I layer 441 respectively covers the first conduction end 4311 and the second conduction end 4321 by opening a window, so as to avoid the direct connection between the first conduction end 4311 and the second conduction end 4321, thereby avoiding the first connection terminal 421a and the second connection terminal 421b are directly connected.
  • the first conductive II layer 442 covers the first cut-off end 4312 and the second cut-off end 4322 respectively by opening a window, so as to avoid the direct connection between the first cut-off end 4312 and the second cut-off end 4322, thereby avoiding the connection between the first connection terminal 421a and the second cut-off end.
  • the terminal 421b is directly connected.
  • the insulating layer 46 may include a first insulating layer 461 disposed on the first surface 401 and a second insulating layer 462 disposed on the second surface 402 .
  • the first insulating layer 461 covers the first conductive I layer 441 and the first surface 401 at the same time
  • the second insulating layer 462 covers the first conductive II layer 442 and the second surface 402 at the same time.
  • the first insulating layer 461 is provided with a conductive blind hole 450 .
  • the conductive blind hole 450 corresponds to the configuration of the conducting end 4301 of the conductive hole 430 and is electrically connected to the first conductive I layer 441 .
  • the conductive blind hole 450 may include a first conductive blind hole 451 disposed corresponding to the first conducting end 4311 and a second conductive blind hole 452 disposed corresponding to the second conducting end 4321 .
  • the first conductive blind hole 451 is electrically connected to the first conductive I layer 441 on the first conducting end 4311, and the second conductive blind hole 452 is electrically connected to the first conductive I layer 441 on the second conducting end 4321, The first conductive blind hole 451 is electrically connected to the first conducting end 4311 , and the second conductive blind hole 452 is electrically connected to the second conducting end 4321 .
  • the second conductive layer 47 may include a second conductive I layer 471 disposed on the first insulating layer 461 and a second conductive II layer 472 disposed on the second insulating layer 462 .
  • the first conductive blind hole 451 is electrically connected to the second conductive I layer 471
  • the second conductive blind hole 452 is electrically connected to the second conductive I layer 471, so that the first conduction terminal 4311 and the second conductive I layer 471 Electrically connected
  • the second conductive end 4321 is electrically connected to the second conductive I layer 471, so that the first connection terminal 421a of the electronic component 42 is connected to the second conductive I layer 471 through the first conductive hole 431, and the second connection
  • the terminal 421b is connected to the second conductive I-layer 471 through the second conductive hole 432, so as to realize conduction of electronic components on one side of the substrate, that is, the first surface.
  • a technical solution for the conduction of electronic components on the second surface of the substrate can also be derived,
  • FIG. 14 is another structural schematic view of the fourth embodiment of the embedded electronic component of the present application. Wherein, the difference between the embodiment in FIG. 14 and the embodiment in FIG. 13 lies in that the electronic components are conducted on both sides of the substrate.
  • the electronic component 42 is provided with two connection terminals, that is, a first connection terminal 421a and a second connection terminal 421b.
  • the first conductive layer 44 may include a first conductive I layer 441 disposed on the first surface 401 and a first conductive II layer 442 disposed on the second surface 402 .
  • the conductive hole 430 may include a first conductive hole 431 and a second conductive hole 432 arranged at intervals, the two ends of the first conductive hole 431 are connected to the first conductive I layer 441 and the first conductive II layer 442 respectively, The two ends are connected to the first conductive I layer 441 and the first conductive II layer 442 respectively.
  • the first conductive hole 431 may include a first conduction end 4311 and a first cut-off end 4312 oppositely arranged
  • the second conduction hole 432 may include a second conduction end 4321 and a second cut-off end 4322 oppositely arranged.
  • the first conduction end 4311 and the second cut-off end 4322 can be electrically connected to the first conductive I-layer 441 on the first surface 401 respectively.
  • the second conduction end 4321 and the first cut-off end 4312 can be electrically connected to the first conductive II layer 442 on the second surface 402 respectively.
  • the first conductive I layer 441 covers the first conduction end 4311 and the second cut-off end 4322 respectively by opening a window, so as to avoid direct connection between the first conduction end 4311 and the second cut-off end 4322, thereby avoiding the connection between the first connection terminal 421a and the second cut-off end 4322.
  • the second connection terminal 421b is directly connected.
  • the first conductive II layer 442 respectively covers the second conduction end 4321 and the first cut-off end 4312 by opening a window, so as to avoid the direct connection between the second conduction end 4321 and the first cut-off end 4312, thereby avoiding the connection between the first connection terminal 421a and the first cut-off end 4312.
  • the two connection terminals 421b are directly connected.
  • the insulating layer 46 may include a first insulating layer 461 disposed on the first surface 401 and a second insulating layer 462 disposed on the second surface 402 .
  • the first insulating layer 461 covers the first conductive I layer 441 and the first surface 401 at the same time
  • the second insulating layer 462 covers the first conductive II layer 442 and the second surface 402 at the same time.
  • the insulating layer 46 is provided with a conductive blind hole 450 .
  • the conductive blind hole 450 corresponds to the setting of the conducting end 4301 of the conductive hole 430 and is electrically connected to the first conductive layer 44 .
  • the conductive blind hole 450 may include a first conductive blind hole 451 disposed corresponding to the first conducting end 4311 and a second conductive blind hole 452 disposed corresponding to the second conducting end 4321 .
  • the first conductive blind hole 451 is electrically connected to the first conductive I layer 441 on the first conduction end 4311, and the second conductive blind hole 452 is electrically connected to the first conductive II layer 442 on the second conduction end 4321, The first conductive blind hole 451 is electrically connected to the first conducting end 4311 , and the second conductive blind hole 452 is electrically connected to the second conducting end 4321 .
  • the second conductive layer 47 may include a second conductive I layer 471 disposed on the first insulating layer 461 and a second conductive II layer 472 disposed on the second insulating layer 462 .
  • the first conductive blind hole 451 is electrically connected to the second conductive I layer 471
  • the second conductive blind hole 452 is electrically connected to the second conductive II layer 472, so that the first conduction terminal 4311 and the second conductive I layer 471 Electrically connected
  • the second conducting end 4321 is electrically connected to the second conductive II layer 472, so that the first connecting terminal 421a of the electronic component 42 is electrically connected to the first conductive hole 431 and the first conductive blind hole 451.
  • the second conductive I layer 471, the second connection terminal 421b is electrically connected to the second conductive II layer 472 through the second conductive hole 432 and the second conductive blind hole 452, so as to realize the electronic components on both sides of the substrate, that is, the first surface and the second conductive blind hole 452.
  • the second surface is simultaneously turned on.
  • the first connection terminal 421a of the electronic component 422 is connected to the second conductive II layer 472 through the first conductive hole 431
  • the second connection terminal 421b is connected to the second conductive I layer 471 through the second conductive hole 432 .
  • FIG. 15 is a schematic flowchart of a method for manufacturing an embedded electronic component in the fourth embodiment of the present application.
  • the manufacturing method can be used to manufacture the embedded electronic component in the fourth embodiment.
  • the preparation method generally includes the following steps:
  • FIG. 15a-FIG. 15f are schematic structural diagrams corresponding to the manufacturing method in the embodiment of FIG. 15 .
  • the substrate 40 has a first surface 401 and a second surface 402 disposed opposite to each other, and the electronic component 42 is provided with a connecting terminal 421 extending laterally.
  • the specific structural features of the substrate 40 and the electronic components 42 reference may be made to the specific descriptions in the foregoing embodiments, which will not be repeated here.
  • a conductive hole 430 penetrating through the substrate can be firstly drilled on the substrate, and then the inner wall of the conductive hole is covered with a conductive material or the conductive hole is covered by a process such as copper sinking and electroplating.
  • the holes are filled with conductive substances.
  • the metal layer 48 can be formed on the surface of the substrate simultaneously, and then the metal layer 48 can be patterned to obtain the required circuit.
  • the metal layer 48 can cover the first surface 401 and the second surface 402 respectively, and the two ends of the conductive hole 430 are respectively electrically connected to the metal layer 48 .
  • the metal layer 48 may be patterned by etching, photolithography and other processes to obtain the first conductive layer 44 .
  • the first conductive layer 44 may include a first conductive I layer 441 disposed on the first surface 401 and a first conductive II layer 442 disposed on the second surface 402, and the two ends of the conductive hole 430 are respectively connected to the first conductive layer 442.
  • the I layer 441 is electrically connected to the first conductive II layer 442 .
  • the first conductive layer 44 is disposed on the first surface 401 or the second surface 402 of the substrate 40 .
  • the first conductive layer 44 is disposed on the first surface 401 and the second surface 402 of the substrate 40 .
  • This embodiment takes the conduction of the electronic component 42 on both sides of the substrate 40 as an example, that is, the first conductive layer 44 includes a first conductive I layer 441 and a first conductive II layer 442, and the two ends of the conductive hole 430 are respectively connected to the first conductive layer 442.
  • the I layer 441 is electrically connected to the first conductive II layer 442 .
  • the conductive hole 430 may include a first conductive hole 431 and a second conductive hole 432 arranged at intervals, the first conductive hole 431 may include a first conducting end 4311 and a first cut-off end 4312 oppositely arranged, and the second conductive hole 432 may include oppositely disposed A second conduction end 4321 and a second cut-off end 4322 are provided.
  • the first conducting end 4311 and the second stopping end 4322 can be electrically connected to the first conductive I-layer 441 respectively.
  • the second conduction end 4321 and the first cut-off end 4312 can be electrically connected to the first conductive II layer 442 respectively.
  • the insulating layer 46 is disposed on the side of the first conductive layer 44 facing away from the substrate 40 , and the insulating layer 46 is provided with a conductive blind hole 450 electrically connected to the first conductive layer 44 .
  • the insulating layer 46 may include a first insulating layer 461 disposed on the first surface 401 and a second insulating layer 462 disposed on the second surface 402 .
  • the conductive blind holes 450 and the conductive holes 430 are arranged correspondingly, that is, each conductive blind hole 450 can be electrically connected to one end of the conductive hole 430 .
  • the insulating layer 46 may include a first insulating layer 461 disposed on the first surface 401 and a second insulating layer 462 disposed on the second surface 402 .
  • the first insulating layer 461 covers the first conductive I layer 441 and the first surface 401 at the same time
  • the second insulating layer 462 covers the first conductive II layer 442 and the second surface 402 at the same time.
  • the first insulating layer 461 defines a first conductive blind hole 451
  • the second insulating layer 462 defines a second conductive blind hole 452 .
  • the first conductive I layer 441 is located between the first conductive blind hole 451 and the first conductive hole 431
  • the first conductive II layer 442 is located between the second conductive blind hole 452 and the second conductive hole 432 .
  • the first conductive end 4311 of the first conductive hole 431 is electrically connected to the first conductive blind hole 451 through the first conductive I layer 441
  • the second conductive end 4321 of the second conductive hole 432 is electrically connected through the first conductive II layer 441.
  • the layer 442 is electrically connected to the second conductive via 452 .
  • the first conductive blind hole 451 and the second conductive blind hole 452 can be spaced apart from the first insulating layer 461 or the second insulating layer 462, and respectively It is electrically connected with the first conductive hole 431 and the second conductive hole 432 .
  • the insulating layer 46 that are not described in detail, reference may be made to the descriptions of the foregoing embodiments.
  • the specific implementation manners of opening the conductive blind hole 450 on the insulating layer 46 generally include the following two types: (1), firstly, opening the conductive blind hole on the insulating sheet, and then attaching the insulating sheet to the surface of the substrate and covering the first A conductive layer is used to form an insulating layer, and the above-mentioned conductive blind hole is arranged corresponding to the first conductive layer and is electrically connected. (2), first attach the insulating sheet to the surface of the substrate and cover the first conductive layer to form an insulating layer, and then open a conductive blind hole on the insulating layer corresponding to the area of the first conductive layer, so that the blind hole and the first conductive layer are connected. A conductive layer is electrically connected.
  • the second conductive layer 47 may include a second conductive I layer 471 disposed on the first insulating layer 461 and a second conductive II layer 472 disposed on the second insulating layer 462 .
  • the first conductive blind hole 451 is electrically connected to the second conductive I layer 471
  • the second conductive blind hole 452 is electrically connected to the second conductive II layer 472 .
  • the first conductive hole 431 is electrically connected to the second conductive I layer 471 through the first conductive blind hole 451
  • the second conductive hole 432 is electrically connected to the second conductive II layer 472 through the second conductive blind hole 452 .
  • first connection terminal 421a of the electronic component 42 is electrically connected to the second conductive I layer 471 through the first conductive hole 431
  • second connection terminal 421b is electrically connected to the second conductive II layer 472 through the second conductive hole 432, In order to realize the conduction of electronic components on both sides of the substrate.
  • the first conductive blind hole 451 is electrically connected to the second conductive I layer 471, and the second conductive blind hole 452 is electrically connected to the second conductive I layer 471. sexual connection.
  • the first conductive hole 431 is electrically connected to the second conductive I layer 471 through the first conductive blind hole 451
  • the second conductive hole 432 is electrically connected to the second conductive I layer 471 through the second conductive blind hole 452 .
  • the first conductive blind hole 451 is electrically connected to the second conductive II layer 472
  • the second conductive blind hole 452 is electrically connected to the second conductive II layer 472 .
  • the first conductive hole 431 is electrically connected to the second conductive II layer 472 through the first conductive blind hole 451
  • the second conductive hole 432 is electrically connected to the second conductive II layer 472 through the second conductive blind hole 452 .
  • FIG. 16 is a schematic structural diagram of a fifth embodiment of the embedded electronic component of the present application. Wherein, the difference between the fifth embodiment and the first to fourth embodiments lies in: the communication modes between the electronic components and the conductive layer are different.
  • the embedded electronic component 500 of this embodiment may include: a substrate 50 and an electronic component 52 , and the electronic component 52 is disposed in the substrate 50 .
  • the electronic component 52 is provided with a connecting terminal 521 extending laterally.
  • the substrate 50 has a first surface 501 and a second surface 502 opposite to each other, and a conductive blind hole 530 is disposed in the substrate 50 .
  • the connection terminal 521 extends from the side of the electronic component 52 to the conductive blind hole 530 .
  • the conductive blind hole 530 extends from the surface of the substrate 50 to the inside of the substrate 50 .
  • multiple conductive blind holes 530 may be provided, and the multiple conductive blind holes 530 may extend from the first surface 501 or the second surface 502 of the substrate 50 to the interior of the substrate 50 .
  • part of the conductive blind holes 530 in the plurality of conductive blind holes 530 extends from the first surface 501 of the substrate 50 to the inside of the substrate 50
  • another part of the conductive blind holes 530 in the plurality of conductive blind holes 530 extends from the second surface of the substrate 50 502 extends to the interior of the substrate 50 .
  • a plurality of conductive blind holes 530 and connection terminals 521 can be respectively provided, and the conductive blind holes 530 and the connection terminals 521 are arranged correspondingly, that is, each connection terminal 521 is arranged on the surface of the substrate 50 through a conductive blind hole 530 The conductive layer is electrically connected.
  • the inner wall of the conductive blind hole 530 is covered with a conductive substance, so as to realize the electrical connection between the conductive blind hole 530 and the conductive layer on the surface of the substrate.
  • a conductive substance such as a copper layer, a copper-nickel alloy layer, and a copper-nickel-gold alloy layer can be covered on the inner sidewall of the conductive blind hole 530 by electroplating.
  • the conductive blind hole 530 is filled with a conductive substance, so as to realize the electrical connection between the conductive blind hole 530 and the conductive layer on the surface of the substrate.
  • metal columnar structures such as copper pillars and alloy pillars or metal cone structures may be formed in the conductive blind holes 530 .
  • the conductive blind hole 530 communicates with the connection terminal 521 and is electrically connected with the connection terminal 521 .
  • the bottom wall of the conductive blind hole 530 abuts against the connecting terminal 521 , so that the bottom wall of the conductive blind hole 530 is electrically connected to the connecting terminal 521 .
  • one end of the conductive blind hole 530 extends to the inside of the connecting terminal 521 , so that the bottom wall and the sidewall of the conductive blind hole 530 are electrically connected to the connecting terminal 521 .
  • the conductive blind hole 530 may pass through the connection terminal 521 , and at this time, the sidewall of the conductive blind hole 530 is electrically connected to the connection terminal 521 .
  • connection terminal 521 of the electronic component 52 includes a first connection terminal 521a and a second connection terminal 521b.
  • the conductive blind vias 530 may include a first conductive blind via 531 and a second conductive blind via 532 .
  • the first conductive blind hole 531 is connected to the first connection terminal 521a
  • the second conductive blind hole 532 is connected to the second connection terminal 521b.
  • the first conductive blind holes 531 and the second conductive blind holes 532 are arranged at intervals on the first surface 501 of the substrate 50 , and both extend from the first surface 501 to the inside of the substrate 50 . Wherein, the axes of the first conductive blind hole 531 and the second conductive blind hole 532 are substantially parallel.
  • a conductive layer 54 is disposed on the first surface 501 of the substrate 50 .
  • the first conductive blind hole 531 and the second conductive blind hole 532 are respectively electrically connected to the conductive layer 54, the first connecting terminal 521a is electrically connected to the conductive layer 54 through the first conductive blind hole 531, and the second connecting terminal 521b is electrically connected to the conductive layer 54 through the second conductive
  • the conductive blind hole 532 is electrically connected to the conductive layer 54, so that the electronic components can be conducted on one side of the substrate.
  • the first conductive blind holes 531 and the second conductive blind holes 532 are arranged at intervals on the second surface 502 of the substrate 50 , and both extend from the second surface 502 to the inside of the substrate 50 .
  • the second surface 502 of the substrate 50 is provided with a conductive layer 54
  • the first connection terminal 521a is electrically connected to the conductive layer 54 through the first conductive blind hole 531
  • the second connection terminal 521b is connected to the conductive layer 54 through the second conductive blind hole 532. electrical connection.
  • FIG. 18 is another structural schematic diagram of the fifth embodiment of the embedded electronic component of the present application. Wherein, the difference between the embodiment shown in FIG. 18 and the embodiment shown in FIG. 16 lies in that the electronic components are conducted on both sides of the substrate.
  • connection terminals of the electronic component 52 include a first connection terminal 521a and a second connection terminal 521b.
  • the conductive layer includes a first conductive layer 541 arranged on the first surface 501 and a second conductive layer 542 arranged on the second surface 502, and the conductive blind hole 530 includes a first conductive blind hole connected to the first conductive layer 541.
  • the first connection terminal 521a is connected to the first conductive layer 541 through the first conductive blind hole 531
  • the second connection terminal 521b is connected to the second conductive layer 542 through the second conductive blind hole 532, so that the electronic components are on the first conductive layer 542 of the substrate.
  • the first surface and the second surface are conducted simultaneously.
  • first connection terminal 521a of the electronic component 52 can be connected to the second conductive layer 542 through the first conductive blind hole 531, and the second connection terminal 521b can be connected to the second conductive layer 542 through the second conductive blind hole.
  • the hole 532 is connected to the first conductive layer 541 .
  • FIG. 19 is a schematic flowchart of a method for manufacturing an embedded electronic component in the fifth embodiment of the present application.
  • the manufacturing method can be used to manufacture the embedded electronic component in the fifth embodiment.
  • the preparation method generally includes the following steps:
  • FIG. 19a-FIG. 19d are schematic structural diagrams corresponding to the manufacturing method in the embodiment of FIG. 19.
  • the substrate 50 has a first surface 501 and a second surface 502 disposed opposite to each other, and the electronic component 52 is provided with a connecting terminal 521 extending laterally.
  • the specific structural features of the substrate 50 and the electronic components 52 reference may be made to the specific descriptions in the foregoing embodiments, which will not be repeated here.
  • connection terminal 521 of the electronic component 52 is electrically connected to the conductive blind hole 530 .
  • connection terminals 521 and conductive blind holes 530 may be respectively provided, and each conductive blind hole 530 and each connection terminal 521 are respectively corresponding and electrically connected.
  • connection terminal 521 of the electronic component 52 includes a first connection terminal 521 a and a second connection terminal 521 b arranged at intervals.
  • the conductive blind holes 530 may include first conductive blind holes 531 and second conductive blind holes 532 arranged at intervals. The first conductive blind hole 531 is connected to the first connection terminal 521a, and the second conductive blind hole 532 is connected to the second connection terminal 521b.
  • first conductive blind hole 531 and the second conductive blind hole 532 extend from the surface of the substrate to the inside of the substrate. As shown in FIG. 19 b , both the first conductive blind hole 531 and the second conductive blind hole 532 extend from the first surface 501 of the substrate 50 to the interior of the substrate 50 . As shown in FIG. 19 c , the first conductive blind hole 531 extends from the first surface 501 of the substrate 50 to the interior of the substrate 50 , and the second conductive blind hole 532 extends from the second surface 502 of the substrate 50 to the interior of the substrate 50 .
  • the first conductive blind hole 531 is electrically connected to the first connection terminal 521a
  • the second conductive blind hole 532 is electrically connected to the second connection terminal 521b.
  • both the first conductive blind hole 531 and the second conductive blind hole 532 extend from the second surface 502 of the substrate 50 to the interior of the substrate 50 .
  • conductive blind holes may be formed on the surface of the substrate by drilling deep holes, so that the conductive blind holes are connected to the connection terminals of the electronic components.
  • first conductive blind hole 531 and a second conductive blind hole 532 deep holes are respectively drilled on the first surface 501 of the substrate 50 to form a first conductive blind hole 531 and a second conductive blind hole 532 .
  • first conductive blind hole 531 and the second conductive blind hole 532 can be formed synchronously; when the first connection terminal 521a and the second When the distance between the connecting terminal 521b and the first surface 501 is different, the first conductive blind hole 531 and the second conductive blind hole 532 can be separately formed.
  • first conductive blind holes 531 are drilled on the first surface 501 of the substrate 50 to form first conductive blind holes 531
  • second conductive blind holes 532 deep holes are drilled on the second surface 502 of the substrate 50 to form second conductive blind holes 532 .
  • first conductive blind hole 531 and the second conductive blind hole 532 can be synchronized molding; when the distance between the first connection terminal 521a and the first surface 501 is different from the distance between the second connection terminal 521b and the second surface 502, the first conductive blind hole 531 and the second conductive blind hole 532 can be respectively Individually molded.
  • the first conductive blind hole 531 extends from the first surface 501 of the substrate 50 to the interior of the substrate 50
  • the second conductive blind hole 532 extends from the second surface 502 of the substrate 50 to the interior of the substrate 50 as an example.
  • the conductive layer may include a first conductive layer 541 disposed on the first surface 501 and a second conductive layer 542 disposed on the second surface 502, the first conductive layer 541 is electrically connected to the first conductive blind hole 531, and the second The conductive layer 542 is electrically connected to the second conductive blind hole 532 .
  • the first connection terminal 521a is connected to the first conductive layer 541 through the first conductive blind hole 531
  • the second connection terminal 521b is connected to the second conductive layer 542 through the second conductive blind hole 532, so that the electronic components are on the first conductive layer 542 of the substrate.
  • the first surface and the second surface are conducted simultaneously.
  • the conductive layer can be formed on one surface of the substrate.
  • the conductive layer 54 is disposed on the first surface 501 .
  • the inner sidewall of the conductive blind hole may be covered with conductive material or filled with conductive material through processes such as copper sinking and electroplating.
  • a conductive layer is simultaneously formed on the surface of the substrate, so that the conductive blind hole is electrically connected to the conductive layer.
  • the manufacturing method of the embedded electronic component provided by the embodiment of the present application is to open a conductive blind hole on the surface of the substrate to connect to the connecting terminal of the electronic component, so that the electronic component can be connected to the conductive layer on the surface of the substrate through the conductive blind hole, the process flow Simple and conducive to improving production efficiency.

Abstract

本申请公开了一种埋入式电子元件及其制作方法、电压调节模块，所述埋入式电子元件包括基板和电子元件；所述基板内设有容置槽和导电孔，所述基板表面设有导电层，所述电子元件设于所述容置槽内，所述电子元件设有侧向延伸至所述导电孔的第一连接端子和第二连接端子；其中，所述第一连接端子和所述第二连接端子通过所述导电孔与所述导电层电性连接。本申请实施例提供的埋入式电子元件，通过在电子元件的侧向设置连接端子，并通过导电孔将连接端子和基板表面的导电层电性连接，可在电子元件封装过程中降低埋入式电子元件的整体厚度。

Description

埋入式电子元件及其制作方法、电压调节模块 技术领域
本申请涉及电子元件埋入的技术领域，具体是涉及一种埋入式电子元件及其制作方法、电压调节模块。
背景技术
随着电子产品朝轻薄短小方向不断发展，产品上电源模块密度越来越高，体型也越来越小。在表面贴装电子元件中，电子元件占用电路板的表面积较大，不利于实现高密度小型化。如果能将电子元件埋入到电路板内部，可以节约板面空间增强布线布件的能力，实现高密度小型化。
发明内容
本申请实施例提供了一种埋入式电子元件，其中，所述埋入式电子元件包括基板和电子元件；所述基板内设有容置槽和导电孔，所述基板表面设有导电层，所述电子元件设于所述容置槽内，所述电子元件设有侧向延伸至所述导电孔的第一连接端子和第二连接端子；其中，所述第一连接端子和所述第二连接端子通过所述导电孔与所述导电层电性连接。
另一方面，本申请实施例还提供了一种埋入式电子元件的制作方法，其中，所述制作方法包括：提供一基板以及电子元件，并将所述电子元件设于所述基板内；在所述基板上开设导电孔，并将所述导电孔进行导电化处理；在所述基板表面形成导电层，所述导电层和所述导电孔电性连接；其中，所述电子元件设有侧向延伸至所述导电孔的第一连接端子和第二连接端子，所述第一连接端子和所述第二连接端子通过所述导电孔与所述导电层电性连接。
又一方面，本申请实施例还提供了一种电压调节模块，其中，所述电压调节模块包括MOS管以及埋入式电子元件，所述埋入式电子元件包括基板和电子元件；所述基板内设有容置槽和导电孔，所述基板表面设有导电层；所述电子元件设于所述容置槽内，所述电子元件设有侧向延伸至所述导电孔的第一连接端子和第二连接端子；其中，所述第一连接端子和所述第二连接端子通过所述导电孔与所述导电层电性连接；所述MOS管堆叠于所述基板上。
本申请实施例提供的埋入式电子元件及其制作方法、电压调节模块，通过在电子元件的侧向设置连接端子，并通过导电孔将连接端子和基板表面的导电层电性连接，可在电子元件封装过程中降低埋入式电子元件的整体厚度。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请埋入式电子元件的第一实施例的结构示意图；
图2是图1实施例中埋入式电子元件的又一结构示意图；
图3是图1实施例中埋入式电子元件的应用时的结构示意图；
图4是图3实施例中埋入式电子元件应用时的布局效果示意图；
图5是一般技术中电子元件应用时的布局效果示意图；
图6是本申请埋入式电子元件的第二实施例的结构示意图；
图7是本申请埋入式电子元件的第二实施例的又一结构示意图；
图8是第二实施例中埋入式电子元件的制作方法的流程示意图；
图8a-图8c是图8实施例中制作方法对应的结构示意图；
图9是第二实施例中埋入式电子元件又一制作方法的流程示意图；
图9a是图9实施例中制作方法对应的结构示意图；
图10是本申请埋入式电子元件的第三实施例的结构示意图；
图11是本申请埋入式电子元件的第三实施例的又一结构示意图；
图12是第三实施例中埋入式电子元件的制作方法的流程示意图；
图12a-图12h是图12实施例中制作方法对应的结构示意图；
图13是本申请埋入式电子元件的第四实施例的结构示意图；
图14是本申请埋入式电子元件的第四实施例的又一结构示意图；
图15是第四实施例中埋入式电子元件的制作方法的流程示意图；
图15a-图15f是图15实施例中制作方法对应的结构示意图；
图16是本申请埋入式电子元件的第五实施例的结构示意图；
图17是图16实施例中埋入式电子元件的又一结构示意图；
图18是本申请埋入式电子元件的第五实施例的又一结构示意图；
图19是第五实施例中埋入式电子元件的制作方法的流程示意图；
图19a-图19d是图19实施例中制作方法对应的结构示意图。
具体实施方式
下面结合附图和实施例，对本申请作进一步的详细描述。特别指出的是，以下实施例仅用于说明本申请，但不对本申请的范围进行限定。同样的，以下实施例仅为本申请的部分实施例而非全部实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
本申请实施例一方面提供了一种埋入式电子元件，其中，所述埋入式电子元件包括基板和电子元件；所述基板内设有容置槽和导电孔，所述基板表面设有导电层；所述电子元件设于所述容置槽内，所述电子元件设有侧向延伸至所述导电孔的第一连接端子和第二连接端子；其中，所述第一连接端子和所述第二连接端子通过所述导电孔与所述导电层电性连接。
其中，所述基板表面包括相背的第一表面以及第二表面，所述导电层设置在所述第一表面和/或者第二表面。
其中，所述导电孔包括相对的导通端和截止端，所述导通端相接于所述第一表面和第二表面中的一者，所述截止端临近于所述第一表面和第二表面中的另一者，所述截止端和临近所述截止端的所述基板表面之间设置有绝缘槽。
其中，所述绝缘槽的底壁与所述导电孔截止端相接，且所述绝缘槽孔径大于所述导电孔的截止端。
其中，所述绝缘槽内填充有绝缘材料。
其中，所述基板表面包括相背的第一表面和第二表面，所述导电层包括设于所述第一表面上的第一导电层和设于所述第二表面上的第二导电层，所述导电孔包括连通至所述第一导电层的第一导电孔和连通至所述第二导电层的第二导电孔；所述第一连接端子通过所述第一导电孔连接至所述第一导电层，所述第二连接端子通过所述第二导电孔连接至所述第二导电层。
其中，所述第一导电孔穿设于所述第一连接端子，所述第二导电孔穿设于所述第二连接端子。
其中，所述导电孔的内侧壁覆盖有导电物质，或者所述导电孔内填充有导电物质，以实现所述导电孔和所述导电层的电连接。
其中，所述基板为绝缘基板，所述电子元件为无源电子元件。
其中，所述埋入式电子元件还包括绝缘层，所述绝缘层设于所述基板表面且覆盖于所述导电孔的一端，所述导电孔的另一端和所述导电层电性连接。
其中，所述基板表面设有焊盘，所述焊盘和所述导电孔的一端相接，所述绝缘层完全覆盖于所述焊盘。
其中，所述埋入式电子元件还包括绝缘层，所述导电层包括第一导电层和第二导电层；所述第一导电层设于所述基板表面，且覆盖于所述导电孔的端部；所述绝缘层覆盖于所述第一导电层背离所述基板的一侧，所述绝缘层开设有导电盲孔，所述导电盲孔和所述第一导电层电性连接；所述第二导电层覆盖于所述绝缘层背离所述基板的一侧，所述第二导电层和所述导电盲孔电性连接。
其中，所述导电盲孔对应于所述导电孔的一端设置，并与所述导电孔电性连接，所述第一连接端子和所述第二连接端子通过所述导电孔和所述第二导电层电性连接。
其中，所述基板表面包括相背的第一表面以及第二表面，所述第一导电层包括设于所述第一表面上的第一导电I层和设于所述第二表面上的第一导电II层；绝缘层包括设于所述第一表面上的第一绝缘层和设于所述第二表面上的第二绝缘层；所述第一绝缘层覆盖于所述第一导电I层，所述第二绝缘层覆盖于所述第一导电II层。
其中，所述导电盲孔包括第一导电盲孔和第二导电盲孔，所述第一导电盲孔设于所述第一绝缘层并与所述第一导电I层电性连接，所述第二导电盲孔设于所述第二绝缘层并与所述第一导电II层电性连接；所述第二导电层包括设于所述第一绝缘层上的第二导电I层和设于所述第二绝缘层上的第二导电II层；所述第一导电盲孔和所述第二导电I层电性连接，所述第二导电盲孔和所述第二导电II层电性连接。
其中，所述导电孔包括间隔设置的第一导电孔和第二导电孔，所述第一导电孔的导通端通过所述第一导电I层和所述第一导电盲孔电性连接，所述第二导电孔的导通端通过所述第一导电II层和所述第二导电盲孔电性连接；所述第一连接端子通过所述第一导电孔和所述第一导电盲孔电性连接至所述第二导电I层，所述第二连接端子通过所述第二导电孔和所述第二导电盲孔电性连接至所述第二导电II层。
其中，所述导电孔包括第一导电盲孔和第二导电盲孔，所述第一连接端子通过所述第一导电盲孔和所述导电层电性连接，所述第二连接端子通过所述第二导电盲孔和所述导电层电性连接。
本申请实施例另一方面还提供了一种埋入式电子元件的制作方法，其中，所述制作方法包括：提供一基板以及电子元件，并将所述电子元件设于所述基板内；在所述基板上开设导电孔，并将所述导电孔进行导电化处理；在所述基板表面形成导电层，所述导电层和所述导电孔电性连接；其中，所述电子元件设有侧向延伸至所述导电孔的第一连接端子和第二连接端子，所述第一连接端子和所述第二连接端子通过所述导电孔与所述导电层电性连接。
其中，所述在所述基板上开设导电孔的步骤进一步包括：对所述导电孔的一端进行处理以形成绝缘槽；其中，所述导电孔包括相对的导通端和截止端，所述导通端和所述基板的一表面相接，所述截止端临近于所述基板的另一表面设置；所述绝缘槽位于所述截止端和临近所述截止端的所述基板表面之间。
本申请实施例又一方面还提供了一种电压调节模块，其中，所述电压调节模块包括MOS管和埋入式电子元件，所述埋入式电子元件包括基板和电子元件；所述基板内设有容置槽和导电孔，所述基板表面设有导电层；所述电子元件设于所述容置槽内，所述电子元件设有侧向延伸至所述导电孔的第一连接端子和第二连接端子；其中，所述第一连接端子和所述第二连接端子通过所述导电孔与所述导电层电性连接；所述MOS管堆叠于所述基板上
请参阅图1，图1是本申请埋入式电子元件的第一实施例的结构示意图，该电子元件可为无源电子元件，例如可为电感元件、电容元件、电阻元件等。本申请实施例中的电子元件以电感元件为例进行示例性说明。本实施例的 埋入式电子元件100可以包括：基板10和电子元件12。基板10内设有至少一个容置槽111，电子元件12设有至少一个，每个容置槽111内设置有至少一个电子元件12。其中，本申请实施例中所有方向性指示(诸如上、下、左、右、前、后……)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
其中，基板10采用绝缘材质，本实施例的基板10可采用同一种绝缘材质。具体而言，基板10包括一体成型的框架110和填充层120。
框架110设有容置槽111。框架110的高度可大于或等于放置于容置槽111中的电子元件12的高度，使得在填充或压合填充层120时，框架110可起到支撑的作用，以避免电子元件12受力太大而损坏。另外，框架110的容置槽111还起到一个定位电子元件12的放置位置的作用。
填充层120填充于容置槽111以覆盖和/或包裹电子元件12。其中，填充层120的材料可采用热塑性树脂，如聚丙烯(PP)，用于对电子元件12进行封装；框架110材料可采用热固性树脂，如环氧树脂，框架110设置于电子元件12周围，环氧树脂固化后成型，再受热也不会软化，溶解，用于形成保护框架110，以避免封装过程对电子元件12造成损伤。
在本申请实施例中，基板10具有相背的第一表面101和第二表面102，第一表面101和第二表面102为沿基板10厚度方向(如图1所示的Z方向)上相背设置的两个表面。即基板10表面可包括上述的第一表面101和第二表面102。填充层120覆盖于框架110靠近第一表面101的一侧。电子元件12设于容置槽111内，且该电子元件12设有侧向延伸的连接端子121，即连接端子121的延伸方向和Z方向相交。具体而言，电子元件12具有相背设置的顶面122、底面124以及连接顶面122和底面124的侧面126，连接端子121设于侧面126上。
其中，顶面122和底面124沿基板10厚度方向(如图1所示的Z方向)上相背设置。顶面122靠近于第一表面101设置，底面124靠近于第二表面102设置，侧面126位于顶面122和底面124之间。可以理解的，电子元件12的顶面122和底面124大体平行，且二者所在平面和基板10的第一表面101、第二表面102所在的平面大体上平行。电子元件12的侧向延伸方向即可认为是大体上平行于电子元件12的顶面122或者底面124所在平面的方向。
进一步地，基板10内设有导电孔130，该导电孔130的轴线延伸方向与基板10的第一表面101和第二表面102均相交。换言之，导电孔130的轴线延伸方向和基板10的厚度方向大体相同，或者导电孔130的轴线延伸方向和图1所示的Z方向大体相同，即导电孔130的端面和第一表面101或者第二表面102大体平行设置。优选地，第一表面101和第二表面102平行设置，导电孔130的两端面均和第一表面101平行。
其中，连接端子121自电子元件12的侧面延伸至导电孔130，即连接端子121的侧向延伸方向大致为基板10的第一表面101或第二表面102所在平面的延伸方向。导电孔130连通至连接端子121或者导电孔130穿设于连接端子121，以使得连接端子121和导电孔130电性连接。
在本申请实施例中，基板10的表面设有导电层14。其中，导电层14可以设在基板10的第一表面101或者第二表面102。此时，导电孔130连通至导电层14并与导电层14电性连接，连接端子121通过导电孔130和导电层14电性连接，即电子元件12可在基板10的单面实现导通。如图1所示，导电层14设于基板10的第一表面101。即导电孔130和连接端子121可分别设有多个，且导电孔130和连接端子121对应设置，每一连接端子121通过一个导电孔130和设于第一表面101上的导电层14电性连接。当然，导电层14也可设于基板10的第二表面102。每一连接端子121通过一个导电孔130和设于第二表面102上的导电层14电性连接，以此可使电子元件12在基板10的单面实现导通。
当然，在其他实施方式中，导电层14可以分别设在基板10的第一表面101和第二表面102上。请参阅图2，图2是图1实施例中埋入式电子元件的又一结构示意图。其中，导电层14可包括第一导电层141和第二导电层142。第一导电层141设于第一表面101上，第二导电层142设于第二表面102上。需要说明的是，本申请中的术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”、“第三”的特征可以明示或者隐含地包括至少一个该特征。
导电孔130可包括第一导电孔131和第二导电孔132，连接端子121可包括第一连接端子121a和第二连接端子121b。其中，第一导电孔131连通至第一导电层141，第二导电孔132连通至第二导电层142。第一连接端子121a通过第一导电孔131连接至第一导电层141，第二连接端子121b通过第二导电孔132连接至第二导电层142。此时，电子元件12可以在基板10的第一表面101和第二表面102即双面实现导通。
本申请实施例提供的埋入式电子元件，通过在电子元件的侧面设置连接端子，并通过导电孔连通至基板表面的导电层，从而实现电子元件在基板的单面或者双面导通。同时，相较于连接端子设置电子元件的顶面或者侧面的技术方案，本申请实施例将连接端子设于电子元件的侧面，在电子元件封装时可降低整体结构厚度，且在电子元件埋入基板内的过程中，相较于电子元件贴装过程的环境要求相对较低。另外，相较于电子元件贴装于基板表面的技术方案，本申请实施例中电子元件埋入基板内部，可以增加基板表面其他元器件或者芯片等器件的贴装面积。
可以理解的，电子元件12可以具有多个连接端子121，本申请上述实施例中示例出了电子元件12具有两个连接端子121的实施例。与此相应的，导电孔130设有两个，且和两个连接端子121分别对应设置，即每一导电孔130穿设于每一连接端子121。当然，在其他实施例中，电子元件12可以具有三个连接端子，例如三脚结构的电感元件，其具有三个引脚。此时，导电孔130可以设有三个，且和三个连接端子分别对应设置，即每一连接端子121和每一导电孔130分别电性连接。其中，多个连接端子121中的部分连接端子可以通过导电孔130连接至设于第一表面101或者第二表面102上的导电层，多个连接端子121中的另一部分连接端子可以通过导电孔130连接至设于第一表面101或者第二表面102上的导电层，以此实现电子元件在基板的单面或者双面导通。
其中，在一些实施方式中，导电孔130内侧壁覆盖有导电物质，以实现导电孔130和基板表面的导电层的电连接。例如，可以通过电镀的方式在导电孔130的内侧壁覆盖铜层、铜镍合金层、铜镍金合金层等金属层。当然，在 其他一些实施方式中，导电孔130内填充有导电物质，以实现导电孔130和基板表面的导电层的电连接。例如，可以在导电孔130内形成铜柱、合金柱等金属柱状结构。
进一步地，本申请实施例提供的埋入式电子元件在一些应用场景中对提高电路板板面有效贴装面积具有较大的贡献。请参阅图3-图5，图3是图1实施例中埋入式电子元件的应用时的结构示意图，图4是图3实施例中埋入式电子元件应用时的布局效果示意图，图5是一般技术中电子元件应用时的布局效果示意图。
其中，以埋入式电子元件用于电压调节模块为例，电压调节模块一般用于为CPU提供稳定的工作电压。电压调节模块1000大致包括埋入式电子元件100以及MOS管800(Metal-Oxide-Semiconductor Field-Effect Transistor，金氧半场效晶体管)。如图5所示，在一般技术方案中，通常将MOS管800以及埋入式电子元件100中的基板10和电子元件12等平铺在PCB母板900上，并通过电性连接导通以为CPU供电，而通常一个CPU需要大致10个电压调节模块1000来为其提供稳定的供电电压。基于此，上述平铺方案将占用较大的贴装面积，不利于小型化布局。
本申请实施例将电子元件12埋入基板10内，并在基板10上堆叠MOS管800，以形成电压调节模块1000，然后将该电压调节模块1000设于PCB母板900上，以此来为CPU提供稳定的供电电压。结合图4和图5可以很明显看出，通过埋入式电子元件堆叠形成的电压调节模块在PCB母板上占用的贴装面积大幅下降，为小型化布局具有很好的促进效果。当然，在一些其他应用场景中，也可以在埋入式电子元件上堆叠IC、电容、电感等器件，以减小电路板板面的贴装面积。
请参阅图6，图6是本申请埋入式电子元件的第二实施例的结构示意图。其中，第二实施例和第一实施例的区别在于：导电孔和导电层之间的连通方式不同。
本实施例的埋入式电子元件200可以包括：基板20和电子元件22，电子元件22设于基板20内。其中，电子元件22设有侧向延伸的连接端子221。基板20具有相背的第一表面201和第二表面202，基板20内设有导电孔230。连接端子221自电子元件22的侧面延伸至导电孔230。关于基板20和电子元件22的具体结构可参考前述实施例。
导电孔230可包括相对设置的导通端2301和截止端2302，导通端2301和截止端2302分别与第一表面201和第二表面202对应设置。即导通端2301和截止端2302中的一者对应于第一表面201设置，另一者对应于第二表面202设置。其中，导通端2301用于实现导电孔230和基板表面的导电层之间的电性连接，截止端2302用于实现导电孔230和基板表面的导电层之间的绝缘。例如，导通端2301和第一表面201对应设置即相接设置，导通端2301和第一表面201上的导电层电性连接。截止端2302和第二表面202对应设置即邻近设置，截止端2302和第二表面202上的导电层绝缘，以实现导电孔230的单端导通。进一步地，截止端2302和临近该截止端2302的基板20表面之间设置有绝缘槽250，该绝缘槽250的底壁和导电孔230的截止端2302相接，且绝缘槽250的孔径大于截止端2302的孔径。
具体而言，绝缘槽250内填充有绝缘材料，以隔离开导电孔230的截止端2302和基板表面的导电层，使得导电孔230的一端可以导通，另一端截止导通，使得电子元件22的连接端子221通过导电孔230连接至导电层并在导电孔230的一端实现电性连接。
在本申请实施例中，以电子元件22设有两个连接端子即第一连接端子221a和第二连接端子221b为例。其中，导电层包括设于第一表面201上的第一导电层241和设于第二表面202上的第二导电层242，导电孔230包括连通至第一导电层241的第一导电孔231和连通至第一导电层241的第二导电孔232。其中，第一连接端子221a通过第一导电孔231连接至第一导电层241，第二连接端子221b通过第二导电孔232连接至第一导电层241。
其中，第一导电孔231可包括相对设置的第一导通端2311和第一截止端2312，第二导电孔232可包括相对设置的第二导通端2321和第二截止端2322。具体而言，第一导通端2311和第二导通端2321可分别与第一表面201上的导电层即第一导电层241电连接。第一截止端2312和第二表面202之间设置有第一绝缘槽251，第二截止端2322和第二表面202之间设置有第二绝缘槽252。
本实施例通过在导电孔230的截止端2302和第二表面202的第二导电层242之间设置绝缘槽250，使得第一导电孔231和第二导电孔232分别与第一表面201的第一导电层241电性连接，进而使得电子元件22的第一连接端子221a通过第一导电孔231连接至第一导电层241，第二连接端子221b通过第二导电孔232连接至第一导电层241，以此实现电子元件在基板的单面即第一表面导通。同理也可以得出电子元件在基板的第二表面实现导通的技术方案，本申请实施例不再赘述。
请参阅图7，图7是本申请埋入式电子元件的第二实施例的又一结构示意图。其中，图7实施例和图6实施例的区别在于：电子元件在基板的双面实现导通。
在本实施例中，电子元件22设有两个连接端子即第一连接端子221a和第二连接端子221b。其中，导电层24包括设于第一表面201上的第一导电层241和设于第二表面202上的第二导电层242，导电孔230包括连通至第二导电层242的第一导电孔231和连通至第一导电层241的第二导电孔232。其中，第一连接端子221a通过第一导电孔231连接至第二导电层242，第二连接端子221b通过第二导电孔232连接至第一导电层241。
其中，第一导电孔231可包括相对设置的第一导通端2311和第一截止端2312，第二导电孔232可包括相对设置的第二导通端2321和第二截止端2322。具体而言，第一导通端2311和第二表面202上的导电层即第二导电层242电连接，第二导通端2321和第一表面201上的导电层即第一导电层241电连接。第一截止端2312和第一表面201之间设置有第一绝缘槽251，第二截止端2322和第二表面202之间设置有第二绝缘槽252。
本实施例通过在第一导电孔231的截止端和第一表面201的第一导电层之间设置第一绝缘槽251，以及在第二导电孔232的截止端和第二表面202的第二导电层之间设置第二绝缘槽252，使得第一导电孔231和第二表面202的第二导电层242电性连接，第二导电孔232和第一表面201的第一导电层241电性连接。进而使得电子元件22 的第一连接端子221a通过第一导电孔231连接至第二导电层242，第二连接端子221b通过第二导电孔232连接至第一导电层241，以此实现电子元件在基板的双面即第一表面和第二表面同时导通。同理，可以得出电子元件22的第一连接端子221a可通过第一导电孔231连接至第一导电层241，第二连接端子221b通过第二导电孔232连接至第二导电层242。
请参阅图8，图8是本申请第二实施例中埋入式电子元件的制作方法的流程示意图，该制作方法能够被用于制作第二实施例中的埋入式电子元件。其中，该制作方法大致包括如下步骤：
S801、提供一基板以及电子元件，并将电子元件设于基板内。请参阅图8a-图8c，图8a-图8c是图8实施例中制作方法对应的结构示意图。其中，基板20具有相背设置的第一表面201和第二表面202，电子元件22设有侧向延伸的连接端子221。关于基板20以及电子元件22的具体结构特征可参考前述实施例的具体描述，此处不再赘述。
例如，将电子元件埋入到基板中的具体过程可以为：首先将电子元件放置在框架的容置槽中，然后对容置槽和框架填充绝缘材料，并对绝缘材料进行压合以形成与框架一体成型的填充层。
S802、在基板上开设导电孔，并将导电孔进行导电化处理。其中，电子元件22的连接端子221侧向延伸至导电孔230，导电孔230穿设于电子元件22的连接端子221，以使得电子元件22的连接端子221和导电孔230电性连接。可以理解的，连接端子221和导电孔230可分别设有多个，且每一导电孔230和每一连接端子221分别对应设置，具体可参阅前述实施例的具体描述。
进一步地，可以通过电镀工艺将导电孔进行导电化处理。即可通过沉铜、电镀等工艺在导电孔的内侧壁覆盖一层导电物质，以实现导电孔和连接端子的电连接。或者可通过沉铜、电镀等工艺在导电孔内填充导电物质，即可以在导电孔内形成金属柱状结构，以实现导电孔和连接端子的电连接。
可以理解的，在实际生产工艺中，基板上开设的导电孔一般贯穿于基板的第一表面和第二表面，即可以通过钻孔的方式在基板上形成通孔，然后通过沉铜、电镀等工艺在通孔的基础上形成导电孔。
S803、在基板表面形成导电层，且该导电层和导电孔电性连接，以使得连接端子通过导电孔和导电层电性连接。
具体而言，可以通过沉铜、电镀等工艺在基板的第一表面201和/或第二表面202形成导电层24。如图8c所示，通过沉铜、电镀等工艺在基板的第一表面201形成导电层24。可以理解的，在图2所示的实施例中，可以通过沉铜、电镀等工艺在基板的第一表面201和第二表面202分别形成第一导电层241和第二导电层242。关于导电层24未尽详述的具体结构特征可以参考前述实施例中的具体描述。
在本申请部分实施方式中，即在实际生产工艺中，可首先通过钻孔的方式在基板上开设贯穿于基板的导电孔，然后通过沉铜、电镀等工艺在导电孔的内侧壁覆盖导电物质或者在导电孔内填充导电物质。与此同时，可以同步在基板表面形成导电层，然后对导电层进行图形化处理以得到所需的线路。换言之，导电孔内的导电物质和基板表面的导电层可以通过相同的工艺一次同步形成，可以提升生产效率。
本实施例提供的埋入式电子元件的制作方法，通过将电子元件埋入基板内，并在基板开设和电子元件侧向延伸的连接端子电性连接的导电孔，以及在基板表面设置导电层使得该导电层和导电孔电性连接，从而使得电子元件的连接端子可以通过导电孔连接至导电层，进而实现电子元件在基板的单面或者双面导通。本实施例提供的制作方法在电子元件封装时可降低整体结构厚度，且可以增加基板表面其他元器件或者芯片等器件的贴装面积。
可以理解的，每一个连接端子一般从基板的一个表面引出导通，这就使得导电孔需要实现单端导通。基于此，本申请实施例在步骤S803之前需要对导电孔进行进一步处理，以使得导电孔能够实现单端导通。
具体而言，请参阅图9，图9是本申请第二实施例中埋入式电子元件的又一制作方法的流程示意图，该制作方法能够被用于制作第二实施例中的埋入式电子元件。其中，该制作方法大致包括如下步骤：
S901、提供一基板以及电子元件，并将电子元件设于基板内。该步骤可参考前述实施例中的步骤S801，故此不再赘述。
S902、在基板上开设导电孔，并对导电孔的一端进行处理以形成绝缘槽。请参阅图9a，图9a是图9实施例中制作方法对应的结构示意图。其中，导电孔230可包括相对设置的导通端2301和截止端2302，导通端2301相接于基板20的一表面，截止端2302临近于基板20的另一表面设置，绝缘槽250位于截止端2302和临近该截止端2302的基板20表面之间。例如，导通端2301和第一表面201相接，截止端2302临近于第二表面202设置，绝缘槽250位于截止端2302和第二表面202之间。可以理解的，在实际生产工艺中，基板20上开设贯穿于基板20的第一表面201和第二表面202的通孔，然后通过沉铜、电镀等工艺在通孔的基础上形成导电孔230。进一步通过背钻的方式在导电孔230的一端形成截止端2302以及绝缘槽250。
进一步地，绝缘槽250的底壁和导电孔230的截止端2302相接，且绝缘槽250的孔径大于截止端2302的孔径。绝缘槽250内填充有绝缘材料，以隔离开导电孔230的截止端2302和基板表面的导电层24，使得导电孔230的一端可以导通，另一端截止导通，进而将电子元件22的连接端子221电性导出并在导电孔230的一端实现电连接。关于绝缘槽以及导电孔未尽详述的结构特征可参考前述实施例中的具体描述。
S903、将导电孔进行导电化处理，并在基板表面形成导电层。其中，导电层和导电孔电性连接，以使得连接端子通过导电孔和导电层电性连接。该步骤可参考前述实施例中的具体描述，故此不再赘述。
在本申请部分实施例中，即在实际生产工艺中，可首先通过钻孔方式在基板上开设贯穿于基板的导电孔，然后通过背钻对导电孔的一端进行处理以形成绝缘槽并在绝缘槽内填充绝缘材料；接下来通过沉铜、电镀等工艺在导电孔的内侧壁覆盖导电物质或者在导电孔内填充导电物质。与此同时，可以同步在基板表面形成导电层，然后对导电层进行图形化处理以得到所需的线路。换言之，导电孔内的导电物质和基板表面的导电层可以通过相同的工艺一次同步形成，可以提升生产效率。
当然，在本申请另一些实施例中，可首先通过钻孔方式在基板上开设贯穿于基板的导电孔，然后通过沉铜、电镀等工艺在导电孔的内侧壁覆盖导电物质或者在导电孔内填充导电物质，并同步在基板表面形成导电层。接下来通 过背钻对导电孔的一端进行处理以形成绝缘槽并在绝缘槽内填充绝缘材料；然后对导电层进行图形化处理以得到所需的线路。
本申请实施例提供的制作方法，通过在导电孔的一端和基板表面之间设置绝缘槽，以实现导电孔的单端导通，进而可以通过导电孔将电子元件的连接端子电性连接至基板的第一表面或第二表面上的导电层。
请参阅图10，图10是本申请埋入式电子元件的第三实施例的结构示意图。其中，第三实施例和第一、二实施例的区别在于：导电孔和导电层之间的连通方式不同。
本实施例的埋入式电子元件300可以包括：基板30和电子元件32，电子元件32设于基板30内。其中，电子元件32设有侧向延伸的连接端子321。基板30具有相背的第一表面301和第二表面302，基板30内设有导电孔330。连接端子321自电子元件32的侧面延伸至导电孔330。关于基板30和电子元件32的具体结构可参考前述实施例。
导电孔330可包括相对设置的导通端3301和截止端3302，导通端3301和截止端3302分别与第一表面301和第二表面302对应设置。即导通端3301和截止端3302中的一者对应于第一表面301设置，另一者对应于第二表面302设置。其中，导通端3301用于实现导电孔330和基板表面的导电层之间的电性连接，截止端3302用于实现导电孔330和基板表面的导电层之间的绝缘。例如，导通端3301相接于第一表面301，导通端3301和第一表面301上的导电层电性连接。截止端3302相接于第二表面302，截止端3302和第二表面302上的导电层绝缘设置，以实现导电孔330的单端导通。
进一步地，基板30表面设有绝缘层360，该绝缘层360完全覆盖于导电孔330的截止端3302。本实施例通过将绝缘层360覆盖于导电孔330的截止端3302，以隔离开导电孔330的截止端3302和基板表面的导电层，使得导电孔330的一端可以导通，另一端截止导通，进而将电子元件32的连接端子321连接至导电孔330并在导电孔330的一端实现电连接。可以理解的，绝缘层360采用绝缘材料制成，例如可以采用诸如聚丙烯、环氧树脂等树脂材料制成。
在本申请实施例中，以电子元件32设有两个连接端子即第一连接端子321a和第二连接端子321b为例。其中，导电层可包括设于第一表面301上的第一导电层341和设于第二表面302上的第二导电层342，导电孔330包括连通至第一导电层341的第一导电孔331和连通至第一导电层341的第二导电孔332。其中，第一连接端子321a通过第一导电孔331连接至第一导电层341，第二连接端子321b通过第二导电孔332连接至第一导电层341。
其中，第一导电孔331可包括相对设置的第一导通端3311和第一截止端3312，第二导电孔332可包括相对设置的第二导通端3321和第二截止端3322。具体而言，第一导通端3311和第二导通端3321可分别与第一表面301上的导电层即第一导电层341电连接。第一截止端3312和第二导电层342之间设置有第一绝缘层361，第二截止端3322和第二导电层342之间设置有第二绝缘层362。换言之，第一绝缘层361设于第二表面302上，且覆盖于第一截止端3312。第二绝缘层362设于第二表面302上，且覆盖于第二截止端3322。第二表面302上的第二导电层342同时覆盖于第一绝缘层361、第二绝缘层362以及第二表面302。
本实施例通过在导电孔330的截止端3302和第二表面302的第二导电层342之间设置绝缘层360，使得第一导电孔331和第二导电孔332分别与第一表面301的第一导电层341电性连接，进而使得电子元件32的第一连接端子321a通过第一导电孔331连接至第一导电层341，第二连接端子321b通过第二导电孔332连接至第一导电层341，以此实现电子元件在基板的单面即第一表面导通。同理也可以得出电子元件在基板的第二表面实现导通的技术方案，本申请实施例不再赘述。
请参阅图11，图11是本申请埋入式电子元件的第三实施例的又一结构示意图。其中，图11实施例和图10实施例的区别在于：电子元件在基板的双面实现导通。
在本实施例中，电子元件32设有两个连接端子即第一连接端子321a和第二连接端子321b。其中，导电层可包括设于第一表面301上的第一导电层341和设于第二表面302上的第二导电层342，导电孔330包括连通至第二导电层342的第一导电孔331和连通至第一导电层341的第二导电孔332。其中，第一连接端子321a通过第一导电孔331连接至第二导电层342，第二连接端子321b通过第二导电孔332连接至第一导电层341。
其中，第一导电孔331可包括相对设置的第一导通端3311和第一截止端3312，第二导电孔332可包括相对设置的第二导通端3321和第二截止端3322。具体而言，第一导通端3311和第二表面302上的导电层即第二导电层342电连接，第二导通端3321和第一表面301上的导电层即第一导电层341电连接。第一截止端3312和第一导电层341之间设置有第一绝缘层361，第二截止端3322和第二导电层342之间设置有第二绝缘层362。换言之，第一绝缘层361设于第一表面301上，且覆盖于第一截止端3312。第二绝缘层362设于第二表面302上，且覆盖于第二截止端3322。第一表面301上的第一导电层341同时覆盖于第一绝缘层361以及第一表面301。第二表面302上的第二导电层342同时覆盖于第二绝缘层362以及第二表面302。
本实施例通过在第一导电孔331的截止端和第一表面301上的第一导电层之间设置第一绝缘层361，以及在第二导电孔332的截止端和第二表面302上的第二导电层之间设置第二绝缘层362，使得第一导电孔331和第二表面302的第二导电层342电性连接，第二导电孔332和第一表面301的第一导电层341电性连接。进而使得电子元件32的第一连接端子321a通过第一导电孔331连接至第二导电层342，第二连接端子321b通过第二导电孔332连接至第一导电层341，以此实现电子元件在基板的双面即第一表面和第二表面同时导通。同理，可以得出电子元件32的第一连接端子321a可通过第一导电孔331连接至第一导电层341，第二连接端子321b通过第二导电孔332连接至第二导电层342。
进一步地，在本申请部分实施例中，基板30表面设有焊盘370，该焊盘370和导电孔330的截止端3302相接，且该焊盘370的尺寸不小于导电孔330的截止端3302。换言之，焊盘370位于绝缘层360和截止端3302之间，且绝缘层360完全覆盖于焊盘370，以避免截止端3302和设于基板对应表面的导电层发生连通的风险。
具体而言，基板30表面分别设有第一焊盘371和第二焊盘372。第一焊盘371和第一截止端3312相接，且位于第一截止端3312和第一绝缘层361之间。第二焊盘372和第二截止端3322相接，且位于第二截止端3322和第二绝缘层362之间。其中，第一绝缘层361完全覆盖于第一焊盘371，且第一焊盘371的尺寸不小于第一截止端3312。第二绝缘层362完全覆盖于第二焊盘372，且第二焊盘372的尺寸不小于第二截止端3322。
请参阅图12，图12是本申请第三实施例中埋入式电子元件的制作方法的流程示意图，该制作方法能够被用于制作第三实施例中的埋入式电子元件。其中，该制作方法大致包括如下步骤：
S1201、提供一基板以及电子元件，并将电子元件设于基板内。请参阅图12a-图12h，图12a-图12h是图12实施例中制作方法对应的结构示意图。其中，基板30具有相背设置的第一表面301和第二表面302，电子元件32设有侧向延伸的连接端子321。关于基板30以及电子元件32的具体结构特征可参考前述实施例中的具体描述，此处不再赘述。
S1202、在基板上开设导电孔，且该导电孔穿设于电子元件的连接端子。其中，电子元件32的连接端子321和导电孔330电性连接。可以理解的，连接端子321和导电孔330可分别设有多个，且每一导电孔330和每一连接端子321分别对应设置，具体可参阅前述实施例的描述。
S1203、将导电孔进行导电化处理，并在基板表面形成导电层。其中，导电层和导电孔电性连接，以使得连接端子通过导电孔和导电层电性连接。该步骤可参考前述实施例中的具体描述，故此不再赘述。
在实际生产工艺中，可首先通过钻孔方式在基板上开设贯穿于基板的导电孔，然后通过沉铜、电镀等工艺在导电孔的内侧壁覆盖导电物质或者在导电孔内填充导电物质。与此同时，可以同步在基板表面形成导电层，然后对导电层进行图形化处理以得到所需的线路。换言之，导电孔内的导电物质和基板表面的导电层可以通过相同的工艺一次同步形成，可以提升生产效率。
其中，如图12c所示，导电层可包括设于第一表面301上的第一导电层341和设于第二表面302上的第二导电层342。此时，导电孔330的两端分别与第一导电层341和第二导电层342电性连接。
S1204、对导电层进行局部处理以露出部分基板表面。其中，在该露出的基板表面上可以保留部分导电物质以形成焊盘，该焊盘完全覆盖于导电孔的截止端，且该焊盘和导电层间隔设置。
如图12d所示，导电孔330包括连通至第二导电层342的第一导电孔331和连通至第一导电层341的第二导电孔332。第一连接端子321a通过第一导电孔331连接至第二导电层342，第二连接端子321b通过第二导电孔332连接至第一导电层341。第一导电孔331可包括相对设置的第一导通端3311和第一截止端3312，第二导电孔332可包括相对设置的第二导通端3321和第二截止端3322。第一导通端3311和第二导电层342电连接，第二导通端3321和第一导电层341电连接。第一截止端3312和第一表面301相接，第二截止端3322和第二表面302相接。
在第一导电层341对应于第一截止端3312的区域进行局部处理以露出部分第一表面301，以使得第一截止端3312和第一导电层341间隔绝缘。在第二导电层342对应于第二截止端3322的区域进行局部处理以露出部分第二表面302，以使得第二截止端3322和第二导电层342间隔绝缘。其中，当第一导电层141和第二导电层342为铜层时，可以通过减铜工艺对导电层进行局部处理以露出部分基板表面。当然，也可以通过钻孔等其他工艺对导电层进行处理以露出部分基板表面。
在本实施例中，在对导电层进行处理后会保留一部分导电物质以形成覆盖于导电孔一端的焊盘结构。该焊盘结构和导电孔相接并完全覆盖于导电孔的一端，且该焊盘结构和导电层间隔绝缘，以使得导电孔的一端和导电层绝缘。具体而言，在第一导电层341对应于第一截止端3312的区域进行局部处理形成第一焊盘371，该第一焊盘371覆盖于第一表面301的部分表面以及完全覆盖于第一截止端3312。在第二导电层342对应于第二截止端3322的区域进行局部处理形成第二焊盘372，该第二焊盘372覆盖于第二表面302的部分表面以及完全覆盖于第二截止端3322。其中，第一焊盘371和第一导电层341间隔绝缘，第二焊盘372和第二导电层342间隔绝缘。
当然，在其他实施方式中，在部分露出的基板表面上可以不用保留导电物质，即不会形成焊盘结构。如图12e所示，在对导电层进行处理后露出基板表面，并形成以基板表面为底壁的凹槽380结构，且该凹槽380结构完全覆盖于导电孔的截止端，以使得导电孔的截止端和导电层绝缘。例如，去除部分第一导电层341形成以第一表面301为底壁的第一凹槽381，去除部分第二导电层342形成以第二表面302为底壁的第二凹槽382。其中，第一凹槽381的底壁和第一截止端3312相接，且第一凹槽381的孔径大于第一截止端3312，进而使得第一截止端3312和第一导电层341绝缘。第二凹槽382的底壁和第二截止端3322相接，且第二凹槽382的孔径大于第二截止端3322，进而使得第二截止端3322和第二导电层342绝缘。
S1205、在露出的基板表面上填充绝缘材料以形成绝缘层，且该绝缘层完全覆盖于导电孔的截止端。
如图12f所示，露出的基板表面形成有焊盘结构，绝缘层完全覆盖于上述焊盘结构。其中，该焊盘结构和导电孔相接并完全覆盖于导电孔的一端，且该焊盘结构和导电层间隔绝缘，以使得导电孔的一端和导电层绝缘。具体而言，第一焊盘371完全覆盖于第一截止端3312，在第一焊盘371上形成有第一绝缘层361，该第一绝缘层361完全覆盖于第一焊盘371。第二焊盘372完全覆盖于第二截止端3322，在第二焊盘372上形成有第二绝缘层362，该第二绝缘层362完全覆盖于第二焊盘372。
如图12g所示，露出的基板表面没有形成有焊盘结构，绝缘层完全覆盖于凹槽的底壁。其中，在第一凹槽381内填充绝缘材料形成第一绝缘层361，该第一绝缘层361完全覆盖于第一凹槽381的底壁以及第一截止端3312。在第二凹槽382内填充绝缘材料形成第二绝缘层362，该第二绝缘层362完全覆盖于第二凹槽382的底壁以及第二截止端3322。
本申请实施例提供的制作方法，通过去除部分导电层以露出部分基板表面，并在露出的基板表面上形成绝缘层，且使得该绝缘层完全覆盖于导电孔的一端，使得导电孔的一端和导电层绝缘，另一端和导电层电性连接，进而使得电子元件的连接端子可通过导电孔连接至导电层。
进一步地，在形成绝缘层后为了保持埋入式电子元件的外观一致性以及便于后续制作线路，通常会在绝缘层上填充导电物质以与导电层形成完整面。具体而言，请继续参阅图12h，在步骤S1205之后还包括步骤S1206，即在绝缘层上填充导电物质，以使得导电层背离基板的一侧表面平齐，进而保持整体结构的外观一致性以及便于后续制作线路。
其中，可通过沉铜、电镀等工艺上在绝缘层上覆盖导电物质，以填补去除的部分导电层，使得导电层背离基板的表面平齐。例如，在第一绝缘层361上覆盖填充导电物质使得第一导电层341在背离第一表面301的一侧平齐，在第二绝缘层362上覆盖填充导电物质使得第二导电层342在背离第二表面302的一侧平齐。
请参阅图13，图13是本申请埋入式电子元件的第四实施例的结构示意图。其中，第四实施例和第一至第三实施例的区别在于：导电孔和导电层之间的连通方式不同。
本实施例的埋入式电子元件400可以包括：基板40和电子元件42，电子元件42设于基板40内。其中，电子元件42设有侧向延伸的连接端子421。基板40具有相背的第一表面401和第二表面402，基板40内设有导电孔430。连接端子421自电子元件42的侧面延伸至导电孔430。关于基板40和电子元件42的具体结构可参考前述实施例。
导电孔430可包括相对设置的导通端4301和截止端4302，导通端4301和截止端4302分别与第一表面401和第二表面402对应设置。即导通端4301和截止端4302中的一者对应于第一表面401设置，另一者对应于第二表面402设置。其中，导通端4301用于实现导电孔430的电性连接，截止端4302用于实现导电孔430的绝缘，以此实现导电孔430的单端导通。例如，导通端4301相接于第一表面401，截止端4302相接于第二表面402，以实现导电孔430的单端导通。
基板40的表面设有第一导电层44，第一导电层44可以设于基板的第一表面401和/或第二表面402。第一导电层44覆盖于导电孔430的端部，并与导电孔430电性连接。在本实施例中，第一导电层44可设有两层，一层设于第一表面401上，一层设于第二表面402上。第一表面401上的第一导电层44完全覆盖于导电孔430的一端，第二表面402上的第一导电层44完全覆盖于导电孔430的另一端。其中，第一表面401上的第一导电层44未覆盖导电孔430的区域露出第一表面401，第二表面402上的第一导电层44未覆盖导电孔430的区域露出第二表面402。换言之，第一导电层44开窗以露出部分基板表面，第一导电层44未开窗区域覆盖于导电孔430的端部。
第一导电层44背离基板40的一侧设有绝缘层46，即绝缘层46覆盖于第一导电层44背离基板40的一侧。可以理解的，绝缘层46投影于基板表面的正投影可以完全覆盖于该基板表面，即绝缘层46同时覆盖于第一导电层44和基板40表面，且该绝缘层46背离基板40的一面与基板40表面大体上平行。其中，绝缘层46开设有导电盲孔450，该导电盲孔450和第一导电层44电性连接，以使得导电盲孔450和导电孔430电性连接。其中，导电盲孔450的内侧壁覆盖有导电物质，以实现导电盲孔450和导电层的电性连接。例如，可以通过电镀的方式在导电盲孔450的内侧壁覆盖铜层、铜镍合金层、铜镍金合金层等金属层。当然，在其他一些实施方式中，导电盲孔450内填充有导电物质，以实现导电盲孔450和导电层的电性连接。例如，可以在导电盲孔450内形成铜柱、合金柱等金属柱状结构。
绝缘层46背离基板40的一侧设有第二导电层47，即第二导电层47覆盖于绝缘层46背离基板40的一侧。其中，第二导电层47和导电盲孔450电性连接，使得第二导电层47和导电孔430电性连接。
进一步地，导电盲孔450对应于导电孔430的一端设置，使得导电孔430形成单端导通的连接方式。即导电盲孔450对应于导电孔430的导通端4301的设置，并与导通端4301电性连接。电子元件42的连接端子421通过导电孔430和第二导电层47电性连接。
在本申请实施例中，以电子元件42设有两个连接端子即第一连接端子421a和第二连接端子421b为例。其中，第一导电层44可包括设于第一表面401上的第一导电I层441和设于第二表面402上的第一导电II层442。导电孔430可包括间隔设置的第一导电孔431和第二导电孔432，第一导电孔431的两端分别连通至第一导电I层441和第一导电II层442，第二导电孔432的两端分别连通至第一导电I层441和第一导电II层442。
其中，第一导电孔431可包括相对设置的第一导通端4311和第一截止端4312，第二导电孔432可包括相对设置的第二导通端4321和第二截止端4322。具体而言，第一导通端4311和第二导通端4321可分别与第一表面401上的第一导电I层441电性连接。第一截止端4312和第二截止端4322可分别与第二表面402上的第一导电II层442电性连接。
即第一导电I层441通过开窗分别覆盖第一导通端4311和第二导通端4321，以避免第一导通端4311和第二导通端4321直接连接，从而避免第一连接端子421a和第二连接端子421b直接连接。第一导电II层442通过开窗分别覆盖第一截止端4312和第二截止端4322，以避免第一截止端4312和第二截止端4322直接连接，从而避免第一连接端子421a和第二连接端子421b直接连接。
绝缘层46可包括设于第一表面401上的第一绝缘层461和设于第二表面402上的第二绝缘层462。第一绝缘层461同时覆盖于第一导电I层441以及第一表面401，第二绝缘层462同时覆盖于第一导电II层442以及第二表面402。
其中，第一绝缘层461开设有导电盲孔450，导电盲孔450对应于导电孔430的导通端4301的设置，并与第一导电I层441电性连接。例如，导电盲孔450可包括对应于第一导通端4311设置的第一导电盲孔451和对应于第二导通端4321设置的第二导电盲孔452。第一导电盲孔451和第一导通端4311上的第一导电I层441电性连接，第二导电盲孔452和第二导通端4321上的第一导电I层441电性连接，使得第一导电盲孔451和第一导通端4311电性连接，第二导电盲孔452和第二导通端4321电性连接。
第二导电层47可包括设于第一绝缘层461上的第二导电I层471和设于第二绝缘层462上的第二导电II层472。其中，第一导电盲孔451和第二导电I层471电性连接，第二导电盲孔452和第二导电I层471电性连接，使得第 一导通端4311和第二导电I层471电性连接，第二导通端4321和第二导电I层471电性连接，进而使得电子元件42的第一连接端子421a通过第一导电孔431连接至第二导电I层471，第二连接端子421b通过第二导电孔432连接至第二导电I层471，以此实现电子元件在基板的单面即第一表面导通。同理也可以得出电子元件在基板的第二表面实现导通的技术方案，本申请实施例不再赘述。
请参阅图14，图14是本申请埋入式电子元件的第四实施例的又一结构示意图。其中，图14实施例和图13实施例的区别在于：电子元件在基板的双面实现导通。
在本实施例中，电子元件42设有两个连接端子即第一连接端子421a和第二连接端子421b。其中，第一导电层44可包括设于第一表面401上的第一导电I层441和设于第二表面402上的第一导电II层442。导电孔430可包括间隔设置第一导电孔431和第二导电孔432，第一导电孔431的两端分别连通至第一导电I层441和第一导电II层442，第二导电孔432的两端分别连通至第一导电I层441和第一导电II层442。
其中，第一导电孔431可包括相对设置的第一导通端4311和第一截止端4312，第二导电孔432可包括相对设置的第二导通端4321和第二截止端4322。具体而言，第一导通端4311和第二截止端4322可分别与第一表面401上的第一导电I层441电性连接。第二导通端4321和第一截止端4312可分别与第二表面402上的第一导电II层442电性连接。
即第一导电I层441通过开窗分别覆盖第一导通端4311和第二截止端4322，以避免第一导通端4311和第二截止端4322直接连接，从而避免第一连接端子421a和第二连接端子421b直接连接。第一导电II层442通过开窗分别覆盖第二导通端4321和第一截止端4312，以避免第二导通端4321和第一截止端4312直接连接，从而避免第一连接端子421a和第二连接端子421b直接连接。
绝缘层46可包括设于第一表面401上的第一绝缘层461和设于第二表面402上的第二绝缘层462。第一绝缘层461同时覆盖于第一导电I层441以及第一表面401，第二绝缘层462同时覆盖于第一导电II层442以及第二表面402。
其中，绝缘层46开设有导电盲孔450，导电盲孔450对应于导电孔430的导通端4301的设置，并与第一导电层44电性连接。例如，导电盲孔450可包括对应于第一导通端4311设置的第一导电盲孔451和对应于第二导通端4321设置的第二导电盲孔452。第一导电盲孔451和第一导通端4311上的第一导电I层441电性连接，第二导电盲孔452和第二导通端4321上的第一导电II层442电性连接，使得第一导电盲孔451和第一导通端4311电性连接，第二导电盲孔452和第二导通端4321电性连接。
第二导电层47可包括设于第一绝缘层461上的第二导电I层471和设于第二绝缘层462上的第二导电II层472。其中，第一导电盲孔451和第二导电I层471电性连接，第二导电盲孔452和第二导电II层472电性连接，使得第一导通端4311和第二导电I层471电性连接，第二导通端4321和第二导电II层472电性连接，进而使得电子元件42的第一连接端子421a通过第一导电孔431、第一导电盲孔451电性连接至第二导电I层471，第二连接端子421b通过第二导电孔432、第二导电盲孔452电性连接至第二导电II层472，以此实现电子元件在基板的双面即第一表面和第二表面同时导通。同理可得出电子元件422的第一连接端子421a通过第一导电孔431连接至第二导电II层472，第二连接端子421b通过第二导电孔432连接至第二导电I层471。
请参阅图15，图15是本申请第四实施例中埋入式电子元件的制作方法的流程示意图，该制作方法能够被用于制作第四实施例中的埋入式电子元件。其中，该制作方法大致包括如下步骤：
S1501、提供一基板以及电子元件，并将电子元件设于基板内。请参阅图15a-图15f，图15a-图15f是图15实施例中制作方法对应的结构示意图。其中，基板40具有相背设置的第一表面401和第二表面402，电子元件42设有侧向延伸的连接端子421。关于基板40以及电子元件42的具体结构特征可参考前述实施例中的具体描述，此处不再赘述。
S1502、在基板上开设导电孔，且该导电孔穿设于电子元件的连接端子。其中，电子元件42的连接端子421和导电孔430电性连接。可以理解的，连接端子421和导电孔430可分别设有多个，且每一导电孔430和每一连接端子421分别对应设置，具体可参阅前述实施例的描述。
S1503、将导电孔进行导电化处理，并在基板表面形成金属层。如图15c所示，在实际生产工艺中，可首先通过钻孔方式在基板上开设贯穿于基板的导电孔430，然后通过沉铜、电镀等工艺在导电孔的内侧壁覆盖导电物质或者在导电孔内填充导电物质。与此同时，可以同步在基板表面形成金属层48，然后对金属层48进行图形化处理以得到所需的线路。其中，金属层48可分别覆盖于第一表面401和第二表面402，导电孔430的两端分别与金属层48电性连接。
S1504、对上述金属层进行图形化处理以得到第一导电层。如图15d所示，可以通过蚀刻、光刻等工艺对金属层48进行图形化处理以得到第一导电层44。其中，第一导电层44可包括设于第一表面401上的第一导电I层441和设于第二表面402上的第一导电II层442，导电孔430的两端分别与第一导电I层441、第一导电II层442电性连接。
可以理解的，当电子元件42在基板40的单面导通时，第一导电层44设于基板40的第一表面401或者第二表面402。当电子元件42在基板40的双面导通时，第一导电层44设于基板40的第一表面401和第二表面402。本实施例以电子元件42在基板40的双面导通为例，即第一导电层44包括第一导电I层441和第一导电II层442，导电孔430的两端分别与第一导电I层441、第一导电II层442电性连接。
导电孔430可包括间隔设置第一导电孔431和第二导电孔432，第一导电孔431可包括相对设置的第一导通端4311和第一截止端4312，第二导电孔432可包括相对设置的第二导通端4321和第二截止端4322。第一导通端4311和第二截止端4322可分别与第一导电I层441电性连接。第二导通端4321和第一截止端4312可分别与第一导电II层442电性连接。关于第一导电层44未尽详述的特征可参考前述实施例的描述。
S1505、在第一导电层上设置绝缘层，且该绝缘层覆盖于基板表面。如图15e所示，绝缘层46设于第一导电层44背离基板40的一侧，绝缘层46上设有导电盲孔450，该导电盲孔450和第一导电层44电性连接。
其中，绝缘层46可包括设于第一表面401上的第一绝缘层461和设于第二表面402上的第二绝缘层462。导电盲孔450和导电孔430对应设置，即每一导电盲孔450能够与导电孔430的一端电性连接。
在本实施例中，绝缘层46可包括设于第一表面401上的第一绝缘层461和设于第二表面402上的第二绝缘层462。第一绝缘层461同时覆盖于第一导电I层441以及第一表面401，第二绝缘层462同时覆盖于第一导电II层442以及第二表面402。
第一绝缘层461开设有第一导电盲孔451，第二绝缘层462开设有第二导电盲孔452。第一导电I层441位于第一导电盲孔451和第一导电孔431之间，第一导电II层442位于第二导电盲孔452和第二导电孔432之间。以此使得第一导电孔431的第一导通端4311通过第一导电I层441和第一导电盲孔451电性连接，第二导电孔432的第二导通端4321通过第一导电II层442和第二导电盲孔452电性连接。
可以理解的，当电子元件42需要在基板40的单面导通时，第一导电盲孔451和第二导电盲孔452可以间隔设于第一绝缘层461或者第二绝缘层462，并分别与第一导电孔431和第二导电孔432电性连接。关于绝缘层46未尽详述的特征可参考前述实施例的描述。
其中，在绝缘层46上开设导电盲孔450的具体实施方式大致包括如下两种：(1)、首先在绝缘片材上开设导电盲孔，然后将绝缘片材贴合在基板表面并覆盖第一导电层以形成绝缘层，上述导电盲孔与第一导电层对应设置且电性连接。(2)、首先将绝缘片材贴合在基板表面并覆盖第一导电层以形成绝缘层，然后在绝缘层上对应于第一导电层的区域开设导电盲孔，使得导通盲孔和第一导电层电性连接。
S1506、在绝缘层上形成第二导电层。如图15f所示，绝缘层46中的导电盲孔450和第二导电层47电性连接。
第二导电层47可包括设于第一绝缘层461上的第二导电I层471和设于第二绝缘层462上的第二导电II层472。第一导电盲孔451和第二导电I层471电性连接，第二导电盲孔452和第二导电II层472电性连接。此时，第一导电孔431通过第一导电盲孔451和第二导电I层471电性连接，第二导电孔432通过第二导电盲孔452和第二导电II层472电性连接。进而使得电子元件42的第一连接端子421a通过第一导电孔431和第二导电I层471电性连接，第二连接端子421b通过第二导电孔432和第二导电II层472电性连接，以实现电子元件在基板的双面导通。
可以理解的，当电子元件42需要在基板40的单面导通时，第一导电盲孔451和第二导电I层471电性连接，第二导电盲孔452和第二导电I层471电性连接。第一导电孔431通过第一导电盲孔451和第二导电I层471电性连接，第二导电孔432通过第二导电盲孔452和第二导电I层471电性连接。或者，第一导电盲孔451和第二导电II层472电性连接，第二导电盲孔452和第二导电II层472电性连接。第一导电孔431通过第一导电盲孔451和第二导电II层472电性连接，第二导电孔432通过第二导电盲孔452和第二导电II层472电性连接。关于第二导电层47未尽详述的特征可参考前述实施例的描述。
请参阅图16，图16是本申请埋入式电子元件的第五实施例的结构示意图。其中，第五实施例和第一至第四实施例的区别在于：电子元件和导电层之间的连通方式不同。
本实施例的埋入式电子元件500可以包括：基板50和电子元件52，电子元件52设于基板50内。其中，电子元件52设有侧向延伸的连接端子521。基板50具有相背的第一表面501和第二表面502，基板50内设有导电盲孔530。连接端子521自电子元件52的侧面延伸至导电盲孔530。关于基板50和电子元件52的具体结构可参考前述实施例。
其中，导电盲孔530自基板50表面延伸至基板50内部。例如，导电盲孔530可以设置多个，多个导电盲孔530可以自基板50的第一表面501或者第二表面502延伸至基板50内部。或者，多个导电盲孔530中的部分导电盲孔530自基板50的第一表面501延伸至基板50内部，多个导电盲孔530中的另一部分导电盲孔530自基板50的第二表面502延伸至基板50内部。可以理解的，导电盲孔530和连接端子521可分别设有多个，且导电盲孔530和连接端子521对应设置，即每一连接端子521通过一个导电盲孔530和设于基板50表面上的导电层电性连接。
具体而言，导电盲孔530内侧壁覆盖有导电物质，以实现导电盲孔530和基板表面的导电层的电连接。例如，可以通过电镀的方式在导电盲孔530的内侧壁覆盖铜层、铜镍合金层、铜镍金合金层等金属层。当然，在其他一些实施方式中，导电盲孔530内填充有导电物质，以实现导电盲孔530和基板表面的导电层的电连接。例如，可以在导电盲孔530内形成铜柱、合金柱等金属柱状结构或者金属锥形结构。
进一步地，导电盲孔530连通至连接端子521，并与连接端子521电性连接。例如，导电盲孔530的底壁抵接于连接端子521，以使得导电盲孔530的底壁和连接端子521电性连接。或者，导电盲孔530的一端延伸至连接端子521的内部，以使得导电盲孔530的底壁、侧壁和连接端子521电性连接。
当然，在其他实施方式中，如图17所示，导电盲孔530可以穿设于连接端子521，此时导电盲孔530的侧壁和连接端子521电性连接。
在本实施例中，以电子元件52的连接端子521包括第一连接端子521a和第二连接端子521b为例。导电盲孔530可包括第一导电盲孔531和第二导电盲孔532。第一导电盲孔531连通至第一连接端子521a，第二导电盲孔532连通至第二连接端子521b。
第一导电盲孔531和第二导电盲孔532在基板50的第一表面501上间隔设置，且均自第一表面501延伸至基板50内部。其中，第一导电盲孔531和第二导电盲孔532的轴线大体平行。
基板50的第一表面501上设有导电层54。第一导电盲孔531和第二导电盲孔532分别与导电层54电性连接，第一连接端子521a通过第一导电盲孔531和导电层54电性连接，第二连接端子521b通过第二导电盲孔532和导电层54电性连接，以此可使电子元件在基板单面导通。
当然，在其他实施方式中，第一导电盲孔531和第二导电盲孔532在基板50的第二表面502上间隔设置，且 均自第二表面502延伸至基板50内部。基板50的第二表面502上设有导电层54，第一连接端子521a通过第一导电盲孔531和导电层54电性连接，第二连接端子521b通过第二导电盲孔532和导电层54电性连接。
请参阅图18，图18是本申请埋入式电子元件的第五实施例的又一结构示意图。其中，图18实施例和图16实施例的区别在于：电子元件在基板的双面实现导通。
在本实施例中，电子元件52的连接端子包括第一连接端子521a和第二连接端子521b。其中，导电层包括设于第一表面501上的第一导电层541和设于第二表面502上的第二导电层542，导电盲孔530包括连通至第一导电层541的第一导电盲孔531和连通至第二导电层542的第二导电盲孔532。其中，第一连接端子521a通过第一导电盲孔531连接至第一导电层541，第二连接端子521b通过第二导电盲孔532连接至第二导电层542，以使得电子元件在基板的第一表面和第二表面同时导通。
可以理解的，上述结构可以进行简单变化即可得出电子元件52的第一连接端子521a可通过第一导电盲孔531连接至第二导电层542，第二连接端子521b可通过第二导电盲孔532连接至第一导电层541。
请参阅图19，图19是本申请第五实施例中埋入式电子元件的制作方法的流程示意图，该制作方法能够被用于制作第五实施例中的埋入式电子元件。其中，该制作方法大致包括如下步骤：
S1901、提供一基板以及电子元件，并将电子元件设于基板内。请参阅图19a-图19d，图19a-图19d是图19实施例中制作方法对应的结构示意图。其中，基板50具有相背设置的第一表面501和第二表面502，电子元件52设有侧向延伸的连接端子521。关于基板50以及电子元件52的具体结构特征可参考前述实施例中的具体描述，此处不再赘述。
S1902、在基板上开设导电盲孔，且该导电盲孔连通至电子元件的连接端子。其中，电子元件52的连接端子521和导电盲孔530电性连接。可以理解的，连接端子521和导电盲孔530可分别设有多个，每一导电盲孔530和每一连接端子521分别对应且电性连接，具体可参阅前述实施例中的描述。
具体而言，以电子元件52的连接端子521包括间隔设置的第一连接端子521a和第二连接端子521b为例。导电盲孔530可包括间隔设置的第一导电盲孔531和第二导电盲孔532。第一导电盲孔531连通至第一连接端子521a，第二导电盲孔532连通至第二连接端子521b。
进一步地，第一导电盲孔531和第二导电盲孔532自基板表面延伸至基板内部。如图19b所示，第一导电盲孔531和第二导电盲孔532均自基板50的第一表面501延伸至基板50内部。如图19c所示，第一导电盲孔531自基板50的第一表面501延伸至基板50内部，第二导电盲孔532自基板50的第二表面502延伸至基板50内部。第一导电盲孔531和第一连接端子521a电性连接，第二导电盲孔532和第二连接端子521b电性连接。当然，在其他实施例中，第一导电盲孔531和第二导电盲孔532均自基板50的第二表面502延伸至基板50内部。
可以理解的，可通过钻控深孔的方式在基板表面开设导电盲孔，以使得导电盲孔连通至电子元件的连接端子。
如图19b所示，在基板50的第一表面501分别钻控深孔以形成第一导电盲孔531和第二导电盲孔532。其中，当第一连接端子521a和第二连接端子521b与第一表面501的间距相同时，第一导电盲孔531和第二导电盲孔532可同步成型；当第一连接端子521a和第二连接端子521b与第一表面501的间距不同时，第一导电盲孔531和第二导电盲孔532可分别单独成型。
如图19c所示，在基板50的第一表面501钻控深孔以形成第一导电盲孔531，在基板50的第二表面502钻控深孔以形成第二导电盲孔532。其中，当第一连接端子521a和第一表面501之间的间距与第二连接端子521b和第二表面502之间的间距相同时，第一导电盲孔531和第二导电盲孔532可同步成型；当第一连接端子521a和第一表面501之间的间距与第二连接端子521b和第二表面502之间的间距不同时，第一导电盲孔531和第二导电盲孔532可分别单独成型。
S1903、将导电盲孔进行导电化处理，并在基板表面形成导电层。如图19d所示，以第一导电盲孔531自基板50的第一表面501延伸至基板50内部，第二导电盲孔532自基板50的第二表面502延伸至基板50内部为例。导电层可包括设于第一表面501上的第一导电层541和设于第二表面502上的第二导电层542，第一导电层541和第一导电盲孔531电性连接，第二导电层542和第二导电盲孔532电性连接。其中，第一连接端子521a通过第一导电盲孔531连接至第一导电层541，第二连接端子521b通过第二导电盲孔532连接至第二导电层542，以使得电子元件在基板的第一表面和第二表面同时导通。
可以理解的，当电子元件在基板单面导通时，导电层可形成于基板的一个表面。例如，当第一导电盲孔531和第二导电盲孔532均自基板50的第一表面501延伸至基板50内部时，导电层54设于第一表面501。
进一步地，在实际生产工艺中，可通过沉铜、电镀等工艺在导电盲孔的内侧壁覆盖导电物质或者在导电盲孔内填充导电物质。与此同时，同步在基板表面形成导电层，以此使得导电盲孔和导电层电性连接。
本申请实施例提供的埋入式电子元件的制作方法，通过在基板表面开设导电盲孔连通至电子元件的连接端子，使得电子元件可以借由导电盲孔连通至基板表面的导电层，工艺流程简单，有利于提高生产效率。
需要说明的是，术语“包括”和“具有”以及他们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设置固有的其他步骤或单元。
以上所述仅为本申请的部分实施例，并非因此限制本申请的保护范围，凡是利用本申请说明书及附图内容所作的等效装置或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种埋入式电子元件，其中，所述埋入式电子元件包括：
    基板，所述基板内设有容置槽和导电孔，所述基板表面设有导电层；
    电子元件，设于所述容置槽内，所述电子元件设有侧向延伸至所述导电孔的第一连接端子和第二连接端子；
    其中，所述第一连接端子和所述第二连接端子通过所述导电孔与所述导电层电性连接。
  2. 根据权利要求1所述的埋入式电子元件，其中，所述基板表面包括相背的第一表面以及第二表面，所述导电层设置在所述第一表面和/或者第二表面。
  3. 根据权利要求2所述的埋入式电子元件，其中，所述导电孔包括相对的导通端和截止端，所述导通端相接于所述第一表面和第二表面中的一者，所述截止端临近于所述第一表面和第二表面中的另一者，所述截止端和临近所述截止端的所述基板表面之间设置有绝缘槽。
  4. 根据权利要求3所述的埋入式电子元件，其中，所述绝缘槽的底壁与所述导电孔截止端相接，且所述绝缘槽孔径大于所述导电孔的截止端。
  5. 根据权利要求3所述的埋入式电子元件，其中，所述绝缘槽内填充有绝缘材料。
  6. 根据权利要求1所述的埋入式电子元件，其中，所述基板表面包括相背的第一表面和第二表面，所述导电层包括设于所述第一表面上的第一导电层和设于所述第二表面上的第二导电层，所述导电孔包括连通至所述第一导电层的第一导电孔和连通至所述第二导电层的第二导电孔；所述第一连接端子通过所述第一导电孔连接至所述第一导电层，所述第二连接端子通过所述第二导电孔连接至所述第二导电层。
  7. 根据权利要求6所述的埋入式电子元件，其中，所述第一导电孔穿设于所述第一连接端子，所述第二导电孔穿设于所述第二连接端子。
  8. 根据权利要求1所述的埋入式电子元件，其中，所述导电孔的内侧壁覆盖有导电物质，或者所述导电孔内填充有导电物质，以实现所述导电孔和所述导电层的电连接。
  9. 根据权利要求1所述的埋入式电子元件，其中，所述基板为绝缘基板，所述电子元件为无源电子元件。
  10. 根据权利要求1所述的埋入式电子元件，其中，所述埋入式电子元件还包括绝缘层，所述绝缘层设于所述基板表面且覆盖于所述导电孔的一端，所述导电孔的另一端和所述导电层电性连接。
  11. 根据权利要求10所述的埋入式电子元件，其中，所述基板表面设有焊盘，所述焊盘和所述导电孔的一端相接，所述绝缘层完全覆盖于所述焊盘。
  12. 根据权利要求1所述的埋入式电子元件，其中，所述埋入式电子元件还包括绝缘层，所述导电层包括第一导电层和第二导电层；所述第一导电层设于所述基板表面，且覆盖于所述导电孔的端部；所述绝缘层覆盖于所述第一导电层背离所述基板的一侧，所述绝缘层开设有导电盲孔，所述导电盲孔和所述第一导电层电性连接；所述第二导电层覆盖于所述绝缘层背离所述基板的一侧，所述第二导电层和所述导电盲孔电性连接。
  13. 根据权利要求12所述的埋入式电子元件，其中，所述导电盲孔对应于所述导电孔的一端设置，并与所述导电孔电性连接，所述第一连接端子和所述第二连接端子通过所述导电孔和所述第二导电层电性连接。
  14. 根据权利要求13所述的埋入式电子元件，其中，所述基板表面包括相背的第一表面以及第二表面，所述第一导电层包括设于所述第一表面上的第一导电I层和设于所述第二表面上的第一导电II层；绝缘层包括设于所述第一表面上的第一绝缘层和设于所述第二表面上的第二绝缘层；所述第一绝缘层覆盖于所述第一导电I层，所述第二绝缘层覆盖于所述第一导电II层。
  15. 根据权利要求14所述的埋入式电子元件，其中，所述导电盲孔包括第一导电盲孔和第二导电盲孔，所述第一导电盲孔设于所述第一绝缘层并与所述第一导电I层电性连接，所述第二导电盲孔设于所述第二绝缘层并与所述第一导电II层电性连接；所述第二导电层包括设于所述第一绝缘层上的第二导电I层和设于所述第二绝缘层上的第二导电II层；所述第一导电盲孔和所述第二导电I层电性连接，所述第二导电盲孔和所述第二导电II层电性连接。
  16. 根据权利要求15所述的埋入式电子元件，其中，所述导电孔包括间隔设置的第一导电孔和第二导电孔，所述第一导电孔的导通端通过所述第一导电I层和所述第一导电盲孔电性连接，所述第二导电孔的导通端通过所述第一导电II层和所述第二导电盲孔电性连接；所述第一连接端子通过所述第一导电孔和所述第一导电盲孔电性连接至所述第二导电I层，所述第二连接端子通过所述第二导电孔和所述第二导电盲孔电性连接至所述第二导电II层。
  17. 根据权利要求1所述的埋入式电子元件，其中，所述导电孔包括第一导电盲孔和第二导电盲孔，所述第一连接端子通过所述第一导电盲孔和所述导电层电性连接，所述第二连接端子通过所述第二导电盲孔和所述导电层电性连接。
  18. 一种埋入式电子元件的制作方法，其中，包括：
    提供一基板以及电子元件，并将所述电子元件设于所述基板内；
    在所述基板上开设导电孔，并将所述导电孔进行导电化处理；
    在所述基板表面形成导电层，所述导电层和所述导电孔电性连接；
    其中，所述电子元件设有侧向延伸至所述导电孔的第一连接端子和第二连接端子，所述第一连接端子和所述第二连接端子通过所述导电孔与所述导电层电性连接。
  19. 根据权利要求18所述的制作方法，其中，所述在所述基板上开设导电孔的步骤进一步包括：
    对所述导电孔的一端进行处理以形成绝缘槽；
    其中，所述导电孔包括相对的导通端和截止端，所述导通端和所述基板的一表面相接，所述截止端临近于所述 基板的另一表面设置；所述绝缘槽位于所述截止端和临近所述截止端的所述基板表面之间。
  20. 一种电压调节模块，其中，所述电压调节模块包括：
    MOS管；
    埋入式电子元件，所述埋入式电子元件包括：
    基板，所述基板内设有容置槽和导电孔，所述基板表面设有导电层；及
    电子元件，所述电子元件设于所述容置槽内，所述电子元件设有侧向延伸至所述导电孔的第一连接端子和第二连接端子；
    其中，所述第一连接端子和所述第二连接端子通过所述导电孔与所述导电层电性连接；所述MOS管堆叠于所述基板上。
PCT/CN2021/103816 2021-06-30 2021-06-30 埋入式电子元件及其制作方法、电压调节模块 WO2023272647A1 (zh)

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JP2007053328A (ja) * 2004-09-13 2007-03-01 Murata Mfg Co Ltd チップ型電子部品内蔵型多層基板及びその製造方法
JP2007258756A (ja) * 2007-06-27 2007-10-04 Kyocera Corp 電気素子内蔵配線基板
CN101772994A (zh) * 2007-07-26 2010-07-07 株式会社村田制作所 多层陶瓷基板及其制造方法
CN109416963A (zh) * 2016-05-10 2019-03-01 Tdk电子股份有限公司 多层式器件和用于制造多层式器件的方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007053328A (ja) * 2004-09-13 2007-03-01 Murata Mfg Co Ltd チップ型電子部品内蔵型多層基板及びその製造方法
JP2007258756A (ja) * 2007-06-27 2007-10-04 Kyocera Corp 電気素子内蔵配線基板
CN101772994A (zh) * 2007-07-26 2010-07-07 株式会社村田制作所 多层陶瓷基板及其制造方法
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