TWI338356B - Substrate having conductive bump and process thereof - Google Patents

Description

0612001 23124twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to a substrate and a process thereof, and more particularly to a substrate having conductive bumps and a process therefor. ' [Introduction Technology] In the semiconductor industry, the production of Integrated Circuits (1C) is mainly divided into three stages: the design of integrated circuits, the fabrication of integrated circuits, and the packaging of integrated circuits. . In the package of the integrated circuit, the bare wafer is completed by the steps of wafer fabrication, circuit design, mask fabrication, and wafer dicing, and each bare wafer formed by wafer dicing is passed through The pad on the bare die (B〇ndingPad) is electrically connected to the 1 (: IC carrier), and then encapsulated (M〇Wing)

Compound ) A bare chip is coated to form a chip package structure. As described above, in the trend of thinning and thinning electronic devices, wafer package junctions are also being developed toward volume miniaturization. Figure] shows the conventional; ί ΐ, the schematic diagram of the structure. In the prior art, the chip package structure 100 is fabricated by the A9 Chip Seale Paekage (CSP) technology to achieve the purpose of miniaturization of the package structure. In addition, the wafer structure can be connected to the printed circuit 11 via a solder ball 130, and the ball 13G is a solder pad disposed on the 1C carrier 12G.

In the process of miniaturization of the chip package structure, the area of the pad 122 on the carrier plate 120 of the 1C 0612001 23124 twf.doc/p is also reduced, resulting in the solder ball not easily adhering to the contact area. Pad surface. Therefore, how to make the solder 130 effectively and firmly adhere to the surface of the miniaturized chip package structure is an important issue. The present invention provides a substrate having conductive bumps and a process thereof for enabling solder balls to be effectively and firmly adhered to the pad surface of the miniaturized chip package structure. Sigma Rod For the above or other purposes, the present invention provides a substrate having conductive bumps comprising a dielectric layer, at least one pad, a conductive pillar, and a block. The dielectric layer has a first surface, a second surface, and a opening surface of the second surface and the second surface. The solder pad is disposed on the first surface, and the aperture of the opening corresponds to the inner diameter of the solder pad. In addition, the conductive post is disposed in the opening, and the conductive bump is disposed on the second surface and correspondingly protrudes from the end of the conductive post. Wherein the conductive bump is electrically connected to the solder tab by the conductive post. In the embodiment of the invention, the substrate having the conductive bump further comprises a conductive line, and the conductive line is disposed on the first surface. In an embodiment of the invention, the dielectric layer is a resin sheet. In an embodiment of the invention, the mattress is a ring-shaped pad. ^ Month is further proposed - a substrate process with conductive bumps, including the lower (four) ^ first, provide a substrate, the substrate is provided with a - first conductive layer, - Di two electrical layer and - dielectric layer, wherein the dielectric layer There is a first surface 0612001 23124twf.doc/p and a second surface, and the first conductive air and the electric layer are disposed on the first surface, and the second conductive layer is disposed on the second surface. Then, an opening is formed in the substrate, and a conductive 枉 is formed in the opening, which is electrically connected [the second conductive layer of the conductive layer. The patterned first conductive layer is then patterned to form at least one solder fillet on the first surface. Thereafter, at least one conductive bump is formed on the second surface of the patterned second conductive layer (10), wherein the conductive bump protrudes from the column end, and the conductive bump is electrically connected to the pad by the conductive pillar in the present invention - The forming the conductive bump further includes forming a solder ball to cover the conductive bump. In one embodiment of the invention, the manner in which the substrate is formed includes the following steps. A dielectric layer is first provided. Next, a first conductive layer and a second conductive layer are formed on the first surface and the second surface, respectively, to form a substrate. In one embodiment of the invention, the manner in which the first conductive layer and the second conductive layer are formed includes an electroplating process. In one embodiment of the invention, the manner in which the substrate is formed includes the next step. Firstly, a dielectric layer, a first conductive layer and a second conductive layer are provided with a press-fit dielectric layer, a [conductive layer and a second conductive layer, to form a conductive pillar in an embodiment of the present invention. The way to do this includes the following steps. 1. First, a portion of the first conductive material and a portion of the dielectric layer are formed into openings, wherein the openings expose a portion of the second conductive layer. Connected to a second (filled with a conductive material to form a conductive column. Open-hole drill in the present invention - to perform the shot, forming an opening < a method comprising the mechanical 1338356 0612001 23124 twf.doc / p hole plating process in the present invention - implementation In the embodiment of the present invention, the method of filling the conductive material includes electricity. In one embodiment of the present invention, the method of filling the conductive material includes electricity.

The substrate of the present invention has conductive bumps electrically connected to the pads. Therefore, in the miniaturized chip package structure, the solder balls can be efficiently and stably disposed on the substrate by having a large contact area with the conductive bumps. The above and other objects, features and advantages of the present invention will become more apparent and understood. The following detailed description of the preferred embodiments and the accompanying drawings are set forth below. A flow chart of a substrate process having conductive bumps according to an embodiment of the present invention. Referring to FIG. 2, in the embodiment, the substrate process having conductive bumps includes the following steps: First, step S1 is performed to provide a substrate. The substrate is provided with a first conductive layer, a second conductive layer and a dielectric layer, wherein the dielectric layer has a first surface and a second surface, and the first conductive layer is disposed on the first surface The layer is matched with the second surface. Then, the step S2' is formed on the substrate to form an opening, and a conductive is formed in the opening, wherein the conductive pillar is electrically connected to the first conductive layer and the second conductive layer. Then, The step S3 is performed to pattern the first conductive layer to form a v-weld on the first surface. Then, the step is performed to pattern the second conductive layer to form on the second surface of 8 0612001 23124 twf.doc/p At least one guide, a bump, wherein the conductive The bump protrudes from one end of the conductive post, and the conductive bump is electrically connected to the solder bump by the conductive post. Hereinafter, the substrate process will be described in detail in the detailed process cross-section of the embodiment. FIGS. 3A to 3F illustrate 2 is a process sectional view of the substrate of FIG. 2. The substrate having the conductive bumps is as follows. First, as shown in FIG. 3A, a substrate 210 is provided. The substrate 210 is provided with a first conductive layer 212 and a second. The conductive layer 214 and a dielectric layer 216 (for example, a resin sheet). In this embodiment, the dielectric layer 216 has a first surface 216a and a second surface 216b, and the first conductive layer 212 is disposed on the first The surface 216a, the second conductive layer 214 is disposed on the surface 216b. In the following, the embodiment will first describe the formation of the substrate. For example, the dielectric layer 216 may be provided in this embodiment. A first conductive layer 212 and a second conductive layer 214 are formed on the first surface 216a and the second surface 216b of the dielectric layer 216, respectively, to form the substrate 21A, and the first conductive layer 212 and the second conductive layer 214 are formed. The method is, for example, an electroplating process or A suitable process "Of course, this embodiment can also provide a dielectric layer 216, a first conductive layer 212, and a second conductive layer 214, and then press-bond the dielectric layer 216, the first conductive layer by lamination. The layer 212 and the second conductive layer 214 are formed to form the substrate 21A. Regarding the manner of fabrication of the substrate, the present invention is not limited thereto.

Next, as shown in FIG. 3B to FIG. 3C, a conductive pillar 22 is electrically connected to the first conductive layer 212 and the second conductive layer 214 on the substrate 210. Wherein, the manner of forming the conductive pillars 220 includes the following steps: First, as shown in FIG. 3B 1338356 0612001 23124twf.doc/i, 'remove part of the first conductive layer 2】 9 Β ·*β eight people $ year private increase 212 and A portion of the dielectric layer 216 is formed to form an opening 222 of the second conductive layer 214. Thereafter, a conductive material 224 is filled in the gate hole 222 to form a conductive pillar 22 (Fig. 2). For example, the way to form the opening 222 is, for example, mechanical drilling, reaming plasma remnant or other suitable technique, such as an electric ore process or other suitable embodiment, which can be opened. The conductive material 224 is filled in the 222, and the conductive pillar 224 is formed. The conductive material 224 is formed on the inner wall of the opening 222, and then the filling material is filled in the opening 222 to complete the fabrication of the conductive pillar 22 (Fig. 3 The conductive pillar 2 2 绘 is not filled with the conductive material 224 directly into the opening 222 to make the conductive pillar 220). The hole filling material 222 is filled with the hole filling material in order to prevent the moisture of the external environment from entering the opening hole 222 and causing a popcorn effect. The above hole filling material may also be a suitable conductive material. . < After the conductive pillars 220 are formed on the substrate 210, then as shown in FIG. 3D, the first conductive layer 212 is patterned to form at least one solder pad 212 on the first surface 216a (such as a solder joint 212'塾) and a conductive line 212". Thereafter, as shown in FIG. 3E, the second conductive layer 214 is patterned to form at least one conductive bump 214 on the second surface 216b, and the conductive bump 214' and the conductive pillar 220 The material may be copper, silver or a suitable conductive polymer material (the material of the conductive bump 214' may be the same as or different from the material of the conductive pillar 220.) Thus, the substrate process with the conductive bump 214 is completed. The conductive bump 214 protrudes from one end of the conductive pillar 220, and the conductive bump 214' is electrically connected to the solder pad 214 by the conductive pillar 220. When 0612001 23124twf.d〇c/pt 'is patterned The first conductive layer 212 and the second conductive layer 214 are formed to form the pad 212, the conductive line 212, and the conductive bump 214. Thereafter, the embodiment further continues the post-hardening process to complete the W package operation to form a daily date. Chip package structure (not shown). For example, this The embodiment may form a coated conductive bump 214 on the substrate, the solder ball

230 (shown in FIG. 3Fj), the solder ball 230 is, for example, a solder ball. In this embodiment, the size of the solder ball 23 can be controlled by the size of the electric bump 214'. The material, ^ 塾 212, the conductive line 2 丨 2, and the conductive bump 214, after which, the present invention can also form a cover soldering potential 12 and a conductive line 212 on the first surface 2 of the dielectric layer 216, and the other A dielectric layer and a metal layer (none) are used to facilitate fabrication of a substrate having a multilayer wiring. It is worth mentioning that, & financial implementation of the substrate · (Please refer to Figure 曰 has a large contact area of the conductive bumps 214, so in the micro-span = 4 pieces of the process of the city's solder ball 23G (please refer to 3F) and the conductive bumps have better bonding properties, and the solder balls 23 can be effectively and stably disposed on the substrate 200 by being connected to the bumps 4'. In other words, the implementation For example, the reliability of the ball is better. In addition, since the earth plate 200 of the second embodiment uses the conductive bump 2M at the same time, and the solder ball 2 == is electrically connected, the present embodiment can be substantially 2 Π, '焊 'Although the pad conductive bumps 214 of the present embodiment shown in FIGS. 3A to 3F are located at both ends of the conductive pillars 220. However, in the embodiment, the welding (four) 2 can be formed in the / surface of the first surface 21 & Alternatively, the conductive bumps 214' may be formed on other regions of the second surface 1338356 0612001 23124twf, doc/p 21=. Specifically, in the present invention, the pad 212 is disposed at the position of the first surface 216a or the conductive bump 214. The position of the second surface 216b is not limited, and the conductive column can be used. 22〇来^,, the soldering iron 212, and the conductive bumps 214 are all the spirit disk of the present invention.

As described above, the substrate of the present invention has a conductive connection (10) electrically connected to the pad, and the substrate of the present invention is suitable for miniaturizing the wafer, and is suitable as a span between the pads of less than 0.3. The 1C of mm can be effectively disposed on the substrate by a large contact area with the conductive bumps, thereby increasing the reliability of the ball placement. Further, the electro-hydraulic substrate is connected to the printing and the like by using the conductive bumps and the solder balls at the same time. Therefore, the present invention can greatly reduce the amount of tin used. The invention has been disclosed in the above preferred embodiments, but it is not intended to be used by those skilled in the art, and may be modified in some ways without departing from the spirit of the invention.

It’s fresh to define the towel. d protection.蔓 [Simple description of the schema] = a schematic diagram of the traditional Japanese-Japanese package structure. The manufacturing process is the process of the present invention - the substrate having the conductive bumps. Figs. A to 3F are not process cross-sectional views of the substrate of Fig. 2. [Main component symbol description] 12 1338356 0612001 23124twf.doc/p 100 : chip package structure 11 ο. wafer 120 : 1C carrier plate 122 : pad 130 : solder ball 200 : substrate 210 with conductive bumps : substrate 212 : A conductive layer 212': a pad 212": a conductive line 214: a second conductive layer 214': a conductive bump 216: a dielectric layer 216a: a first surface 216b of the dielectric layer: a second surface 220 of the dielectric layer: Conductive column • 222: opening 224: conductive material 230: solder ball 13

Claims (1)

1338356 0612001 23124twf.doc/p X. Patent Application Range: 1. A substrate having conductive bumps, comprising: a dielectric layer having a first surface, a second surface, and an opening, wherein the opening The first surface and the second surface; at least one pad disposed on the first surface, and the aperture of the opening corresponds to the inner diameter of the pad; a conductive post 'disposed in the opening; and the guide The conductive bump 'is disposed on the second surface and correspondingly protrudes from the nature of the end-end', wherein the conductive bump detects the soldering plate by the conductive, and has the conductive bump according to the first item The base plate of the block further comprises a conductive line, the conductive line is disposed on the board, the =:= two items have a conductive two plate, and the base 5β with the conductive bump is a substrate with conductive bumps. The process includes: providing: a substrate having a “first conductive layer, a first conductive layer=and a dielectric layer, wherein the dielectric layer has a first layer, and the a first conductive layer disposed on the third layer and disposed on the second surface; In the other side of the device, the second plate is formed by the opening plate and forming a conductive (10) main in the opening, and the electric layer and the second conductive layer; 14 1338356 0612001 23124twf.doc/p patterning the first a conductive layer for the first pad; the second conductive layer of the second layer is formed on the second surface to form a V-electrode bump, wherein the conductive bump protrudes from the conductive pillar - the mountain, the conductive bump The conductive pad is electrically connected to the pad. End and whai 6. As described in claim 5, after forming the conductive bump, it further comprises forming - tin = 7. The process of claim 5, wherein the substrate is formed by: providing the dielectric layer; and forming the layer and the second conductive layer on the first surface and the second surface, respectively. To form the substrate. X 8. The substrate process having conductive bumps as described in claim 7, wherein the forming of the first conductive layer and the second conductive layer comprises an electroplating process. 3 >匕 The substrate 9 having at least one conductive bump formed on the surface has a conductive process as described in claim 5, wherein the substrate is formed by: providing the dielectric layer, the first conductive layer, and the second conductive The layer and 3' are pressed against the dielectric layer, the first conductive layer, and the first conductive layer to form the substrate. 10. The substrate process having conductive bumps according to claim 5, wherein the method of forming the conductive germanium comprises: 15 1338356, 0612001 23124iwf.doc/p removing a portion of the first conductive layer and a portion thereof a dielectric layer to form the opening, wherein the opening exposes a portion of the second conductive layer; and filling the opening with a conductive material to form the conductive pillar. 11. The substrate process having conductive bumps according to claim 10, wherein the manner of forming the openings comprises mechanical drilling. 12. The substrate process having conductive bumps according to claim 10, wherein the opening is formed by a laser burn hole. 13. The substrate process having conductive bumps according to claim 10, wherein the manner of forming the openings comprises plasma etching. 14. The substrate process having conductive bumps according to claim 10, wherein the method of filling the conductive material comprises an electroplating process. - 16