Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by group G11C11/00
  • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
  • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
  • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
  • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger

Definitions

• This disclosure relates generally to semiconductor integrated circuits, and more specifically, to power conservation for semiconductor integrated circuits.
• a known technique for achieving power reduction is to test an integrated circuit having a processor and determine the utilization level of the processor. As the processor's utilization factor decreases, the operating frequency of the processor is reduced. Also, the amount of voltage supplied to the processor is reduced a predetermined amount that permits the processor to operate in a more efficient manner.
• Another known technique for achieving power reduction is to test an integrated circuit in a test environment which induces temperature variation and measures performance for the specific integrated circuit. A power supply voltage value is then selected and programmed into the integrated circuit based upon the measured test results. The value of the power supply voltage that is determined during the test mode remains constant after the integrated circuit has been tested and thus must be selected sufficiently high to meet all operating environments that the integrated circuit has been specified to be functional.
• FIG. 1 Illustrated in FIG. 1 in block diagram form is an integrated circuit having memory with dynamic voltage adjustment in accordance with one form of the present invention
• FIG. 2 Illustrated in FIG. 2 is a flow chart of one form of the operation of the integrated circuit of FIG. 1 ;
• FIG. 3 Illustrated in FIG. 3 in a block diagram is an integrated circuit having memory with dynamic voltage adjustment in accordance with another form of the present invention; and [0008] Illustrated in FIG. 4 is a flow chart of one form of the operation of the integrated circuit of FIG. 3.
• FIG. 1 Illustrated in FIG. 1 is a system 10 that implements one form of a dynamic voltage adjustment circuit for a memory within system 10.
• system 10 is an integrated circuit 12.
• a voltage supply 20 for providing a supply voltage.
• System 10 has a memory 14 which may be either a volatile memory or a nonvolatile memory (NVM). It should be understood that the memory 14 further includes decode circuitry, sense amplifiers and other conventional circuitry which are not shown for convenience of explanation.
• a test memory 16 is also provided on the integrated circuit 12. The test memory 16 is the same type of memory device as the memory 14.
• Integrated circuit 12 also has other circuitry 18 which represents any of a variety of additional logic and processing circuitry.
• test memory 16 and the memory 14 may be physically located in different parts of the integrated circuit 12, adjacent to each other in the integrated circuit 12 or have memory cells that are interspersed.
• Voltage supply 20 is connected to an input of a voltage regulator 22. While voltage regulator 22 is illustrated as being a part of the integrated circuit 12, it should be understood that voltage regulator 22 may be implemented external to integrated circuit 12.
• Voltage regulator 22 has a first output connected to a voltage input of memory 14 for providing a first supply voltage labeled V DD1 .
• Voltage regulator 22 has a second output connected to a voltage input of the other circuit 18 for providing a second supply voltage labeled V DD2 .
• the first supply voltage can be lower, equal to, or higher than the second supply voltage for operating the memory 14 at a more power efficient level while satisfying other operating characteristics of a specified memory specification.
• Voltage regulator 22 has a third output connected to a voltage input of a voltage reduction circuit 24 for providing the V DD1 supply voltage.
• An output of voltage reduction circuit 24 is connected to a voltage input of the test memory 16 and provides a voltage labeled "V DD1 - V drop ".
• the value of V drop is determined during design for a particular integrated circuit and a particular application.
• the value V drO p represents a voltage gradation between the value V DD1 and a reduced supply voltage used to test the test memory 16 for functional operation.
• the test memory 16 has an output for providing Read data for a read input of a test circuit 26.
• the test memory has a data input for receiving Write data from a write output of the test circuit 26.
• Control information provided by the test circuit 26 to the test memory 16 is coupled via control signals (not shown) in a conventional manner.
• An output of the test circuit 26 provides a Pass/Fail signal to an input of a test controller 28.
• the test controller 28 has a first output connected to an enable input of the test circuit 26 for providing a Test signal.
• a first output of the test controller 28 provides a first control signal labeled "Increase” and a second control signal labeled "Decrease” to first and second inputs of a voltage adjust circuit 30, respectively.
• An output of the voltage adjust circuit 30 provides a Voperating signal to a control input of the voltage regulator 22.
• the integrated circuit has a test memory 16 that is added to dynamically determine an optimum minimum supply voltage to be provided to the memory 14.
• the optimum minimum supply voltage for memory 14 is a supply voltage value which permits memory 14 to reliably be read and written at the specified (i.e. intended) frequency while consuming the minimal power required to implement memory operation without errors.
• the test memory 16 receives a supply voltage that is less than the memory 14.
• the test memory 16 is a same form of memory circuitry as the memory 14 (i.e. same process and same bit cell configuration) and is present on the integrated circuit 12 for the purpose of testing its functional operation in response to differing values of power supply voltage.
• a clock frequency is selected for operating the memory 14 and test memory 16 and that frequency of operation is maintained.
• the clock circuitry within integrated circuit 12 is powered by the V DD2 power supply voltage and that power supply voltage is not modified by test circuit 26, test controller 28 and voltage adjust circuit 30.
• the test circuit 26, test controller 28 and voltage adjust circuit 30 function in combination to determine an optimum low value for the power supply voltage V DD1 so that the memory 14 of system 10 operates in a power-efficient and reliable way.
• the voltage reduction circuit 24 functions to supply a lower supply voltage to the test memory 16 than is supplied to the memory 14.
• the test circuit 26 functions to write predetermined data to the test memory 16 and to read that data.
• Test circuit 26 functions as a comparator to compare the data that was written with what is read. If the data values exactly match, a pass signal is provided to the test controller 28.
• the test controller 28 provides a Decrease control signal to the voltage adjust circuit 30 indicating that the supply voltage can be further lowered since test memory 16 is fully operational without errors.
• the test controller 28 implements and tracks a count value that represents a number of test iterations or passes that are made with the same supply voltage without errors before lowering the supply voltage.
• the test controller 28 has a predetermined threshold value for the number of test iterations to test the test memory 16.
• test controller 28 If the threshold number has not been exceeded, the test controller 28 generates the Test signal to the test circuit 26. In response to the Test signal, the test circuit 26 again writes a known data value to the test memory 16 and reads that value to determine if the same data is written and read. In an alternative form, the test circuit 26 may only read a previously written data value and compare the read value with an expected value for determining if any errors exist. After the threshold number for the count value is exceeded with no errors encountered, the test controller 28 indicates to the voltage adjust circuit 30 that the supply voltage may be further decreased. The voltage adjust circuit 30 provides the V op ⁇ r at ⁇ n g control signal to the voltage regulator 22.
• the voltage regulator 22 reduces the value of V DD1 to the Vope r ati n g voltage as determined by the voltage adjust circuit 30.
• the voltage reduction circuit 24 then provides a further reduced voltage which is a V drO p less than the just-reduced V DD1 voltage.
• the test controller 28 will generate the Increase control signal.
• the voltage adjust circuit 30 provides the V op ⁇ r at ⁇ n g signal in a form that indicates to the voltage regulator 22 that the value of V DD1 needs to be raised.
• the memory 14 is powered by a supply voltage value that is at least two increments of the gradations of the voltage regulator 22 greater than a voltage that has been determined to begin to experience operational failures.
• FIG. 2 Illustrated in FIG. 2 is a flowchart of a method 32 of operation of the dynamic voltage adjustment within the integrated circuit 12.
• a count value labeled "Pass #" is set to zero.
• the word "pass” refers to the number of iterations or passes of the described method which will be made before any reduction in the supply voltage will be made.
• V DD1 a voltage value of supply voltage V DD1 is provided to the memory 14.
• V t ⁇ S t is determined.
• the test voltage is equal to the supply voltage V DD1 minus a predetermined drop amount labeled V DROP -
• the calculated test voltage is provided to the test memory 16.
• a step 42 the test memory 16 is tested for functional operation at the supply voltage value of V t ⁇ S t.
• step 52 is performed.
• step 52 the value of the supply voltage VDD1 provided to the memory 14 and to the test memory 16 is increased by a predetermined incremental amount.
• Step 36 is then repeated and processing continues sequentially as shown in FIG. 2. It should be understood that once the start operation begins, the method 32 continues sequentially from step 36 through step 44 until power is removed from the integrated circuit 12.
• FIG. 3 Illustrated in FIG. 3 is a system 54 that is another form of a dynamic voltage adjustment for a memory 58 within an integrated circuit 56.
• the integrated circuit 56 has a test memory 60 and other circuitry 62.
• the memory 58 is powered by a supply voltage V DD1 and the other circuitry is powered by a supply voltage V DD2 .
• the supply voltage V DD1 is different from supply voltage V DD2 . In one form the supply voltage V DD1 is less than supply voltage V DD2 in order to save power.
• Voltage regulator 66 provides a fixed bias voltage, V B ⁇ as , to a voltage adjust circuit 68.
• a first output of the voltage adjust circuit 68 is connected to a power supply terminal or node of the test memory 60 for providing a test power supply voltage labeled V t ⁇ St .
• a second output of the voltage adjust circuit 68 provides the V t ⁇ St voltage and is connected to a first input of a test controller 72.
• a data input of test memory 60 is connected to an output of a test circuit 70 for providing Write data.
• a data output of test memory 60 is connected to an input of the test circuit 70 for providing Read data.
• the test circuit 70 provides a Pass/Fail result signal to a second input of the test controller 72.
• a first output of the test control 72 is connected to an input of the test circuit 70 for providing a Test enable signal.
• a second output of the test controller 72 is connected to a second input of the voltage adjust circuit 68 for providing a control signal labeled V A d j ust-
• a third output of the test controller 72 is connected to a second input of the voltage regulator 66 for providing a voltage control signal labeled V Op erat ⁇ ng-
• the integrated circuit 56 has a test memory 60 that is present for dynamically determining an optimum minimum supply voltage to be provided to the memory 58.
• the optimum minimum supply voltage for memory 58 is a supply voltage value which permits memory 58 to reliably be read and written at the specified (i.e. intended) frequency while consuming the minimal power required to implement memory operation without errors.
• the test memory 60 initially receives a supply voltage that is equal to a bias voltage V B ⁇ as - A determination is made by the test circuit 70 under control of the test controller 72 and the voltage adjust circuit 68. It should again be understood that a clock frequency is selected for operating the memory 58 and test memory 60 and that frequency of operation is maintained.
• the clock circuitry within integrated circuit 56 is powered by the V DD2 power supply voltage and that power supply voltage is not modified by test circuit 70, test controller 72 and voltage adjust circuit 68.
• the test circuit 70, test controller 72 and voltage adjust circuit 68 function in combination to determine an optimum low value for the power supply voltage V DD1 so that the memory 58 of system 54 operates in a power-efficient and reliable way.
• the voltage adjust circuit 68 functions to supply a test voltage to the test memory 16 that is initially at a V B ⁇ as value.
• the test circuit 70 functions to write predetermined data to the test memory 60 and to read that data.
• Test circuit 70 functions as a comparator to compare the data that was written with what is read.
• test controller 72 If the data values exactly match, a pass signal is provided to the test controller 72.
• the test controller 72 provides a V A d j ust control signal to the voltage adjust circuit 68 indicating that the supply voltage can be further lowered since test memory 60 is fully operational without errors.
• the test controller 72 subsequently provides a Test enable signal to the test circuit 70.
• the test circuit 70 again writes a known data value to the test memory 60 and reads that value to determine if the same data is written and read.
• the test circuit 70 may only read a previously written data value and compare the read value with an expected value for determining if any errors exist.
• Test circuit 70 determines that a failure of the test memory 60 operation has occurred.
• Test circuit 70 then generates a Fail signal to the test controller 72.
• the test controller 72 provides a Voperating signal to the voltage regulator 66.
• the V op ⁇ rat ⁇ ng signal is a sum of the value of the previous test voltage (i.e. the test voltage in which no failure of operation had occurred) and a predetermined additional amount of voltage known as a voltage margin.
• the voltage regulator adjusts the value of V DD1 to the memory 58 to be equal to the voltage V O p ⁇ ra t ⁇ ng-
• FIG. 4 Illustrated in FIG. 4 is a flowchart that describes a method 78 of operation of the dynamic voltage adjustment within the integrated circuit 56.
• a step 80 is implemented in which a supply voltage V DD1 is provided to memory 58 to operate memory 58.
• the V DD1 supply voltage has a sufficiently high supply voltage value to ensure reliable operation of the memory 58.
• a test voltage, V Test is supplied by the voltage adjust circuit 68.
• the value of the V Test voltage is equal to the voltage of the fixed bias voltage, V B ⁇ as , provided by the voltage regulator 66.
• the voltage adjust circuit 68 provides the supply voltage V Test to the test memory 60.
• a step 86 the test memory 60 is then tested by the test circuit 70 at the supply voltage value of V Test .
• a step 88 a determination is made by the test circuit 70 whether the test memory 60 has correctly functioned in a write and a read operation. If the test memory 60 has correctly functioned, the test supply voltage V Tes t is lowered by a gradated amount in a step 90. With the lowered V Tes t voltage, steps 84-86 are repeated. If the test memory 60 continues to pass a write and read operation with the lowered V Tes t, the V Tes t is again lowered, steps 84-86 are repeated and so on until the test memory 60 fails at a lowered V Tes t supply voltage value.
• the operating voltage signal, V op ⁇ r at ⁇ n g, is placed at a value by the test controller 72 to be equal to the V Tes t value that was used prior to the failure of the test memory 60 and is further increased by a predetermined voltage margin.
• a safety margin is added in.
• the supply voltage V DD1 is adjusted upward by making V DD1 equal to the newly determined value of V op ⁇ rat ⁇ ng-
• the method 78 continues until power is removed from the integrated circuit 56.
• a return to the beginning of step 82 occurs and the V Tes t supply voltage is again provided to the test memory 60 as the known value of V B ⁇ as-
• the memory may be implemented as either a "stand-alone" type of memory or as an embedded memory in an integrated circuit with other types of circuit functions commonly referred to as a System On Chip (SOC).
• SOC System On Chip
• SRAM static random access memory
• SRAM static random access memory
• the SRAM bit cells it is common for the SRAM bit cells to start failing before the logic circuitry when supply voltage is reduced for power conservation. Additionally, memory operation reliability is not easily predictable as supply voltage varies. Therefore, the memory typically determines the minimum supply voltage that is required.
• an optimal supply voltage for the memory is determined so that bifurcation between a memory power supply values and logic circuitry power supply values is implemented. Additionally, the method described herein permits a dynamic variation so that variations in temperature and other operating conditions are readily accounted for.
• the dynamic adjustment occurs while the memory of the integrated circuit is fully functional and thus no interruption in the operation and functionality of the memory occurs. The dynamic adjustment thus occurs when operating a memory implemented in an integrated circuit and that includes adjusting the supply voltage when the memory is storing or holding data as well as during read and write modes of operation.
• the test memory 16 and the test memory 60 are implemented with any of varying sizes. A large enough number of memory bit cells in the test memory is desired to ensure that the test memory represents a wide distribution of bit-cell behavior.
• FIG. 1 Some of the above embodiments, as applicable, may be implemented using a variety of different information processing systems.
• Figure 1 and the discussion thereof describe an exemplary memory system architecture
• this exemplary architecture is presented merely to provide a useful reference in discussing various aspects of the invention.
• the description of the architecture has been simplified for purposes of discussion, and it is just one of many different types of appropriate architectures that may be used in accordance with the invention.
• Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements.
• any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components.
• any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.
• the illustrated memory circuits are SRAM.
• the illustrated memory circuits are implemented as DRAM, MRAM, ferroelectric memories and nonvolatile memories (NVMs) including Flash memory, and volatile storage media including registers, buffers or caches, main memory.
• NVMs nonvolatile memories
• the computer readable media may include, for example and without limitation, any number of the following: magnetic storage media including disk and tape storage media; optical storage media such as compact disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media; nonvolatile memory storage media including semiconductor-based memory units such as FLASH memory, EEPROM, EPROM, ROM; ferromagnetic digital memories; MRAM; volatile storage media including registers, buffers or caches, main memory, RAM, etc.; and data transmission media including computer networks, point-to-point telecommunication equipment, and carrier wave transmission media, just to name a few.
• magnetic storage media including disk and tape storage media
• optical storage media such as compact disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media
• nonvolatile memory storage media including semiconductor-based memory units such as FLASH memory, EEPROM, EPROM, ROM
• ferromagnetic digital memories such as FLASH memory, EEPROM, EPROM, ROM
• system 10 is implemented in a computer system such as a personal computer system.
• Computer systems are information handling systems which can be designed to give independent computing power to one or more users.
• Computer systems may be found in many forms including but not limited to mainframes, minicomputers, servers, workstations, personal computers, notepads, personal digital assistants, electronic games, automotive and other embedded systems, cell phones and various other wireless devices.
• a typical computer system includes at least one processing unit, associated memory and a number of input/output (I/O) devices.
• a method of powering a memory A memory of an integrated circuit is operated by powering the memory at a supply voltage.
• a test memory of the integrated circuit is tested concurrently while operating the memory.
• the test memory and the memory each include bit cells of a first bit cell configuration type.
• a voltage level of the supply voltage is adjusted, while operating the memory, based on the testing the test memory.
• the testing includes determining a minimum voltage level for powering the test memory in which the test memory passes testing.
• the adjusting includes providing the supply voltage at a voltage level based on the determining a minimum voltage level.
• the test memory is tested while powering the test memory at a plurality of voltage levels.
• a highest voltage level of the plurality of voltage levels that the test memory fails testing is determined.
• the supply voltage is adjusted to a voltage level that is higher than the highest voltage level.
• the test memory is powered at a voltage level that is less than the voltage level of the supply voltage by a predetermined amount. During the powering the test memory at a plurality of voltage levels, the memory is powered at a plurality of voltage levels.
• the testing includes writing a data pattern to the test memory, reading a data unit from the test memory, and comparing the data pattern with the data unit.
• a method of powering a memory by powering a memory of an integrated circuit at an operating voltage level includes powering the test memory at a first test voltage level based on the operating voltage level.
• the testing for a second time includes powering the test memory at a second test voltage level based on the first adjusted operating voltage level.
• the first test voltage level is a predetermined amount less than the operating voltage level.
• the second test voltage level is the predetermined amount less than the first adjusted operating voltage level.
• the adjusting for the first time includes increasing the operating voltage level to the first adjusted operating voltage, where the first adjusted operating voltage level is greater than the operating voltage level.
• the adjusting for the first time includes decreasing the operating voltage level to the first adjusted operating voltage, where the first adjusted operating voltage level is less than the operating voltage level.
• the testing for a first time includes testing the test memory while powering the test memory at a plurality of voltage levels and determining a first lowest voltage level of the plurality of voltage levels that the testing indicates passing, wherein the first adjusted voltage level is based on the first lowest voltage level.
• the testing for the second time includes testing the test memory while powering the test memory at a plurality of voltage levels and determining a second lowest voltage level of the plurality of voltage levels that the testing indicates passing, wherein the second adjusted voltage level is based on the second lowest voltage level.
• a system has a memory of an integrated circuit, the memory including a supply terminal for receiving an operating supply voltage.
• a test memory of the integrated circuit includes a test supply terminal for receiving a test supply voltage for powering the test memory, the test memory and the memory each including bit cells of a first bit cell configuration type.
• the test circuitry is coupled to the test memory for testing and determining performance of the test memory, the test circuitry operable for finding a lowest test supply voltage level received at the test supply terminal at which the test memory passes testing.
• the supply terminal of the memory is configured to receive the operating supply voltage that is adjustable during memory operation based on performance of the test memory as determined by the test circuitry.
• the supply terminal of the memory is configured to receive the operating supply voltage at a voltage level that is at a predetermined amount above the minimum test supply voltage level.
• the test supply voltage is supplied at a voltage level less than a voltage level of the operating supply voltage by a predetermined amount.
• the operating supply voltage is increased based on a failed test of the test memory as determined by the test circuit.
• the test circuitry tests the test memory with the test supply terminal being supplied at a first test voltage level that is based on the operating supply voltage at a first voltage level. The operating supply voltage is lowered to a second voltage level based upon a determination that the test memory passes testing while being supplied at the first test voltage level.
• the operating supply voltage is lowered to the second voltage level based upon a determination that the test memory consecutively passes a predetermined number of tests while being supplied at the first test voltage level.
• the test circuitry tests the test memory with the test supply terminal being supplied at a test voltage level that is based on the operating supply voltage at a first voltage level, wherein the operating supply voltage is raised to a second voltage level based upon a determination that the test memory fails testing while being supplied at the first test voltage level.
• a voltage adjustment circuit for supplying the test operating voltage at a plurality of voltage levels, wherein the test circuitry tests the test memory at levels of the plurality to determine a lowest voltage level of the plurality that the test memory passes testing, the operating supply voltage is supplied at a voltage level based on the determined lowest voltage level.
• a voltage regulator including an output coupled to the operating supply terminal and an input coupled to the testing circuitry to receive an indication for adjusting the operating supply voltage based on performance of the test memory as determined by the test circuitry.
• test circuit test controller and voltage adjusting may be implemented in software code wherein the test circuitry would include a processing unit for executing the required code to perform the memory testing and voltage control functions. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
• Coupled is not intended to be limited to a direct coupling or a mechanical coupling.

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• Engineering & Computer Science (AREA)
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• For Increasing The Reliability Of Semiconductor Memories (AREA)
• Tests Of Electronic Circuits (AREA)
• Semiconductor Integrated Circuits (AREA)
• Semiconductor Memories (AREA)
• Dram (AREA)

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