WO2008141481A1 - Structure et procédé de fabrication d'un câblage métallique sur une carte multicouches - Google Patents

Structure et procédé de fabrication d'un câblage métallique sur une carte multicouches Download PDF

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Publication number
WO2008141481A1
WO2008141481A1 PCT/CN2007/001678 CN2007001678W WO2008141481A1 WO 2008141481 A1 WO2008141481 A1 WO 2008141481A1 CN 2007001678 W CN2007001678 W CN 2007001678W WO 2008141481 A1 WO2008141481 A1 WO 2008141481A1
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WO
WIPO (PCT)
Prior art keywords
metal
layer
dielectric layer
metal wiring
predetermined position
Prior art date
Application number
PCT/CN2007/001678
Other languages
English (en)
French (fr)
Inventor
Chih-Kuang Yang
Original Assignee
Princo Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Princo Corp. filed Critical Princo Corp.
Priority to JP2010508687A priority Critical patent/JP5331799B2/ja
Priority to PCT/CN2007/001678 priority patent/WO2008141481A1/zh
Priority to EP07721251.2A priority patent/EP2161973B1/en
Priority to KR1020097024333A priority patent/KR101159514B1/ko
Publication of WO2008141481A1 publication Critical patent/WO2008141481A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
    • H05K3/048—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0166—Polymeric layer used for special processing, e.g. resist for etching insulating material or photoresist used as a mask during plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809—Coaxial layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/09—Treatments involving charged particles
    • H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate

Definitions

  • Multilayer substrate metal circuit manufacturing method and structure thereof Multilayer substrate metal circuit manufacturing method and structure thereof
  • the present invention relates to a method and a structure for manufacturing a multilayer substrate metal line, and more particularly to a method and a method for manufacturing a multilayer substrate metal line suitable for a flexible multilayer substrate.
  • FIG. 1 shows a simplified schematic diagram of a prior art process for fabricating metal lines by etching.
  • metal lines are generally fabricated by wet etching. Since the isotropic nature of wet etching is inevitable as shown by the arrow in FIG. 1, the side surface of the metal line 102 is also etched, resulting in an undercut structure of the metal line. And limited by the size of the metal grain (Grain), resulting in a rough side surface of the metal line.
  • the aforementioned etching method cannot satisfy the current metal due to the above-mentioned defects in the undercut of the metal wiring structure and the roughness of the side surface.
  • Line fineness requirements when manufacturing a multilayer substrate, copper is used as a material of the metal wiring, which is susceptible to erosion or contamination during the fabrication of a dielectric layer or other processes, particularly when polyimide (Polyimide) is used as the dielectric layer material. If you want to coat the surface of the metal circuit with a protective cladding layer, avoid more The erosion or contamination of other materials of the layer substrate improves the reliability of the metal circuit.
  • the etching method must be used to make the cladding metal layer covering the metal line with an additional exposure and etching process, and the additional exposure and etching processes may be caused by
  • the accuracy requirements for the alignment of the metal lines with the cladding metal layer increase the likelihood of failure to fabricate the multilayer substrate metal lines and also increase the manufacturing cost of the multilayer substrate.
  • the prior art etching method cannot form a cladding metal layer on the side surface or even the bottom surface of the metal line in a single exposure process, that is, the reliability of the metal line cannot be improved by completely covering the metal line. It is not possible to make metal lines that can be used as coaxial conductors.
  • FIG. 2A shows a schematic view of a prior art fabrication of a multilayer substrate metal line by a build-up method.
  • Figure 2A shows a very thin metal layer 102 formed on a dielectric layer 100 of a multilayer substrate.
  • 2B shows that after coating a photoresist 104 outside the predetermined position, a metal layer is proliferated at the predetermined position (for example, electroplating).
  • FIG. 2C shows the dielectric after removing the photoresists 10 and 4. Layer 100 and metal layer 102.
  • FIG. 2D shows that the metal layer 102 is etched to remove the metal material outside the predetermined position, and due to the isotropic nature of the wet etching method, the side surface of the metal line 102 is necessarily generated as indicated by the arrow in FIG. 2D. Etching, and limited by the size of the metal grain, results in a rough surface of the metal line.
  • the main object of the present invention is to provide a method for fabricating a multi-layer substrate metal line and a structure thereof, which can form a lower cladding metal layer by forming an upper cladding metal layer or even a bottom surface on an upper surface and a side surface of a metal wiring in an exposure process.
  • Another object of the present invention is to provide a method and a structure for manufacturing a multilayer substrate metal line, which can avoid being eroded or contaminated by other materials of the multilayer substrate, and can produce a fine and reliable food line.
  • the method of manufacturing a multilayer substrate metal wiring of the present invention comprises the following steps:
  • An over cladding metal layer is formed on the surface of the metal line.
  • the under cladding metal layer can be formed at a predetermined position before the metal wiring is formed, that is, the bottom surface of the metal wiring can be covered. After the step of coating the metal layer under the foregoing, covering the bottom surface of the metal line, forming a lower cladding dielectric layer over the lower cladding metal layer, and forming a cladding metal on the upper surface and both side surfaces of the metal wiring Before the step of the layer, an upper cladding dielectric layer is formed, and then the metal wiring, the upper and lower cladding dielectric layers are coated with the metal layer and the lower cladding metal layer forms a coaxial conductor.
  • the multilayer substrate metal wiring structure of the present invention comprises a metal wiring and an upper cladding metal layer.
  • the metal line is located at a predetermined location on the dielectric layer.
  • the upper cladding metal layer is formed on the upper surface and the two side surfaces of the metal circuit, and even the underlying metal layer is formed on the bottom surface to protect the metal circuit, and the upper metal surface of the metal circuit is completely covered with the metal layer as described above,
  • a dielectric layer is formed on the upper and lower sides, and the metal circuit, the upper and lower cladding dielectric layers, the upper cladding metal layer and the lower cladding metal layer can be used as The application of a coaxial wire.
  • the metal line and the cladding metal layer can be formed by only one mask process, and the etching method or the build-up method of the prior art is not used, and the metal is not applied.
  • the side surface of the line is etched to meet the requirements of the fineness of today's metal lines. .
  • the manufacturing method of the present invention forms an upper and lower cladding metal layer on the upper surface and both side surfaces and even the bottom surface of the metal circuit, which can completely protect the metal circuit, avoid erosion or pollution, and improve the reliability of the metal circuit. Can be used as a coaxial wire. Therefore, the metal line density of the multilayer substrate can be further improved.
  • the method for manufacturing a multilayer substrate metal line of the present invention is also applicable to a flexible substrate having deformable or flexible properties.
  • FIG. 1 is a schematic view showing a metal circuit manufactured by an etching method in the prior art
  • FIGS. 2A to 2D are schematic views showing a metal circuit manufactured by a build-up method in the prior art
  • 3A to 3E are flowcharts showing a first embodiment of the method of manufacturing a multilayer substrate metal wiring of the present invention and a structure thereof;
  • 4A to 4F are flowcharts showing a second embodiment of the method of manufacturing a multilayer substrate metal wiring of the present invention and a structure thereof;
  • 5A to 5E are flowcharts showing a third embodiment of the method of manufacturing a multilayer substrate metal wiring of the present invention and a structure thereof;
  • FIGS. 6A to 6F are flowcharts showing a fourth embodiment of the method of manufacturing a multilayer substrate metal wiring of the present invention and a structure thereof.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Figures 3A through 3E, there is shown a flow chart of a first embodiment of a method of fabricating a multi-layer substrate metal circuit of the present invention and a structure thereof.
  • FIG. 3A shows the coating of at least one photoresist layer 304 on the surface of a dielectric layer 300.
  • Fig. 3B shows a step of exposing the photoresist layer 301 other than a predetermined position of the metal wiring after the photoresist layer 304 is applied.
  • 3C shows the step of removing the photoresist layer 301 at a predetermined position, and since the negative resist is selected in the embodiment, when the photoresist layer 301 is removed using a developer (Developer), Since the photoresist layer above the photoresist layer 304 receives more light than the underlying photoresist layer, the edge of the photoresist layer 304 adjacent to the predetermined position forms a structure in which the upper side protrudes from the lower side as shown in the drawing.
  • the present invention is not limited to the use of a negative photoresist, and a double-layer photoresist or the like may be used.
  • a positive photoresist having a double layer of different development rates is coated, and a photoresist layer 301 having a predetermined position on the metal line is exposed.
  • a developer Developer
  • 3D shows a step of forming a metal line 302 at a predetermined position (while a metal layer 303 is also formed over the photoresist layer 304), and an upper cladding metal layer 306 is formed on the surface of the metal line 302 to protect the metal.
  • Figure 3E shows the steps of removing the photoresist layer 304 and the metal layer 303 for subsequent processing.
  • the multilayer substrate metal line manufacturing method of the present invention may further comprise a step of applying an interface adhesion strengthening to the surface 400 of the dielectric layer 300 at a predetermined position. Processing to increase the adhesion strength between the dielectric layer 300 and the metal line 302.
  • FIG. 4A shows the coating of at least one photoresist layer 304 on the surface of a dielectric layer 300.
  • Fig. 4B shows a step of exposing the photoresist layer 301 other than a predetermined position of the metal wiring after the photoresist layer 304 is applied.
  • Fig. 4C shows the step of removing the photoresist layer 301 at a predetermined position, and further includes removing a portion of the dielectric layer 300 at a predetermined position by etching.
  • the photoresist layer 301 when the photoresist layer 301 is removed by using a developer, since the photoresist layer above the photoresist layer 304 receives more light than the lower photoresist layer, it is adjacent to the predetermined position.
  • the edge of the photoresist layer 304 may have a structure in which the upper side protrudes from the lower side as shown in the drawing.
  • the present invention can also produce the same structure by a method such as double-layer photoresist.
  • FIG. 4D shows a step of forming a metal line 302 at a predetermined position (while a metal layer 303 is also formed over the photoresist layer 304), and an upper cladding metal layer 306 is formed on the surface of the metal line 302 to protect the metal.
  • Figure 4E shows the steps of removing the photoresist layer 304 and the metal layer 303 for subsequent processing.
  • the dielectric layer 300 at a predetermined position is a depressed structure. This depressed structure not only increases adhesion enhancement to the dielectric layer 300 when the metal line 302 is formed.
  • the thickness of the metal line 302 can also be adjusted such that the upper surface of the metal line 302 is equal to the surface of the dielectric layer 300 to provide a flat surface for subsequent packaging with other components.
  • the thickness of the metal line 302 is adjusted to fabricate the metal line 302 between the dielectric layer 300 and the dielectric layer 307.
  • the method of manufacturing the multilayer substrate metal line of the present invention may further comprise a step of applying an interface adhesion strengthening treatment to the surface 400 of the dielectric layer 300 at a predetermined position. To increase the adhesion strength between the dielectric layer 300 and the metal line 302.
  • FIGS. 3A to 3C of the first embodiment show a flow chart of a third embodiment of the method of fabricating a multi-layer substrate metal circuit of the present invention and a structure thereof.
  • 5A to 5C are the same as FIGS. 3A to 3C of the first embodiment, and FIG. 5D shows that after the lower cladding metal layer 306-1 is formed at the predetermined position, the metal wiring 302 is formed (also A metal layer 303 is formed over the photoresist layer 304, and an over cladding metal layer 306 is formed on the surface of the metal trace 302 to completely cover the metal trace 302.
  • the method for fabricating a multilayer substrate metal line of the present invention may further comprise the steps of forming a lower cladding dielectric layer on the lower cladding metal layer 306-1 after forming the lower cladding metal layer 306-1 at a predetermined position.
  • an upper cladding dielectric layer is also formed before the upper cladding metal layer 306 is formed on the upper surface and the side surface of the metal wiring 302.
  • the metal line 302, the upper and lower cladding dielectric layers, the upper cladding metal layer 306, and the lower cladding metal layer 306-1 can be applied as coaxial wires to facilitate conduction,
  • the upper cladding metal layer 306 and the lower cladding metal layer 306-1 transmit high frequency signals.
  • an upper cladding dielectric layer may be formed in place of the upper cladding metal layer 3Q6 by vacuum plating.
  • a lower cladding dielectric layer is formed instead of the lower cladding metal layer 306-1 by vacuum plating. Therefore, the bottom surface, the upper surface, and the side surface of the metal line constitute a top and bottom cladding Complete protection of the dielectric layer. As shown in FIG.
  • the multilayer substrate metal wiring manufacturing method of the present invention may further include a step of applying the surface 400 of the dielectric layer 300 at a predetermined position.
  • the adhesion strengthening treatment is performed by an interface to increase the adhesion strength between the dielectric layer 300 and the lower cladding metal layer 306-1.
  • FIGS. 4A to 4C of the second embodiment show a flow chart of a fourth embodiment of the method of fabricating a multilayer substrate metal circuit of the present invention and a structure thereof.
  • 6A to 6C are the same as FIGS. 4A to 4C of the second embodiment, and FIG. 6D shows that after the lower cladding metal layer 306-1 is formed at the predetermined position, the metal wiring 302 is formed (also at A metal layer 303 is formed over the photoresist layer 304, and an over cladding metal layer 306 is formed on the surface of the metal trace 302 for completely covering the metal trace 302.
  • the method for fabricating a multilayer substrate metal line of the present invention may further comprise the steps of forming a lower cladding dielectric layer on the lower cladding metal layer 306-1 after forming the lower cladding metal layer 306-1 at a predetermined position.
  • an upper cladding dielectric layer is also formed before the upper cladding metal layer 306 is formed on the upper surface and the side surface of the metal wiring 302.
  • the metal line 302, the upper and lower cladding dielectric layers, the upper cladding metal layer 306, and the lower cladding metal layer 306-1 can be used as coaxial wires to facilitate conduction.
  • the upper cladding metal layer 306 and the lower cladding metal layer 306-1 transmit high frequency signals.
  • an upper cladding dielectric layer is formed instead of the upper cladding metal layer 306 by vacuum plating.
  • a lower cladding dielectric layer is formed instead of the lower cladding metal layer 306-1 by vacuum plating. Therefore, the bottom surface, the upper surface, and the side surface of the metal wiring constitute a complete protection of the upper and lower cladding dielectric layers. As shown in FIG.
  • the multilayer substrate metal wiring manufacturing method of the present invention may further include a step of applying the surface 400 of the dielectric layer 300 at a predetermined position.
  • the adhesion strengthening treatment is performed by an interface to increase the adhesion strength between the dielectric layer 300 and the under cladding gold layer 306-1.
  • the dielectric layer 300 at the predetermined position is in a depressed configuration.
  • the depressed structure not only increases the formation of metal
  • the adhesion to the dielectric layer 300 is enhanced at line 302.
  • the thickness of the metal line 302 can also be adjusted such that the upper surface of the metal line 302 is equal to the surface of the dielectric layer 300 to provide a flat surface for subsequent packaging with other components.
  • the thickness of the metal line 302 is adjusted to fabricate a metal line between the dielectric layer 300 and the dielectric layer 307, 302, which provides better stress when the multilayer substrate is bent by an external force. Balancing, making flexible multilayer substrates with more characteristic flex properties.
  • the material of the dielectric layer 300 may be polyimide.
  • the metal line 302 can be made of copper.
  • the material of the upper cladding metal layer 306 and the lower cladding metal layer 306-1 may be chromium, titanium, platinum, gold or nickel.
  • the interface adhesion enhancement process can be a plasma process.
  • the metal circuit manufacturing method of the present invention can not only form the upper cladding metal layer 306 on the upper surface of the metal circuit 302, but also simultaneously form the upper cladding metal layer 306 on both sides of the metal circuit 302. In order to completely protect the metal line 302, the metal line 302 is prevented from being corroded or contaminated, and the reliability of the metal line is improved. Further, as in the metal line 302 and the upper cladding metal layer 306 and the lower cladding metal layer 306-1, Forming the upper and lower cladding dielectric layers can be applied as a coaxial wire.
  • the metal line 302 of the present invention is not formed by etching, and is not limited by the size of the metal grain.
  • the surface of the metal line is fine, and the edge of the line is good. Produces a rough surface.
  • the present invention can manufacture the metal line 302 having the upper cladding metal layer 306 and the lower cladding metal layer 306-1 in a single pass exposure process, the size of the metal wiring 302 continues to increase with the circuit of the multilayer substrate.
  • the metal wiring manufacturing method of the present invention can improve the reliability and yield of the multilayer substrate in addition to the fineness of the metal wiring 302 and the simplification of the prior art. '

Description

多层基板金属线路制造方法及其结构
技术领域 本发明是关于一种多层基板金属线路制造方法及其结构， 尤指一种适用于 软性多层基板的多层基板金属线路制造方法及其结 ^。 确
背景技术
认
现今任何类型电子产品的小型化， 是本无可避免的趋势， 随着半导体晶圓制 程尺寸不断地缩小， 后段封装的相关技术也必须随之朝微型化的方向进步。 当 今集成电路的积集度已不断地提高， 其中使用多层基板用以对各种组件进行封 装， 整合成高密度系统已为必然的趋势。 而依据业界的现行作法， 均以蚀刻法 或增层法来制作多层基板的金属线路。 多层基板的电路积集度越高， 金属线路 的尺寸要求便越精细。 、 请参考图 1 , 其显示的是现有技术以蚀刻法制造金属线路的简单示意图。 表示在一多层基板的介电层 100上，先形成一金属层，,涂布光阻 104并曝光后， 以蚀刻法形成金属线路 102的状态。 业界一般均是以湿蚀刻法制造金属线路， 由于湿蚀刻的等向性必然产生如图 1中箭头所示， 对金属线路 102侧表面亦产 生蚀刻， 造成金属线路产生底切 (undercut)结构， 并且受限于金属晶粒 (Grain) 的大小， 造成金属线路粗糙的侧表面。 但是当根据集成电路的积集度不断提高 '的趋势， 金属线路精细度的要求随之不断提高时， 由于前述于金属线路结构底 切、 侧表面粗糙的缺点， 前述蚀刻法已无法满足现今金属线路精细度的要求。 再者， 制造多层基板时， 是使用铜作为金属线路的材料， 在制作介电层或 其它制程时， 容易受到侵蚀或污染， 特别是以聚酰亚胺 (Polyimide)作为介电层 材料时， 如果想在金属线路的表面包覆一保护作用的包覆金属层， 避免受到多 层基板其它材质的侵蚀或污染， 提高金属线路的可靠度， 蚀刻法必须以额外的 曝光、 蚀刻制程方能制作包覆该金属线路的包覆金属层， 而额外的曝光、 蚀刻 制程便可能因金属线路与包覆金属层位置对准的准确性要求， 增加制造多层基 板金属线路失败的可能性， 同时也增加多层基板的制造成本。 并且， 现有技术 的蚀刻法并无法以一次曝光制程即在金属线路的侧表面， 甚至底面形成包覆金 属层， 也就是无法通过完全地包覆金属线路， 来提高金属线路的可靠度， 也无 法制作可作为同轴导线应用的金属线路。
请参考图 2A至图 2D,其显示的是现有技术以增层法制造多层基板金属线 路的示意图。 图 2A表示在一多层基板的介电层 100上， 先形成一非常薄的金 属层 102。 图 2B表示于该预定位置以外涂布一光阻 104后， 再在该预定位置 表面增生一金属层 (例如： 以电铸法, Electroplating) 图 2C表示移除光阻 10、4 后的介电层 100以及金属层 102。 图 2D表示对金属层 102进行蚀刻， 以移除 该预定位置之外的金属材料， 而由于湿蚀刻法的等向性， 也必然产生如图 2D 中箭头所示， 对金属线路 102侧表面产生蚀刻， 并且受限于金属晶粒 (Grain)的 大小， 造成金属线路粗糙的表面。
因此， 无论是蚀刻法或增层法， 均受限于金属晶粒 (Grain)的大小， 金属线 路侧表面必然具有一定的粗糙度， 而当金属线路的尺寸要求越精细时， 此缺点 便会限制金属线路的精细度。 并且无论是蚀刻法或是增层法， 均无法以一次曝 光制程即在金属线路的上表面、 侧表面， 甚至底面形 ^包覆金属层， 而完全地 包覆金属线路， 提高金属线路的可靠度。
因此， 若能发展一种多层基板金属线路制造方法及其结构， 能以一道曝光 制程即在金属线路的上表面、 侧表面， 甚至底面形成包覆金属层， 则能制作精 细、 可靠度高的金属线路， 同时也能制作作为同轴导线应用的金属线路。 发明内容 本发明的主要目的在于提供一种多层基板金属线路制造方法及其结构， 能 以一道曝光制程即在金属线路的上表面、侧表面形成上包覆金属层甚至底面形 成下包覆金属层。
： 本发明的另一目的在于提供一种多层基板金属线路制造方法及其结构， 能 避免受到多层基板其它材质的侵蚀或污染， 制作精细、 可靠度高的食属线路。
为达成本发明的前述目的， 本发明的多层基板金属线路制造方法包含下列 步骤：
. 在介电层表面涂布光阻层；
对光阻层进行曝光， 以定义金属线路的预定位置；
去除位于预定位置的光阻层；
在预定位置形成金属线路； 以及
在金属线路的表面形成上包覆金属层。
本发明的制造方法更可在形成金属线路前， 先在预定位置形成下包覆金属 层， 即可包覆金属线路的底面。 如在前述形成下包覆金属层， 包覆金属线路底 面的步骤后， 再在下包覆金属层上方形成一下包覆介电层， 且在金属线路的上 表面以及两側表面形成上包覆金属层的步骤前， 先形成一上包覆介电层， 则金 属线路、 上下包覆介电层上包覆金属层以及下包覆金属层便形成一同轴导线。
本发明的多层基板金属线路结构包含一金属线路以及一上包覆金属层。金 属线路位于介电层上的预定位置。 上包覆金属层则形成于金属线路的上表面以 及两侧表面， 甚至于底面形成一下包覆金属层， 用以保护金属线路， 且如上下 包覆金属层完整包覆金属线路的上表面、 两侧表面以及底面， 在金属线路与上 下包覆金属层间， 更形成上下包覆介电层， 金属线路、 上下包覆介电层、 上包 覆金属层以及下包覆金属层则可作为一同轴导线的应用。
依据本发明的多层基板金属线路制造方法， 能仅以一道光罩制程即制作金 属线路及其包覆金属层， 且并非使用现有技术的蚀刻法或增层法， 不会对金属 线路侧表面产生蚀刻， 而能满足现今金属线路精细度的要求。。并且， 本发明的 制造方法是在金属线路的上表面以及两側表面、 甚至底面形成上下包覆金属 层， 能完全保护金属线路， 避免受到侵蚀或污染， 而提高金属线路的可靠度， 同时也能作为同轴导线应用。 因此， 能进一步提升多层基板的金属线路密度。 本发明的多层基板金属线路制造方法也适用于具有可变形或可挠曲特性的软 性基板》 附图说明 . 图 1是现有技术以蚀刻法制造金属线路的示意图；
图 2A至图 2D是现有技术以增层法制造金属线路的示意图；
图 3A至图 3E是本发明多层基板金属线路制造方法的第一实施例及其结 构的流程图；
图 4A至图 4F是本发明多层基板金属线路制造方法的第二实施例及其结构 的流程图；
图 5A至图 5E是本发明多层基板金属线路制造方法的第三实施例及其结 构的流程图； 以及
图 6A至图 6F是本发明多层基板金属线路制造方法的第四实施例及其结构 的流程图。 具体实施方式 请参考图 3A至图 3E，其显示本发明多层基板金属线路制造方法的第一实 施例及其结构的流程图。 图 3A表示在一介电层 300表面涂布至少一光阻层 304。 图 3B表示涂布光阻层 304后， 对金属线路的一预定位置以外的光阻层 301进行曝光的步骤。 图 3C表示去除位于预定位置的光阻层 301的步骤， 而 由于本实施例是选用负型光阻， 当使用显影剂 (Developer)去除光阻层 301时， 由于光阻层 304上方的光阻层受光程度比下方的光阻层多， 因此与预定位置相 邻的光阻层 304边缘会形成如图中所示上侧较下侧突出的结构。 然而， 本发明 并非限于使用负型光阻， 使用双层光阻等方法也可， 例如： 涂布双层不同显影 速率的正光阻剂， 对金属线路预定位直的光阻层 301进行曝光， 当使用显影剂 (Developer)去除光阻层 301时， 由于上层光阻层与下层光阻层显影速率不同， 也可形成如前述上侧较下侧突出的结构。 图 3D表示在预定位置形成金属线路 302的步骤后（同时也会在光阻层 304上方形成一金属层 303)， 再在金属线路 302的表面形成一上包覆金属层 306， 用以保护金属线路 302的步骤。 图' 3E表 示移除光阻层 304以及金属层 303 , 以利后续制程进行的步骤。
如图 3D所示， 在预定位置形成金属线路 302的步骤前， 本发明的多层基 板金属线路制造方法可更包含一步骤，对预定位置的介电层 300的表面 400施 以一接口附着强化处理， 以增加介电层 300与金属线路 302间的附着强度。
请参考图 4A至图 4F，其显示本发明多层基板金属线路制造方法的第二实 施例及其结构的流程图。 图 4A表示在一介电层 300表面涂布至少一光阻层 304。 图 4B表示涂布光阻层 304后， 对金属线路的一预定位置以外的光阻层 301进行曝光的步骤。 图 4C表示去除位于预定位置的光阻层 301的步骤后， 更包含一以蚀刻方式去除位于预定位置的介电层 300的部份。 由于本实施例是 选用负型光阻,. 当使用显影剂 (Developer)去除光阻层 301时， 由于光阻层 304 上方的光阻层受光程度比下方的光阻层多， 因此邻接预定位置的光阻层 304边 缘会形成如图中所示上侧较下侧突出的结构。 然而， 如前所述， 本发明也可使 用如双层光阻等的方法， 制作相同的结构。 图 4D表示在预定位置形成金属线 路 302的步骤后（同时也会在光阻层 304上方形成一金属层 303)， 再在金属线 路 302的表面形成一上包覆金属层 306， 用以保护金属线路 302的步骤。 图 4E 表示移除光阻层 304以及金属层 303， 以利后续制程进行的步骤。
在本发明第二实施例中， 由于去除位于预定位置的介电层 300的部份， 所 以预定位置的介电层 300为一下陷的构造。 该下陷的构造不仅可增加形成金属 线路 302时对介电层 300的附着强化。 在形成金属线路 302的步骤中， 也可调 整金属线路 302的厚度， 使金属线路 302的上表面与介电层 300表面等高， 以 提供一平坦表面， 以利与其它组件的后续封装。 或者， 如图 4F所示， 调整金 属线路 302的厚度，以制造介于介电层 300与介电层 307中间的金属线路 302, 当多层基板受外力曲折时， 可提供较佳的应力平衡， 制造更具桡曲特性的软性 多层基板。
图 4D所示在预定位置形成金属线路 302的步骤前， 本发明的多层基板金 属线路制造方法可更包含一步骤， 对预定位置的介电层 300的表面 400施以一 接口附着强化处理， 以增加介电层 300与金属线路 302间的附着强度。
请参考图 5A至图 5E，其显示本发明多层基板金属线路制造方法的第三实 施例及其结构的流程图。图 5A至图 5C所显示的步骤与第一实施例的图 3A至. 图 3C相同， 图 5D表示在该预定位置先形成下包覆金属层 306-1后， 形成金属 线路 302 (同时也会在光阻层 304上方形成一金属层 303), 再在金属线路 302 的表面形成上包覆金属层 306， 用以完全包覆金属线路 302。 再者， 本发明的 多层基板金属线路制造方法可更包含下列步骤， 即在预定位置形成下包覆金属 层 306-1后，在下包覆金属层 306-1上形成一下包覆介电层，且在金属线路 302 的上表面、 侧表面形成上包覆金属层 306前， 也先形成一上包覆介电层。 当应 用于传输高频讯号时，则金属线路 302、该上下包覆介电层、上包覆金属层 306 以及下包覆金属层 306-1能作为同轴导线应用， 以利导通透过、 上包覆金属层 306以及下包覆金属层 306-1传输的高频讯号。
并且， 本发明也可在图 5D所示形成上包覆金属层 306的步骤中， 以真空 镀膜的方式， 形成一上包覆介电层来取代上包覆金属层 3Q6。 且在预定位置形 成金属线路 302前， 也以真空镀膜的方式， 形成一下包覆介电层取代下包覆金 属层 306-1。 因此， 对金属线路的底面、 上表面以及侧表面， 构成一上下包覆 介电层完整的保护。 如图 5D所示， 在预定位置形成下包覆金属层 306-1的步 骤前， 本发明的多层基板金属线路制造方法可更包含一步骤， 对预定位置的介 电层 300的表面 400施以一接口附着强化处理， 以增加介电层 300与下包覆金 属层 306-1间的附着强度。
请参考图 6A至图 6F，其显示本发明多层基板金属线路制造方法的第四实 施例及其结构的流程图。图 6A至图 6C所显示的步骤与第二实施例的图 4A至 图 4C相同， 图 6D表示于该预定位置先形成下包覆金属层 306-1后， 形成金属 线路 302 (同时也会在光阻层 304上方形成一金属层 303)， 再在金属线路 302 的表面形成上包覆金属层 306， 用以完全包覆金属线路 302。 再者， 本发明的 多层基板金属线路制造方法可更包含下列步骤， 即在预定位置形成下包覆金属 层 306-1后，在下包覆金属层 306-1上形成一下包覆介电层，且在金属线路 302 的上表面、 侧表面形成上包覆金属层 306前， 也先形成一上包覆介电层。 当应 用于传输高频讯号时， 则金属线路 302、该上下包覆介电层、上包覆金属层 306 以及下包覆金属层 306-1能作为同轴导线的应用， 以利导通透过上包覆金属层 306以及下包覆金属层 306-1传输的高频讯号。
并且, 本发明也可在图 6D所示形成上包覆金属层 306的步骤中， 以真空 镀膜的方式， 形成一上包覆介电层来取代上包覆金属层 306。 且在预定位置形 成金属线路 302前， 也以真空镀膜的方式， 形成一下包覆介电层取代下包覆金 属层 306-1。 因此， 对金属线路的底面、 上表面以及侧表面， 构成一上下包覆 介电层完整的保护。 如图 6D所示， 在预定位置形成下包覆金属层 306-1的步 骤前, 本发明的多层基板金属线路制造方法可更包含一步骤， 对预定位置的介 电层 300的表面 400施以一接口附着强化处理， 以增加介电层 300与下包覆金. 属层 306-1间的附着强度。
在本发明第四实施例中， 由于去除位于预定位置的介电层 300的部份， 所 以预定位置的介电层 300为一下陷的构造。该下陷的构造不仅可增加形成金属 线路 302时对介电层 300的附着强化。 在形成金属线路 302的步骤中， 也可调 整金属线路 302的厚度， 使金属线路 302的上表面与介电层 300表面等高， 以 提供一平坦表面， 以利与其它组件的后续封装。 或者， 如图 6F所示， 调整金 属线路 302的厚度，以制造介于介电层 300与介电层 307中间的金属线路, 302， 当多层基板受外力曲折时， 可提供较佳的应力平衡， 制造更具特性挠曲特性的 软性多层基板。
在本发明的所有实施例中 ,介电层 300的材质可为聚酰亚胺。金属线路 302 的材质可为铜。 上包覆金属层 306、 下包覆金属层 306-1的材质可为铬、 钛、 铂、 金或者镍等。 接口附着强化处理则可为一电浆制程处理。
值得一提的是， 本发明的金属线路制造方法不仅能于金属线路 302的上表 面形成上包覆金属层 306， 更能同时于金属线路 302的两侧表面同时形成上包 覆金属层 306, 以完全保护金属线路 302， 避免金属线路 302受到侵蚀或污染， 提高金属线路的可靠度， 再者， 如于金属线路 302与上包覆金属层 306、 下包 覆金属层 306-1间， 再形成上下包覆介电层， 则可作为同轴导线应用。
总而言之， 与现有技术相比， 本发明的金属线路 302并非使用蚀刻的方式 形成， 是以不受金属晶粒 (Grain)的大小所限制， 其表面精细， 线缘平直性佳， 不会产生粗糙的表面。 且由于本发明能仅以单一道曝光制程即制造具有上包覆 金属层 306、 下包覆金属层 306-1的金属线路 302， 当金属线路 302尺寸随着 多层基板的电路积集度不断地缩小时， 本发明的金属线路制造方法除能确保金 属线路 302精细度的要求外， 也因相对现有技术较单纯化的制程， 更能提高该 多层基板的可靠度以及良率。 '

Claims

1. 一种多层基板金属线路制造方法，其特征在于： 该制造方法包含下列步 骤： 在一介电层表面涂布至少一光阻层； 对该光阻层进行曝光， 以定义该金属线路的预定位置； 去除位于该预定位置的光阻层； 在该预定位置形成该金属线路； 以及 在该金属线路的表面形成至少一上包覆金属层。
2. 如权利要求 1所述的制造方法， 其特征在于： 该上包覆金属层包覆该 金属线路的上表面以及两侧表面。
3. 如权利要求 1所述的制造方法， 其特征在于： 在该预定位置形成该金 属线路的步骤前， 更包含在该预定位置形成一下包覆金属层的步骤。
4. 如权利要求 3所述的制造方法， 其特征在于： 该下包覆金属层是包覆 该金属线路的一底面。
5. 如权利要求 3所述的制造方法， 其特征在于： 在该预定位置形成该下 包覆金属层的步骤后， 更包含在该下包覆金属层上形成一下包覆介电层的步 骤。
6. 如权利要求 5所述的制造方法， 其特征在于： 在该金属线路的表面形 成该上包覆金属层的步骤前， 更包含在金属线路的表面形成一上包覆介电层， 用以形成一同轴导线的步骤。
7. 如权利要求 6所述的制造方法， 其特征在于： 该上包覆介电层与该下 包覆介电层包覆该金属线路的一底面、 一上表面以及两侧表面。
8. 如权利要求 1所述的制造方法， 其特征在于： 该介电层的材质为聚酰 亚胺。 '
9. 如权利要^ ^ 1所述的制造方法， 其特征在于： 该金属线路的材质为铜。
10. 如权利要求 1所述的制造方法， 其特征在午： 该包覆金属层的材质是 选自铬、 钛、 铂、 金以及镍。
11. 如权利要求 1所述的制造方法， 其特征在于： 在形成该金属线路的步 骤前， 更包含对该预定位置的该介电层的表面施以一接口附着强化处理， 以 增加该介电层与该金属线路间的附着强度的步骤。
12. 如权利要求 11所述的制造方法， 其特征在于： 该接口附着强化处理 为一电浆制程处理。
13. 如权利要求 1所述的制造方法， 其特征在于： 在去除该光阻层的步骤 后， 更包含去除位于该预定位置的该介电层的部份的步骤。
14. 如权利要求 13所述的制造方法， 其特征在于： 在形成该金属线路的 步骤前， 更包含对该预定位置妁该介电层的表面施以一接口附着强化处理， 以增加该介电层与该金属线路间的附着强度的步骤。
15. 一种多层基板金属线路制造方法， 其特征在于： 该制造方法包含下列 步骤： 在一介电层表面涂布至少一光阻层； 对该光阻层进行曝光， 以定义该金属线路的一预定位置； 去除位于该预定位置的该光阻层； 在该预定位置形成该金属线路; 以及 在该金属线路的表面形成至少一上包覆介电层。
16. 如权利要求 15所述的制造方法， 其特征在于： 该上包覆介电层包覆 该金属线路的一上表面以及两侧表面。
17. 如权利要求 15所述的制造方法， 其特征在于： 在该预定位置形成该 金属线路的步骤前， 更包含在该预定位置形成一下包覆介电层的步骤。
18. 如权利要求 17所述的制造方法， 其特征在于： 该下包覆介电层包覆 该金属线路的一底面。
19. 如权利要求 15所述的制造方法， 其特征在于： 该上包覆介电层是以 真空镀膜方式， 形成于该金属线路的表面。
20. 一种多层基板金属线路结构， 该结构包含一金属线路； 其特征在于： 该金属线路位于一介电层上的一预定位置， 该结构还包括一上包覆金属层， 形成于该金属线路的一上表面以及两侧表面。
• 21. 如权利要求 20所述的金属线路结构， 其特征在于： 其更包含一下包 覆金属层， 形成于该金属线路的一底面。
22. 如权利要求 21所述的金属线路结构， 其特征在于： 其更包含一上包 覆介电层以及一下包覆介电层， 形成于该金属线路与该包覆金属层之间， 用 以形成一同轴导线。
23. 如权利要求 20所述的金属线路结构， 其特征在于： 与该预定位置以 外的该介电层相比， 该预定位置的该介电层为一下陷的构造。
24. 如权利要求 20所述的金属线路结构， 其特征在于： 对该预定位置的 该介电层表面施以一接口附着强化处理， 以增加该介电层与该金属线路间的 附着强度。 '
25. 如权利要求 24所述的金属线路结构， 其特征在于： 该接口附着强化 处理为一电浆制程^理。
26. 如权利要求 20所述的金属线路结构， 其特征在于： 该介电层的材质 为聚酰亚胺。
27. 如权利要求 20所述的金属线路结构， 其特征在于： 该金属线路的材 质为铜。
28. 如权利要求 20所述的金属线路结构， 其特征在于： 该包覆金属层的 材质是选自铬、 钛、 铂、 金以及镍。
29. 一种多层基板金属线路结构， 该结构包含一金属线路， 其特征在于： 所述金属线路位于一介电层上的一预定位置， 该结构还包含一上包覆介电层， 形成于该金属线路的一上表面以及两侧表面。
30. 如权利要求 29所述的金属线路结构， 其特征在于： 其更包含一下包 覆介电层， 形成于该金属线路的一底面。
31. 如权利要求 29所述的金属线路结构， 其特征在于： 该上包覆介电层 是以真空镀膜方式， 形成于该金属线路的该上表面以及该两侧表面。
PCT/CN2007/001678 2007-05-24 2007-05-24 Structure et procédé de fabrication d'un câblage métallique sur une carte multicouches WO2008141481A1 (fr)

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EP07721251.2A EP2161973B1 (en) 2007-05-24 2007-05-24 A structure and manufacturing method of metal wiring on multilayered board
KR1020097024333A KR101159514B1 (ko) 2007-05-24 2007-05-24 다층기판 금속배선 제조방법 및 그 구조

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111465202A (zh) * 2020-03-05 2020-07-28 珠海崇达电路技术有限公司 一种提高锣平台精度的钻孔加工方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103547055B (zh) * 2012-07-10 2016-06-08 绿点高新科技股份有限公司 具有电路图案的电路基板的制造方法

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0089604A1 (en) 1982-03-18 1983-09-28 International Business Machines Corporation Method for selectively coating metallurgical patterns on dielectric substrates
US4493856A (en) 1982-03-18 1985-01-15 International Business Machines Corporation Selective coating of metallurgical features of a dielectric substrate with diverse metals
EP0215557A2 (en) 1985-09-13 1987-03-25 Gould Inc. Copper-chromium-polyimide composite
JPH01205495A (ja) * 1988-02-10 1989-08-17 Furukawa Electric Co Ltd:The フレキシブルプリント回路基板の製造方法
US5158657A (en) * 1990-03-22 1992-10-27 Canon Kabushiki Kaisha Circuit substrate and process for its production
US5485352A (en) * 1993-12-27 1996-01-16 Nec Corporation Element joining pad for semiconductor device mounting board
EP1005073A1 (en) 1998-11-27 2000-05-31 Murata Manufacturing Co., Ltd. Method of forming dielectric thin film pattern and method of forming laminate pattern comprising dielectric thin film and conductive thin film
JP2000340901A (ja) * 1999-05-27 2000-12-08 Kyocera Corp 配線基板
US6633045B1 (en) 1999-09-24 2003-10-14 Kabushiki Kaisha Toshiba Assembly part with wiring and for manufacturing system, method of manufacturing such assembly part, and semiconductor manufacturing system constituted using assembly part
CN1505123A (zh) * 2002-12-04 2004-06-16 ������������ʽ���� 电路装置的制造方法
US20050179129A1 (en) 2004-02-16 2005-08-18 Alps Electric Co., Ltd. High-frequency wiring structure and method for producing the same
WO2006134399A1 (en) * 2005-06-15 2006-12-21 Bae Systems Plc Transmission line
WO2007037553A1 (ja) * 2005-09-30 2007-04-05 Zeon Corporation 金属配線付き基板の製造方法
CN1957298A (zh) * 2004-04-06 2007-05-02 麦克德米德有限公司 在基材上形成金属图案的方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5062731A (zh) * 1973-10-05 1975-05-28
US4339305A (en) * 1981-02-05 1982-07-13 Rockwell International Corporation Planar circuit fabrication by plating and liftoff
JPH03229484A (ja) * 1990-02-05 1991-10-11 Fujikura Ltd プリント配線板の製造方法
JP2001177951A (ja) * 1999-12-15 2001-06-29 Yazaki Corp 導電回路構造
JP2002261189A (ja) * 2001-03-05 2002-09-13 Murata Mfg Co Ltd 高周波用回路チップ及びその製造方法
JP2005317836A (ja) * 2004-04-30 2005-11-10 Nitto Denko Corp 配線回路基板およびその製造方法
JP4351129B2 (ja) * 2004-09-01 2009-10-28 日東電工株式会社 配線回路基板

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0089604A1 (en) 1982-03-18 1983-09-28 International Business Machines Corporation Method for selectively coating metallurgical patterns on dielectric substrates
US4493856A (en) 1982-03-18 1985-01-15 International Business Machines Corporation Selective coating of metallurgical features of a dielectric substrate with diverse metals
EP0215557A2 (en) 1985-09-13 1987-03-25 Gould Inc. Copper-chromium-polyimide composite
JPH01205495A (ja) * 1988-02-10 1989-08-17 Furukawa Electric Co Ltd:The フレキシブルプリント回路基板の製造方法
US5158657A (en) * 1990-03-22 1992-10-27 Canon Kabushiki Kaisha Circuit substrate and process for its production
US5485352A (en) * 1993-12-27 1996-01-16 Nec Corporation Element joining pad for semiconductor device mounting board
EP1005073A1 (en) 1998-11-27 2000-05-31 Murata Manufacturing Co., Ltd. Method of forming dielectric thin film pattern and method of forming laminate pattern comprising dielectric thin film and conductive thin film
JP2000340901A (ja) * 1999-05-27 2000-12-08 Kyocera Corp 配線基板
US6633045B1 (en) 1999-09-24 2003-10-14 Kabushiki Kaisha Toshiba Assembly part with wiring and for manufacturing system, method of manufacturing such assembly part, and semiconductor manufacturing system constituted using assembly part
CN1505123A (zh) * 2002-12-04 2004-06-16 ������������ʽ���� 电路装置的制造方法
US20050179129A1 (en) 2004-02-16 2005-08-18 Alps Electric Co., Ltd. High-frequency wiring structure and method for producing the same
CN1957298A (zh) * 2004-04-06 2007-05-02 麦克德米德有限公司 在基材上形成金属图案的方法
WO2006134399A1 (en) * 2005-06-15 2006-12-21 Bae Systems Plc Transmission line
WO2007037553A1 (ja) * 2005-09-30 2007-04-05 Zeon Corporation 金属配線付き基板の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2161973A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111465202A (zh) * 2020-03-05 2020-07-28 珠海崇达电路技术有限公司 一种提高锣平台精度的钻孔加工方法

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