CN1505123A - 电路装置的制造方法 - Google Patents

电路装置的制造方法 Download PDF

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Publication number
CN1505123A
CN1505123A CNA200310119584A CN200310119584A CN1505123A CN 1505123 A CN1505123 A CN 1505123A CN A200310119584 A CNA200310119584 A CN A200310119584A CN 200310119584 A CN200310119584 A CN 200310119584A CN 1505123 A CN1505123 A CN 1505123A
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Prior art keywords
manufacture method
plasma
conductive foil
separating tank
conductive pattern
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CN100418202C (zh
Inventor
ʾ
臼井良辅
水原秀树
五十岚优助
坂本则明
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Publication of CN1505123A publication Critical patent/CN1505123A/zh
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Abstract

一种电路装置的制造方法，使用等离子体除去导电图案21表面上黏附的污染物，提高导电图案21和密封树脂28的粘附。通过选择地蚀刻导电箔10形成分离槽11，形成导电图案21。在导电图案21的规定位置安装半导体元件22A等电路元件，并和导电图案21电连接。通过自导电箔10上方照射等离子体除去分离槽11表面黏附的污染物。

Description

电路装置的制造方法
技术领域
本发明涉及电路装置的制造方法，特别是涉及通过在导电箔上照射等离子体除去其表面黏附的残渣的电路装置的制造方法。
背景技术
近年来，由于在电子设备上设置的电路装置被使用在手机、笔记本电脑等上，因而寻求小型化、薄型化及轻量化。例如，在作为电路装置的半导体装置中，为满足这样的所需而开发了被称为CSP(Chip size package(芯片尺寸封装))的，和芯片尺寸相同或稍大尺寸的半导体装置。但是，在一般的CSP中，为支撑装置整体必须使用玻璃环氧树脂衬底或陶瓷衬底等作为支撑衬底的构成要素。由此，由于支撑衬底为厚的部件，因而具有半导体装置整体尺寸变大等问题。
鉴于上述这样的问题而开发了不需要支撑衬底的电路装置(例如，参照专利文献1)。以下说明该电路装置的制造方法。
参照图10(A)，准备由铜等金属构成的导电箔100，形成实现规定电气电路这样的导电图案100A。作为形成分离槽的方法可由使用耐蚀刻掩膜的公知的蚀刻工序进行。
参照图10(B)，在导电图案100A表面固定电路元件。作为电路元件，电容或电阻等片状部件103及半导体元件102等被固定。另外，半导体元件102的电极和导电图案100A介由金属细线电连接。
参照图(C)，利用密封树脂105进行覆盖，由前工序固定的电路元件被覆盖，在导电箔100的分离槽101中也填充密封树脂。
参照图10(D)，将导电箔100自背面进行蚀刻，直至露出在分离槽101中填充的密封树脂105，进行导电箔100的除去。由此，各导电图案100A被电分离。然后，进行抗焊剂的形成和外部电极的形成等。最后，通过由点划线位置切割密封树脂105将各电路装置分离。由上述的工序制造不需要支撑衬底的电路装置。
另外，进行由金属构成的图案表面上黏附的污染物的除去等的技术有照射等离子体的技术。参照图11说明在安装半导体装置的引线架上照射等离子体来除去表面黏附的污染物的方法。
参照图11(A)说明经过进行引线架加工的工序及元件安装的工序等后引线架110的结构。在接合面状形成的岛114上安装半导体元件112，并包围岛114设置多条引线111。另外，引线111与半导体元件112表面设置的电极相对应，且各电极介由金属细线113和引线111电连接。
参照图11(B)说明进行等离子体照射的工序。首先，在密封的容器内部载置引线架110。其次，将气体导入容器内部，通过放电生成等离子体气体。而后，在等离子体气体中存在的自由基或离子在引线架110表面碰撞进行引线架110表面的清洗。
专利文献1
特开2002-076246号公报(第7页，图1)
发明内容
但是，在所述的电路装置的制造方法中，具有如下问题，由于直至进行树脂密封的工序等，导电箔100表面被污染。该污染物考虑有分离槽101的形成工序使用的蚀刻剂中包含的有机性残渣或空气中的尘埃等。另外，当在所述这样的污染物黏附在导电箔100的表面上的状态下进行密封树脂105的密封时，密封树脂105和导电箔100的黏附力会降低。
另外，在利用图11所示的离子照射进行的引线架的清洗方法中，由于以复杂的形状加工，以形成岛114或引线111，因而通过离子照射在引线架110上会产生局部电位的增加。因此，引线架局部的电位差介由金属细线113把电流流入半导体元件112上，会使在半导体元件表面形成的CMOS等元件被击穿。另外，由于在等离子体照射的工序中引线架110形成高温，故具有引线变形和金属细线113折断的问题。
本发明是鉴于这样的问题而开发的，本发明的主要目的在于，提供通过在导电箔表面照射等离子体进行导电箔表面的清洗及粗糙化的电路装置的制造方法。另外，本发明的主要目的在于，提供解决在使用等离子体除去导电性材料表面黏附的污染物时产生的半导体元件的击穿等问题的电路装置的制造方法。
本发明提供一种电路装置的制造方法，其包括如下工序：在导电箔上形成自表面形成分离槽且底部连结为一体的导电图案的工序；在所述导电图案的所需位置安装电路元件的工序；由树脂层密封，以覆盖所述电路元件，且填充在所述分离槽中的工序，其中，在所述导电箔表面照射等离子体。通过在导电箔表面照射等离子体可除去导电箔表面黏附的污染物，另外，可将导电箔表面粗糙化，提高和绝缘性树脂的粘附。
另外，本发明的特征在于，在进行安装电路元件的工序之前，进行所述等离子体的照射。这样，在导电箔上未安装电路元件的状态下进行等离子体照射，可在导电箔整体上进行等离子体照射。从而，可在载置电路元件的规定的导电箔及分离槽的区域进行等离子体照射。
本发明提供一种电路装置的制造方法，其包括如下工序：在导电箔上形成自表面形成分离槽且底部连结为一体的导电图案的工序；在所述导电图案的所需位置安装电路元件的工序；在所述导电箔表面包括所述电路元件上照射等离子体的工序；由树脂层密封，以覆盖所述电路元件，且填充在所述分离槽中的工序，由于本发明的导电图案由底部连结，故在照射等离子体的工序中不产生局部的电位差，可抑制半导体元件等电路元件被击穿的现象。另外，由于导电图案作为导电箔形成一体，故会减少通过进行等离子体照射的工序加热引起的变形，从而，可抑制连接电路元件和导电图案的金属细线的变形或折断。
另外，本发明的特征在于，利用所述等离子体清除在所述分离槽表面黏附的污染物。由于照射的等离子体由分离槽表面反射，故利用反射的等离子体进一步地提高其清洗效果。另外，利用等离子体照射使导电箔表面粗糙化，提高导电图案和绝缘性树脂的粘附性。
附图说明
图1是说明本发明电路装置制造方法的剖面图(A)，平面图(B)；
图2是说明本发明电路装置制造方法的剖面图；
图3是说明本发明电路装置制造方法的剖面图(A)，平面图(B)；
图4是说明本发明电路装置制造方法的剖面图；
图5是说明本发明电路装置制造方法的剖面图(A)，剖面图(B)，剖面图(C)；
图6是说明本发明电路装置制造方法的剖面图(A)，平面图(B)；
图7是说明本发明电路装置制造方法的剖面图；
图8是说明本发明电路装置制造方法的平面图；
图9是说明本发明电路装置制造方法的剖面图；
图10是说明现有的电路装置制造方法的剖面图(A)，剖面图(B)，剖面图(C)，剖面图(D)；
图11是说明现有的电路装置制造方法的平面图(A)、剖面图(B)。
具体实施方式
本发明电路装置的制造方法包括如下工序：在导电箔10上形成自表面形成分离槽11并由底部连结为一体的导电图案21的工序；在导电图案21的规定位置安装电路元件22的工序；由密封树脂28密封，以覆盖电路元件22且填充在分离槽11中的工序，在导电箔10表面照射等离子体制造电路装置。等离子体的照射有两种方法，第一方法是，在进行电路元件22的安装前进行等离子体照射的方法，第二方法是，在进行电路元件22的安装后进行等离子体照射的方法。以下详细说明所述的各工序。
本发明的第一工序是，如图1～图3所示，在导电箔10上形成自表面形成分离槽11并由底部连结为一体的导电图案21的工序。
在本工序中，首先如图1(A)，准备片状导电箔10。该导电箔10考虑焊剂的黏附性、接合性、镀敷性来选择其材料，其材料采用以Cu为主材料的导电箔、以Al为主材料的导电箔或以Fe-Ni等合金构成的导电箔等。
具体地说，如图1(B)所示，在矩形的导电箔10上4～5个形成多个搭载部的模块12被间隔排列。在各模块12之间设有缝隙13，以吸收由模制工序等的加热处理产生的导电箔10的应力。另外，在导电箔10的上下周端以一定间隔设置标示孔14，用于各工序的定位。接着形成每个模块的导电图案21。
首先，如图2所示，在导电箔10上形成光致抗蚀剂(耐蚀刻掩膜)PR，并对光致抗蚀剂PR制图，使除去形成导电图案21的区域外的导电箔10露出。而后，如图3(A)所示，介由光致抗蚀剂PR选择地蚀刻导电箔10。利用蚀刻形成的分离槽11的深度为例如50um，由于其侧面为粗面，故和密封树脂28的粘接性被提高。
另外，该分离槽11的侧壁根据除去方法不同而形成不同结构。该除去工序可采用通过湿蚀法、干蚀法、激光蒸发和切割。在湿蚀法时，蚀刻剂主要采用氯化铁或氯化铜，导电箔10或浸渍在该蚀刻剂中，或由该蚀刻剂喷射。在此，由于湿蚀法一般被非各向异性蚀刻，故侧面形成弯曲结构。
图3(B)显示具体的导图案21。本图放大显示一个图1(B)所示的模块12。虚线包围的部分的一个是一个搭载部15，构成导电图案21，并在一个模块12上以五行十列矩阵状配列多个搭载部15，在每一个搭载部15上设置相同的导电图案21。
本发明的第二工序在于，如图4所示，在导电图案21的规定位置安装电路元件22。电路元件22为晶体管、二极管、IC芯片等半导体元件和片状电容、片状电阻等无源元件。另外，虽然厚度会加厚，但也可以安装CSP、BGA等倒装的半导体元件。
在此，在导电图案21上安装裸的半导体元件22，介由金属细线电连接半导体元件22A的电极和导电图案21。另外，标号22B是片状电容或无源元件等片状部件，由焊锡等焊剂24等导电膏固定。
参照图5，本发明的第三工序在于，在导电箔10表面包括电路元件22上照射等离子体进行清洗。图5(A)是显示进行等离子体清洗的概要图，图5(B)是在一个搭载部15上进行等离子体照射的状况的剖面图。
参照图5(A)说明利用等离子体照射进行的清洗。等离子体清洗机30包括：上段电极31，其设置在密封容器34内部；下段电极32，其与上段电极31相对设置，在上部载置导电箔10。另外，设有向容器内部供给气体的注入口35和进行其排气的排气口36。上段电极31和下段电极32的任意一方和高频电源连接，未和电源连接的电极接地。
进行导电箔表面污染物的等离子体清洗有两种方法，即，化学蚀刻和物理蚀刻。在化学蚀刻中包括DP(Direct Plazma)或PE(Plazma Etching)，可使用氧气作为气体。在物理、化学蚀刻中包括RIE(Reactive Ion Etching)，可使用氩气、氖气或氦气作为气体。在化学蚀刻中，可使用化学效果除去有机物污染物，在物理蚀刻中，可使用喷射效果除去有机物及无机物污染物。在本发明中，可使用任何一种方法。
参照图5(B)详细说明利用等离子体进行的清洗。在本发明中，等离子体照射在导电箔10的整个区域上进行。具体地说，使放电生成的等离子体33中的离子在导电箔10整个表面碰撞。从而，离子在导电图案21表面、分离槽11、电路元件22及金属细线25上碰撞，来除去这些表面黏附的有机或无机污染物。
在分离槽11侧面黏附有蚀刻工序中使用的蚀刻剂的残渣或空气中的尘埃等污染物，这些污染物也利用等离子体清洗被除去。另外，由于分离槽11通过蚀刻形成，故其侧面形成曲面。从而，自上方进入的离子由分离槽11的侧面反射，故一个离子会多次在分离槽11侧面碰撞。由此，在分离槽11侧面，采用离子进行的表面清洗效果很大，故分离槽11侧面黏附的有机及无机污染物被除去。
另外，各导电图案21利用在作为一片金属箔的导电箔10上形成浅的分离槽被制图，并连结为一体。从而，各导电图案21在电气一体化的导电箔10的状态下被保持，因此，即使暴露在等离子体的影响下，也可抑制各导电图案引起的电位差的产生。由此，即使半导体元件22A是极其容易电压击穿的CMOS等，也可将给予半导体元件22的损伤抑制到最小。
另外，利用等离子体清洗，分离槽11的侧面被粗糙化。从而，提高了由以后的工序形成的密封树脂28和分离槽11的侧面的粘附性。在此，由于分离槽11的侧面是导电图案21侧面，因此，导电图案21和密封树脂23的粘附性得到提高，可防止导电图案21的剥离等。
另外，由于等离子体清洗，导电图案21被加热，但是，由于导电图案21作为导电箔10成为一体，故防止了导电图案21局部的热膨胀或变形。从而，可抑制由于导电图案21的膨胀或变形引起的金属细线25的弯曲或折断。
通过向进行等离子体清洗的气体中混入氧气，可将导电箔10的表面氧化。这样，通过将表面氧化，可进一步提高密封树脂25和导电图案21的粘附性。
参照图5(C)，在以上的本工序说明中，是对安装电路元件22的导电箔10进行等离子体照射，但也可对在进行电路装置22安装之前的导电箔10进行等离子体照射。通过在未安装电路元件22的状态下进行等离子体照射，可在导电箔10的整个表面上进行等离子体照射。即，在图示的状态下，在进行等离子体照射的导电箔10的表面及分离槽11和上段电极31之间未阻断等离子体照射。由此，导电箔10表面及分离槽11整面地进行等离子体照射，进行这些表面的污染物的除去及表面的粗糙化。
参照图6，本发明的第四工序在于，利用密封树脂28进行密封，覆盖电路元件22，并在分离槽11中填充密封树脂28。
参照图6(A)说明进行树脂密封后的状态。密封树脂28覆盖电路元件22及多个导电图案21，在导电图案21之间的分离槽11填充密封树脂28，以和各导电图案21例面的弯曲结构嵌合并紧固结合。而后，利用密封树脂28支撑导电图案21。另外，在本工序中，可使用环氧树脂等热塑性树脂进行传递模模制。采用本工序的优点是，在覆盖密封树脂28之前，使作为导电图案21的导电箔10作为支撑衬底。由此，具有可极其节省构成材料来作业的优点，也可实现成本的降低。
其次，参照图7，通过将未设置分离槽11的厚度部分的导电箔10除去，电分离各导电图案21。具体地说，将未设置分离槽11的厚度部分的导电箔10的模块12的至少设置导电图案21的区域除去。在本工序中，如图7所示，将导电箔10背面进行整面蚀刻直至露出密封树脂28。其结果形成在密封树脂28上露出导电图案21背面的结构。
本发明的第五工序在于，如图8所示，通过按每各搭载部15切割，将模块12的密封树脂28分离。
在本工序中，在切割装置载置台上利用真空吸附在粘结板上粘贴的多个模块12，由切割刀32沿各搭载部15之间的切割线切割分离槽11的密封树脂28，分离出一个个电路装置。
参照图9说明由所述的工序制造的电路装置的构成。同图显示的电路装置包括：导电图案21；电路元件22，其固定在导电图案21上；金属细线22，其电连接半导体元件22A和导电图案21；密封树脂28，露出导电图案21的背面，进行整体的支撑及密封。另外，自密封树脂28背面露出的导电图案21由抗蚀剂26覆盖，在规定位置形成由焊锡等焊剂构成的外部电极27。
利用本发明电路装置的制造方法可得到以下所示的效果。
第一，由于在形成分离导电图案21的分离槽11的导电箔10的表面进行等离子体照射，因此，可进行在表面黏附的污染物的除去及表面的粗糙化。由此可提高导电图案21和密封树脂28的粘附。
第二，通过在进行电路装置22的安装之前进行等离子体照射，可在导电箔10的表面及分离槽11中整面地进行等离子体照射，可进一步提高污染物的除去及表面粗糙化的效果。
第三，也可在进行电路元件22的安装之后进行等离子体照射。由于在导电图案21作为导电箔10电气一体化的状态下进行等离子体清洗，因此，可抑制因等离子体影响在导电图案21上产生局部的电位差的现象。从而，可抑制由等离子体影响产生的电位差给予半导体元件22的损伤。另外，也可以进行金属细线25及电路元件22表面的清洗及粗糙化。
第四，由于自导电箔10上方进入的离子，由分离槽11的侧面反射，因此，可进一步提高由等离子体照射进行的除去污染物的效果。
第五，由于可利用等离子体使分离槽11侧面粗糙化，故可进一步提高密封树脂28和导电图案21的粘附性。
第六，由于可利用等离子体照射除去分离槽11表面的黏附物，因此，填充在分离槽11中、在背面露出的密封树脂28的露出面上附着物不会除去。从而，可加强自分离槽11露出的密封树脂28和抗蚀剂26的附着强度。
在本发明中，通过在导电箔表面照射等离子体可进行导电箔表面的清洗及粗糙化。另外，可解决使用等离子体除去导电性材料表面黏附的污染物时产生的半导体元件的击穿等问题。

Claims (13)

1、一种电路装置的制造方法，其特征在于，包括如下工序：在导电箔上形成自表面形成分离槽而底部连结为一体的导电图案的工序；在所述导电图案的所需位置安装电路元件的工序；由树脂层密封，以覆盖所述电路元件，且填充在所述分离槽中的工序，其中，在所述导电箔表面照射等离子体。
2、一种电路装置的制造方法，其特征在于，包括如下工序：在导电箔上形成自表面形成分离槽而底部连结为一体的导电图案的工序；在所述导电图案的所需位置安装电路元件的工序；对所述导电箔表面包括所述电路元件照射等离子体的工序；由树脂层密封，以覆盖所述电路元件，且填充在所述分离槽中的工序。
3、如权利所需1所述的电路装置的制造方法，其特征在于，在安装所述电路元件的工序之前进行所述等离子体照射。
4、如权利所需1所述的电路装置的制造方法，其特征在于，在安装所述电路元件的工序之后进行所述等离子体照射。
5、如权利所需1或2所述的电路装置的制造方法，其特征在于，利用所述等离子体除去所述分离槽表面黏附的污染物。
6、如权利所需5所述的电路装置的制造方法，其特征在于，所述污染物由有机物或无机物构成。
7、如权利所需1或2所述的电路装置的制造方法，其特征在于，利用所述等离子体照射将所述分离槽表面粗糙化。
8、如权利所需1或2所述的电路装置的制造方法，其特征在于，利用所述等离子体照射使所述分离槽表面氧化。
9、如权利所需1或2所述的电路装置的制造方法，其特征在于，使用氧气进行所述等离子体的照射。
10、如权利所需1或2所述的电路装置的制造方法，其特征在于，使用惰性气体氩气、氖气、氦气进行所述等离子体照射。
11、如权利所需1或2所述的电路装置的制造方法，其特征在于，所述导电箔由以铜为主材料的金属构成。
12、如权利所需1或2所述的电路装置的制造方法，其特征在于，所述电路元件是半导体元件，并介由金属细线和所述导电图案电连接。
13、如权利所需1或2所述的电路装置的制造方法，其特征在于，在所述导电箔背面，通过除去所述导电箔背面直至露出所述树脂层，将所述各导电图案电分离。
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