WO2008093957A1 - Module haute fréquence et son procédé de fabrication - Google Patents

Module haute fréquence et son procédé de fabrication Download PDF

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Publication number
WO2008093957A1
WO2008093957A1 PCT/KR2008/000411 KR2008000411W WO2008093957A1 WO 2008093957 A1 WO2008093957 A1 WO 2008093957A1 KR 2008000411 W KR2008000411 W KR 2008000411W WO 2008093957 A1 WO2008093957 A1 WO 2008093957A1
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WO
WIPO (PCT)
Prior art keywords
high frequency
signal processor
signal
module
frequency module
Prior art date
Application number
PCT/KR2008/000411
Other languages
English (en)
Inventor
Kyung Joo Son
Original Assignee
Lg Innotek Co., Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020070009700A external-priority patent/KR101349504B1/ko
Priority claimed from KR1020070009698A external-priority patent/KR101338563B1/ko
Application filed by Lg Innotek Co., Ltd filed Critical Lg Innotek Co., Ltd
Publication of WO2008093957A1 publication Critical patent/WO2008093957A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
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    • H01L2924/151—Die mounting substrate
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Definitions

  • the embodiment relates to a high frequency module and a manufacturing method thereof.
  • wireless communication terminals such as cell phones, PDAs (personal digital assistants), smart phones and DMB (digital multimedia broadcasting) terminals
  • PDAs personal digital assistants
  • DMB digital multimedia broadcasting terminals
  • the embodiment provides a high frequency module capable of inter-shielding chip parts interfering with each other on a module board, and a manufacturing method thereof.
  • the embodiment provides a high frequency module having internal and external shield structures, and a manufacturing method thereof.
  • the embodiment provides a high frequency module comprising: a module board comprising a plurality of signal processors; a resin member on module board; a plating layer on resin member; and an internal shielding part formed between the signal processors.
  • the embodiment provides a high frequency module comprising: a module board; a first signal processor with a packaged chip part for processing a first signal on the module board; a second signal processor with a packaged chip part for processing a second signal on the module board; a third signal processor with a packaged chip part for switching a path of the first and second signals on the module board; and an internal shileding part formed in at least one of boundary areas among the first signal processor, the second signal processor and the third signal processor.
  • the embodiment provides the method for manufacturing the high frequency module comprising: arranging ground patterns among signal processing areas on a module board; mounting chip parts at the signal processing areas on the module board; forming a resin member on the module board; forming a shield groove on the ground patterns of the module board through the resin member; and forming a plating layer on the resin member and in the shield groove.
  • chip parts interfering each other in a high frequency module are inter-shielded, so that interference between the chip parts can be minimized.
  • a plating layer is formed in areas among chip parts and on the ground pattern of the edge of a module board, so that the electrical reliability of a high frequency module can be improved.
  • chip part areas are inter- shielded from each other, so that intervals among the chip part areas can be reduced.
  • a shield can is not used, so that the number of assembly parts can be reduced and the assembly process can be simplified.
  • grounding is automatically achieved during a plating process of the plating layer, so that a ground structure can be simplified.
  • a high frequency module can be fabricated in a small size and be integrated with high density.
  • FIG. 1 is a side sectional view showing a high frequency module according to an embodiment
  • FIGS. 2 to 8 are views illustrating the manufacturing process of a high frequency module according to an embodiment. Best Mode for Carrying Out the Invention
  • FIG. 1 is a side sectional view showing the high frequency module according to the embodiment.
  • the high frequency module 100 comprises a module board 110, chip parts 121 and 123, passive devices 122 and 124, a resin member 130, a plating layer 140 and an internal shielding part 150.
  • a high frequency module 100 is obtained by modularizing parts that process RF signals in various wireless commu- nication apparatuses such as portable terminals.
  • the module board 110 comprises a ceramic substrate using HTCC (high temperature co-fired ceramic) or LTCC (low temperature co-fired ceramic), a silicon substrate, an MCPCB (metal core PCB), a common PCB (printed circuit board) and the like.
  • the embodiment is not limited thereto.
  • the wiring patterns 111 to 115 comprise routing patterns, line patterns, bonding patterns 112, patterns 111 for a bare die, patterns for connecting vias, first and second ground patterns 114 and 115 and the like.
  • Bare-die-type chip parts 121 and 123 adhere on the patterns 111 for a bare die and are connected to the bonding patterns 112 through a wire 129.
  • the passive devices 122 and 124 are soldered to the bonding patterns 112. Further, flip-type chip parts may also be mounted on the patterns 111 in a flip type.
  • the first ground pattern 114 is formed at the edge of the module board 110, and at least one second ground pattern 115 is formed at the inner side of the module board 110.
  • the first and second ground patterns 114 and 115 can be electrically connected to the patterns 111 for a bare die, or are electrically connected to the ground of a bottom layer through a via, a via hole 119 or a through hole.
  • the module board 110 may be divided into a first signal processor 101, a second signal processor 102 and a third signal processor (not shown) according to the characteristics of signal processing.
  • the first signal processor 101 processes a transmission signal, which is a first signal, and comprises the chip parts 121 and passive device 122 that process a transmitted high frequency signal.
  • the second signal processor 102 processes a received signal, which is a second signal, and comprises the chip parts 123 and passive device 124 that process a received high frequency signal.
  • the third signal processor switches a path of the first and second signals and comprises a high frequency switch such as a duplexer.
  • the second ground patterns 115 can be arranged in a boundary area B2 between the first and second signal processors 101 and 102 and a boundary area between other signal processors, respectively.
  • the resin member 130 is formed on the module board 110.
  • the resin member 130 is molded by a predetermined position in order to protect the chip parts 121 and 123, the passive devices 122 and 124 arranged on the module board 110.
  • the resin member 130 is formed a height higher than that of the chip parts 121 and 123, the passive devices 122 and 124, or the wire 129.
  • the resin member 130 can be prepared in the form of one of an epoxy molding compound, poly phenylene oxide, epoxy sheet molding and silicon.
  • the plating layer 140 for electronic shielding is formed on the resin member 130.
  • the plating layer 140 is connected to the first and second ground patterns 114 and 115, so that harmful electromagnetic waves introduced into the chip parts 121 and 123 or emitted to the exterior can be blocked.
  • the internal shileding part 150 is formed in the boundary area between the signal processors on the module board 110.
  • the internal shileding part 150 is formed between the first and second signal processors 101 and 102, and comprises the second ground pattern 115, a shield groove 132 and a ground connection terminal 141.
  • the second ground pattern 115 is formed along the boundary area B2 between the first and second signal processors 101 and 102, and may have a bent shape if the situation requires.
  • the shield groove 132 is formed in the resin member 130 on the second ground pattern 115 to partially expose the second ground pattern 115.
  • the shield groove 132 may have a circular shape, a quadrangular shape or a rectangular shape. At least one shield groove 132 may be formed on the second ground pattern 115.
  • the ground connection terminal 141 is a part of the plating layer 140 and is electrically connected to the second ground pattern 115 through the shield groove 132.
  • Such a ground connection terminal 141 is prepared in the form of column or wall.
  • the internal shileding part 150 is formed between the first and second signal processors 101 and 102 to prevent interference from being generated between the chip part 121 of the first signal processor 101 and the chip part 123 of the second signal processor 102. That is, the internal shileding part 150 prevents interference, which may be generated between the chip parts 121 and 123 of the first and second signal processors 101 and 102 packaged in the high frequency module 100.
  • the outer side 145 of the plating layer 140 is located at the outer side of the module board 110.
  • the outer side end 143 of the plating layer 140 is electrically connected to the first ground pattern 114, so that electromagnetic waves can be prevented from being emitted to the exterior.
  • the internal shileding part 150 is provided between the areas, in which signal interference is generated, according to the operational characteristics of the high frequency module 100, so that the areas do not interfere with each other. Further, the plating layer 140 for electronic shielding is electrically connected to the first and second ground patterns 114 and 115, so that EMI/EMC phenomenon can be prevented.
  • FIGS. 2 to 8 are views illustrating the manufacturing process of the high frequency module according to the embodiment.
  • FIG. 2 is a side sectional showing an example in which chip parts are arranged on the module board.
  • a tin copper layer is patterned on the module board 110, so that the wiring patterns 111 to 115 designed in advance are formed.
  • the wiring patterns 111 to 115 comprise routing patterns, line patterns, bonding patterns 112, patterns 111 for a bare die, patterns for connecting vias, first and second ground patterns 114 and 115 and the like.
  • the bare-die-type chip parts 121 and 123 adhere on the patterns 111 for a bare die and are electrically connected to the bonding patterns 112 through the wire 129.
  • the passive devices 122 and 124 are soldered to the bonding patterns 112. Further, flip-type chip parts may also be mounted on the patterns 111 in a flip manner.
  • the first ground pattern 114 is selectively arranged at the edge of the module board
  • the second ground pattern 115 is arranged at the boundary part between the first and second signal processors 101 and 102.
  • the first and second ground patterns 114 and 115 are electrically connected to the ground of a bottom layer through a via, a through hole or a via hole 119.
  • FIG. 3 is a plan view schematically showing a state in which the chip parts and the ground patterns in FIG. 2 are arranged.
  • the second to fourth ground patterns 115 to 117 are arranged in areas among the signal processors 101 to 103, respectively.
  • the ground pattern arranged in the areas among the signal processors will be referred to as the second to fourth ground patterns.
  • the second ground pattern 115 is arranged in the boundary area between the first and second signal processors 101 and 102
  • the third ground pattern 116 is arranged in the boundary area between the second and third signal processors 102 and 103
  • the fourth ground pattern 117 is arranged in the boundary area between the first and third signal processors 101 and 103.
  • the fifth ground pattern 118 is arranged at the outer side of the first signal processor 101.
  • the ground patterns 115 to 118 can be prepared in the form of at least one pattern.
  • the first signal processor 101 processes a transmitted signal and comprises parts such as a modulator, a phase locked loop, a power and gain amplifier, a transmission filter and a transmitter.
  • the chip part 121 can be defined as a transmitter.
  • the second signal processor 102 processes a received signal and comprises chip parts such as an LNA (low noise amplifier), a receive filter (Rx SAW filter), a frequency mixer, a demodulator, and a receiver.
  • the chip part 123 can be prepared in the form of a receiver.
  • the third signal processor 103 switches a path of a transmitted signal or a received signal and comprises chip parts such as at least one high frequency switch 125, i.e. a duplexer. Further, a baseband section may also be comprised in a specific area, and active devices, the passive devices 122 and 124 and the like may also be additionally mounted at the processors 101 to 103. The embodiment is not limited thereto.
  • the embodiment can comprise two signal processors 101 and 102 or more according to the operation characteristics of the high frequency module that processes a high frequency signal.
  • the embodiment is not limited thereto.
  • chip parts such as the receiver 123 and the transmitter 121 of the chip parts as described above, are bonded to the bonding patterns by using the wire after adhering to the patterns 111 for a bare die by using an adhesive. Further, bonding the parts, such as the passive devices 122 and 124, is achieved through surface mount technology by using solder, so that chip parts and the passive devices can be mounted on the module board 110.
  • the first ground pattern 114 formed at the edge of the module board 110 is patterned to overlap with an adjacent high frequency module, and is electrically connected to the ground through a via structure.
  • FIG. 4 is a sectional view illustrating a state in which the resin member is formed on the module board.
  • the resin member 130 is formed on the module board 110.
  • the resin member 130 is molded on the module board 110 to the extent that the resin member 130 exceeds the heights of the chip parts 121 and 123, the passive devices 122 and 124, or the wire 129, so that the resin member 130 protects the chip parts 121 and 123, the passive devices 122 and 124, or the wire 129.
  • the resin member 130 can be formed using various methods such as a transfer molding method using epoxy molding compound, a method of molding an epoxy sheet through thermo-compression, a method of thermally curing exhausted liquid-phase molding material, or an injection molding method.
  • a transfer molding method using epoxy molding compound a method of molding an epoxy sheet through thermo-compression, a method of thermally curing exhausted liquid-phase molding material, or an injection molding method.
  • the resin member 130 can be formed in the areas comprising the chip parts, or over the whole area of the module board.
  • FIG. 5 is a sectional view illustrating a state in which the shield groove is formed in the resin member.
  • the shield groove 132 on the second ground pattern 115 is formed in the surface of the resin member 130.
  • the shield groove 132 can be formed in the surface of the second ground pattern 115 or can pass through the second ground pattern 115 by laser or a drill. Further, the shield groove 132 can comprise a circular or rectangular shape.
  • FIG. 6 is a plan view schematically illustrating an example in which the shield grooves are formed in the resin member of the high frequency module.
  • the shield grooves 132 having a circular shape are formed on the second ground pattern 115 at regular intervals, a shield groove 133 having a rectangular shape is formed on the third ground pattern 116, shield grooves 134 having a circular shape are formed on the fourth ground pattern 117 at regular intervals, and shield grooves 135 having a circular shape are formed on the fifth ground pattern 118 at regular intervals.
  • the each ground patterns 115, 116, 117 and 118 are exposed to the shield grooves 132, 133, 134 and 135.
  • the interval among such shield grooves or the shape of such shield grooves can be varied according to the range of each ground pattern.
  • the internal shielding part 150 can be formed through such shield grooves, respectively.
  • the first ground pattern 114 is exposed to the half groove 131 in FIG. 5.
  • the plating layer 140 is formed on the resin member 130.
  • the plating layer 140 is formed on the resin member 130 and is electically connected to the ground patterns 114 and 115 of the module board 110 through the shield groove 132 and the half groove 131.
  • the plating layer 140 is formed on an exposed part of the module board 110 and the surface of the resin member 130.
  • the plating layer 140 can be formed by selectively using a sputtering scheme, an evaporation scheme, electrolysis or non-electrolysis plating, and the like.
  • the plating layer 140 can comprise at least one metal layer in consideration of adhesive properties with the resin member 130 and rigidity of a plating member.
  • at least one plating layer can be stacked on the resin member 130 by using one or a mixture of conductive materials such as Cu, Ti, Ni and Au.
  • the plating layer 140 formed on the surface of the resin member 130 is electrically connected to the second ground pattern 115 along the shield groove 132, so that the plating layer 140 is electrically grounded. Accordingly, the internal chip parts 121 and 123 can be electrically inter- shielded from each other, so EMI/EMC phenomenon can be prevented. Further, the plating layer 140 of FIG. 7 is formed in the shield grooves 132 to 135 as shown in FIG. 6, so that the ground connection terminal 141 of the plating layer 140 is electrically connected to the ground patterns 115 to 118.
  • the high frequency module 100 can comprise a plurality of internal shileding part 150. That is, the first internal shileding part is arranged between the first signal processor and the second signal processor, the second internal shileding part is arranged between the second signal processor and the third signal processor, and the third internal shileding part is arranged between the first signal processor and the third signal processor.
  • the plating layer 140 is formed in the half groove 131 and the first ground pattern 114 is electrically connected to the end 143 of the outer side 145 of the plating layer 140, so that the outer side of the high frequency module 100 is electrically inter- shielded.
  • the chip parts 121 and 123, the passive devices 122 and 124 are mounted on the module board 110, and the layer for protecting the parts by using the resin member 130 is formed.
  • the shield groove 132 on the second ground pattern 115 is formed in the resin member 130, and then the plating layer 140 for electronic shielding is formed over the surface of the module board 110 and the resin member 130, so that a part of the plating layer 140 is electrically grounded to the second ground pattern 115. Accordingly, harmful electromagnetic waves generated from the inside and/or outside of the high frequency module can be blocked without an additional assembly process.
  • the chip parts interfering each other in a high frequency module are inter- shielded, so that interference among the chip parts can be minimized.
  • the plating layer is formed in the areas among the chip parts and on the ground pattern of the edge of the module board, so that the electrical reliability of the high frequency module can be improved.
  • chip part areas are inter- shielded from each other, so that intervals among the chip part areas can be reduced.
  • a shield cap is not used, so that the number of assembly parts can be reduced and the assembly process can be simplified.
  • grounding is automatically achieved during a plating process of the plating layer, so that a ground structure can be simplified.
  • the high frequency module can be fabricated in a small size and be integrated with high density.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

L'invention porte sur un module haute fréquence. Le module haute fréquence comprend une carte de module comprenant une pluralité de processeurs de signaux, un élément de résine sur une carte de module, une couche de placage sur l'élément de résine, et une partie de blindage interne formée entre les processeurs de signaux.
PCT/KR2008/000411 2007-01-30 2008-01-23 Module haute fréquence et son procédé de fabrication WO2008093957A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2007-0009698 2007-01-30
KR1020070009700A KR101349504B1 (ko) 2007-01-30 2007-01-30 고주파 모듈과 그 제조방법
KR1020070009698A KR101338563B1 (ko) 2007-01-30 2007-01-30 고주파 모듈 제조방법
KR10-2007-0009700 2007-01-30

Publications (1)

Publication Number Publication Date
WO2008093957A1 true WO2008093957A1 (fr) 2008-08-07

Family

ID=39674225

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2008/000411 WO2008093957A1 (fr) 2007-01-30 2008-01-23 Module haute fréquence et son procédé de fabrication

Country Status (1)

Country Link
WO (1) WO2008093957A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012020064A1 (fr) * 2010-08-10 2012-02-16 St-Ericsson Sa Mise en boîtier d'une puce de circuit intégré
EP2405731A3 (fr) * 2010-07-08 2013-09-04 Sony Corporation Module et terminal portable
TWI452665B (zh) * 2010-11-26 2014-09-11 矽品精密工業股份有限公司 具防靜電破壞及防電磁波干擾之封裝件及其製法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667058A (en) * 1985-07-01 1987-05-19 Solarex Corporation Method of fabricating electrically isolated photovoltaic modules arrayed on a substrate and product obtained thereby
US20040252475A1 (en) * 2002-08-29 2004-12-16 Michiaki Tsuneoka Module part
JP2005183884A (ja) * 2003-12-24 2005-07-07 Nec Compound Semiconductor Devices Ltd 高周波モジュール及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667058A (en) * 1985-07-01 1987-05-19 Solarex Corporation Method of fabricating electrically isolated photovoltaic modules arrayed on a substrate and product obtained thereby
US20040252475A1 (en) * 2002-08-29 2004-12-16 Michiaki Tsuneoka Module part
JP2005183884A (ja) * 2003-12-24 2005-07-07 Nec Compound Semiconductor Devices Ltd 高周波モジュール及びその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2405731A3 (fr) * 2010-07-08 2013-09-04 Sony Corporation Module et terminal portable
WO2012020064A1 (fr) * 2010-08-10 2012-02-16 St-Ericsson Sa Mise en boîtier d'une puce de circuit intégré
TWI452665B (zh) * 2010-11-26 2014-09-11 矽品精密工業股份有限公司 具防靜電破壞及防電磁波干擾之封裝件及其製法

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