WO2008093187A1 - Procédé de production d'un substrat du type silicium sur isolant - Google Patents

Procédé de production d'un substrat du type silicium sur isolant Download PDF

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Publication number
WO2008093187A1
WO2008093187A1 PCT/IB2008/000132 IB2008000132W WO2008093187A1 WO 2008093187 A1 WO2008093187 A1 WO 2008093187A1 IB 2008000132 W IB2008000132 W IB 2008000132W WO 2008093187 A1 WO2008093187 A1 WO 2008093187A1
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Prior art keywords
layer
silicon
substrate
thickness
carried out
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PCT/IB2008/000132
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English (en)
Inventor
Eric Neyret
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S.O.I.Tec Silicon On Insulator Technologies
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Application filed by S.O.I.Tec Silicon On Insulator Technologies filed Critical S.O.I.Tec Silicon On Insulator Technologies
Priority to DE112008000226.6T priority Critical patent/DE112008000226B4/de
Publication of WO2008093187A1 publication Critical patent/WO2008093187A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Definitions

  • the present invention relates to the field of processes for fabricating what are called SOI (silicon on insulator) substrates.
  • Such an SOI substrate comprises a silicon dioxide (SiO 2 ) layer buried between a bulk silicon substrate and an active silicon layer.
  • SiO 2 silicon dioxide
  • Such substrates are intended to be used in the fields of electronics, optics or optoelectronics.
  • the invention relates more particularly to the finishing steps of a process for fabricating SOI substrates, the thickness of the silicon active layer of which is less than 150 nanometers (150 run).
  • a finishing annealing operation is then carried out in an atmosphere containing hydrogen, an inert gas or a mixture of the two gases, at a temperature between HOO 0 C and 1350 0 C.
  • the aforementioned heat treatment may be carried out by a technique called "long annealing” for a time between 10 minutes and 8 hours, or by a technique known to those skilled in the art by the name RTA (rapid thermal annealing). In the latter case, this process is carried out in an RTA annealing apparatus that allows rates of temperature rise of greater than 10°C/s and relatively short annealing times, of around 30 seconds to 1 minute, to be achieved.
  • Annealing for several hours from the proposed temperature ranges results in at least partial dissolution of the buried silicon dioxide (SiO 2 ) layer, by diffusion of the oxygen forming the silicon dioxide and by evaporation of this oxygen at the surface of the active silicon layer.
  • SiO 2 buried silicon dioxide
  • the dissolution phenomenon is also linked with the increase in solubility of oxygen in silicon and consequently its dissolution in the bulk substrate and the active silicon layer. This effect is even more pronounced for silicon subsurface active layers with a thickness of 150 nanometers or less.
  • the SOI substrate obtained has a buried oxide layer of poorly controlled thickness, that is to say the thickness is both less than that normally expected in the absence of the aforementioned diffusion phenomenon and also not uniform over the entire surface of the substrate.
  • the results are plotted in the appended figure 1, which shows on the y-axis the thickness E S ⁇ O2 of the buried silicon dioxide layer of an SOI substrate after thermal annealing and on the x-axis the average thickness E SJ of the active silicon layer before annealing.
  • the thicknesses are expressed in nanometers.
  • Curves a, b and c represent the results obtained after annealing at temperatures of 1100°C, 1150°C and 1200°C, respectively.
  • Curves d, e and f represent the results obtained after annealing at temperatures of HOO 0 C, 1150 0 C and 1200 0 C, respectively.
  • An annealing operation at 1200 0 C for example is an operation during which the temperature gradually rises over several hours and is then held for 5 minutes at 1200 0 C.
  • the term "thickness uniformity" denotes the maximum deviation in thickness of the buried SiO 2 layer within the SOI wafer.
  • a uniformity of 1 to 1.5 nm for an SiO 2 layer with an average thickness of 145 nm is acceptable and commonplace.
  • the "change in thickness uniformity" on the final product corresponds to the change between the thickness uniformity values measured before and after the annealing, respectively.
  • the 0% value of the change in uniformity in figure 2 corresponds to the case in which there is no change in thickness uniformity.
  • the uniformity remains the same as that of the SiO 2 layer before the annealing, that is to say of about 1 to 1.5 nm for an SiO 2 layer whose thickness before annealing was 145 nm.
  • the reduction in the thickness of the SiO 2 layer exceeds 10 nanometers (see figure 1) and the change in uniformity may be up to 500% of the initial uniformity value of 1 to 1.5 nm considered as being acceptable, as may be seen in curve f, that is to say this change may reach 5 to 7.5 nm.
  • Figure 2 also shows that this phenomenon, namely the loss of uniformity of the buried oxide thickness, is even greater for SOI substrates in which the silicon active surface layer is less than 60 nm.
  • the steps of finishing this substrate consist in carrying out, in succession, sacrificial oxidation, deoxidation of the sacrificial silicon layer and then heat treatment in a reducing atmosphere.
  • the heat treatment in a reducing atmosphere is a treatment of the RTA (rapid thermal annealing) type carried out in a temperature range from 1000°C to 1300°C, for a very short time of 1 to 60 seconds.
  • the oxide dissolution problem is not appreciable as the time during which the substrate is exposed to a high temperature is too short.
  • the rapid annealing treatment is applied to SOI substrates in which the silicon surface layer has a thickness of at least 230 nanometers. With such a relatively large thickness, and especially greater than 200 nanometers, the oxide dissolution problem does not arise.
  • the aim of the invention is to solve the aforementioned drawbacks of the prior art.
  • the subject of the invention is to provide a process for fabricating an SOI substrate in which the silicon surface layer has a thickness less than 150 nanometers and the buried oxide layer of which has the most uniform thickness possible and even more preferably this buried oxide layer is thin.
  • the invention relates to a process for fabricating a substrate of the SOI (silicon on insulator) type, comprising a silicon substrate covered with a silicon dioxide layer which is itself covered with what is called an "ultrathin" silicon layer, the thickness of said silicon layer being 150 nm or less, this process comprising the following steps:
  • said finishing steps comprise the following successive steps: a) thinning of said thick silicon layer so as to obtain what is called a "thin" silicon layer, the thickness of which is less than that of said thick layer but remains greater than 150 nm; b) long annealing, in a gaseous atmosphere comprising hydrogen and/or argon, of said semifinished SOI substrate obtained from step a), and c) thinning of said thin silicon layer so a to obtain said ultrathin silicon layer, the thickness of which is equal to 150 nm or less, and said finished substrate of the SOI (silicon on insulator) type.
  • the long annealing is carried out in a temperature range from 950°C to 1350°C, preferably from HOO 0 C to 1250°C;
  • the long annealing is carried out for a time of at least 10 minutes;
  • step c) the thinning of said thin silicon layer of step c) is carried out by chemical-mechanical polishing
  • step c) the thinning of said thin silicon layer of step c) is carried out by sacrificial oxidation followed by deoxidation;
  • said sacrificial oxidation is carried out under dry or wet conditions at a temperature between 700°C and 1100 0 C ;
  • said weakened zone is formed by implantation of atomic or ionic species into said donor substrate;
  • the process consists in forming the silicon dioxide layer by thermal oxidation of the donor substrate and/or of the receiver substrate and in bonding the two substrates to each other so that said silicon dioxide layer lies at the interface;
  • said ultrathin silicon layer has, over its entire extent, an RMS surface roughness of less than 3 angstroms over a scanning area of 30 ⁇ m x 30 ⁇ m;
  • the thickness of the buried silicon dioxide SiO 2 layer is 50 nanometers or less;
  • the uniformity of the thickness of the buried silicon dioxide SiO 2 layer is equal to 1.8 nm or better; and - the difference in uniformity of the thickness of the buried silicon dioxide (SiO 2 ) layer before and after the long smoothing annealing is less than 20%, preferably less than 10%.
  • FIG. 1 is a graph showing the thickness Esi O2 of the silicon dioxide layer of an SOI substrate after annealing as a function of the thickness Esi of the silicon active layer before annealing, for heat treatments carried out at various temperatures and in accordance with the prior art;
  • - figure 2 is a graph showing the change in thickness uniformity ⁇ S ⁇ O2 as a result of the annealing of the silicon dioxide layer of an SOI substrate as a function of the thickness E S ⁇ of the silicon active layer before annealing, for heat treatments carried out various temperatures and in accordance with the prior art;
  • - figures 3A to 3H are diagrams showing the various steps of the process according to the invention;
  • - figure 4 is a graph showing the values of the surface roughness R of two batches of SOI substrates obtained by a process of the prior art (A) and by the process according to the invention (B), respectively;
  • - figure 5 is a graph showing a parameter called "haze”, meaning the "background noise”, on the surface of two batches of SOI substrates obtained by a process of the prior art (A) and by the process according to the invention (B), respectively;
  • FIG. 6 is a graph showing the change in thickness uniformity ⁇ S ⁇ O2 for two batches of SOI substrates obtained by a process of the prior art (A) and by the process according to the invention (B), respectively.
  • Figure 3A shows a donor substrate 1 made of preferably single-crystal silicon (Si) covered with a silicon dioxide (SiO 2 ) layer 2, the free surface of which bears the numerical reference 20.
  • the oxide layer 2 may result from thermal oxidation of the donor substrate 1 or may have been formed by deposition, conventionally by one of the chemical vapor deposition techniques known to those skilled in the art by the acronyms "CVD” (Chemical Vapor Deposition) and "LPCVD” (Low Pressure
  • Figure 3 A also shows a receiver substrate 3, made of single-crystal or polycrystalline silicon.
  • Figure 3B shows an alternative embodiment in which there is a weakened zone 10 within the donor substrate 1.
  • the donor substrate 1 is subjected to implantation of atomic or ionic species through the oxide layer 2.
  • implantation of atomic or ionic species is understood to mean any bombardment by these species capable of introducing them into the donor substrate with a maximum concentration at a predetermined depth of the substrate with respect to the bombarded surface 20, for the purpose of creating therein said weakened zone 10.
  • This type of implantation may be carried out for example using the process known by the name Smart-Cut®.
  • the weakened zone 10 forms the boundary between a layer 1 1 and the remainder 12 of the donor substrate 1.
  • the implantation of atomic or ionic species may be a single implantation, that is to say implantation of a single atomic species, such as for example an implantation of hydrogen, helium or another rare gas.
  • the implantation may also be a co-implantation of atomic or ionic species, that is to say successive implantation of at least two different species, such as for example co-implantation of hydrogen and helium.
  • the following implantation conditions may be used as an example: - implantation of just hydrogen: the implantation dose is preferably between 4XlO 16 H + ZCm 2 and 7 ⁇ lO 16 H + /cm 2 and the implantation energy between 20 keV and l00 keV;
  • the implantation dose is between 0.5 ⁇ l0 16 He + /cm 2 and 2 ⁇ lO 16 He + /cm 2 and the implantation energy between 20 keV and 100 keV
  • the implantation dose is between 0.5XlO 16 H + ZCm 2 and 2 ⁇ lO 16 H + Zcm 2 and the implantation energy between 20 keV and 100 keV.
  • the helium is preferably implanted before the hydrogen.
  • This implantation or co-implantation is carried out so that the thickness of the layer 11 formed is at least 150 ran.
  • this layer 11 is chosen to be referred to as "thick layer” even though it is simply of a thickness greater than 150 nm, as opposed to its state after subsequent thinning.
  • Figure 3 C shows the step in which the receiver substrate 3 is brought into intimate contact via one of its faces, referenced 30, with the face 20 of the SiO 2 layer 2 of the donor substrate 1.
  • the bonding between the two substrates preferably, but not necessarily, takes place by molecular adhesion and the bonding interface bears the numerical reference 4.
  • Figure 3D shows that the process then continues with the detachment of the remainder 12 of the donor substrate, along the weakened zone 10, so as to transfer the thick layer 11 onto the support substrate 3, more precisely onto the oxide layer 2.
  • Detachment may be accomplished by any appropriate technique known to those skilled in the art, for example by applying stresses of a thermal, mechanical or chemical origin.
  • these steps comprise at least:
  • the sacrificial oxidation operation is carried out on the surface of the thick layer 11. This operation is made up of an oxidation step, shown in figure 3E, an optional heat treatment and then a deoxidation step shown in figure 3F.
  • the first step consisting of an oxidation is preferably carried out at a temperature between 700 0 C and 1100 0 C.
  • It may be carried out under dry conditions, for example by heating the SOI substrate in a gaseous atmosphere, or under wet conditions, for example by heating in an atmosphere containing water vapor.
  • the oxidation atmosphere may also be charged with hydrochloric acid.
  • the oxidation step results in the formation of a silicon dioxide (SiO 2 ) layer 111 on the surface of the thick silicon layer 11.
  • the optional heat treatment second step may be carried out by increasing the temperature at a constant or varying rate until a temperature of above about 1000 0 C, and preferably between about 1 100 0 C and 1200 0 C, is reached, in a nonoxidizing gaseous atmosphere.
  • the gaseous atmosphere contains for example argon, nitrogen or other nonoxidizing gases, or a mixture of these gases.
  • the heat treatment may also be carried out under a vacuum.
  • the duration of this heat treatment is typically about 2 hours. It should be noted that this heat treatment may be carried out up to a temperature of 1200 0 C without any risk of the buried SiO 2 layer 2 dissolving, since the upper layer 110 of the silicon layer 1 1 is oxidized (reference 11 1), thereby preventing the phenomenon of transport to the surface and evaporation thereat.
  • the total deoxidation step shown in figure 3 F allows the oxide layer 111 formed during the oxidation step to be removed. This step is for example carried out by immersing the SOI substrate for a few minutes in a solution of hydrofluoric acid (HF) diluted in water to 10 or 20% by volume, for example.
  • HF hydrofluoric acid
  • the thinning of the thick layer 11 is carried out so that said thin layer 112 still has a thickness of greater than 150 run before the next step, thermal annealing, is carried out, this being shown in figure 3G.
  • This thermal annealing to smooth the SOI substrate is carried out in a gaseous atmosphere comprising hydrogen and/or argon, in the absence of oxygen, at a temperature between 950°C and 1350°C, preferably between 1000°C and 1250 0 C.
  • This annealing is called long annealing, that is to say the SOI substrate is held in the aforementioned temperature range for at least about 10 minutes and for a maximum time of a few hours, possibly even up to 8 hours. For a time of less than 10 minutes, the treatment is ineffective while for longer than 8 hours it is no longer economic in terms of production costs.
  • This annealing is carried out in a suitable furnace.
  • the finished SOI substrate obtained bears the reference 6.
  • the last step of the process is an additional thinning of the thin silicon layer 112 which, once thinned, is called “ultrathin layer” and bears the reference 1 13.
  • the thinning is carried out so that the thickness of said ultrathin layer 113 is less than 150 run.
  • the Applicant has carried out measurements and observed that by carrying out the finishing steps according to the invention it is possible, surprisingly, to limit the roughness of the ultrathin layer 113 obtained and above all to considerably reduce the dissolution of the buried oxide (SiO 2 ) layer 2.
  • the aforementioned roughness is expressed by an RMS (Root Mean Square) value. It is measured by AFM (Atomic Force Microscopy), the tip of which scans an area expressed in square microns.
  • the measurements were made on the one hand on a first batch A of SOI substrates obtained by a process in which the finishing steps comprised only a long annealing operation, carried out immediately after the step of detaching and transferring the thick layer and, on the other hand, on a second batch B of SOI substrates obtained by a process in which the finishing steps were in accordance with the invention and included an oxidation step followed by a sacrificial deoxidation step before the detachment, and then a long annealing step.
  • the process according to the invention allows the roughness of the ultrathin layer 113 to be appreciably reduced.
  • the RMS roughness values obtained are small, less than 5 or even 4 angstroms for a scanning area of 30 ⁇ m x 30 ⁇ m, and are reproducible, as indicated by the low scatter in the values obtained for B.
  • Figure 5 illustrates the value of the mean haze, which is used to characterize the uniformity of the roughness over an entire area.
  • This haze value, measured in ppm, is obtained by a method using the optical reflectivity properties of the surface to be characterized, and corresponds to an optical "background noise" scattered by the surface, owing to its microroughness.
  • the haze value is correlated in particular with the roughness and the defectuosity of a surface.
  • a low haze value H corresponds to a good surface finish.
  • the haze measurement is preferably carried out using an instrument of the Surfscan SP2 (registered trademark) type as sold by the company KLA TENCOR.
  • the measurements were carried out on the batches of substrates A and B as defined above and the results are plotted in figure 6.
  • the 0% change value corresponds to an SiO 2 thickness uniformity that is acceptable and commonplace
  • This detachment step was carried out by annealing at a temperature of about 500°C.
  • the thick silicon layer then underwent a sacrificial oxidation step, that is to say dioxidation followed by deoxidation, so as to obtain on top of the buried silicon dioxide layer a thin silicon layer with a thickness of more than 150 nanometers.
  • a thermal annealing operation was carried out for a time of 4 hours, at a temperature of 1200°C, in a gaseous atmosphere containing exclusively hydrogen and argon.
  • the RMS roughness of the surface of the thin silicon layer obtained was from 2 to 3 angstroms for an AFM scanning area of 30 ⁇ m x 30 ⁇ m.
  • the thickness of the buried oxide (SiO 2 ) layer was around 50 nm and remained almost uniform over its entire surface.
  • the measured thickness uniformity of the final product was better than 1.8 nm, for an initial SiO 2 thickness of 50 nm, i.e. less than 20% greater than the acceptable and commonplace thickness uniformity mentioned in the introduction of the application.
  • This detachment step was carried out by annealing at a temperature of about 500°C.
  • a sacrificial oxidation step was carried out, but on a larger thickness, so as to obtain a thin silicon layer with a thickness of 100 nm.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un procédé pour produire un substrat (6) du type silicium sur isolant (SO), qui consiste à relier et transférer des couches pour obtenir un substrat SOI semi-fini comprenant un substrat de silicium (3) recouvert d'une couche de dioxyde de silicium (2) et d'une couche de silicium épaisse dont l'épaisseur est supérieure à 150 ran. Ce procédé est remarquable en ce qu'il comprend les opérations suivantes : a) amincissement de la couche de silicium épaisse pour obtenir une couche de silicium épaisse (112) dont l'épaisseur est inférieure à celle de la couche épaisse et supérieure à 150 nm; b) long traitement thermique dans une atmosphère gazeuse comprenant de l'hydrogène et/ou de l'argon; et c) amincissement de la couche de silicium mince (112) pour obtenir le substrat SOI (6) comprenant le substrat de silicium (3) recouvert de la couche de dioxyde de silicium (2) et d'une couche de silicium ultra mince dont l'épaisseur est égale à 150 nm ou moins.
PCT/IB2008/000132 2007-02-01 2008-01-16 Procédé de production d'un substrat du type silicium sur isolant WO2008093187A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE112008000226.6T DE112008000226B4 (de) 2007-02-01 2008-01-16 Verfahren zum Herstellen eines Substrats vom Typ Silizium auf Isolator (SOI)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0700718A FR2912258B1 (fr) 2007-02-01 2007-02-01 "procede de fabrication d'un substrat du type silicium sur isolant"
FR0700718 2007-02-01

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DE (1) DE112008000226B4 (fr)
FR (1) FR2912258B1 (fr)
WO (1) WO2008093187A1 (fr)

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JP5490393B2 (ja) * 2007-10-10 2014-05-14 株式会社半導体エネルギー研究所 半導体基板の製造方法
JP5527956B2 (ja) * 2007-10-10 2014-06-25 株式会社半導体エネルギー研究所 半導体基板の製造方法
US7820527B2 (en) * 2008-02-20 2010-10-26 Varian Semiconductor Equipment Associates, Inc. Cleave initiation using varying ion implant dose
FR2965396B1 (fr) * 2010-09-29 2013-02-22 S O I Tec Silicon On Insulator Tech Substrat démontable, procédés de fabrication et de démontage d'un tel substrat
JP6086031B2 (ja) * 2013-05-29 2017-03-01 信越半導体株式会社 貼り合わせウェーハの製造方法
FR3036200B1 (fr) * 2015-05-13 2017-05-05 Soitec Silicon On Insulator Methode de calibration pour equipements de traitement thermique
US20210389183A1 (en) * 2018-11-09 2021-12-16 Yale University High-speed ultrathin silicon-on-insulator infrared bolometers and imagers
FR3103055A1 (fr) * 2019-11-08 2021-05-14 Soitec Procédé de finition d’une couche semi-conductrice monocristalline transférée sur un substrat receveur

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FR2797713A1 (fr) * 1999-08-20 2001-02-23 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
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FR2912258A1 (fr) 2008-08-08
US7666758B2 (en) 2010-02-23
FR2912258B1 (fr) 2009-05-08
US20080188060A1 (en) 2008-08-07
DE112008000226T5 (de) 2010-01-21
DE112008000226B4 (de) 2024-02-01

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