JP5042837B2 - 気泡の形成を回避し、かつ、粗さを制限する条件により共注入工程を行う薄層転写方法 - Google Patents
気泡の形成を回避し、かつ、粗さを制限する条件により共注入工程を行う薄層転写方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims description 102
- 238000002513 implantation Methods 0.000 claims description 60
- 229910052739 hydrogen Inorganic materials 0.000 claims description 30
- 229910052734 helium Inorganic materials 0.000 claims description 28
- 239000001257 hydrogen Substances 0.000 claims description 25
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 22
- 239000001307 helium Substances 0.000 claims description 21
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 20
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000002474 experimental method Methods 0.000 description 9
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- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
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- 229910017214 AsGa Inorganic materials 0.000 description 1
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Description
ドナー基板の厚み部分内に脆化領域を作製するように薄層が作られなければならないドナー基板表面下へ核種の注入を行う工程と、
注入が行われた後にドナー基板の面を支持基板と緊密に接触させる工程と、
ドナー基板の一部を支持基板上に転写し、かつ、支持基板上に薄層を形成するように脆化領域の高さでドナー基板を剥離する工程と、を含む方法に関する。
・12×1015/cm2のHe原子の核種量
・34、40、および、46keVであるY軸に沿って示されたHe注入エネルギー
・9、12、および、15×1015/cm2であるX軸に沿って示された注入されたH原子の核種量
・27keVのH注入エネルギー
ドナー基板の厚み部分内に脆化領域を作製するように薄層が作られなければならないドナー基板の面の下方への少なくとも2つの異なった核種の共注入を行う工程と、
注入が施された後にドナー基板の面を支持基板と緊密に接触させる工程と、
ドナー基板の一部を支持基板上に転写し、かつ、支持基板上に薄層を形成するように脆化領域の高さでドナー基板を剥離する工程と、を含む、基板上に半導体材料の薄層を含む構造物の作製方法であって、
少なくとも第1の核種は注入されて、ドナー基板中に小板状欠陥を形成するために実質上化学的に機能し、少なくとも第2の核種は注入されて、前記欠陥において応力を与えるための注入されたドナー基板における内部圧力の供給源として実質上物理的に機能し、前記第1および第2の核種の各々は、正規分布曲線に従って、最大濃度ピークを有し、かつ、注入核種の70%が集中する展開領域がドナー基板の厚み部分内にそれぞれ分布し、共注入工程が、
・前記第2の核種のピークが、前記脆化領域内のドナー基板の厚み部分内において、かつ、前記第1の核種の展開領域よりも深く所在するように前記第1および第2の核種の注入エネルギーが選択され、かつ、
・前記第1および第2の核種の注入核種量が実質上同じとなり、第1の核種の注入核種量が総注入核種量の40%から60%に達するように選択される、
という共注入条件に従って行われることを特徴とする方法を提案する。
・ドナー基板は(究極的には表面のSiO2層を含む)シリコン基板であり、前記第1および第2の核種の注入核種量は総注入核種量として実質上3.2×1016/cm2よりも小さな核種量となるように選択されることが可能であり、
・総注入核種量は2.2×1016/cm2より小さくすることが可能であり、
・各核種の注入核種量は0.9×1016/cm2と1.5×1016/cm2の間に含まれることが可能であり、
・第1の核種の最大濃度ピークと第2の核種の最大濃度ピークの間の隔たり(offset)は実質上500と1,000オングストロームの間に含まれることが可能であり、
・共注入工程はヘリウムおよび水素を共注入することにより行うことができ、ドナー基板において、ヘリウムは実質上物理的に機能し、水素は実質上化学的に機能し、
・共注入工程はヘリウムと水素を順次共注入することにより行うことができ、
・支持基板はシリコン基板とすることができ、かつ、究極的には表面の酸化物層をこの基板の頂部上に含むことができ、
・方法は、ドナー基板の面が支持基板と緊密に接触される前の緊密に接触されるべきドナー基板および支持基板の面の少なくとも1つのプラズマ活性化処理をさらに含むことができる。
Claims (6)
- 基板上に半導体材料の薄層を含む構造物の作製方法であって、
(1)前記薄層が形成されるべきドナー基板の表面下へ、水素およびヘリウムの核種の共注入を行うことにより、前記ドナー基板の厚み部分内に脆化領域を作製する工程、
(2)注入が施された後に、前記ドナー基板の表面を支持基板と緊密に接触させる工程、
(3)前記脆化領域の高さで前記ドナー基板を剥離することにより、前記ドナー基板の一部を前記支持基板上に転写し、かつ、前記支持基板上に前記薄層を形成する工程、
を含み、
注入された第1の水素の核種は、化学的に作用して前記ドナー基板中に小板状欠陥を形成し、
注入された第2のヘリウムの核種は、注入されたドナー基板の内部圧力源として、物理的に作用して、前記欠陥に応力を与え、
前記第1の水素および第2のヘリウムの核種の各々は、正規分布曲線に従って、最大濃度ピークを有し、かつ、注入核種の70%が集中する展開領域が前記ドナー基板の厚み方向にそれぞれ分布し、
前記方法は、前記共注入工程が、以下の共注入条件により行われる、
(a)前記第2のヘリウムの核種のピークが、前記脆化領域内の前記ドナー基板の厚み部分内に、かつ、前記第1の水素の核種の展開領域よりも深く所在するように前記第1および第2の核種の注入エネルギーが選択され、
(b)総注入核種量が、2.2×10 16 /cm 2 よりも小さく、前記第1の水素の核種の注入核種量が、前記総注入核種量の40%から60%の範囲内に達するように選択され、かつ
前記第1の水素の最大濃度ピークと前記第2のヘリウムの最大濃度ピークの間の隔たりは500と1000オングストロームの間に含まれる、
ことを特徴とする方法。 - 各核種の注入核種量は、0.9×1016/cm2と1.5×1016/cm2の間に含まれることを特徴とする請求項1に記載の方法。
- 前記共注入工程は、ヘリウムに次いで水素を順次共注入することにより行うことを特徴とする請求項1から2のいずれか一項に記載の方法。
- 前記支持基板は、シリコンで作製されていることを特徴とする請求項1から3のいずれか一項に記載の方法。
- 前記シリコンで作製されたドナー基板は、表面の酸化物層を前記基板の頂部上に含むことを特徴とする請求項4に記載の方法。
- 前記ドナー基板の表面を前記支持基板と緊密に接触される前に、緊密に接触されるべき前記ドナー基板および前記支持基板の少なくとも1つの表面に、プラズマ活性化処理をさらに施すことを特徴とする請求項1から5のいずれか一項に記載の方法。
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PCT/IB2004/003300 WO2006032947A1 (en) | 2004-09-21 | 2004-09-21 | Thin layer transfer method wherein a co-implantation step is performed according to conditions avaoiding blisters formation and limiting roughness |
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JP2008513989A JP2008513989A (ja) | 2008-05-01 |
JP5042837B2 true JP5042837B2 (ja) | 2012-10-03 |
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US (1) | US7326628B2 (ja) |
EP (1) | EP1792338A1 (ja) |
JP (1) | JP5042837B2 (ja) |
CN (1) | CN101027768B (ja) |
WO (1) | WO2006032947A1 (ja) |
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US6600173B2 (en) * | 2000-08-30 | 2003-07-29 | Cornell Research Foundation, Inc. | Low temperature semiconductor layering and three-dimensional electronic circuits using the layering |
US6593212B1 (en) * | 2001-10-29 | 2003-07-15 | The United States Of America As Represented By The Secretary Of The Navy | Method for making electro-optical devices using a hydrogenion splitting technique |
FR2834820B1 (fr) * | 2002-01-16 | 2005-03-18 | Procede de clivage de couches d'une tranche de materiau | |
FR2847076B1 (fr) * | 2002-11-07 | 2005-02-18 | Soitec Silicon On Insulator | Procede de detachement d'une couche mince a temperature moderee apres co-implantation |
FR2858462B1 (fr) * | 2003-07-29 | 2005-12-09 | Soitec Silicon On Insulator | Procede d'obtention d'une couche mince de qualite accrue par co-implantation et recuit thermique |
-
2004
- 2004-09-21 EP EP04769600A patent/EP1792338A1/en not_active Withdrawn
- 2004-09-21 JP JP2007531847A patent/JP5042837B2/ja not_active Expired - Lifetime
- 2004-09-21 CN CN2004800440311A patent/CN101027768B/zh not_active Expired - Lifetime
- 2004-09-21 WO PCT/IB2004/003300 patent/WO2006032947A1/en active Application Filing
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2005
- 2005-07-13 US US11/181,405 patent/US7326628B2/en active Active
Also Published As
Publication number | Publication date |
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US20060060943A1 (en) | 2006-03-23 |
JP2008513989A (ja) | 2008-05-01 |
US7326628B2 (en) | 2008-02-05 |
CN101027768A (zh) | 2007-08-29 |
WO2006032947A1 (en) | 2006-03-30 |
EP1792338A1 (en) | 2007-06-06 |
CN101027768B (zh) | 2010-11-03 |
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