WO2008031255A1 - Procédé de recouvrement au nitrure de silicium à auto-alignement pour un trou de contact sans bordure basé sur la technologie du cuivre - Google Patents

Procédé de recouvrement au nitrure de silicium à auto-alignement pour un trou de contact sans bordure basé sur la technologie du cuivre Download PDF

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WO2008031255A1
WO2008031255A1 PCT/CN2006/002102 CN2006002102W WO2008031255A1 WO 2008031255 A1 WO2008031255 A1 WO 2008031255A1 CN 2006002102 W CN2006002102 W CN 2006002102W WO 2008031255 A1 WO2008031255 A1 WO 2008031255A1
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layer
silicon nitride
metal
copper
contact hole
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PCT/CN2006/002102
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WO2008031255A8 (fr
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Chiu-Te Lee
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He Jian Technology(Suzhou)Co., Ltd
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Priority to CN2006800555121A priority Critical patent/CN101501837B/zh
Priority to PCT/CN2006/002102 priority patent/WO2008031255A1/zh
Publication of WO2008031255A1 publication Critical patent/WO2008031255A1/zh
Publication of WO2008031255A8 publication Critical patent/WO2008031255A8/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

Definitions

  • the present invention relates to an integrated circuit fabrication process, and more particularly to a self-aligned silicon nitride for a copper process edgeless via. Coating method.
  • Duel Damascene has been widely used in semiconductor manufacturing technology below 0.13 ⁇ .
  • the borderless vias have become a major challenge in current semiconductor processes. It is well known that whether it is to solve the stress release or the weak point resistivity of the interface, the most critical part is the bottom end of the via. The most common occurrence is that metal copper diffuses out of the metal barrier along the silicon nitride cap, low dielectric constant material, and microchannels when the silicon nitride (SiN) cap is opened, so the stress center must be removed or blocked.
  • the present invention has been made to solve the above problems, and an object thereof is to provide a self-aligned silicon nitride coating method for a copper process edgeless via.
  • the self-aligned silicon nitride coating method for the copper process edgeless via hole of the present invention includes the following
  • Step 1 etching a pattern on a substrate on which a sacrificial layer is deposited, and then filling a metal barrier layer and metal copper;
  • Step 2 After chemical mechanical polishing, the sacrificial layer is removed to form a metal copper head; Step 3: depositing an inter-metal insulating medium;
  • Step 4 Defining the etched area, etching the inter-metal insulating medium to form a borderless via.
  • the method for depositing an inter-metal dielectric in the above step 3 is to sequentially deposit an etch stop layer, such as a SiN layer, a layer of low dielectric constant material, such as SiCOH, a first hard mask.
  • etch stop layer such as a SiN layer
  • a layer of low dielectric constant material such as SiCOH
  • a first hard mask for example, SiC, a sacrificial layer, such as SiO 2 , and a second hard mask, such as SiN.
  • the above low dielectric constant material may be, for example, silicon oxyhydroxide.
  • the etch stop layer may be, for example, a silicon nitride layer.
  • the invention applies the self-aligned silicon nitride coating method to the edgeless via copper process and solves the problem that the metal copper is extruded along the silicon nitride cap, the low dielectric constant material and the micro trench when the silicon nitride cap is opened.
  • the problem. ⁇ in the aligned vias the stress point above the metal copper head will be away from the bottom corner of the via hole, which facilitates the interface peeling and solves the weak point resistivity of the interface; in the misaligned via hole, the adjacent metal
  • the etch stop layer forms a cladding to block etching through the low dielectric constant material.
  • Figure 1 is a schematic view of aligned vias in an existing Cu double-layer damascene structure.
  • Figure 2 is a schematic view of a misaligned via hole in an existing Cu double-layer damascene structure.
  • Fig. 3 is a schematic view showing a sacrificial layer left after Cu chemical mechanical polishing in the Cu double-layer damascene structure of the present invention.
  • Fig. 4 is a schematic view showing the removal of the sacrificial layer in the Cu double-layer damascene structure of the present invention.
  • Fig. 5 is a view showing the deposition of an intermediate metal dielectric layer in the Cu double-layer damascene structure of the present invention.
  • FIGS. 1 and 2 An existing Cu double-layer mosaic structure is shown in FIGS. 1 and 2.
  • the existing process of Cu double layer inlaying means that the metal layer pattern and the metal deposition of the metal plug below it are completed at one time.
  • the etching of the metal layer pattern and the etching of the metal plug must use two lithography steps. Depending on the method, the order of the two lithography is sequential.
  • Figure 1 is an ideal state, which is a schematic diagram of aligned via holes in an existing Cu double-layer damascene structure, as shown by a dashed box. 14 is shown.
  • Figure 2 is a schematic view of a misaligned via hole in an existing Cu double-layer damascene structure. The appearance of the above problem can be seen from the dashed box 15 of the figure.
  • the invention proposes a novel Cu double-layer mosaic structure, which solves the problems existing in the existing Cu double-layer mosaic structure.
  • This structure is implemented by the process shown in Figure 3 and Figure 7.
  • Figure 7 In order to more clearly disclose the implementation of each step, a preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.
  • a sacrificial layer is left after chemical mechanical polishing of Cu.
  • the pattern is etched on the substrate 21 on which the sacrificial layer 22 is deposited, and then the metal copper layer 23 is filled; then the metal copper layer on the surface is removed by chemical mechanical polishing; the sacrificial layer 22 is left.
  • FIG. 4 With continued reference to Figure 4, there is shown a schematic view of the sacrificial layer 22 removed. After the sacrificial layer 22 is removed, a metal copper head 23 is formed.
  • FIG. 5 is a continuation of the process of Figure 4.
  • Fig. 5 is a schematic view showing the deposition of an intermediate metal dielectric layer in the Cu double-layer damascene structure of the present invention.
  • an etch stop layer such as SiN 24, a layer of Low K material such as SiC 25, a first hard mask 26, a sacrificial layer 27 and a second hard mask are sequentially deposited. 28.
  • the deposited multilayer film is separately etched to form a borderless via hole to expose the via hole.
  • FIG. 6 is a schematic view of the aligned via holes after the etching process in the Cu double-layer damascene structure of the present invention.
  • the etched region is defined to sequentially etch the second hard mask 28, the sacrificial layer 27, the first hard mask 26, the SiC 25 and the SiN 24 while exposing the via holes.
  • Xf is aligned with the via hole, and the stress point above the metal copper head 23 is away from the corner of the bottom end of the via hole, which facilitates the interface peeling and solves the problem of the weak point electrical barrier rate of the interface.
  • 7 is a schematic view of a misaligned via hole in the Cu double-layer damascene structure of the present invention. The via hole is exposed while the etching process is performed. Xf is in the unaligned via hole, and an etch stop layer of the adjacent metal is formed to form a cladding layer to block etching through the low dielectric constant material.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

一种用于铜工艺无边导通孔的自对准氮化硅覆层方法 技术领域 本发明涉及集成电路制造工艺，特别是涉及一种用于铜工艺无边导通 孔的自对准氮化硅覆层方法。
说
背景技术
书
在铜（Cu) /低介电常数 (Low K)材料连线工艺中，双层镶嵌 (Duel Damascene)已广泛应用到 0.13μιη以下的半导体制造技术中。但是因为在 刻蚀过程中， 导通孔底端薄膜堆叠的复杂性及通孔刻蚀工艺的低选择性 导致了无边导通孔成为目前半导体工艺的主要挑战。 众所周知， 无论是 解决应力释放还是界面的弱点电阻率问题， 最关键的部位都在于导通孔 底端。最常出现的情况是在氮化硅（SiN)盖打开时金属铜沿氮化硅帽盖、 低介电常数材料及微沟槽扩散出金属阻绝层， 因此必须去除或阻挡住应 力中心。 同时， 虽然无边导通孔很小， 伹必须通过刻蚀终止层或者是优 化刻蚀工艺来防止出现微沟槽。 该课题一直受到各半导体厂家与集成电 路 （Integrated Circuit) (以下简称 IC) 设计制造公司的关心。 发明内容 本发明是为了解决上述课题而开发的，其目的在于提供一种用于铜工 艺无边导通孔的自对准氮化硅覆层方法。 本发明的用于铜工艺无边导通孔的自对准氮化硅覆层方法包括以下
步骤 1 : 在沉积有牺牲层的基材上刻蚀出图案， 接着填充金属阻绝层 及金属铜；
步骤 2: 进行化学机械抛光后， 再除去牺牲层， 形成金属铜头； 步骤 3 : 沉积金属间绝缘介质；
步骤 4: 定义刻蚀区， 对上述金属间绝缘介质进行刻蚀， 形成无边导 通孔。
上述步骤 3中所述的沉积金属间绝缘介质的方法是依次沉积一层刻蚀 终止层，例如为 SiN层，一层低介电常数材料层，例如为 SiCOH,—层第 1硬掩模， 例如为 SiC， 一层牺牲层， 例如为 Si02， 及一层第 2硬掩模， 例如为 SiN。
上述低介电常数材料可以为例如碳化氢氧硅。
上述刻蚀终止层可以为例如氮化硅层。
本发明将自对准氮化硅覆层方法用于无边导通孔铜工艺并解决了在 氮化硅帽盖打开时金属铜沿氮化硅帽盖、低介电常数材料及微沟槽挤出的 问题。 Χί于对准的导通孔， 金属铜头上方应力点会远离导通孔底端拐角， 利于界面剥离并解决了界面的弱点电阻率问题； 于未对准的导通孔，接 邻金属的刻蚀终止层形成覆层用以阻挡通过低介电常数材料的刻蚀。
下面结合附图， 对本发明的具体实施作进一步的详细说明。 Χί于所属 技术领域的技术人员而言，从对本发明的详细说明中， 本发明的上述和其 他目的、 特征和优点将显而易见。 附图说明 图 1是在已有的 Cu双层镶嵌结构中， 对准的导通孔示意图。
图 2是在已有的 Cu双层镶嵌结构中， 未对准的导通孔示意图。
图 3是本发明的 Cu双层镶嵌结构中， 进行 Cu化学杌械抛光后留下 牺牲层的示意图。
图 4是本发明的 Cu双层镶嵌结构中， 移除牺牲层后的示意图。
图 5是本发明的 Cu双层镶嵌结构中， 进行中间金属介电层沉积的示 意图。
图 6是本发明的 Cu双层镶嵌结构中， 对准的导通孔的示意图。 图 7是本发明的 Cu双层镶嵌结构中， 未对准的导通孔的示意图。 具体实施方式 已有的 Cu双层镶嵌结构如图 1和图 2所示。 已有的工艺的 Cu双层 镶嵌指的是金属层图案与其下方的金属栓塞的金属沉积是一次完成的。当 然金属层图案的刻蚀及金属栓塞的刻蚀须使用两次微影步骤。 依方法不 同， 此两次微影的次序互有先后。一般情况下， 刻蚀完后形成导通孔会出 现两种状况： 图 1是理想状态， 该图是在已有的 Cu双层镶嵌结构中， 对 准的导通孔示意图， 具体如虚线框 14所示。 但实际上， 由于已有刻蚀工 艺的限制， 工艺窗的低选择性及导通孔底端薄膜堆梭的复杂性导致了在 SiN 12帽盖打开时 Cu ll沿 SiN 12， Low K材料 13及沟槽挤出。 如图 2， 该图是在已有的 Cu双层镶嵌结构中， 未对准的导通孔示意图。 从该图虚 线框 15可以看出上述问题的出现。
本发明提出了一种新型的 Cu双层镶嵌结构， 解决了已有的 Cu双层 镶嵌结构所出现的问题。该结构是通过图 3 图 7所示的过程实现的。为 了更清楚地揭示每一步的实施过程， 下面参照附图， 本发明的一较佳实 施例进行详细说明。
先参照图 3，该图是本发明的 Cu双层镶嵌结构中，进行 Cu化学机械 拋光后留下牺牲层的示意图。在沉积有牺牲层 22的基材上 21上刻蚀出图 案， 接着填充金属铜层 23 ; 然后利用化学机械抛光除去表面的金属铜层; 留下牺牲层 22。
继续参照图 4，该图中显示了将牺牲层 22移除后的示意图。在移除牺 牲层 22后， 形成金属铜头 23。
图 5是图 4过程的延续。 图 5是本发明的 Cu双层镶嵌结构中， 进行 中间金属介电层沉积的示意图。在图 4的基础上，依次沉积一层刻蚀终止 层例如 SiN 24， 一层 Low K材料例如 SiC 25， 一层第 1硬掩模 26， 一层 牺牲层 27及一层第 2硬掩模 28。 然后对沉积好的多层膜分别进行刻蚀，形成无边导通孔，露出导通孔。 其结果可参照图 6和图 7， 图 6是本发明的 Cu双层镶嵌结构中， 在进行 刻蚀工艺后， 对准的导通孔的示意图。 定义刻蚀区依次对第 2硬掩模 28， 牺牲层 27, 第 1硬掩模 26, SiC 25与 SiN 24进行刻蚀同时露出导通孔。 Xf于对准的导通孔， 金属铜头 23上方应力点会远离导通孔底端拐角， 利 于界面剥离并解决了界面的弱点电障率问题。 而图 7是本发明的 Cu双层 镶嵌结构中，未对准的导通孔的示意图。在进行刻蚀工艺同时露出导通孔。 Xf于未对准的导通孔，接邻金属的刻蚀终止层形成覆层用以阻挡通过低介 电常数材料的刻蚀。
当然， 本发明还可有其他实施例，在不背离本发明精神及其实质的情 况下，所属技术领域的技术人员当可根据本发明作出各种相应的变更和改 型， 但这些相应的变更和改型都应属于本发明的权利要求的保护范围。

Claims

权 利 要 求 书
1.一种用于铜工艺无边通孔的自 准氮化硅覆层方法，其特征在于包 括：
步骤 1 : 在沉积有牺牲层的基材上刻蚀出图案， 接着填充金属铜； 步骤 2 : 进行化学机械抛光后除去牺牲层， 形成金属铜头；
步骤 3 : 沉积金属间绝缘介质；
步骤 4 : 定义刻蚀孔区， 对上述金属间绝缘介质进行刻蚀， 形成无边 导通孔。
2.根据权利要求 1 所述用于铜工艺无边通孔的自对准氣化硅覆层方 法，其特征在于上述步骤 3所述的沉积金属间绝缘介质的方法是依次沉积 一层蚀刻终止层，一层低介电常数材料层，一层第 1硬掩模，一层牺牲层， 及一层第 2硬掩模。
3.根据权利要求 2所述的用于铜工艺无边通孔的自对准氮化硅覆层 方法， 其特征在于上述低介电常数材料为碳化氢氧硅。
4.根据权利要求 2或 3所述的用于铜工艺无边通孔的自对准氮化硅覆 层方法， 其特征在于上述蚀刻终止层为氮化硅层。
PCT/CN2006/002102 2006-08-18 2006-08-18 Procédé de recouvrement au nitrure de silicium à auto-alignement pour un trou de contact sans bordure basé sur la technologie du cuivre WO2008031255A1 (fr)

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CN2006800555121A CN101501837B (zh) 2006-08-18 2006-08-18 一种用于铜工艺无边导通孔的自对准氮化硅覆层方法
PCT/CN2006/002102 WO2008031255A1 (fr) 2006-08-18 2006-08-18 Procédé de recouvrement au nitrure de silicium à auto-alignement pour un trou de contact sans bordure basé sur la technologie du cuivre

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US20140001646A1 (en) * 2012-06-29 2014-01-02 Lijun Dong Solid hole array and manufacture method thereof
US9136160B2 (en) * 2012-06-29 2015-09-15 Institute of Microelectronics, Chinese Academy of Sciences Solid hole array and method for forming the same

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