WO2008022454A1 - Système de mémoire évolutif - Google Patents

Système de mémoire évolutif Download PDF

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Publication number
WO2008022454A1
WO2008022454A1 PCT/CA2007/001469 CA2007001469W WO2008022454A1 WO 2008022454 A1 WO2008022454 A1 WO 2008022454A1 CA 2007001469 W CA2007001469 W CA 2007001469W WO 2008022454 A1 WO2008022454 A1 WO 2008022454A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
command
memory device
data
packet
Prior art date
Application number
PCT/CA2007/001469
Other languages
English (en)
Inventor
Jin-Ki Kim
Hakjune Oh
Hong Beom Pyeon
Steven Przybylski
Original Assignee
Mosaid Technologies Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/840,692 external-priority patent/US7904639B2/en
Application filed by Mosaid Technologies Incorporated filed Critical Mosaid Technologies Incorporated
Priority to KR1020127021608A priority Critical patent/KR101476515B1/ko
Priority to CN2007800313409A priority patent/CN101506895B/zh
Priority to EP07800496A priority patent/EP2062261A4/fr
Priority to JP2009524855A priority patent/JP5575474B2/ja
Priority to CA002659828A priority patent/CA2659828A1/fr
Publication of WO2008022454A1 publication Critical patent/WO2008022454A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Definitions

  • the present invention relates generally to memory systems. More particularly, the present invention relates to a memory system of serially connected memory devices for mass storage applications.
  • Flash memory is a commonly used type of non- volatile memory in widespread use as mass storage for consumer electronics, such as digital cameras and portable digital music players for example.
  • the density of a presently available Flash memory chip can be up to 32Gbits (4GB), which is suitable for use in popular USB Flash drives since the size of one Flash chip is small.
  • each bitline is connected to one NAND memory cell string in each of blocks [0] to [k].
  • Each wordline (WLO to WLi), SSL and GSL signal is connected to the same corresponding transistor device in each NAND memory cell string in the block.
  • data stored in the flash memory cells along one wordline is referred to as a page of data.
  • a data register 32 Connected to each bitline outside of the bank 30 is a data register 32 for storing one page of write data to be programmed into one page of flash memory cells, or read data accessed from the flash memory cells.
  • Data register 32 also includes sense circuits for sensing data read from one page of flash memory cells. During programming operations, the data registers perform program verify operations to ensure that the data has been properly programmed into the flash memory cells connected to the selected wordline.
  • Each memory cell of bank 30 can store a single bit of data or multiple bits of data. Some flash memory devices will have more than one set of data registers to increase throughput.
  • FIG. 2 is a block diagram of a prior art flash memory system 10 integrated with a host system 12.
  • Flash memory system 10 includes a memory controller 14 in communication with host system 12, and multiple non-volatile memory devices 16.
  • the host system will include a processing device such as a microcontroller, microprocessor, or a computer system.
  • the Flash memory system 10 of Figure 2 is configured to include one channel 18, where memory devices 16 are connected in parallel to channel 18.
  • the memory system 10 can have more or less than four memory devices connected to it.
  • a memory system having a controller and a memory device.
  • the controller includes a serial channel output port for providing a serial bitstream command packet, and a serial channel input port for receiving a serial bitstream read data packet.
  • the serial bitstream command packet includes an operational code and a device address.
  • the memory device has an input port for receiving the serial bitstream command packet from the controller and for executing the operation code if the device address corresponds to the memory device.
  • the memory device provides the serial bitstream command packet through an output port and subsequently provides the serial bitstream read data packet through the output port if the operation code corresponds to a read function.
  • a first command strobe is received in parallel with the first command, the first command strobe having an active duration corresponding to the length of the first command
  • a second command strobe is received in parallel with the second command, the second command strobe having an active duration corresponding to the length of the second command.
  • the first command strobe and the second command strobe are separated by at least one data latching clock edge.
  • a data input strobe is received for enabling outputting of the read data packet while the data input strobe is at the active level, such that the second command strobe and data input strobe are separated by at least one data latching clock edge.
  • the plurality of memory devices are connected in series, the first and last memory devices being connected to the controller, and the controller sends a bitstream data packet to the first device of the plurality of memory devices.
  • the bitstream data packet from the controller and the bitstream read data packet comprises a serial bitstream or comprises parallel bitstreams.
  • the plurality of memory devices are either of the same type or a mix of different types of memory devices.
  • Fig. 6 is a block diagram of a dynamically adjustable serial memory system
  • Fig. 7 is a block diagram of a memory device having a native core and a serial input/output interface suitable for use in the serial memory systems of Figures 3A to 3C and 4 to 6
  • Fig. 8 is an illustration of a modular command packet structure
  • Fig. 10 is a flow chart of a method for executing concurrent operations in one memory device
  • Fig. 11 is a sequence diagram illustrating a concurrent read operation for two different banks of a memory device
  • Fig. 12 is a sequence diagram illustrating a concurrent program operation for two different banks of a memory device
  • Fig. 14 is a sequence diagram illustrating a concurrent block erase for two different banks of a memory device
  • Figure 3A is a block diagram illustrating the conceptual nature of a serial memory system architecture, according to one embodiment.
  • the serial memory system 100 includes a memory controller 102 having at least one serial channel output port Sout and a serial channel input port Sin, and memory devices 104, 106, 108, 110, 112, 114 and 116 that are connected in series.
  • the memory devices can be flash memory devices.
  • the memory devices can be DRAM, SRAM or any other type of memory device provided it has a serial input/output interface compatible with a specific command structure, for executing commands or passing through commands and data to the next memory device. Further details of such memory device configuration and a specific command structure will be described later.
  • the current embodiment includes seven memory devices, but alternate embodiments can include as few as one memory device, and up to any number of memory devices.
  • memory device 104 is the first device of serial memory system 100 as it is connected to Sout
  • memory device 116 is the Nth or last device as it is connected to Sin, where N is an integer number greater than zero.
  • Memory devices 106 to 114 are then intervening serially connected memory devices between the first and last memory devices.
  • Each memory device can assume a distinct identification number, or device address (DA) upon power up initialization of the system, so that they are individually addressable.
  • DA device address
  • Commonly owned U.S. Patent Application Nos. 11/622,828, 11/750,649, 11/692,452, 11/692,446, 11/692,326 and 11/771,023 describe methods for generating device addresses for serially connected memory devices of a memory system.
  • the memory device having the matching device address referred to as a selected memory device, will execute the operation dictated by the command. If the command is to read data, the selected memory device will output the read data through its output port, which is serially passed through intervening memory devices until it reaches the Sin port of the memory controller 102.
  • Serial memory system 200 includes a memory controller 202 and four memory devices 204, 206, 208 and 210.
  • the memory controller 202 provides several signals in parallel to the memory devices. These include the chip enable signal CE#, the reset signal RST#, and complementary clocks CK# and CK.
  • CE# the device is enabled when CE# is at the low logic level. Once the memory device starts a program or erase operation, CE# can be de-asserted, or driven to a high logic level. In addition, CE# at the low logic level can activate the internal clock signals and CE# at the high logic level can deactivate the internal clock signals.
  • the memory device is set to a reset mode when RST# is at the low logic level.
  • the reset mode the power is allowed to stabilize and the device prepares itself for operation by initializing all finite state machines and resetting any configuration and status registers to their default states.
  • the memory device can be statically configured or dynamically configured for any width of Qn and Dn. Hence, in a configuration where n is greater than 1, the memory controller provides data in parallel bitstreams.
  • CSI is used for latching command data appearing on the input port Dn, and has a pulse duration corresponding to the length of the command data received. More specifically, the command data will have a duration measured by a number of clock cycles, and the pulse duration of the CSI signal will have a corresponding duration.
  • DSI is used for enabling the output port Qn buffer to output data, and has a pulse duration corresponding to the length of the read data being requested. Further details of the DSI and CSI signals will be discussed later.
  • Serial memory system 300 of Figure 5 is similar to the embodiment of Figure 4, except that instead of a parallel clock distribution scheme, a source synchronous clock scheme is used.
  • Serial memory system 300 includes a memory controller 302 and four memory devices 304, 306, 308 and 310.
  • the memory controller 302 includes clock output ports CKO# and CKO for providing complementary clock signals, and clock input ports CK# and CK for receiving the complementary clock signals from the last memory device of the system.
  • the memory devices are the same as those shown in Figure 4, except that they now have clock input ports CK# and CK, and clock output ports CKO# and CKO, where the received clocks by one memory device at its CK# and CK ports is provided to the next device through its CKO# and CKO ports.
  • the last memory device 310 provides the clock signals back to the memory controller 302.
  • the main advantage of the embodiment of Figure 5 is the absence of any complex clock distribution scheme and the minimum clock interconnection between memory devices. Therefore, the minimum clock frequency can be increased to 166MHz, resulting in a minimum 333 Mbps data rate per pin.
  • the embodiment of Figure 5 can be scaled to include any number of memory devices.
  • a fifth memory device can be added to the embodiment of Figure 5 simply by connecting the output ports of memory device 310 to the corresponding input ports of the fifth memory device, and connecting the output ports of the fifth memory device to the memory controller 302.
  • memory controller 302 can include a simple phase locked loop (PLL) circuit to maintain the clock frequency.
  • PLL phase locked loop
  • serial memory system 200 and 300 can be statically fixed for a specific number of memory devices. Different configurations can be set for providing different memory system capacities, simply by adjusting the number of memory devices in the serial chain. In alternate embodiments, memory devices having different capacities can be mixed together in the serial chain, thereby providing more flexibility in the overall memory system capacity. There may be applications where the memory system capacity can be dynamically adjusted by adding or removing modules from the serial chain, where a module can be a single memory device, an SIP memory, or a PCB having memory devices and/or SIP memory devices.
  • Adjustable serial memory system 400 includes a memory controller 402, fixed memory devices 404, 406, 408 and 410, expansion links 412, 414, 416, 418 and 420, and expansion modules 422, 424 and 426.
  • Fixed memory devices 404, 406, 408 and 410 are serially connected to each other, to intervening expansion links, and to the memory controller 402.
  • Each expansion link is a male or female coupling means for releasably receiving and retaining a module having a corresponding female or male coupling means.
  • Each module includes at least one memory device serially connected with the terminals of the expansion link.
  • serial memory systems of Figures 3 A to 3C and 4 to 6 can include a mix of memory device types, each providing different advantages for the greater system.
  • the high speed of DRAM memory can be used for caching operations while the non- volatility of flash memory can be used for mass data storage.
  • each memory device is individually addressable to act upon a command because the serial interface and control logic block 506 is configured to receive commands according to a predetermined protocol.

Abstract

L'invention concerne une architecture de système de mémoire comprenant des dispositifs de mémoire montés en série. Ce système de mémoire est évolutif de manière à pouvoir comprendre un certain nombre de dispositifs de mémoire sans dégradation des performances, ni restructuration complexe. Chaque dispositif de mémoire comprend une interface série d'entrée/sortie pour communiquer avec d'autres dispositifs de mémoire et un contrôleur de mémoire. Ce contrôleur de mémoire émet des commandes dans au moins un flux binaire, ce flux binaire suivant un protocole de commande modulaire. Une commande comporte un code d'opération comprenant des informations d'adresse facultatives et une adresse de dispositif, de sorte que seul le dispositif de mémoire adressé réagisse à cette commande. Des signaux stroboscopiques de sortie de données et d'entrée de commande distincts sont fournis parallèlement à chaque flux de données de sortie et chaque flux de données de commande d'entrée respectivement, pour identifier le type de données et la longueur de ces données. Le protocole de commande modulaire est utilisé pour exécuter des opérations concurrentes dans chaque dispositif de mémoire afin d'améliorer davantage les performances.
PCT/CA2007/001469 2006-08-22 2007-08-22 Système de mémoire évolutif WO2008022454A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020127021608A KR101476515B1 (ko) 2006-08-22 2007-08-22 스케일러블 메모리 시스템
CN2007800313409A CN101506895B (zh) 2006-08-22 2007-08-22 可扩缩的存储器系统
EP07800496A EP2062261A4 (fr) 2006-08-22 2007-08-22 Système de mémoire évolutif
JP2009524855A JP5575474B2 (ja) 2006-08-22 2007-08-22 スケーラブルメモリシステム
CA002659828A CA2659828A1 (fr) 2006-08-22 2007-08-22 Systeme de memoire evolutif

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US83932906P 2006-08-22 2006-08-22
US60/839,329 2006-08-22
US86877306P 2006-12-06 2006-12-06
US60/868,773 2006-12-06
US90200307P 2007-02-16 2007-02-16
US60/902,003 2007-02-16
US89270507P 2007-03-02 2007-03-02
US60/892,705 2007-03-02
US11/840,692 US7904639B2 (en) 2006-08-22 2007-08-17 Modular command structure for memory and memory system
US11/840,692 2007-08-17

Publications (1)

Publication Number Publication Date
WO2008022454A1 true WO2008022454A1 (fr) 2008-02-28

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2007/001469 WO2008022454A1 (fr) 2006-08-22 2007-08-22 Système de mémoire évolutif

Country Status (7)

Country Link
EP (1) EP2062261A4 (fr)
JP (2) JP5575474B2 (fr)
KR (2) KR101476515B1 (fr)
CN (2) CN102760476A (fr)
CA (1) CA2659828A1 (fr)
TW (1) TWI437577B (fr)
WO (1) WO2008022454A1 (fr)

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WO2011134051A1 (fr) * 2010-04-26 2011-11-03 Mosaid Technologies Incorporated Mémoire connectée en série dotée d'une interface de données subdivisée
JP2012504263A (ja) * 2008-09-30 2012-02-16 モサイド・テクノロジーズ・インコーポレーテッド 出力遅延調整によるシリアル接続のメモリシステム
JP2012505448A (ja) * 2008-10-14 2012-03-01 モサイド・テクノロジーズ・インコーポレーテッド ディスクリートメモリデバイスをシステムに接続するためのブリッジデバイスを有する複合メモリ
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KR102532528B1 (ko) * 2016-04-07 2023-05-17 에스케이하이닉스 주식회사 메모리 장치 및 이의 동작 방법
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US11209981B2 (en) 2018-06-28 2021-12-28 Micron Technology, Inc. Apparatuses and methods for configurable memory array bank architectures
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CN101506895A (zh) 2009-08-12
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EP2062261A1 (fr) 2009-05-27
JP2010501916A (ja) 2010-01-21
JP5575474B2 (ja) 2014-08-20
TW200828338A (en) 2008-07-01
KR101476463B1 (ko) 2014-12-24
KR101476515B1 (ko) 2014-12-24
KR20120110157A (ko) 2012-10-09
CN102760476A (zh) 2012-10-31
KR20090045366A (ko) 2009-05-07
EP2062261A4 (fr) 2010-01-06
CA2659828A1 (fr) 2008-02-28
CN101506895B (zh) 2012-06-27

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