JP5575474B2 - スケーラブルメモリシステム - Google Patents

スケーラブルメモリシステム Download PDF

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Publication number
JP5575474B2
JP5575474B2 JP2009524855A JP2009524855A JP5575474B2 JP 5575474 B2 JP5575474 B2 JP 5575474B2 JP 2009524855 A JP2009524855 A JP 2009524855A JP 2009524855 A JP2009524855 A JP 2009524855A JP 5575474 B2 JP5575474 B2 JP 5575474B2
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JP
Japan
Prior art keywords
memory
memory device
command
data
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009524855A
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English (en)
Japanese (ja)
Other versions
JP2010501916A5 (fr
JP2010501916A (ja
Inventor
ジン−キ・キム
ハク・ジュン・オー
ホン・ボム・ピョン
スティーブン・プルジビルスキー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Conversant Intellectual Property Management Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/840,692 external-priority patent/US7904639B2/en
Application filed by Conversant Intellectual Property Management Inc filed Critical Conversant Intellectual Property Management Inc
Publication of JP2010501916A publication Critical patent/JP2010501916A/ja
Publication of JP2010501916A5 publication Critical patent/JP2010501916A5/ja
Application granted granted Critical
Publication of JP5575474B2 publication Critical patent/JP5575474B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP2009524855A 2006-08-22 2007-08-22 スケーラブルメモリシステム Expired - Fee Related JP5575474B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US83932906P 2006-08-22 2006-08-22
US60/839,329 2006-08-22
US86877306P 2006-12-06 2006-12-06
US60/868,773 2006-12-06
US90200307P 2007-02-16 2007-02-16
US60/902,003 2007-02-16
US89270507P 2007-03-02 2007-03-02
US60/892,705 2007-03-02
US11/840,692 2007-08-17
US11/840,692 US7904639B2 (en) 2006-08-22 2007-08-17 Modular command structure for memory and memory system
PCT/CA2007/001469 WO2008022454A1 (fr) 2006-08-22 2007-08-22 Système de mémoire évolutif

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012182111A Division JP2012226786A (ja) 2006-08-22 2012-08-21 スケーラブルメモリシステム

Publications (3)

Publication Number Publication Date
JP2010501916A JP2010501916A (ja) 2010-01-21
JP2010501916A5 JP2010501916A5 (fr) 2012-09-20
JP5575474B2 true JP5575474B2 (ja) 2014-08-20

Family

ID=39106444

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2009524855A Expired - Fee Related JP5575474B2 (ja) 2006-08-22 2007-08-22 スケーラブルメモリシステム
JP2012182111A Ceased JP2012226786A (ja) 2006-08-22 2012-08-21 スケーラブルメモリシステム

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2012182111A Ceased JP2012226786A (ja) 2006-08-22 2012-08-21 スケーラブルメモリシステム

Country Status (7)

Country Link
EP (1) EP2062261A4 (fr)
JP (2) JP5575474B2 (fr)
KR (2) KR101476463B1 (fr)
CN (2) CN101506895B (fr)
CA (1) CA2659828A1 (fr)
TW (1) TWI437577B (fr)
WO (1) WO2008022454A1 (fr)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7865756B2 (en) 2007-03-12 2011-01-04 Mosaid Technologies Incorporated Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices
US8467486B2 (en) 2007-12-14 2013-06-18 Mosaid Technologies Incorporated Memory controller with flexible data alignment to clock
US8781053B2 (en) 2007-12-14 2014-07-15 Conversant Intellectual Property Management Incorporated Clock reproducing and timing method in a system having a plurality of devices
EP2329496A4 (fr) * 2008-09-30 2012-06-13 Mosaid Technologies Inc Système de mémoire connecté en série présentant un ajustement de délai de sortie
US7957173B2 (en) * 2008-10-14 2011-06-07 Mosaid Technologies Incorporated Composite memory having a bridging device for connecting discrete memory devices to a system
KR101687038B1 (ko) * 2008-12-18 2016-12-15 노바칩스 캐나다 인크. 에러 검출 방법 및 하나 이상의 메모리 장치를 포함하는 시스템
US20110002169A1 (en) 2009-07-06 2011-01-06 Yan Li Bad Column Management with Bit Information in Non-Volatile Memory Systems
US20110258366A1 (en) * 2010-04-19 2011-10-20 Mosaid Technologies Incorporated Status indication in a system having a plurality of memory devices
WO2011134051A1 (fr) * 2010-04-26 2011-11-03 Mosaid Technologies Incorporated Mémoire connectée en série dotée d'une interface de données subdivisée
US8856482B2 (en) * 2011-03-11 2014-10-07 Micron Technology, Inc. Systems, devices, memory controllers, and methods for memory initialization
US9239806B2 (en) * 2011-03-11 2016-01-19 Micron Technology, Inc. Systems, devices, memory controllers, and methods for controlling memory
US9342446B2 (en) 2011-03-29 2016-05-17 SanDisk Technologies, Inc. Non-volatile memory system allowing reverse eviction of data updates to non-volatile binary cache
CN102508797B (zh) * 2011-10-27 2015-02-11 忆正存储技术（武汉）有限公司 闪存控制扩展模块、控制器、存储系统及其数据传输方法
TWI581267B (zh) * 2011-11-02 2017-05-01 諾瓦晶片加拿大公司 快閃記憶體模組及記憶體子系統
US8825967B2 (en) 2011-12-08 2014-09-02 Conversant Intellectual Property Management Inc. Independent write and read control in serially-connected devices
US8966151B2 (en) * 2012-03-30 2015-02-24 Spansion Llc Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal
US9760149B2 (en) * 2013-01-08 2017-09-12 Qualcomm Incorporated Enhanced dynamic memory management with intelligent current/power consumption minimization
KR20150110918A (ko) 2014-03-21 2015-10-05 에스케이하이닉스 주식회사 반도체 메모리 장치
US9792227B2 (en) * 2014-08-19 2017-10-17 Samsung Electronics Co., Ltd. Heterogeneous unified memory
JP6453718B2 (ja) * 2015-06-12 2019-01-16 東芝メモリ株式会社 半導体記憶装置及びメモリシステム
KR102296740B1 (ko) * 2015-09-16 2021-09-01 삼성전자 주식회사 메모리 장치 및 그것을 포함하는 메모리 시스템
FR3041806B1 (fr) * 2015-09-25 2017-10-20 Stmicroelectronics Rousset Dispositif de memoire non volatile, par exemple du type eeprom, ayant une capacite memoire importante, par exemple 16mbits
KR102457820B1 (ko) 2016-03-02 2022-10-24 한국전자통신연구원 메모리 인터페이스 장치
KR102532528B1 (ko) * 2016-04-07 2023-05-17 에스케이하이닉스 주식회사 메모리 장치 및 이의 동작 방법
KR102669694B1 (ko) * 2016-09-28 2024-05-28 삼성전자주식회사 서로 직렬로 연결된 스토리지 장치들 중 애플리케이션 프로세서에 직접 연결되지 않는 스토리지 장치를 리셋시키는 전자 기기 및 그것의 동작 방법
KR102514717B1 (ko) * 2016-10-24 2023-03-27 삼성전자주식회사 메모리 컨트롤러 및 이를 포함하는 메모리 시스템
KR102336666B1 (ko) * 2017-09-15 2021-12-07 삼성전자 주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
KR20190112546A (ko) * 2018-03-26 2019-10-07 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작 방법
US10372330B1 (en) 2018-06-28 2019-08-06 Micron Technology, Inc. Apparatuses and methods for configurable memory array bank architectures
US11043488B2 (en) * 2019-01-24 2021-06-22 Western Digital Technologies, Inc. High voltage protection for high-speed data interface
KR102708771B1 (ko) 2020-05-25 2024-09-20 삼성전자주식회사 디스플레이 구동 장치 및 디스플레이 구동 장치를 포함하는 디스플레이 장치
KR20230085629A (ko) 2021-12-07 2023-06-14 에스케이하이닉스 주식회사 저장 장치 및 그 동작 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07327179A (ja) * 1994-05-31 1995-12-12 Canon Inc 複数映像切替装置
US5729683A (en) * 1995-05-18 1998-03-17 Compaq Computer Corporation Programming memory devices through the parallel port of a computer system
US6144576A (en) * 1998-08-19 2000-11-07 Intel Corporation Method and apparatus for implementing a serial memory architecture
JP3853537B2 (ja) * 1999-04-30 2006-12-06 株式会社日立製作所 半導体メモリファイルシステム
US6449308B1 (en) * 1999-05-25 2002-09-10 Intel Corporation High-speed digital distribution system
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
JP2001266579A (ja) * 2000-01-12 2001-09-28 Hitachi Ltd 不揮発性半導体記憶装置および半導体ディスク装置
TW504694B (en) * 2000-01-12 2002-10-01 Hitachi Ltd Non-volatile semiconductor memory device and semiconductor disk device
US6754129B2 (en) * 2002-01-24 2004-06-22 Micron Technology, Inc. Memory module with integrated bus termination
US20040022022A1 (en) * 2002-08-02 2004-02-05 Voge Brendan A. Modular system customized by system backplane
US7308524B2 (en) * 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
JP2004110849A (ja) * 2003-12-01 2004-04-08 Toshiba Corp 半導体システム及びメモリカード
US8375146B2 (en) * 2004-08-09 2013-02-12 SanDisk Technologies, Inc. Ring bus structure and its use in flash memory systems

Also Published As

Publication number Publication date
KR101476463B1 (ko) 2014-12-24
CA2659828A1 (fr) 2008-02-28
KR20090045366A (ko) 2009-05-07
EP2062261A4 (fr) 2010-01-06
WO2008022454A1 (fr) 2008-02-28
CN101506895B (zh) 2012-06-27
KR101476515B1 (ko) 2014-12-24
KR20120110157A (ko) 2012-10-09
CN102760476A (zh) 2012-10-31
EP2062261A1 (fr) 2009-05-27
TW200828338A (en) 2008-07-01
CN101506895A (zh) 2009-08-12
TWI437577B (zh) 2014-05-11
JP2010501916A (ja) 2010-01-21
JP2012226786A (ja) 2012-11-15

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