EP2062261A1 - Système de mémoire évolutif - Google Patents
Système de mémoire évolutifInfo
- Publication number
- EP2062261A1 EP2062261A1 EP07800496A EP07800496A EP2062261A1 EP 2062261 A1 EP2062261 A1 EP 2062261A1 EP 07800496 A EP07800496 A EP 07800496A EP 07800496 A EP07800496 A EP 07800496A EP 2062261 A1 EP2062261 A1 EP 2062261A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- memory
- command
- memory device
- data
- packet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
Definitions
- the present invention relates generally to memory systems. More particularly, the present invention relates to a memory system of serially connected memory devices for mass storage applications.
- Flash memory is a commonly used type of non- volatile memory in widespread use as mass storage for consumer electronics, such as digital cameras and portable digital music players for example.
- the density of a presently available Flash memory chip can be up to 32Gbits (4GB), which is suitable for use in popular USB Flash drives since the size of one Flash chip is small.
- Figure l is a general block diagram of one bank of a known NAND flash memory. Those skilled in the art will understand that a flash memory device can have any number of banks.
- Bank 30 is organized into k+1 blocks. Each block consists of NAND memory cell strings, having up to i+1 flash memory cells serially connected to each other. Accordingly, wordlines WLO to WLi are connected to the gates of each Flash memory cell in the memory cell string.
- a string select device connected to signal SSL selectively connects the memory cell string to a bitline
- a ground select device connected to signal GSL ground select line
- the string select device and the ground select device are n-channel transistors.
- each bitline is connected to one NAND memory cell string in each of blocks [0] to [k].
- Each wordline (WLO to WLi), SSL and GSL signal is connected to the same corresponding transistor device in each NAND memory cell string in the block.
- data stored in the flash memory cells along one wordline is referred to as a page of data.
- a data register 32 Connected to each bitline outside of the bank 30 is a data register 32 for storing one page of write data to be programmed into one page of flash memory cells, or read data accessed from the flash memory cells.
- Data register 32 also includes sense circuits for sensing data read from one page of flash memory cells. During programming operations, the data registers perform program verify operations to ensure that the data has been properly programmed into the flash memory cells connected to the selected wordline.
- Each memory cell of bank 30 can store a single bit of data or multiple bits of data. Some flash memory devices will have more than one set of data registers to increase throughput.
- Flash memory devices are combined together into a memory system to effectively increase the available storage capacity. For example, Flash storage densities of 20GB may be required for such applications.
- FIG. 2 is a block diagram of a prior art flash memory system 10 integrated with a host system 12.
- Flash memory system 10 includes a memory controller 14 in communication with host system 12, and multiple non-volatile memory devices 16.
- the host system will include a processing device such as a microcontroller, microprocessor, or a computer system.
- the Flash memory system 10 of Figure 2 is configured to include one channel 18, where memory devices 16 are connected in parallel to channel 18.
- the memory system 10 can have more or less than four memory devices connected to it.
- Channel 18 includes a set of common buses, which include data and control lines that are connected to all its corresponding memory devices. Each memory device is enabled/disabled with respective chip select signals CE#1, CE#2, CE#3 and CE#4, provided by memory controller 14. The "#" indicates that the signal is an active low logic level signal.
- the memory controller 14 is responsible for issuing commands and data, via the channel 18, to a selected memory device based on the operation of the host system 12. Data read from the memory devices is transferred via the channel 18 back to the memory controller 14 and host system 12. Operation of flash memory system 10 is synchronized to a clock CLK, which is provided in parallel to each memory device 16. Flash memory system 10 is generally referred to as a multi-drop configuration, in which the memory devices 16 are connected in parallel with respect to channel 18.
- non-volatile memory devices 16 can be identical to each other, and are typically implemented as NAND flash memory devices. Those skilled in the art will understand that flash memory is organized into banks, and each bank is organized into blocks to facilitate block erasure. Most commercially available NAND flash memory devices are configured to have two banks of memory.
- Flash memory system 10 imposes physical performance limitations. With the large number of parallel signals extending across the system, the signal integrity of the signals they carry will be degraded by crosstalk, signal skew, and simultaneous switching noise (SSN). Power consumption in such a configuration becomes an issue as each signal track between the flash controller and flash memory devices is frequently charged and discharged for signaling. With increasing system clock frequencies, the power consumption will increase.
- a memory system having a controller and a memory device.
- the controller includes a serial channel output port for providing a serial bitstream command packet, and a serial channel input port for receiving a serial bitstream read data packet.
- the serial bitstream command packet includes an operational code and a device address.
- the memory device has an input port for receiving the serial bitstream command packet from the controller and for executing the operation code if the device address corresponds to the memory device.
- the memory device provides the serial bitstream command packet through an output port and subsequently provides the serial bitstream read data packet through the output port if the operation code corresponds to a read function.
- the at least one intervening memory device having an input port for receiving and passing the serial bitstream command packet to the memory device, and subsequently providing the serial bitstream read data packet if the device address corresponds to the memory device and the operation code corresponds to a read function.
- complementary clock signals are provided to the memory device and the at least one intervening memory device in parallel, or the complementary clock signals are provided to the at least one intervening memory device, and passed by the at least one intervening memory device to the memory device, and passed by the memory device to the controller.
- the memory system includes an expansion link between the controller and the memory device for receiving one of an expansion module and a jumper.
- the at least one intervening memory device is part of an expansion module having coupling means configured for electrical coupling with the expansion link.
- the memory device and the at least one intervening memory device each include a native memory core and a serial interface and control logic block for controlling the native memory core in response to the serial bitstream command packet.
- the memory device native memory core and the at least one intervening memory device native memory core can be NAND flash based, or can be DRAM, SRAM, NAND flash and NOR flash memory cores.
- the serial bitstream command packet has a modular structure where the size of the serial bitstream command packet is variable.
- the serial bitstream command packet can include a command field for providing the operation code and the device address, where the command field includes a first sub-field for providing the operation code, and a second sub-field for providing the device address.
- the serial bitstream command packet can include a command field for providing the operation code and the device address, and an address field for providing one of a row address and a column address.
- the serial bitstream command packet can include a command field for providing the operation code and the device address, an address field for providing one of a row address and a column address, and a data field for providing write data.
- the controller provides a command strobe in parallel with the serial bitstream command packet, the command strobe having an active level matching the length of the serial bitstream command packet. Furthermore, the controller provides a data input strobe in parallel with the serial bitstream read data packet, the data input strobe having an active level matching the length of the serial bitstream read data packet.
- the memory device latches the serial bitstream command packet in response to the active level of the command strobe when the device address corresponds to the memory device, and the memory device output port is enabled in response to the active level of the data input strobe.
- the command strobe and the data input strobe are non-overlapping signals, and are separated by at least one data latching clock edge. Additionally, the command strobe is separated from an adjacent command strobe by at least one data latching clock edge, and the data input strobe is separated from an adjacent data input strobe by at least one data latching clock edge.
- a command packet having a series of bits for a memory system having serially connected memory devices.
- the command packet includes a command field for selecting a memory device of the serially connected memory devices to execute a specific memory operation.
- the command field includes a first sub-field for providing a device address for selecting the memory device, and a second sub-field for providing an operation code corresponding to the specific memory operation.
- the command packet further includes an address field following the command field for providing one of a row address and a column address when the operation code corresponds to a read or write operation, the address field having a bit length corresponding to the row address or the column address.
- a data field follows the address field for providing write data for storage in the memory device when the operation code corresponds to the write operation, the data field having a bit length corresponding to the write data.
- a method for executing concurrent operations in a selected memory device of a memory system having serially connected memory devices includes receiving a first command; executing core operations in a first memory bank of the selected memory device in response to the first command; receiving a second command during execution of core operations in the first memory bank; and, executing core operations in a second memory bank of the selected memory device in response to the second command.
- the method further includes receiving a third command for requesting result information from one of the first memory bank and the second memory bank, and outputting a read data packet containing the result information in response to the third command.
- the result information includes one of status register data and read data.
- the first command, the second command and the third command are command packets including a series of bits logically configured to include a mandatory command field for providing an operation code and a device address, an optional address field following the command field for providing one of a row and column address when the operation code corresponds to a read or write operation, and an optional data field following the address field for providing write data when the operation code corresponds to the write operation.
- a first command strobe is received in parallel with the first command, the first command strobe having an active duration corresponding to the length of the first command
- a second command strobe is received in parallel with the second command, the second command strobe having an active duration corresponding to the length of the second command.
- the first command strobe and the second command strobe are separated by at least one data latching clock edge.
- a data input strobe is received for enabling outputting of the read data packet while the data input strobe is at the active level, such that the second command strobe and data input strobe are separated by at least one data latching clock edge.
- the method further includes powering up the selected memory device before receiving the first command.
- the step of powering up includes asserting a control signal to maintain the selected memory device in a default state prior to a power transition; transitioning a power level of the selected memory device from a first voltage level to a second voltage level while the control signal is asserted; waiting for a predetermined duration of time to allow the power level to stabilize; and de-asserting the control signal to release the selected memory device from the default state thereby preventing accidental program or erase operation in the selected memory device.
- the second voltage level can be a minimum voltage level for stable circuit operation or a maximum operating voltage level of a power supply.
- the first voltage level can correspond to a low power mode operating voltage level of a power supply or the absence of a power supply.
- maintaining the memory device in the default state includes setting device registers in the memory device to a default value, where the device registers include command registers.
- a further step of the method can include performing device initialization upon release of the memory device from the default state. The step of performing device initialization can include generating device address and device identifier information for the memory device.
- the step of powering up includes asserting a control signal at a first time to maintain the memory device in a default state prior to a power transition; transistioning a power level of the memory device from a first level to a second level at a second subsequent time while the control signal is asserted; waiting for a predetermined duration of time to allow the power level to stabilize; and de-asserting the control signal at a third subsequent time for releasing the memory device from the default state thereby preventing accidental program or erase operation in the memory device.
- a memory system comprising a plurality of memory devices and a controller for controlling the devices.
- the controller has an output port for providing a bitstream command packet to a first device of the plurality of memory devices, the bitstream command packet including an operational code and a device address.
- Each of the plurality of memory devices receive the bitstream command packet from one of the controller and a prior memory device, and executes the operation code if the device address corresponds thereto, each of the plurality of memory devices providing the bitstream command packet to one of a next memory device and the controller, a bitstream read data packet being provided from a last memory device of the plurality of memory devices to the controller if the operation code corresponds to a read function.
- the plurality of memory devices are connected in series, the first and last memory devices being connected to the controller, and the controller sends a bitstream data packet to the first device of the plurality of memory devices.
- the bitstream data packet from the controller and the bitstream read data packet comprises a serial bitstream or comprises parallel bitstreams.
- the plurality of memory devices are either of the same type or a mix of different types of memory devices.
- a memory system comprising a plurality of memory devices and a controller for controlling the devices, the memory system being capable of performing the function of powering up a selected memory device before receiving a first command.
- the function of powering up includes: asserting a control signal to maintain the selected memory device in a default state prior to a power transition; transitioning a power level of the selected memory device from a first voltage level to a second voltage level while the control signal is asserted; waiting for a predetermined duration of time to allow the power level to stabilize; and de-asserting the control signal to release the selected memory device from the default state thereby preventing accidental program or erase operation in the selected memory device.
- the function of powering up may include: asserting a control signal at a first time, to maintain the memory device in a default state prior to a power transition; transistioning a power level of the memory device from a first level to a second level at a second subsequent time while the control signal is asserted; waiting for a predetermined duration of time to allow the power level to stabilize; and de-asserting the control signal at a third subsequent time for releasing the memory device from the default state thereby preventing accidental program or erase operation in the memory device.
- Fig. 1 is a schematic of a prior art NAND Flash memory core
- Fig. 2 is a block diagram of a prior art Flash memory system
- Fig. 3A is a general block diagram of a serial memory system
- Fig. 3B is a block diagram of a serial memory system consisting of NAND flash memory devices
- Fig. 3C is a block diagram of a serial memory system consisting of a mix of different memory devices
- Fig. 4 is a block diagram of the serial memory system of Figure 3A configured with a parallel clock scheme
- Fig. 5 is a block diagram of the serial memory system of Figure 3A configured with a source synchronous clock scheme
- Fig. 6 is a block diagram of a dynamically adjustable serial memory system
- Fig. 7 is a block diagram of a memory device having a native core and a serial input/output interface suitable for use in the serial memory systems of Figures 3A to 3C and 4 to 6
- Fig. 8 is an illustration of a modular command packet structure
- Fig. 9 shows a table listing example modular command packets for operating a flash memory device of Figure 7.
- Fig. 10 is a flow chart of a method for executing concurrent operations in one memory device
- Fig. 11 is a sequence diagram illustrating a concurrent read operation for two different banks of a memory device
- Fig. 12 is a sequence diagram illustrating a concurrent program operation for two different banks of a memory device
- Fig. 13 is a sequence diagram illustrating a concurrent read and program operation for two different banks of a memory device
- Fig. 14 is a sequence diagram illustrating a concurrent block erase for two different banks of a memory device
- Fig. 15 is a sequence diagram illustrating a concurrent program and read operations for two different banks of a memory device, with suspended and resumed operation;
- Fig. 16 is a sequence diagram illustrating the operation of two serially connected memory devices;
- Fig. 17A is a block diagram of a flash memory device to which embodiments of the present invention are applicable;
- Fig. 17B is a schematic of a flip-flop;
- Fig. 18 is a sequence diagram of various control signals during power up and power down operations in the flash memory device of Figure 17A;
- Fig. 19 is a sequence diagram of various control signals during power up and power down operations in a non-volatile memory device
- Fig. 20 is a flow chart illustrating a method for data protection during power transitions in a non-volatile memory device
- Fig. 21 is a flow chart illustrating a method for data protection during power transitions in a non- volatile memory device according to another embodiment of the present invention.
- a memory system architecture having serially connected memory devices is described.
- the memory system is scalable to include any number of memory devices without any performance degradation or complex redesign.
- Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller.
- the memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol.
- the command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command.
- Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data.
- the modular command protocol is used for executing concurrent operations in each memory device to further improve performance.
- Figure 3A is a block diagram illustrating the conceptual nature of a serial memory system architecture, according to one embodiment.
- the serial memory system 100 includes a memory controller 102 having at least one serial channel output port Sout and a serial channel input port Sin, and memory devices 104, 106, 108, 110, 112, 114 and 116 that are connected in series.
- the memory devices can be flash memory devices.
- the memory devices can be DRAM, SRAM or any other type of memory device provided it has a serial input/output interface compatible with a specific command structure, for executing commands or passing through commands and data to the next memory device. Further details of such memory device configuration and a specific command structure will be described later.
- the current embodiment includes seven memory devices, but alternate embodiments can include as few as one memory device, and up to any number of memory devices.
- memory device 104 is the first device of serial memory system 100 as it is connected to Sout
- memory device 116 is the Nth or last device as it is connected to Sin, where N is an integer number greater than zero.
- Memory devices 106 to 114 are then intervening serially connected memory devices between the first and last memory devices.
- Each memory device can assume a distinct identification number, or device address (DA) upon power up initialization of the system, so that they are individually addressable.
- DA device address
- Commonly owned U.S. Patent Application Nos. 11/622,828, 11/750,649, 11/692,452, 11/692,446, 11/692,326 and 11/771,023 describe methods for generating device addresses for serially connected memory devices of a memory system.
- Memory devices 104 to 116 are considered serially connected because the data input of one memory device is connected to the data output of a previous memory device, thereby forming a series-connection configuration, with the exception of the first and last memory devices in the chain.
- the channel of memory controller 102 includes a data channel of any data width to carry command, data and address information, and a control channel to carry control signal data. Further details of the channel configuration will be shown later.
- the embodiment of Figure 3A includes one channel, where one channel includes Sout and corresponding Sin ports.
- memory controller 102 can include any number of channels for accommodating separate memory device chains.
- the memory controller 102 issues a command through its Sout port, which includes an operational code (op code), a device address, address information for reading or programming, and data for programming.
- the command is issued as a serial bitstream packet, where the packet can be logically subdivided into predetermined size segments, such as a byte for example.
- a bitstream is a sequence or series of bits provided over time.
- the command is received by the first memory device 104, which compares the device address to its assigned address. If the addresses match, then memory device 104 executes the command. Otherwise, the command is passed through its own output port to the next memory device 106, where the same procedure is repeated.
- the memory device having the matching device address referred to as a selected memory device, will execute the operation dictated by the command. If the command is to read data, the selected memory device will output the read data through its output port, which is serially passed through intervening memory devices until it reaches the Sin port of the memory controller 102.
- FIG. 3B is a block diagram illustrating that the memory system of Figure 3A can include one type of memory device, such as NAND flash memory devices. Each NAND flash memory device can be identical to each other or different from each other, by having different storage densities for example.
- Figure 3C is a block diagram illustrating that the memory system of Figure 3A can include a variety of types of memory devices.
- These memory devices can include NAND flash memory devices, NOR flash memory devices, dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices and magnetoresistive random access memory (MRAM) devices for example.
- DRAM dynamic random access memory
- SRAM static random access memory
- MRAM magnetoresistive random access memory
- alternate memory devices not mentioned here can be employed in the memory system.
- Such a configuration having memory devices of mixed types is disclosed in U.S. Provisional Patent Application No. 60/868,773 filed December 6, 2006.
- Serial memory system 200 includes a memory controller 202 and four memory devices 204, 206, 208 and 210.
- the memory controller 202 provides several signals in parallel to the memory devices. These include the chip enable signal CE#, the reset signal RST#, and complementary clocks CK# and CK.
- CE# the device is enabled when CE# is at the low logic level. Once the memory device starts a program or erase operation, CE# can be de-asserted, or driven to a high logic level. In addition, CE# at the low logic level can activate the internal clock signals and CE# at the high logic level can deactivate the internal clock signals.
- the memory device is set to a reset mode when RST# is at the low logic level.
- the reset mode the power is allowed to stabilize and the device prepares itself for operation by initializing all finite state machines and resetting any configuration and status registers to their default states.
- the channel of memory controller 202 includes a data channel consisting of data output port Qn and data input port Dn, and a control channel consisting of a command strobe input CSI, a command strobe output CSO (echo of CSI), data strobe input DSI, and a data strobe output DSO (echo of DSI).
- Output port Qn and input port Dn can be one bit in width, or n bits in width where n is a non-zero integer, depending on the desired configuration. For example, if n is 1 then one byte of data is received after eight data latching edges of the clock.
- a data latching clock edge can be a rising clock edge for example.
- the memory device can be statically configured or dynamically configured for any width of Qn and Dn. Hence, in a configuration where n is greater than 1, the memory controller provides data in parallel bitstreams.
- CSI is used for latching command data appearing on the input port Dn, and has a pulse duration corresponding to the length of the command data received. More specifically, the command data will have a duration measured by a number of clock cycles, and the pulse duration of the CSI signal will have a corresponding duration.
- DSI is used for enabling the output port Qn buffer to output data, and has a pulse duration corresponding to the length of the read data being requested. Further details of the DSI and CSI signals will be discussed later.
- each memory device has the same serial input/output interface, which includes an RST#, CE#, CK# and CK input ports for receiving the same named signals from the memory controller 202.
- Serial input/output interface further includes a data input port Dn, a data output port Qn, CSI, DSI, CSO and DSO ports.
- the Dn, CSI and DSI input ports for each memory device are connected to the Qn, CSO and DSO output ports respectively, of a previous memory device. Accordingly, the memory devices are considered serially connected to each other as each can pass command and read data to the next memory device in the chain.
- each memory device is positioned on a printed circuit board such that the distance and signal track between input and output ports is minimized.
- the four memory devices can be implemented in a system in package module (SIP) which further minimizes signal tranck lengths.
- SIP system in package module
- Memory controller 202 and memory devices 204 to 210 are serially connected to form a ring topology, meaning that the last memory device 210 provides its outputs back to the memory controller 202. As such, those skilled in the art will understand that the distance between memory device 210 and memory controller 202 is easily minimized.
- the performance of the memory devices in the serial memory system 200 of Figure 4 is significantly improved over the performance of the memory devices in the prior art system of Figure 1.
- the data rate per pin of one of the serially connected memory devices of Figure 4 will be about 133 Mbps.
- the data rate per pin of a multi-drop memory device of Figure 1 having four memory devices will be about 40 Mbps, given that the read cycle time (tRC) and the write cycle time (tWC) for each memory device is rated to be about 25ns.
- the power consumption of the serial memory system 200 will be reduced relative to that of the prior art system of Figure 1.
- the performance and power consumption advantage of the serial memory system 200 is primarily due to the absence of a signal track 18 that must be driven by each memory device.
- a significant advantage of the serial memory system 200 of Figure 4 is the scalability of the system. In other words, more than four memory devices can be included in the memory chain connected to the memory controller 202 without any degradation in performance.
- the prior art system of Figure 1 will reach a practical limitation with diminishing returns as more memory devices are added, because the length of the signal tracks of channel 18 is necessarily increased to accommodate the additional devices. Additional pin loading to the signal tracks is contributed by the additional devices.
- the clock frequency must be reduced in order to ensure data transmission integrity when driving a long channel 18, which degrades performance.
- the distribution of the clock will be designed to accommodate a large number of memory devices, and can include repeaters and a balanced tree to maintain clock integrity for all memory devices.
- serial memory system embodiment of Figure 4 provides significant performance advantages over the prior art memory system, further performance improvements are obtained by using the alternate serial memory system embodiment of
- Serial memory system 300 of Figure 5 is similar to the embodiment of Figure 4, except that instead of a parallel clock distribution scheme, a source synchronous clock scheme is used.
- Serial memory system 300 includes a memory controller 302 and four memory devices 304, 306, 308 and 310.
- the memory controller 302 includes clock output ports CKO# and CKO for providing complementary clock signals, and clock input ports CK# and CK for receiving the complementary clock signals from the last memory device of the system.
- the memory devices are the same as those shown in Figure 4, except that they now have clock input ports CK# and CK, and clock output ports CKO# and CKO, where the received clocks by one memory device at its CK# and CK ports is provided to the next device through its CKO# and CKO ports.
- the last memory device 310 provides the clock signals back to the memory controller 302.
- the main advantage of the embodiment of Figure 5 is the absence of any complex clock distribution scheme and the minimum clock interconnection between memory devices. Therefore, the minimum clock frequency can be increased to 166MHz, resulting in a minimum 333 Mbps data rate per pin.
- the embodiment of Figure 5 can be scaled to include any number of memory devices.
- a fifth memory device can be added to the embodiment of Figure 5 simply by connecting the output ports of memory device 310 to the corresponding input ports of the fifth memory device, and connecting the output ports of the fifth memory device to the memory controller 302.
- memory controller 302 can include a simple phase locked loop (PLL) circuit to maintain the clock frequency.
- PLL phase locked loop
- serial memory system 200 and 300 can be statically fixed for a specific number of memory devices. Different configurations can be set for providing different memory system capacities, simply by adjusting the number of memory devices in the serial chain. In alternate embodiments, memory devices having different capacities can be mixed together in the serial chain, thereby providing more flexibility in the overall memory system capacity. There may be applications where the memory system capacity can be dynamically adjusted by adding or removing modules from the serial chain, where a module can be a single memory device, an SIP memory, or a PCB having memory devices and/or SIP memory devices.
- Adjustable serial memory system 400 includes a memory controller 402, fixed memory devices 404, 406, 408 and 410, expansion links 412, 414, 416, 418 and 420, and expansion modules 422, 424 and 426.
- Fixed memory devices 404, 406, 408 and 410 are serially connected to each other, to intervening expansion links, and to the memory controller 402.
- Each expansion link is a male or female coupling means for releasably receiving and retaining a module having a corresponding female or male coupling means.
- Each module includes at least one memory device serially connected with the terminals of the expansion link.
- expansion modules 422 and 426 each include four memory devices that are serially connected between input connectors and output connectors of the module coupling means.
- Module 424 includes two memory devices serially connected between input connectors and output connectors of its module coupling means. Therefore, by inserting the module into an expansion link, additional serially connected memory devices can be dynamically inserted between fixed memory devices.
- Unused expansion links, such as expansion links 414 and 420 will have suitably configured jumpers 428 and 430 connected thereto for maintaining a continuous serial electrical connection of the chain.
- the adjustable serial memory system 400 can include any number of fixed memory devices and expansion links, and the memory modules can be configured to include any number of serially connected memory devices. Therefore, the adjustable serial memory system 400 has a fully expandable in memory capacity simply by adding new modules or replacing existing modules with larger capacity modules, without impacting overall performance. There is no requirement to change the memory controller, since the same channel is being populated with additional serially connected memory devices, and those skilled in the art will understand how to connect parallel control signals such as CE#, RST# and power supplies to the inserted modules. After insertion of the modules, or removal of modules, the memory system 400 is re-initialized so that the memory controller can automatically set device ID 's for the memory devices in the system.
- serial memory systems shown in Figures 3A to 3C and 4 to 6 employ memory devices, such as flash memory devices, having compatible serial input/output interfaces.
- memory devices such as flash memory devices
- An example of a flash memory device having a serial input/output interface is described in commonly owned U.S. Patent Application Serial No. 11/324,023, filed on December 30, 2005. Accordingly, the memory devices shown in the embodiments of Figures 3A to 3C and 4 to 6 can employ the flash memory devices disclosed in these patent applications.
- the serial input/output interface described in these patent applications are examples of a serial interface that can be used. Any serial input/output interface facilitating serial operation between memory devices can be used, provided it is configured for accepting a predetermined command structure.
- the serial input/output interface can be used with any type of memory device. More specifically, other memory types can be adapted to operate with the serial input/output interface.
- Figure 7 is a block diagram illustrating the conceptual organization of a generic memory device having a native core and a serial input/output interface suitable for use in the serial memory systems of Figures 3A to 3C and 4 to 6.
- Memory device 500 includes a native memory core, which includes memory array banks 502 and 504, and native control and I/O circuits 506 for accessing the memory array banks 502 and 504.
- the native memory core can be DRAM, SRAM, NAND flash, or NOR flash memory based for example.
- any emerging memory and its corresponding control circuits can be used.
- circuit block 506 can include error correction logic, high voltage generators, refresh logic and any other circuit blocks that are required for executing the operations native to the memory type.
- memory devices use command decoders for initializing the relevant circuits in response to a received command by asserting internal control signals. They will also include well known I/O circuitry for receiving and latching data, commands and addresses. According to the present embodiment, the existing I/O circuits are replaced with the serial interface and control logic block 508.
- the serial interface and control logic block 508 receives RST#, CE#, CK#, CK, CSI, DSI and Dn inputs, and provides Qn, CSO, DSO, CKO and CKO# outputs, which matches the input and output ports of the memory devices shown in Figure 5.
- the serial interface and control logic block 508 is responsible for various functions, as discussed in U.S. Patent Application No. 11/324,023.
- the notable functions of serial interface and control logic block 508 being setting a device identifier number, passing data through to the next serially connected memory device, and decoding a received command for executing native operations.
- This circuit can include a command decoder that replaces the native command decoder, which is configured to assert the same control signals that the native command decoder would have asserted, in response to a serially received command corresponding to the native command.
- the command set can be expanded to execute features usable by the memory controller when the memory devices are serially connected. For example, status register information can be requested to assess the status of the memory device.
- serial memory systems of Figures 3 A to 3C and 4 to 6 can include a mix of memory device types, each providing different advantages for the greater system.
- the high speed of DRAM memory can be used for caching operations while the non- volatility of flash memory can be used for mass data storage.
- each memory device is individually addressable to act upon a command because the serial interface and control logic block 506 is configured to receive commands according to a predetermined protocol.
- these commands consist of command packets having a modular command structure, which are used for controlling the individual memory devices of the serial memory system.
- specific commands can be issued to a memory device at different times as individual command packets.
- a command packet can initiate a specific operation for a first memory bank, and a subsequent command packet can then be received for initiating another operation for a second memory bank while core operations are being executed in response to the first command packet.
- Further command packets can be received for completing the operations for the first memory bank and the second memory bank in a similar interleaved manner. This is referred to as executing concurrent operations in the memory device.
- an explanation of the modular command protocol follows. Further details of the modular command protocol are described in commonly owned U.S. Provisional Patent Application Serial No. 60/892,705 filed on March 2, 2007 and titled "Modular Command Structure in Memory System and its Use".
- the command packet 600 has the structure illustrated in Figure 8, and includes three fields, two of which are optional depending on the specific command being issued by the memory controller.
- the first field being a mandatory field, is the command field 602.
- the first optional field is an address field 604, and the second optional field is a data field 606.
- the command field 602 includes two sub-fields, the first being a device address (DA) field 608 and the second being an op-code (OP Code) field 610.
- the device address field 608 can be any number of bits in length, and is used for addressing each memory device in the system. For example, a device address field 608 of 1 byte in length is sufficient for addressing up to 256 memory devices. One address can be reserved for addressing all memory devices simultaneously for broadcasting an operation.
- the device address field 608 can include a device type field to indicate the type of memory device the op-code field 610 is directed to. For example, the device type field can designate a DRAM, SRAM or flash memories.
- the op-code field 610 can be any number of bits in length to represent the commands for any number of memory devices, and can include a bank address.
- the flash memory command set will have different commands than a DRAM command set, hence the op-code field will be configured to accommodate all possible commands from both command sets if the memory system includes both types of memory devices.
- the address field 604 is used for providing either a row address (Row Addr) or a column address (Col Addr) of a memory array, depending on the type of operation specified by the op-code.
- the data field 606 will include any number of bits of data to be written or programmed to the memory device. Therefore, the command packets 600 will vary in size since write data may not be required for a particular operation and both addresses and write data may not be required for a particular operation.
- Figure 9 lists example command packets which can be used for operating a flash memory device having the configuration shown in Figure 7, for use in the previously described serial memory system.
- the byte positions in Figure 9 correspond to the order they are serially received by the memory device.
- the command field 602 occupies the first and second byte positions, which includes the device address (DA) as the first byte of information and an op-code corresponding to the operation as the second byte of information.
- the address field 604 can include a three-byte row address (RA) occupying the third to fifth byte positions, but will be shortened for other commands to include a two-byte column address (CA) occupying only the third and fourth byte positions.
- RA three-byte row address
- CA two-byte column address
- the data field 606 will occupy the fifth bit position to the 2116 th bit position, if the data should be that length.
- the data can occupy fewer or more byte positions.
- Any command packet 600 issued by the memory controller will be received serially by each memory device in the system, and only the memory device having a device address matching the DA sub-field 608 of the command field 602 will act upon the op-code sub-field 610. Otherwise, the command packet is passed through the memory device and to the next memory device in the chain. Since the op-code is specific to a particular operation, the memory device, and more specifically the serial interface and control logic block 508 of the memory device 500, will control the required circuits for latching address and/or data information of the command packet. For example, if a page read command packet is received by the designated memory device, the designated memory device will decode the op-code and control the appropriate circuits to latch the following three byte row address.
- the example command packets listed in Figure 9 are directed to flash memory operations.
- a set of command packets for any other type of memory device having different operations can be configured to follow the described command structure.
- the previously described command packets can be advantageously used for executing concurrent operations in a memory device, such as memory device 500 of Figure 7. If the memory device 500 is configured for accessing any of its banks independently, then substantially concurrent operations can be executed within the memory device. Independent access means that core operations for different memory banks can proceed independently of each other. An example of such a memory device is described in previously mentioned U.S. Patent Application Serial No. 11/324,023. Core operations refers to logical or functional operations which are not to be interrupted since the completion of a core operation may depend on a particular sequence of events executed under the control of a state machine or other logic.
- Concurrent operations will increase performance of the system since the memory controller does not need to wait until the memory device has fully completed the first operation before sending the command packet for the second operation.
- the memory device will not accept another command, or respond to a received command for a different memory bank until the core operations are completed for the current memory bank.
- the memory device will execute several operations in series before accepting another command.
- one command packet will initiate an operation in one memory bank, and a subsequent command packet will immediately initiate another operation in a second memory bank of the same memory device while core operations are being executed for the first memory bank. Therefore, both operations will be executed almost simultaneously by the two memory banks.
- Figure 10 is a flow chart illustrating a method for executing concurrent operations in one memory device, such as memory device 500 which is configured for independent access of its memory banks.
- a first command is issued by the memory controller and received by the memory device.
- the first command can be any one of the command packets previously described and shown in Figure 9.
- core operations will begin at step 702 for the first memory bank of the memory device. Occurring almost simultaneously with the initiation of the first memory bank core operations, a second command is issued by the memory controller and received by the memory device at step 704.
- Result information can include status information or read data, which is provided in response to a supplemental read command packet.
- Status information provides an indication of the success or failure of a particular type of operation, such as a program or erase operation, and is read from a status register associated with that memory bank in response to a supplemental "read status" command packet issued by the memory controller.
- Read data is provided in response to a supplemental "burst read” command packet.
- the core operation for a read operation will include outputting a page of data read from a block of the memory bank to the data registers block 32.
- a burst read operation is executed.
- result information pertaining the second command will be provided.
- the result information from both memory banks are eventually returned to the memory controller.
- the embodiment of Figure 10 illustrates the concurrent operation of two memory banks, but the method is applicable to the concurrent operation of two or more memory banks of the memory device.
- Figures 11 to 15 are sequence diagrams illustrating example concurrent operations executable by a flash memory device of the type described in U.S. Patent Application Serial No. 11/324,023.
- Figures 11 to 15 show signal traces for CSI, Dn, DSI, and Qn over time for one memory device of Figures 4 or 5.
- the illustrated sequences are intended to illustrate relative timing between signals, and not intended to represent specific timing values.
- the command strobe input CSI is generated by the memory controller and acts as an indicator for the length of the command assembled and issued by the memory controller.
- the corresponding CSI has an active edge (a rising edge in this example) corresponding to the first bit of the command and an inactive edge corresponding to the last bit of the command packet.
- the CSI signal controls the memory device command registers to latch the command data.
- the data strobe input signal DSI is also generated by the memory controller, and acts as an indicator for the length of the data being provided by the memory device. For example, if the read data requested by the memory controller is eight bytes in length, then the corresponding DSI generated by the memory controller will have an active edge corresponding to the first bit of the read data and an inactive edge corresponding to the last bit of the read data.
- CSI and DSI are generated by the memory controller as it has knowledge of the issued command bit length and the requested read data bit length.
- FIG 11 is a sequence diagram illustrating a concurrent read operation for two different banks of the memory device.
- a page read command packet 800 for bank 0 is latched by the memory device when CSI is at the high logic level.
- the page read command includes a two-byte command and a three-byte row address.
- Bank O of the memory device will begin executing the read operation for the designated row address after CSI falls to the low logic level, at time t ⁇ .
- a read operation for a flash memory device will include activation of a wordline, such as WLi in Figure 1, and sensing of the bitline data of BLO to BLj. Eventually, the sensed data is latched or stored in data register block 32.
- the page read command packet 800 is passed on to the next memory device through its Qn output port. In another embodiment, the page read command packet 800 is inhibited from being passed on to further memory devices since the present command packet 800 is addressed to the current memory device. For example, the page read command packet 800 provided on the Qn output can be set to a null value after being latched in the command registers. This will conserve power since no rail-to-rail signal switching of the signal line is required.
- a page read command packet 802 for bank 1 is latched by the memory device when CSI is at the high logic level.
- Bank 1 of the memory device will begin executing the read operation for the designated row address after CSI falls to the low logic level, at time tl. Now, concurrent operations are being executed by memory banks 0 and 1. After a specific number of clock cycles, the data is ready to be read out from bank 0 at time t2.
- the memory controller issues a burst read command packet 804, which is received and latched when CSI is at the high logic level. As shown in Figure 9, the burst read command packet will include a column address from which data is to be read.
- DSI will rise to the high logic level to enable the Qn output port buffer, thereby providing the output data for bank 0 as read data packet 806.
- the outputting of the data on the Qn output buffer can correspond to reading out data from the data register block 32 beginning at the column address specified in the burst read command packet 804 and ending when DSI falls to the low logic level.
- the data for bank 1 will be ready for read out at time t3.
- a burst read command packet 808 for bank 1 is received and latched by the memory device.
- DSI is driven to the high logic level again for a predetermined duration in order output the read data from bank 1 on the Qn output port as read data packet 810.
- FIG. 12 is a sequence diagram illustrating a concurrent program operation for two different banks of the memory device.
- command packets received at the Dn input port of the memory device are passed to its Qn output port, which is illustrated in the Qn signal trace of Figures 11 to 15.
- program data is first loaded into data registers of the memory device based on a specific column addresses, and then programmed to specific rows.
- a burst data load command packet 820 for bank 0 is received with the program data, followed shortly after by a page program command packet 822. Both command packets 820 and 822 are latched when CSI is at the high logic level. After the page program packet 822 is latched, and decoded by the memory device, core operations for programming the data to bank 0 begins at time t ⁇ .
- a burst data load command packet 824 for bank 1 is received with the program data, followed shortly after by a page program command packet 826.
- page program packet 826 is latched, and decoded by the memory device, core operations for programming the data to bank 1 begins at time tl.
- the memory controller can request the status of the memory device by issuing a read status command packet 828. This will access the status register of the memory device, whose data will be output on the Qn output port as read data packet 830 when DSI is at the high logic level. Those skilled in the art will understand that the status register is updated internally by the memory device as internal operations are executed. In the present example, the read data packet 830 will indicate that programming to bank 0 has been completed. A subsequently issued read status command packet 832 will result in read data packet 834 providing the value of the status register, which can indicate that programming to bank 1 has been completed. Once again, since the core programming operations of banks 0 and 1 are substantially concurrent and overlap, significant time is saved when compared to a sequential programming of the two banks.
- Figure 13 is a sequence diagram illustrating a concurrent read and program operation for two different banks of the memory device.
- a page read command packet 840 for bank 0 is latched by the memory device, followed by a burst data load start command packet 842 for bank 1, which is then followed by a page program command packet 844 for bank 1.
- core operations for reading data from bank 0 begin, while at time tl, core operations for programming data to bank 1 begin.
- the data will be ready at time t2 while core operations for programming data to bank 1 is in progress. Therefore, a burst read command packet 846 is received, and DSI is asserted to output the read data from bank 0 in read data packet 848.
- FIG. 14 is a sequence diagram illustrating a concurrent block erase for two different banks of the memory device.
- a block erase address input command packet 860 for bank 0 is latched by the memory device, followed by an erase command packet 862 for bank 0. After the erase command packet 862 is latched, core operations for bank 0 begin at time t ⁇ .
- a block erase address input command packet 864 for bank 1 is latched by the memory device, followed by an erase command packet 866 for bank 1.
- core operations for bank 1 begin at time tl.
- the structure of the block erase address input command and the erase command are shown in Figure 9. If the erase operation for bank 0 should be completed at time t2, and that of bank 1 should be completed at time t3, then separate read status command packets 868 and 870 can be issued and latched by the memory device.
- Corresponding read data packets 872 and 874 are provided on the Qn output port of the memory device, each providing the value of the status register.
- the CSI strobe signal is provided by the memory controller for indicating that the command data on the Dn input port is to be latched by the command registers, and can have a duration corresponding to the length of the command packet being issued. Since input data for programming a memory bank and output data read from a memory bank can be over 1000 bytes in length, those skilled in the art will appreciate that a relatively long time is required for inputting or outputting such quantities of data. According to the present embodiment, the CSI and DSI strobe signals can be prematurely de-asserted while program data is loaded or read data is output, and resumed at a later time.
- Figure 15 is a sequence diagram illustrating a concurrent program and read operations for two different banks of the memory device, with suspended and resumed operation.
- a burst data load start command packet 880 for bank 1 is latched, and the data payload in the data field of the command packet is latched by the memory device.
- the data loading into the memory device is suspended when the memory controller de-asserts CSI. In the present example, only 256 bytes of data have been latched by the memory device, which is tracked by the memory controller.
- a page read command packet 882 for bank 0 is latched, and core operations for bank 0 begin at time tl.
- the suspended data loading operation of command packet 880 is resumed at time t2 when a burst data load command packet 884 for bank 1 is received.
- the data payload in the data field of command packet 884 includes the remaining 1856 bytes of data that were not yet latched. Following is a page program command packet 886 for bank 1, and core operations for programming the data to bank 1 commences at time t3. Eventually, the core operations for bank 0 will be completed at time t4, and a burst read command packet 888 for bank 0 is issued by the memory controller and latched by the memory device. The read data is then output as a data read packet 890 when DSI is at the high logic level.
- the host system may wish to confirm that programming to bank 1 is completed, since the controller will know that programming operations should be completed within a certain predetermined time, such as at time t6.
- the outputting of the read data can be suspended at time t5 by deasserting DSI.
- a read status command packet 892 is issued by the memory controller and latched by the memory device. Then a corresponding read data packet 894 containing the status register value is provided. After DSI is deasserted at the end of the read data packet 894, the burst read can resume.
- the suspended operation example of Figure 15 illustrates the advantages of the modular command structure for executing concurrent operations, each of which can be suspended and resumed in order to maximize core utilization and utilization of the channel.
- the example sequences and operations of Figures 11 to 15 rely on the CSI and DSI strobe signals to provide information about the command packets or the read data packets.
- the command packets are variable in size, and there is no header information to indicate the bit length of the command packet
- the CSI strobe signal functions as a header for the command packet that is provided in parallel with the serial command packet.
- the CSI signal is active for the length of the command packet, and is used by the memory device to latch the command packet data appearing on the Dn input port into the appropriate registers.
- the DSI signal is active for the length of the expected read data packet, which is known by the memory controller, and travels in parallel with the read data packet. Hence the active DSI signal functions as a header for the read data packets.
- the lengths of the command packet and the read data packet corresponding to the lengths of their respective CSI and DSI strobe signals. Since both read data packets and command packets travel along the same signal lines connected between the Dn and Qn ports of adjacent memory devices, the presence of a CSI strobe with data designates the data as a command data packet while the presence of a DSI strobe with data designates the data as read data. Therefore, the strobe signals further identify the type of data traveling through the memory system. The memory controller will track the DSI strobes it issues so that can match a received read data packet with the type of data that is expected. For example, the read data packet can include status register information or data read from a memory array.
- a minimum separation time is inserted between subsequent strobe signals of any type. This is for ensuring that every command packet and read data packet is distinct and defined, and to ensure that the proper type of data is latched by the memory device of the memory controller.
- the CSI-to-CSI separation, tecs is the minimum separation time, in clock periods OocX between consecutive command packets to the same or different device. This separation time allows for the previous command to be cleared from the memory device, by clearing the command register and resetting any command logic for example, in preparation for the new command.
- the DSI-to-DSI separation, to DS is the minimum separation time, in clock periods (tcic), between consecutive read data packets to the same device. This separation time allows the output buffer circuits to reset in preparation for the next data to be output.
- the DSI-to-CSI separation, toes is the minimum separation time, in clock periods (tcic), between a read data packet and a subsequent command packet to the same or different device.
- the CSI-to-DSI separation, tcDs is the minimum separation time, in clock periods (tcic), between a command packet and a read data packet to the same device. These two separation times ensures that the proper data type is latched by the memory device, since both may appear in succession on the Dn input port of a memory device. Since the memory controller issues the CSI and DSI signals with knowledge of the command packet or data packet bit lengths, it will ensure that the command packets and data packets themselves are separated by the same minimum time as the strobe signals.
- the minimum separation time can be one data latching edge of the clock, which can be fractions of a clock period depending on the data rate architecture being employed. For example, in a single data rate architecture (SDR) where data is latched on the rising edge of the clock, the minimum separation time would be one clock cycle, or period. In a double data rate architecture (DDR) where data is latched on both the rising edge and the falling edge of the clock, the minimum separation time would be 0.5 of a clock period.
- Figures 11 to 15 are examples of concurrent operations in a single memory device, and do not clearly illustrate the relevance of the CSI-to-DSI separation or DSI-to-CSI separation.
- Figure 16 is a sequence diagram illustrating the relevance of the CSI-to-DSI or DSI-to-CSI separation.
- Figure 16 is an example scenario where a first memory device outputs its read data from its Qn output port and a second serially connected memory device receives a command packet after the read data is output from the first memory device.
- the two memory devices referred to in this example can correspond to those shown in Figures 4 and 5, for example.
- Signal traces for the DSI_1, CSI_1, DSO_1, CSO_1 and Qn_l ports are shown for the first memory device, where the appended "_1" designates ports of the first memory device.
- Signal traces for the DSI_2, CSI_2and Dn_2 ports are shown for the second memory device, where the appended "_2" designates ports of the second memory device.
- DSI_1 receives strobe signal 900 for outputting the data onto the Qn_l port, as a read data packet 902.
- Read data packet 902 is labeled "Qn_l Read DATA". Since the read data and the strobe signals are serially passed from the first memory device to the second memory device, DSO_1 passes the strobe signal 900 received from the DSI_1 port to the DSI_2 port of the second memory device. Similarly, read data packet 902 is passed from the Qn_l port of the first memory device to the DN_2 port of the second memory device.
- the memory controller now issues a command packet 904 addressed to the second memory device, labeled "Dn_2 CMD DATA", with an accompanying CSI strobe signal 906.
- Strobe signal 906 is passed through the first memory device via CSI_1 and the command packet is passed through the Dn input port of the first memory device (not shown in Figure 16) and out through the Qn_l output port.
- the first memory device will ignore command packet 904 because it is addressed to the second memory device.
- the first memory device then passes strobe signal 906 to the CSI_2 port of the second memory device from its CSO_1 port, and passes command packet 904 to the Dn_2 input port of the second memory device from its Qn_l output port.
- the second memory device Because there is a minimum separation tc DS between the falling edge of strobe signal 900 and the rising edge of strobe signal 906, and a minimum separation between the last bit of read data packet 902 and the first bit of command packet 904, the second memory device will reliably latch command packet 904in the appropriate registers. If on the other hand, command packet 904 and its corresponding strobe signal 906 were issued without any separation tcD S , the second memory device could latch read data bits of read data packet 902 as part of command packet 904. Accordingly, the minimum separation ensures that there is no mixing of data types.
- the memory devices in the previously described memory systems have the advantage of being able to retain stored data when there is no power supplied to the memory device.
- the transition between full power operation and no power at all, or a power saving level can jeopardize the integrity of the stored data.
- FIG 17A shows a flash memory device to which embodiments of the present invention are applicable.
- a flash memory 1010 includes logic circuitry such as control circuit 1012, for controlling various functions of the flash circuits, an address register 1012a for storing address information, a data register 1012b for storing program data information, a command register 1012c for storing command data information, high voltage circuits for generating the required program and erase voltages, and core memory circuits for accessing a memory array 1014.
- the control circuit 1012 includes a command decoder and logic for executing internal flash operations, such as read, program and erase functions.
- the registers storing address, data and command information have to be reliable.
- An improper value stored in the register results in device malfunction.
- varying supply voltages can cause the registers to randomly change states of the information stored in a command register 1012c, possibly resulting in a bit pattern corresponding to a received program or erase command.
- a spurious program operation will cause random data in the data register 1012b to be programmed to a random address in the address register 1012a of the memory array 1014. If data exists at this address, then the memory cells corresponding to that address will be subjected to programming voltages, and their threshold voltages may be changed.
- a spurious erase operation may result in erasure of existing data in the memory array 1014. Because the memory controller is not aware of the spurious operations executed by the flash memory 1010, the lost data is irretrievable.
- D flip-flop 1050 has a D-input for receiving input data D_IN, which is latched internally on an active edge of a clock signal CLK, such as a rising edge of CLK. When latched, the Q-output will provide D_OUT, which corresponds to the logic state of D_IN, while the complementary Qb output will provide D_OUTb, which corresponds to the inverted logic state of D_IN.
- a reset input clears the latches while signal RESET is at an active logic level, such as V S s or ground, for example.
- Each flip-flop circuit thereby stores one bit of data
- the command register 1012c will include a plurality of flip-flop circuits.
- the flip-flop latch circuit can include a pair of cross- coupled inverting circuits.
- Figure 18 illustrates a sequence diagram of a voltage supply Vcc, an active low logic level reset signal RST#, and an active low logic level chip enable signal CE# during power up and power down operations in a typical Flash memory 1010.
- the power supply voltage V C c begins its transition from the low GND or V S s voltage level to the high Vcc voltage level at an on time to N -
- the Vcc voltage level ramps up, and at time ts ⁇ ; reaches a stable voltage level V S ⁇ , at which time the flash memory 1010 can be operated.
- Vcc voltage level reaches the maximum Vcc level at time ty.
- the device reset and enable signals, RST# and CE#, respectively, received from an associated memory controller, are driven to the inactive high logic level simultaneously at time to N , but follow the ramping voltage of Vcc-
- the controller de-asserts the CE# signal at time to N by driving it to the inactive high logic level while the device is in the reset state. Since Vcc is ramping towards its maximum voltage level, CE# will follow the Vcc ramp.
- the CE# signal can be asserted at time tcEOff to allow the device enter a normal run state.
- the time tc EOff occurs after at least a time interval of tc ⁇ # has elapsed after the RST# signal has been de-asserted, or driven to the inactive high logic level (i.e., after time tv).
- initialization operations can be performed both at the device level and at the system level.
- the control signals to the registers cannot be precisely controlled. This can lead to spurious information being stored in the various registers of the Flash memory 1010, which can cause improper programming or erasure of data resulting in loss of data integrity in the Flash memory 1010.
- a method for data protection during power transitions such as, power up and power down operations, in a non-volatile memory device is described.
- a reset signal Prior to asserting any power transitions, a reset signal is asserted to disable functions of the memory device. The reset signal is maintained for a preset time during which the device voltage is expected to stabilize. During this time all internal registers, such as command registers of the device, are set to default values thereby preventing data loss due to spurious program/erase commands being executed by the device.
- FIG 19 is an illustration of a sequence diagram of a voltage supply Vcc, an active low logic level reset signal RST#, and an active low logic level chip enable signal CE# during power up and power down operations in a non-volatile memory device according to an embodiment of the present invention.
- the Vcc voltage transitions from the low GND or V$s voltage level to the high Vcc voltage level at time to N - Alternately, the Vcc voltage level can transition from a low power mode level to the Vcc voltage level.
- the Vcc voltage level ramps up in time and at time tsT, exceeds a stable voltage level V ST , at which the flash memory 1010 can be operated.
- a controller such as a memory controller associated with the non-volatile memory device holds the RST# signal at the active low logic level to disable all functions of the device for a wait time period, which is at least the time taken for the Vcc voltage level to reach the stable V S ⁇ voltage level (time from to N to 1 ST )-
- the RST# signal is held at the active low logic level for an extended time period t RS ⁇ , i.e., from toN to t s ⁇ plus at least a time interval t ( after the Vcc level reaches a stable voltage level V ST - All internal registers of the device will therefore be held in a default or reset state while the RST# signal is at the active low logic level.
- the controller will de-assert RST# after a time interval tRST as shown in Figure 19. After this time, the power will be stabilized and the device components can then prepare or initialize themselves for operation.
- the controller de-asserts the CE# signal at time to N by driving it to the inactive high logic level while the device is in the reset state. Since V ⁇ is ramping towards its maximum voltage level, CE# will follow the Vcc ramp.
- the CE# signal can be asserted at time tc EOff to allow the device enter a normal run state. The time tc EOff occurs after at least a time interval of t 2 has elapsed after the RST# signal has been de-asserted, or driven to the inactive high logic level.
- initialization operations can be performed both at the device level and at the system level. Deliberately holding the device in a reset state for a predetermined amount of time during the power transition operation prevents spurious information from being stored in or latched onto the various registers of the device. The device is thus safeguarded against improper and inadvertent programming or erasure of data, ensuring data integrity during power transitions.
- a similar procedure to ensure data protection can be followed during power down operations by asserting RST#, or by driving RST# to active low logic level, at a predetermined time prior to t OFF , when V C c is turned off and driven to the low GND or V S s voltage level.
- a flow chart illustrating a method for data protection during power transitions in a non-volatile memory device according to an embodiment of the present invention is shown in Figure 20.
- a memory controller controlling the non-volatile memory device such as a Flash memory device, maintains the RST# low prior to any power transitions (step 1100) to place the device in a reset state. During this time, the internal registers of the device are set to a default or reset state. The controller then allows the power to transition (step 1102) and waits for a predetermined time period for the internal voltage of the device to stabilize (step 1104).
- the wait time period corresponds to t R s ⁇ shown in Figure 19 and is at least the time taken for the Vcc voltage level to reach the stable V ST voltage level (time from to N to tsx) plus at least a time interval ti after the Vcc level reaches a stable voltage level V ST -
- the time interval tj can be determined based on the device characteristics such as operating voltage and process technology. For example, the total time period for which the RST# is held low, i.e., tRs ⁇ , can be lO ⁇ s or greater. During this time period various components of the device stabilize and the clocks become operational and become frequency and phase stable.
- the controller After the elapse of time period t RS ⁇ , the controller asserts a RST# high signal when the device is expected to be in a "ready" state (step 1106). As described with respect to Figure 19, the controller asserts the CE# signal at time to N while the device is in the reset state and brings it to a disabled state after RST# is de-asserted to release the memory device from the reset state. The CE# signal is de-asserted at time tc EOff to allow the device enter a normal run state. The time tcE Off is after at least a time interval of t 2 has elapsed after the RST# signal has been asserted.
- initialization operations can be performed both at the device level and at the system level (step 1108). Similar to time interval t ⁇ , the time interval t 2 can be determined based on the device characteristics and will vary from one memory system to another. For example, t 2 can be 100 Ds or greater.
- FIG. 21 describes the steps involved at the device during power transitions in order to ensure data protection in accordance with an embodiment of the present invention.
- the non-volatile memory device receives, from a memory controller controlling the device, a RST# low signal prior to any power transitions (step 1200).
- the device then receives power from the controller to activate device components (step 1202).
- This received power can be an increase from a VSS voltage or from a low power mode voltage level to the full VCC operating voltage level.
- Due to the RST# signal being low the device is placed in a reset state. During this time, the internal registers of the device and any finite state machines are set to and maintained at a default or reset state (step 1204).
- the controller then waits for a predetermined time period for the internal voltage of the device to stabilize prior to asserting RST# high. After the elapse of time period tRs ⁇ > the controller asserts a RST# high signal when the device is expected to be in a "ready” state. The device receives the RST# high signal and places the device in a "ready” state (step 1206). The controller asserts the CE# signal at time tcE O ff to allow the device enter a normal run state. As described earlier, once the device enters the normal run state, initialization operations can be performed at the device level (step 1208). Following is a discussion of the method for data protection during power transitions in the memory system 200 of Figure 4.
- the memory controller 202 will hold Reset (RST#) low to keep all the memory devices 204, 206, 208, and 210 in reset while power stabilizes and the devices prepare themselves for operation.
- RST# will be held low by the controller 202 for a minimum of t ! (for example, 20EIs) after V C c stabilizes, as shown in Figure 19.
- t ! for example, 20EIs
- the clocks Prior to RST# being de-asserted to a high logic level, the clocks become operational and become frequency and phase stable.
- the controller 202 de-asserts the CE# signal at time toN while the device is in the reset state and asserts CE# after RST# has been de-asserted.
- the CE# signal is asserted at time tc EOff to allow the device enter a normal run state.
- the time tc EO f f is after at least a time interval of t 2 has elapsed after the RST# signal has been asserted.
- the device By ensuring that the device is in a reset state for a predetermined amount of time during the power transition operation prevents spurious information from being stored in or latched onto the various registers of the device.
- the device is thus safeguarded against improper programming or erasure of data, ensuring data integrity during power transitions.
- Embodiments of the invention can be represented as a software product stored in a machine-readable medium (also referred to as a computer-readable medium, a processor- readable medium, or a computer usable medium having a computer-readable program code embodied therein).
- the machine-readable medium can be any suitable tangible medium, including magnetic, optical, or electrical storage medium including a diskette, compact disk read only memory (CD-ROM), memory device (volatile or non- volatile), or similar storage mechanism.
- the machine-readable medium can contain various sets of instructions, code sequences, configuration information, or other data, which, when executed, cause a processor to perform steps in a method according to an embodiment of the invention.
- Those of ordinary skill in the art will appreciate that other instructions and operations necessary to implement the described invention can also be stored on the machine-readable medium.
- Software running from the machine-readable medium can interface with circuitry to perform the described tasks.
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Abstract
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US89270507P | 2007-03-02 | 2007-03-02 | |
US11/840,692 US7904639B2 (en) | 2006-08-22 | 2007-08-17 | Modular command structure for memory and memory system |
PCT/CA2007/001469 WO2008022454A1 (fr) | 2006-08-22 | 2007-08-22 | Système de mémoire évolutif |
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EP2062261A4 EP2062261A4 (fr) | 2010-01-06 |
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KR (2) | KR101476463B1 (fr) |
CN (2) | CN101506895B (fr) |
CA (1) | CA2659828A1 (fr) |
TW (1) | TWI437577B (fr) |
WO (1) | WO2008022454A1 (fr) |
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- 2007-08-22 CA CA002659828A patent/CA2659828A1/fr not_active Abandoned
- 2007-08-22 CN CN2007800313409A patent/CN101506895B/zh not_active Expired - Fee Related
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- 2007-08-22 TW TW96131131A patent/TWI437577B/zh not_active IP Right Cessation
- 2007-08-22 EP EP07800496A patent/EP2062261A4/fr not_active Withdrawn
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KR101476463B1 (ko) | 2014-12-24 |
CA2659828A1 (fr) | 2008-02-28 |
KR20090045366A (ko) | 2009-05-07 |
EP2062261A4 (fr) | 2010-01-06 |
JP5575474B2 (ja) | 2014-08-20 |
WO2008022454A1 (fr) | 2008-02-28 |
CN101506895B (zh) | 2012-06-27 |
KR101476515B1 (ko) | 2014-12-24 |
KR20120110157A (ko) | 2012-10-09 |
CN102760476A (zh) | 2012-10-31 |
TW200828338A (en) | 2008-07-01 |
CN101506895A (zh) | 2009-08-12 |
TWI437577B (zh) | 2014-05-11 |
JP2010501916A (ja) | 2010-01-21 |
JP2012226786A (ja) | 2012-11-15 |
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