EP2062261A4 - Scalable memory system - Google Patents

Scalable memory system

Info

Publication number
EP2062261A4
EP2062261A4 EP07800496A EP07800496A EP2062261A4 EP 2062261 A4 EP2062261 A4 EP 2062261A4 EP 07800496 A EP07800496 A EP 07800496A EP 07800496 A EP07800496 A EP 07800496A EP 2062261 A4 EP2062261 A4 EP 2062261A4
Authority
EP
European Patent Office
Prior art keywords
memory system
scalable memory
scalable
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07800496A
Other languages
German (de)
French (fr)
Other versions
EP2062261A1 (en
Inventor
Jin-Ki Kim
Hakjune Oh
Hong Beom Pyeon
Steven Przybylski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/840,692 external-priority patent/US7904639B2/en
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of EP2062261A1 publication Critical patent/EP2062261A1/en
Publication of EP2062261A4 publication Critical patent/EP2062261A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
EP07800496A 2006-08-22 2007-08-22 Scalable memory system Withdrawn EP2062261A4 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US83932906P 2006-08-22 2006-08-22
US86877306P 2006-12-06 2006-12-06
US90200307P 2007-02-16 2007-02-16
US89270507P 2007-03-02 2007-03-02
US11/840,692 US7904639B2 (en) 2006-08-22 2007-08-17 Modular command structure for memory and memory system
PCT/CA2007/001469 WO2008022454A1 (en) 2006-08-22 2007-08-22 Scalable memory system

Publications (2)

Publication Number Publication Date
EP2062261A1 EP2062261A1 (en) 2009-05-27
EP2062261A4 true EP2062261A4 (en) 2010-01-06

Family

ID=39106444

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07800496A Withdrawn EP2062261A4 (en) 2006-08-22 2007-08-22 Scalable memory system

Country Status (7)

Country Link
EP (1) EP2062261A4 (en)
JP (2) JP5575474B2 (en)
KR (2) KR101476515B1 (en)
CN (2) CN101506895B (en)
CA (1) CA2659828A1 (en)
TW (1) TWI437577B (en)
WO (1) WO2008022454A1 (en)

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US7865756B2 (en) 2007-03-12 2011-01-04 Mosaid Technologies Incorporated Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices
US8781053B2 (en) 2007-12-14 2014-07-15 Conversant Intellectual Property Management Incorporated Clock reproducing and timing method in a system having a plurality of devices
US8467486B2 (en) 2007-12-14 2013-06-18 Mosaid Technologies Incorporated Memory controller with flexible data alignment to clock
JP2012504263A (en) * 2008-09-30 2012-02-16 モサイド・テクノロジーズ・インコーポレーテッド Serially connected memory system with output delay adjustment
US7957173B2 (en) * 2008-10-14 2011-06-07 Mosaid Technologies Incorporated Composite memory having a bridging device for connecting discrete memory devices to a system
WO2010069045A1 (en) * 2008-12-18 2010-06-24 Mosaid Technologies Incorporated Error detection method and a system including one or more memory devices
US20110002169A1 (en) 2009-07-06 2011-01-06 Yan Li Bad Column Management with Bit Information in Non-Volatile Memory Systems
US20110258366A1 (en) * 2010-04-19 2011-10-20 Mosaid Technologies Incorporated Status indication in a system having a plurality of memory devices
US9009423B2 (en) * 2010-04-26 2015-04-14 Novachips Canada Inc. Serially connected memory having subdivided data interface
US8856482B2 (en) * 2011-03-11 2014-10-07 Micron Technology, Inc. Systems, devices, memory controllers, and methods for memory initialization
US9239806B2 (en) * 2011-03-11 2016-01-19 Micron Technology, Inc. Systems, devices, memory controllers, and methods for controlling memory
US9342446B2 (en) 2011-03-29 2016-05-17 SanDisk Technologies, Inc. Non-volatile memory system allowing reverse eviction of data updates to non-volatile binary cache
CN102508797B (en) * 2011-10-27 2015-02-11 忆正存储技术（武汉）有限公司 Flash memory control expanding module, controller, storage system and data transmission method thereof
US9159374B2 (en) 2011-11-02 2015-10-13 Novachips Canada Inc. Flash memory module and memory subsystem
US8825967B2 (en) 2011-12-08 2014-09-02 Conversant Intellectual Property Management Inc. Independent write and read control in serially-connected devices
US8966151B2 (en) * 2012-03-30 2015-02-24 Spansion Llc Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal
US9760149B2 (en) * 2013-01-08 2017-09-12 Qualcomm Incorporated Enhanced dynamic memory management with intelligent current/power consumption minimization
KR20150110918A (en) 2014-03-21 2015-10-05 에스케이하이닉스 주식회사 Semiconductor memory device
US9792227B2 (en) * 2014-08-19 2017-10-17 Samsung Electronics Co., Ltd. Heterogeneous unified memory
JP6453718B2 (en) * 2015-06-12 2019-01-16 東芝メモリ株式会社 Semiconductor memory device and memory system
KR102296740B1 (en) * 2015-09-16 2021-09-01 삼성전자 주식회사 Memory device and memory system including the same
FR3041806B1 (en) * 2015-09-25 2017-10-20 Stmicroelectronics Rousset NON-VOLATILE MEMORY DEVICE, FOR EXAMPLE OF THE EEPROM TYPE, HAVING IMPORTANT MEMORY CAPACITY, FOR EXAMPLE 16MBITS
KR102457820B1 (en) * 2016-03-02 2022-10-24 한국전자통신연구원 Memory interface apparatus
KR102532528B1 (en) * 2016-04-07 2023-05-17 에스케이하이닉스 주식회사 Memory device and operating method thereof
KR102514717B1 (en) * 2016-10-24 2023-03-27 삼성전자주식회사 Memory controller and memory system including the same
KR102336666B1 (en) * 2017-09-15 2021-12-07 삼성전자 주식회사 Memory device and memory system comprising the same
KR20190112546A (en) * 2018-03-26 2019-10-07 에스케이하이닉스 주식회사 Memory system and operating method thereof
US10372330B1 (en) * 2018-06-28 2019-08-06 Micron Technology, Inc. Apparatuses and methods for configurable memory array bank architectures
US11043488B2 (en) * 2019-01-24 2021-06-22 Western Digital Technologies, Inc. High voltage protection for high-speed data interface
KR20210145480A (en) 2020-05-25 2021-12-02 삼성전자주식회사 A display drive ic and a display device including the same

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US20040148482A1 (en) * 2003-01-13 2004-07-29 Grundy Kevin P. Memory chain
US20040256638A1 (en) * 2000-01-05 2004-12-23 Richard Perego Configurable width buffered module having a bypass circuit
US20060031593A1 (en) * 2004-08-09 2006-02-09 Sinclair Alan W Ring bus structure and its use in flash memory systems

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US5729683A (en) * 1995-05-18 1998-03-17 Compaq Computer Corporation Programming memory devices through the parallel port of a computer system
US6144576A (en) * 1998-08-19 2000-11-07 Intel Corporation Method and apparatus for implementing a serial memory architecture
JP3853537B2 (en) * 1999-04-30 2006-12-06 株式会社日立製作所 Semiconductor memory file system
US6449308B1 (en) * 1999-05-25 2002-09-10 Intel Corporation High-speed digital distribution system
TW504694B (en) * 2000-01-12 2002-10-01 Hitachi Ltd Non-volatile semiconductor memory device and semiconductor disk device
JP2001266579A (en) * 2000-01-12 2001-09-28 Hitachi Ltd Non-volatile semiconductor memory device and semiconductor disk device
US6754129B2 (en) * 2002-01-24 2004-06-22 Micron Technology, Inc. Memory module with integrated bus termination
US20040022022A1 (en) * 2002-08-02 2004-02-05 Voge Brendan A. Modular system customized by system backplane
JP2004110849A (en) * 2003-12-01 2004-04-08 Toshiba Corp Semiconductor system and memory card

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040256638A1 (en) * 2000-01-05 2004-12-23 Richard Perego Configurable width buffered module having a bypass circuit
US20040148482A1 (en) * 2003-01-13 2004-07-29 Grundy Kevin P. Memory chain
US20060031593A1 (en) * 2004-08-09 2006-02-09 Sinclair Alan W Ring bus structure and its use in flash memory systems

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2008022454A1 *

Also Published As

Publication number Publication date
JP5575474B2 (en) 2014-08-20
CA2659828A1 (en) 2008-02-28
CN101506895A (en) 2009-08-12
CN102760476A (en) 2012-10-31
CN101506895B (en) 2012-06-27
WO2008022454A1 (en) 2008-02-28
JP2012226786A (en) 2012-11-15
KR101476463B1 (en) 2014-12-24
JP2010501916A (en) 2010-01-21
TWI437577B (en) 2014-05-11
KR20090045366A (en) 2009-05-07
KR101476515B1 (en) 2014-12-24
KR20120110157A (en) 2012-10-09
TW200828338A (en) 2008-07-01
EP2062261A1 (en) 2009-05-27

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