KR101476463B1 - scalable memory system - Google Patents

scalable memory system Download PDF

Info

Publication number
KR101476463B1
KR101476463B1 KR1020097005767A KR20097005767A KR101476463B1 KR 101476463 B1 KR101476463 B1 KR 101476463B1 KR 1020097005767 A KR1020097005767 A KR 1020097005767A KR 20097005767 A KR20097005767 A KR 20097005767A KR 101476463 B1 KR101476463 B1 KR 101476463B1
Authority
KR
South Korea
Prior art keywords
memory
memory device
data
packet
instruction
Prior art date
Application number
KR1020097005767A
Other languages
Korean (ko)
Other versions
KR20090045366A (en
Inventor
진기 김
학준 오
홍범 편
스티븐 프르지빌스키
Original Assignee
컨버전트 인텔렉츄얼 프로퍼티 매니지먼트 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US83932906P priority Critical
Priority to US60/839,329 priority
Priority to US86877306P priority
Priority to US60/868,773 priority
Priority to US90200307P priority
Priority to US60/902,003 priority
Priority to US89270507P priority
Priority to US60/892,705 priority
Priority to US11/840,692 priority
Priority to US11/840,692 priority patent/US7904639B2/en
Application filed by 컨버전트 인텔렉츄얼 프로퍼티 매니지먼트 인코포레이티드 filed Critical 컨버전트 인텔렉츄얼 프로퍼티 매니지먼트 인코포레이티드
Publication of KR20090045366A publication Critical patent/KR20090045366A/en
Application granted granted Critical
Publication of KR101476463B1 publication Critical patent/KR101476463B1/en

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20Memory initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/04Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Abstract

The memory system architecture has memory devices connected in series. The memory system is scalable to include any number of memory devices without any performance penalties or complex redesign. Each memory device has a serial input / output interface for communication between the other memory devices and the memory controller. The memory controller issues instructions in at least one bitstream, where the bitstream is in accordance with a modular instruction protocol. The instruction includes an operation code with optional address information and a device address, so that only the addressed memory device follows the instruction. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream to identify the type of data and the length of the data. The modular command protocol is used to perform concurrent operations on each memory device to further improve performance.

Description

[0001] SCALABLE MEMORY SYSTEM [0002]

This application is related to U.S. Provisional Patent Application No. 60 / 839,329, filed August 22, 2006; U.S. Provisional Patent Application No. 60 / 868,773, filed December 6, 2006; U.S. Provisional Patent Application No. 60 / 902,003, filed February 16, 2007; U.S. Provisional Patent Application No. 60 / 892,705, filed March 2, 2007, and U.S. Patent Application No. 11 / 840,692, filed August 17, 2007, all of which are incorporated by reference herein.

The present invention relates generally to memory systems. More specifically, the present invention relates to a memory system of a serially-connected memory device for mass storage applications.

Flash memory is a commonly used type of nonvolatile memory that is widely used as a mass storage device for consumer products such as digital cameras and portable digital music players. The density of flash memory chips currently on the market may be up to 32 Gbits (4 GB), which is suitable for use with popular USB flash devices due to the small size of a single flash chip.

1 is an overall block diagram of one bank of a known NAND flash memory. Those skilled in the art will appreciate that flash memory devices may have any number of banks. The bank 30 is composed of (k + 1) blocks. Each block consists of a NAND memory string with up to i + 1 flash memory cells connected in series with each other. Thus, the word lines VL0 to WLi are connected to the gates of each flash memory in the memory cell string. A string selector connected to the signal SSL (string select line) selectively connects the memory cell string to the bit line while the ground selector connected to the signal GSL (ground select line) selectively connects the memory cell string to the VSS To the source line. The string selection device and the ground selection device are n-channel transistors. There are j + 1 bit lines common to all the blocks of the bank 30, and each bit line is connected to one NAND memory cell string in each of the blocks [0] to [k]. Each word line (WL0 to WLi), SSL and GSL signals are connected to the same corresponding transistor device in each NAND memory cell string in the block. Those skilled in the art will appreciate that the data stored in flash memory cells along one word line is the page of data.

Outside the bank 30, each bit line is connected with a data register 32 for storing read data accessed from a flash memory cell, or a page of write data to be programmed into a page of a flash memory cell. The data register 32 also includes a sense circuit for sensing data read from a page of the flash memory cell. During a programming operation, the data register performs a program verify operation to ensure that the data has been properly programmed into the flash memory cell connected to the selected word line. Each memory cell of the bank 30 may store a single bit of data or a plurality of bits of data. Some flash memory devices have one or more sets of data registers to increase throughput.

The advent of portable digital entertainment devices with 8 megapixel digital cameras and music and video capable outputs has increased the need for ultra high capacity to store large amounts of data that can not be satisfied by a single flash memory device. Thus, a plurality of flash memory devices are combined together in a memory system to efficiently increase available storage capacity. For example, a 20 GB play storage density may be required for such applications.

2 is a block diagram of a prior art flash memory system 10 that is integrated with the host system 12. The flash memory system 10 includes a memory controller 14 and a plurality of non-volatile memory devices 16 in communication with the host system 12. The host system includes a processing unit such as a microcontroller, microprocessor, or computer system. The flash memory system 10 of FIG. 2 is configured to include a single channel 18, wherein the memory devices 16 are connected in parallel to the channel 18. Those skilled in the art will appreciate that the memory system 10 may have more or less than four memory devices connected to it.

The channel 18 includes a set of common buses including data and control lines connected to all of their respective memory devices. Each memory device is enabled / disabled with the respective chip select signals CE # 1, CE # 2, CE # 3 and CE # 4 provided by the memory controller 14. "#" Indicates that the signal is an active low logic level signal. The memory controller 14 is responsible for issuing commands and data over the channel 18 to the selected memory device based on the operation of the host system 12. [ The data read from the memory device is transferred back to the memory controller 14 and the host system 12 via the channel 18. The operation of the flash memory system 10 is synchronized to the clock CLK provided in parallel to each memory device 16. [ Flash memory system 10 is generally referred to as a multi-drop configuration, wherein memory device 16 is connected in parallel to channel 18.

In the flash memory system 10, the non-volatile memory devices 16 may be identical to one another and are generally realized as a NAND flash memory device. Those skilled in the art will appreciate that the flash memory is organized in banks, and each bank is organized in blocks to facilitate block erasure. Most commercially available NAND flash memory devices are configured to have two banks of memory.

There is a special problem that adversely affects the performance of the system. The configuration of the flash memory system 10 imposes a physical performance limitation. Due to the enormous number of parallel signals that extend throughout the system, the signal integrity of the signals they carry is degraded by crosstalk, signal skew, and simultaneous switching noise (SSN). The power consumption in such a configuration is problematic because each signal track between the flash controller and the flash memory device is frequently charged and discharged for signaling. Increasing the system clock frequency increases power consumption.

Since the drive capability of a single memory device is small compared to loading of long signal tracks, there is also a practical limit to the number of memory devices that can be connected in parallel to the channel. In addition, as the number of memory devices increases, more chip enable signals CE # are required, and the clock signal CLK needs to be routed to additional memory devices. Clock performance issues due to extended clock distribution are well known in the art and need to be addressed. Thus, to accommodate a large number of memory devices in a memory system, a controller with more channels needs to be used, and / or the system needs to be clocked at a lower frequency. A controller configured to have a plurality of channels and an additional chip enable signal increases the cost of the memory system. Otherwise, the memory system is limited to a small number of memory devices.

Accordingly, it is desirable to provide a memory system architecture capable of supporting any number of memory devices.

It is an aspect of embodiments to remove or mitigate at least one drawback of the prior memory system.

In a first aspect, a memory system having a controller and a memory device is provided. The controller includes a serial channel output port providing a serial bitstream command packet and a serial channel input port receiving a serial bit stream read data packet. The serial bitstream instruction packet includes an operation code and a device address. The memory device having an input port for receiving the serial bitstream instruction packet from the controller and for executing the operation code if the device address corresponds to the memory device. The memory device provides the serial bitstream command packet through an output port and then provides the serial bit stream read data packet through the output port if the operation code corresponds to a read function.

According to one embodiment of this aspect, there is at least one intervening memory device connected in series between the memory device and the controller. Wherein the at least one intervening memory device has an input port for receiving and delivering the serial bitstream instruction packet to the memory device and then if the device address corresponds to the memory device and the operation code corresponds to a read function, Bit stream read data packet.

According to another embodiment, a complementary clock signal is provided in parallel to the memory device and the at least one intervening memory device, or a complementary clock signal is provided to the at least one intervening memory device, And transferred to the memory device by the memory device.

According to another embodiment of this aspect, a memory system includes an expansion link between the controller and the memory device and an expansion link for receiving one of the jumper. The at least one intervening memory device is part of an expansion module having connection means configured for electrical connection with the expansion link.

According to yet another embodiment, the memory device and the at least one intervening memory device each include a native memory core and a serial interface, and a controller for controlling the native memory core in response to the serial bitstream command packet Control logic block. The memory device native memory core and the at least one intervening memory device native memory core may be NAND flash based, or may be DRAM, SRAM, NAND flash, and NOR flash memory cores.

According to another embodiment of the present aspect, the serial bitstream command packet has a modular structure in which the size of the serial bitstream command packet is variable. The serial bitstream instruction packet may include an instruction field providing the operation code and the device address, wherein the instruction field comprises a first subfield providing the operation code and a second subfield providing the device address 2 subfields. The serial bitstream instruction packet may include an instruction field providing the operation code and the device address, and an address field providing one of a row address and a column address. The serial bitstream instruction packet may include an instruction field providing the operation code and the device address, an address field providing one of a row address and a column address, and a data field providing write data.

According to one aspect of the previous embodiment, the controller provides an instruction strobe in parallel with the serial bitstream instruction packet, and the instruction strobe has an active level consistent with the length of the serial bitstream instruction packet.

The controller also provides a data input strobe in parallel with the serial bit stream read data packet, and the data input strobe has an active level that matches the length of the serial bit stream read data packet. Wherein the memory device latches the serial bitstream instruction packet in response to the active level of the instruction strobe when the device address corresponds to the memory device and the memory device output port is responsive to the active level of the data input strobe Lt; / RTI > The command strobe and the data input strobe are non-overlapping signals and are separated by at least one data latching clock edge. [0222] Optionally, the instruction strobe is separated from adjacent instruction strobe by at least one latching clock edge, and the data input strobe is separated from adjacent data input strobe by at least one latching clock edge.

In a second aspect, an instruction packet is provided that includes a series of bits for a memory system having a memory device connected in series. The instruction packet includes an instruction field for selecting a memory device of one of the serially connected memory devices to execute a specific memory operation.

In one embodiment of the second aspect, the instruction field includes a first sub-field providing a device address for selecting the memory device, and a second sub-field providing an op- eration code corresponding to the particular memory operation. Wherein the instruction packet further comprises an address field subsequent to the instruction field providing one of a row address and a column address when the operation code corresponds to a read or write operation and wherein the address field is associated with the row address or the column address And has a corresponding bit length. Wherein the command packet further comprises a data field subsequent to the address field for providing write data for storage in the memory device when the operation code corresponds to the write operation, Lt; / RTI >

In a third aspect, a method is provided for performing concurrent operation in a selected memory device of a memory system having a serially-connected memory device. The method includes receiving a first command; Executing a core operation in a first memory bank of the selected memory device in response to the first instruction; Receiving a second instruction while executing a core operation in the first memory bank; And executing a core operation in a second memory bank of the selected memory device in response to the second instruction.

According to an embodiment of the third aspect, there is provided a method comprising: receiving a third instruction requesting result information from one of the first memory bank and the second memory bank; and receiving the result information in response to the third instruction And outputting the read data packet. The result information includes one of status register data and read data.

In another embodiment of this aspect, the first instruction, the second instruction, and the third instruction may comprise a mandatory command field providing an operation code and a device address, a row of instructions that when the operation code corresponds to a read or write operation, An optional address field following the command field providing one of the column addresses, and an optional data field following the address field providing write data when the operation code corresponds to the write operation. Lt; / RTI >

In one aspect of the present embodiment, a first command strobe is received in parallel with the first command, the first command strobe has an active duration corresponding to the length of the first command, 2 instruction, and the second instruction strobe has an active duration corresponding to the length of the second instruction. The first instruction strobe and the second instruction strobe are separated by at least one data latching clock edge. A data input strobe is also received to enable the output of the read data packet while the data input strobe is at an active level, the second instruction strobe and the data input strobe being coupled by at least one data latching clock edge Separated.

In another embodiment, the method further comprises powering up the selected memory device prior to receiving the first command. Raising the power comprises: asserting a control signal to maintain the selected memory device in a default state prior to power transfer; Transitioning the power level of the selected memory device from a first voltage level to a second voltage level while the control signal is asserted; Waiting for a predetermined duration so that the power level is stabilized; And de-asserting the control signal to release the selected memory device from the default state, thereby preventing an accidental program or erase operation in the selected memory device. The second voltage level may be a minimum voltage level for stable circuit operation or a maximum operating voltage level of the power source. The first voltage level may correspond to the low power mode operating voltage level of the power supply, or the absence (absence) state of the power supply.

In yet another embodiment, maintaining the memory device in the default state includes setting a device register in the memory device to a default value, wherein the device register includes an instruction register. The further step of the method may further comprise performing device initialization upon release of the memory device from the default state. The step of performing the device initialization may comprise generating a device address and device identifier information for the memory device.

In another embodiment, the step of raising the power comprises: asserting a control signal at a first time to keep the memory device in a default state prior to power transfer; Transitioning the power level of the memory device from a first level to a second level at a second subsequent time while the control signal is asserted; Waiting for a predetermined duration so that the power level is stabilized; And deasserting the control signal at a third subsequent time to release the memory device from the default state, thereby preventing an accidental program or erase operation in the memory device.

In a fourth aspect, a memory system is provided that includes a plurality of memory devices and a controller for controlling the devices. The controller has an output port for providing a bitstream command packet to a first one of the plurality of memory devices, wherein the bitstream command packet includes an operation code and a device address. Wherein each of the plurality of memory devices receives the bitstream command packet from one of the controller and an advanced memory device and executes the opcode if the device address corresponds thereto, Providing a command packet to one of the next memory device and the controller, wherein a bitstream read data packet is provided from the last of the plurality of memory devices to the controller if the opcode corresponds to a read function.

According to one embodiment of this aspect, the plurality of memory devices are connected in series, the first and last memory devices are connected to the controller, and the controller is operable to cause the first device of the plurality of memory devices, And transmits a data packet. The bit stream data packet and the bit stream read data packet from the controller comprise a serial bit stream or a parallel bit stream. The plurality of memory devices is one of a mixture of memory devices of the same type or of different types.

According to another aspect, there is provided a memory system including a plurality of memory devices and a controller for controlling the device, the memory system being capable of performing a function of powering up a selected memory device before receiving a first command.

For example, the power-up function may include asserting a control signal to maintain the selected memory device in a default state prior to power transfer; Transitioning the power level of the selected memory device from a first voltage level to a second voltage level while the control signal is asserted; Waiting for a predetermined duration so that the power level is stabilized; And deasserting the control signal to release the selected memory device from the default state, thereby preventing an accidental program or erase operation in the selected memory device. In addition, the power raising function may include asserting a control signal at a first time to maintain the memory device in a default state prior to power transfer; Transitioning the power level of the memory device from a first level to a second level at a second subsequent time while the control signal is asserted; Waiting for a predetermined duration so that the power level is stabilized; And deasserting the control signal at a third subsequent time to release the memory device from the default state, thereby preventing an accidental program or erase operation in the memory device.

Other aspects and features of the present invention will become apparent to those skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying drawings.

Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings.

1 is a schematic diagram of a prior art NAND flash memory core.

2 is a block diagram of a prior art NAND flash memory system.

3A is a general block diagram of a serial memory system.

3B is a block diagram of a serial memory system comprised of a NAND flash memory device.

3C is a block diagram of a serial memory system made up of a mixture of different memory devices.

Figure 4 is a block diagram of the serial memory system of Figure 3A configured with a parallel clock scheme.

Figure 5 is a block diagram of the serial memory system of Figure 3A configured with a source synchronous clock scheme.

Figure 6 is a block diagram of a dynamically adjustable serial memory system.

Figure 7 is a block diagram of a memory device having a serial input / output interface and a native core suitable for use in the serial memory system of Figures 3A-3C and 4-6.

8 is a diagram showing a modular command packet structure.

Figure 9 shows a table listing examples of modular instruction packets operating the flash memory device of Figure 7;

10 is a flowchart of a method of simultaneously executing an operation in one memory device.

11 is a sequence diagram illustrating simultaneous read operations for two different banks of a memory device.

12 is a sequence diagram illustrating concurrent programming operations for two different banks of memory devices.

Figure 13 is a sequence diagram illustrating simultaneous read and program operation for two different banks of memory devices.

14 is a sequence diagram illustrating simultaneous block erase for two different banks of memory devices.

15 is a sequence diagram showing simultaneous programming and read operations for two different banks of memory devices in a pause and resume operation;

16 is a sequence diagram showing the operation of two serially connected memory devices.

17A is a block diagram of a flash memory device to which embodiments of the present invention may be applied.

17B is a schematic diagram of a flip-flop.

FIG. 18 is a sequence diagram of various control signals during the power-up and power-down operations in the flash memory device of FIG. 17A.

19 is a sequence diagram of various control signals during power-up and power-down operations in the nonvolatile memory device.

20 is a flow chart illustrating a method for protecting data during power transition in a non-volatile memory device.

21 is a flowchart illustrating a method of protecting data during power transition in a non-volatile memory device according to another embodiment of the present invention.

In the following detailed description of embodiments of the present invention, reference is made to the accompanying drawings which form a part which, by way of illustration of specific embodiments in which the invention may be practiced, may be embodied. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that logical, electrical, and other changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

A memory system architecture with serially connected memory devices is described. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input / output interface for communication between the other memory devices and the memory controller. The memory controller issues instructions in at least one bitstream, where the bitstream is in accordance with a modular instruction protocol. The instruction includes an operation code with optional address information and a device address, so that only the addressed memory device follows the instruction. A separate data output strobe and command input strobe signal are provided in parallel with each output data stream and input command data stream to identify the type of data and the length of the data. The modular command protocol is used to perform concurrent operations on each memory device to further improve performance.

3A is a block diagram illustrating conceptual features of a serial memory system architecture according to one embodiment. In Figure 3A, the serial memory system 100 includes a memory controller 102 having at least one serial channel output port Sout and a serial channel input port Sin, and a plurality of memory devices 104, 106, 108, 110, 112, 114, and 116). In one embodiment, the memory device may be a flash memory device. Alternatively, the memory device may be a DRAM, SRAM, or some other type of memory device, as long as it has a serial input / output interface compatible with a particular instruction structure to execute instructions or transfer instructions and data to subsequent memory devices. A more detailed description of such memory device configuration and specific command structure will be described later.

Although the current embodiment includes seven memory devices, alternate embodiments may include up to one memory device and any number of memory devices. Thus, since the memory device 104 is connected to Sout, and therefore the first device in the serial memory system 100, the memory device 116 is the Nth or final device since it is connected to Sin, It is a big integer. The memory devices 106-114 are serially connected memory devices interposed between the first and last memory devices. Each memory device can take a separate identification number or a device address (DA) at power-up initialization of the system so that the memory devices are individually addressable. Commonly owned U.S. Patent Applications 11 / 622,828, 11 / 750,649, 11 / 692,452, 11 / 692,446, 11 / 692,326 and 11 / 771,023 disclose device addresses for memory devices connected in series in a memory system Is described.

The memory devices 104 to 116 are considered to be connected in series because the data input of one memory device is connected to the data output of the preceding memory device so that they are connected in series except for the first and last memory devices in the chain Thereby forming a constitution.

The channel of the memory controller 102 includes a data channel of arbitrary data width for carrying command, data and address information, and a control channel for carrying control signal data. A more detailed description of the channel configuration will be described later. The embodiment of FIG. 3A includes one channel, where one channel includes Sout and a corresponding Sin port. However, the memory controller 102 may include any number of channels for accommodating separate memory device chains.

In a typical operation, the memory controller 102 issues an instruction that includes an operation code (opcode), a device address, address information for reading or programming, and data for programming via its Sout port. The command is issued as a serial bitstream packet, which may be logically subdivided into segments of a predetermined size, for example, bytes. A bitstream is a sequence or a sequence of bits provided per hour. An instruction is received by the first memory device 104 and the device address is compared to its assigned address. If their addresses match, the memory device 104 executes an instruction. If their addresses do not match, the command is delivered to the subsequent memory device 106 through its output port, where the same procedure is repeated. Eventually, a memory device having a matching device address, referred to as the selected memory device, will perform the operation indicated by the instruction. If the instruction is to read the data, the selected memory device will output the data read through its output port, and the serial data will be written to the memory device 102 via intervening memory devices Lt; / RTI >

 Since the instructions and data are provided in a serial bitstream, a clock is used by each memory device to clock in and out the serial bits and to synchronize internal memory operations. This clock is used by all the memory devices in the serial memory system 100 and the memory controller. As shown in the embodiments of FIGS. 4 and 5, there are two possible clock configurations for the serial memory system 100.

FIG. 3B is a block diagram illustrating that the memory system of FIG. 3A may include one type of memory device, such as a NAND flash memory device. Each NAND flash memory device may be different from, or identical to, each other, for example, by having different storage densities. FIG. 3C is a block diagram illustrating that the memory system of FIG. 3A may include various types of memory devices. These memory devices may include, for example, a NAND flash memory device, a NOR flash memory device, a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a magnetoresistive random access memory have. Of course, alternative memory devices not mentioned here may be employed in the memory system. A configuration with such a mixed type of memory device is disclosed in U. S. Patent Application 60 / 868,773, filed December 6, 2006.

Figure 4 is a block diagram of a serial memory system using a parallel clock scheme. The serial memory system 200 includes a memory controller 202 and four memory devices 204, 206, 208 and 210. The memory controller 202 provides several signals in parallel to the memory devices. These signals include a chip enable signal CE #, a reset signal RST # and complementary clocks CK # and CK. In one example of the use of CE #, the device is enabled when CE # is at a low logic level. When the memory device initiates a program or erase operation, CE # may be de-asserted or driven to a high logic level. Also, at low logic levels, CE # can activate the internal clock signal, and at high logic levels, CE # can disable the internal clock signal. In one example of the use of RST #, the memory device is set to the reset mode when RST # is at a low logic level. In reset mode, the power is allowed to stabilize, and the device prepares itself for initial operation by initializing all finite state machines and resetting any configuration and status registers to their default state.

The channel of the memory controller 202 includes a data channel composed of a data output port Qn and a data input port Dn and a data strobe input CSI, a command strobe output CSO (echo of CSI) And a control channel made up of a strobe input DSI and a data strobe output DSO (echo of DSI). The output port Qn and the input port Dn may be 1 bit wide or n bits wide, where n is a non-zero integer according to the desired configuration. For example, if n is 1, one byte of data is received after eight data latching edges of the clock.

The data latching clock edge may be, for example, a rising clock edge. If n is 2, one byte of data is received after four latching edges of the clock. If n is 4, one byte of data is received after two latching edges of the clock. The memory device may be statistically constructed or dynamically configured for Qn and Dn of any width. Thus, in a configuration where n is greater than one, the memory controller provides the data as a parallel bit stream. CSI is used to latch the command data appearing at the input port Dn and has a pulse duration corresponding to the length of the received command data. More specifically, the command data will have a duration measured by a number of clock cycles, and the pulse duration of the CSI signal will have a corresponding duration. The DSI is used to enable the output port (Qn) buffer to output data, and has a pulse duration corresponding to the length of the required read data. A more detailed description of the DSI and CSI signals will be discussed later.

4, each memory device has the same serial input / output interface, including RST #, CE #, CK #, and CK input ports, which receive signals of the same name from memory controller 202 . The serial input / output interface further includes a data input port Dn, a data output port Qn, a CSI, a DSI, a CSO, and a DSO port. As shown in FIG. 4, the Dn, CSI, and DSI input ports of each memory device are connected to the Qn, CSO and DSO output ports of the preceding memory device, respectively. Thus, each memory device is considered to be connected in series with each other, since each can transfer instruction and read data to the next memory device in the chain.

In actual implementation of the embodiment of FIG. 4, each memory device is disposed on a printed circuit board so that the distance between the input and output ports and the signal track is minimized. Alternatively, four memory devices may be implemented with a system in package module (SIP), which is a system that further minimizes the signal track length. The memory controller 202 and the memory devices 204-210 are configured to form a ring topology which means that the final memory device 210 provides its output back to the memory controller 202. [ And are connected in series. As such, those skilled in the art will appreciate that the distance between the memory device 210 and the memory controller 202 is easily minimized.

The performance of the memory device in the serial memory system 200 of FIG. 4 is significantly improved over that of the memory device of the prior art system of FIG. For example, assuming that a 66 MHz clock is used and the serial memory system 200 includes four memory devices, the data rate per pin of one of the serially connected memory devices of FIG. 4 will be about 133 Mbps. Conversely, the data rate per pin of the multi-drop memory device of FIG. 1 with four memory devices is such that the read cycle time (tRC) and write cycle time (tWC) for each memory device is set to about 25 ns , It will be about 40 Mbps. Also, the power consumption of the serial memory system 200 will be reduced compared to the prior art system of FIG. The performance and power consumption advantages of the serial memory system 200 are primarily due to the absence of signal tracks 18 that must be driven by each memory device.

An important advantage of the serial memory system 200 of FIG. 4 is the scalability of the system. In other words, four or more memory devices may be included in the memory chain connected to the memory controller 202 without any performance degradation. On the contrary, the prior art system of FIG. 1 assumes that the length of the signal track of the channel 18 is an additional As the number of devices is necessarily increased to accommodate them, more memory devices will be added to reach the practical limit of reducing the return. Additional pin loading to the signal track is contributed by the additional devices. As noted above, the clock frequency must be reduced to ensure data transmission integrity when driving long channels 18 that degrade performance. In the embodiment of Figure 4, the distribution of clocks is designed to accommodate a large number of memory devices and may include repeaters and balanced trees to maintain clock integrity for all memory devices . Those skilled in the art will understand that there are a number of ways to provide a balanced clock signal.

Although the serial memory system embodiment of FIG. 4 provides significant performance advantages over prior art memory systems, additional performance improvements are obtained using the alternate series memory system embodiment of FIG. The serial memory system 300 of FIG. 5 is similar to the embodiment of FIG. 4, except that a source synchronous clock scheme is used instead of a parallel clock distribution scheme. The serial memory system 300 includes a memory controller 302 and four memory devices 304, 306, 308 and 310. Memory controller 302 includes clock output ports CKO # and CKO that provide complementary clock signals and clock input ports CK # and CK that receive complementary clock signals from the final memory device of the system. The memory devices have a clock input port (CK # and CK) and clock output ports (CKO # and CKO) where they are now clocked by their own CK # and CK ports by one memory device to the next device Is the same as that shown in Fig. 4 except that it is provided through its own CKO # and CKO port. The final memory device 310 provides a clock signal back to the memory controller 302.

The main advantage of the embodiment of FIG. 5 is the absence of a minimal clock interconnect between memory devices and some complex clock distribution scheme. Thus, the minimum clock frequency can be increased to 166 MHz, resulting in a data rate of at least 333 Mbps per pin. As in the embodiment of FIG. 4, the embodiment of FIG. 5 may be defined to include any number of memory devices. For example, a fifth memory device may be connected to the memory controller 302 by simply connecting the output port of the memory device 310 to a corresponding input port of the fifth memory device, and connecting the output port of the fifth memory device to the memory controller 302 5 < / RTI > embodiment. Those skilled in the art will appreciate that the memory controller 302 may include a simple phase locked loop (PLL) to maintain the clock frequency.

The configuration of the serial memory systems 200 and 300 may be statically fixed for a certain number of memory devices. Different configurations can be set to provide different memory system capacity by simply adjusting the number of memory devices in the serial chain. In alternative embodiments, memory devices having different capacities can be mixed together in a serial chain, providing greater flexibility for the overall memory system capacity. There may be applications where the memory system capacity can be dynamically adjusted by adding or removing modules from the serial chain, where the module may be a single memory device, a SIP memory, or a memory device and / or a PCB with a SIP memory device .

6 is a block diagram illustrating a dynamically adjustable serial memory system embodiment. The adjustable serial memory system 400 includes a memory controller 402, fixed memory devices 404, 406, 408 and 410, expansion links 412, 414, 416, 418 and 420, and expansion modules 422, 426). The fixed memory devices 404, 406, 408, and 410 are connected to each other, to an intervening expansion link, and to the memory controller 402 in series. Each extension link is male and female connecting means for releasably receiving and holding a module having a male and female connecting means. Each module includes at least one memory device connected in series with a terminal of the expansion link. In the presently illustrated example, the expansion modules 422 and 426 each include four memory devices, which are connected in series between the input connector and the output connector of the module connection means. The module 424 includes two memory devices connected in series between the input connector and the output connector of its module connection means. Thus, by inserting the module into the expansion link, additional serially connected memory devices can be dynamically inserted between fixed memory devices. Unused expansion links, such as expansion links 414 and 420, have appropriately configured jumpers 428 and 430 connected to themselves to maintain a continuous series electrical connection of the chain.

The tunable serial memory system 400 may include any number of fixed memory devices and expansion links, and the memory module may be configured to include any number of serially connected memory devices. Thus, the adjustable serial memory system 400 has an overall expandable memory capacity without adding to the overall performance by simply adding a new module or replacing an existing module with a larger capacity module. There is no requirement to change the memory controller since the same channel resides with the memory device to which it is connected in series, and a person of ordinary skill in the art will understand how to connect a control signal such as CE #, RST # I will understand. After the insertion of the module or removal of the module, the memory system 400 is re-initialized so that the memory controller can automatically set the device ID's for the memory devices in the system.

The serial memory system shown in Figs. 3A to 3C and Figs. 4 to 6 employs a memory device such as a flash memory device having a compatible serial input / output interface. One example of a flash memory device having a serial input / output interface is described in co-owned US patent application 11 / 324,023, filed December 30, 2005. Thus, the memory devices shown in the embodiments of FIGS. 3A to 3C and 4 to 6 can employ the flash memory device disclosed in these patent applications. However, the serial input / output interfaces described in these patent applications are examples of serial interfaces that can be used. Any serial input / output interface that facilitates serial operation between memory devices may be used provided it is configured to accept a given command structure.

According to another embodiment, a serial input / output interface may be used with any type of memory device. More specifically, other memory types may be adapted to operate with the serial input / output interface. FIG. 7 is a block diagram illustrating a conceptual configuration of a general purpose memory device having a serial input / output interface and a native core suitable for use in the serial memory system of FIGS. 3A to 3C and FIGS. 4-6. Memory device 500 includes a native memory core that includes memory array banks 502 and 504 and native control and I / O circuitry 506 that access memory array banks 502 and 504. Those skilled in the art will appreciate that a memory array may consist of a single memory bank or two or more memory banks. The native memory core may be, for example, based on DRAM, SRAM, NAND flash, or NOR flash memory. Of course, any recently made memory and corresponding control circuitry may be used. Thus, depending on the type of native memory core, circuit block 506 may include error correction logic, a high voltage generator, refresh logic, and any other circuit blocks needed to perform operations specific to the memory type .

Generally, a memory device uses an instruction decoder that asserts the internal control signal to initialize the associated circuitry in response to the received command. These memory devices will also include well-known I / O circuits that receive and latch data, instructions and addresses. In accordance with the present embodiment, the existing I / O circuitry is replaced by a serial interface and control logic block 508. In this example, the serial interface and control logic block 508 receives the RST #, CE #, CK #, CK, CSI, DSI and Dn inputs and provides the Qn, CSO, DSO, CKO and CKO # These correspond to the input and output ports of the memory device shown in Fig.

The serial interface and control logic block 508 is responsible for a number of functions, as described in U.S. Patent Application 11 / 324,023. An important function of the serial interface and control logic block 508 is to set the device identification number, pass data to the next serially connected memory device, and decode the received command to perform the native operation. The circuit may include a command decoder that replaces a native command decoder configured to assert the same control signal as the native command decoder asserts in response to a serially received command corresponding to the native command. The instruction set may be extended to execute features available to the memory controller when the memory devices are connected in series. For example, status register information may be required to evaluate the state of the memory device.

Thus, the serial memory system of Figs. 3A-3C and Figs. 4-6 may include a mix of memory device types that each provide different advantages for larger systems. For example, a high-speed DRAM memory may be used for caching operations, while a non-volatile flash memory may be used for storing large amounts of data. Regardless of the type of memory device used, each memory device is individually addressable to follow the instruction because the serial interface and control logic block 506 is configured to receive commands in accordance with a predetermined protocol.

According to another embodiment, these instructions consist of instruction packets with a modular instruction structure used to control the individual memory devices of the serial memory system. In the proposed command structure, a particular command may be issued to the memory device at another time as a separate command packet. A command packet may initiate a specific operation for the first memory bank and a subsequent command packet may be received to initiate another operation for the first memory bank while the core operation is executed in response to the first command packet . Additional instruction packets may be received to complete operations on the first memory bank and the second memory bank in a similar insertion manner. It is assumed that the operation is performed simultaneously in the memory device. Before discussing concurrent operation, a description of the modular command protocol is given. A more detailed description of the modular command protocol is described in U. S. Patent Application 60 / 892,705, filed March 2, 2007, entitled " Modular Command Structure in Memory System and its Use "

The instruction packet 600 has the structure shown in Fig. 8 and includes three fields, two of which are selected according to a specific instruction issued by the memory controller. The first field, which is an essential field, is the command field 602. The first selection field is the address field 604 and the second selection field is the data field 606.

 The command field 602 includes two subfields: a device address (DA) field 608, which is the first field, and an op-code (OP code) field 610, which is the second field. The device address field 608 may be any number of bits long and is used to address each memory device in the system. For example, a one byte long device address field 608 is sufficient to address up to 256 memory devices. One address may be reserved for addressing all memory devices for simultaneously broadcasting operations. In an alternative embodiment, the device address field 608 may include a device type field for indicating the type of memory device to which the op-code field 610 is directed. For example, the device type field may represent DRAM, SRAM, or flash memory. The op-code field 610 may be any number of bits long to represent an instruction for any number of memory devices and may include a bank address. For example, a flash memory instruction set will have a different instruction from the DRAM instruction set, so the op-code field will be configured to accept all possible instructions from both instruction sets if the memory system includes both types of memory devices. The address field 604 is used to provide a row address (Row Addr) or column address (Col Addr) of the memory array, depending on the type of operation specified by the op-code. The data field 606 may contain any number of bits of data to be written to or programmed into the memory device. Thus, the command packet 600 will vary in size, as write data may not be needed for a particular operation and both address and write data may not be needed for a particular operation.

Fig. 9 lists examples of instruction packets that can be used to operate a flash memory device having the configuration shown in Fig. 7 for use in the serial memory system described above. The byte positions in FIG. 9 correspond to the order in which they are received serially by the memory device. The command field 602 occupies the first and second byte positions including the device address DA as the information of the first byte and the op-code corresponding to the operation as the information of the second byte. The address field 604 may include a 3-byte row address (RA) occupying the third through fifth byte positions, but may include a 2-byte column address (CA) occupying only the third and fourth byte positions Command will be shortened. For instructions involving a two byte column address, the data field 606 will occupy the fifth bit position to the twenty-first bit position, if the data has that length. The data can occupy fewer or more byte positions.

Only a memory device having a device address that is to be received serially by each memory device in the system and issued to the DA subfield 608 of the command field 602, - code subfield (610). Otherwise, the instruction packet is passed through the memory device to the subsequent memory device in the chain. Since the op-code is specific to a particular operation, the memory device, and more specifically the serial interface and control logic block 508 of the memory device 500, can be used to control the circuitry required to latch the address and / Control. For example, if a page read command packet is received by a designated memory device, the designated memory device decodes the op-code to control the appropriate circuitry to latch the subsequent 3-byte row address.

An example of the command packet listed in FIG. 9 indicates flash memory operation. A set of instruction packets for any other type of memory device having different operations may be configured to conform to the described instruction structure.

The previously described command packet may be advantageously used to perform concurrent operation in a memory device, such as memory device 500 of FIG. If memory device 500 is configured to access any one of its banks independently, substantially simultaneous operation may be performed within the memory device. Independent access means that core operations for different memory banks can be handled independently of each other. An example of such a memory device is described in the aforementioned U.S. Patent Application 11 / 324,023. Core operation refers to a logical or functional operation that is not interrupted because the completion of the core operation depends on the particular sequence of events being executed under the control of the state machine or other logic.

  The concurrent operation improves the performance of the system because it does not have to wait until the memory controller completes the first operation before sending the command packet for the second operation. In a typical NAND flash memory device, the memory device will either not accept another command or will respond to a command received for a different memory bank until the core operation is completed for the current memory bank. Thus, the memory device executes several operations in series before accepting another instruction. In a simultaneous operation of this embodiment, one instruction packet initiates one operation in one memory bank and a subsequent instruction packet is received from a second memory bank of the same memory device while the core operation is being executed for the first memory bank Will immediately begin another operation of the < / RTI > Thus, both operations will be executed almost simultaneously by the two memory banks.

10 is a flow chart illustrating a method of performing concurrent operation in one memory device, such as memory device 500 configured for independent access of its memory bank. Beginning at step 700, a first instruction is issued by the memory controller and received by the memory device. The first command may be any one of the command packets shown in FIG. 9 and described above. If the entire packet (command field, address field, and data field) has been received, the core operation begins at 702 for the first memory bank of the memory device. The second instruction is issued by the memory controller and is received by the memory device in step 704.

In step 706, the core operation of the second memory bank is executed in response to the second instruction. As a result, the result information belonging to the first instruction will be provided in step 708. The result information may include status information or read data provided in response to the supplemental read command packet. The status information provides an indication of the success or failure of a particular type of operation or erase operation, such as a program, and is read from a status register associated with the memory bank in response to a supplemental "read status" command packet issued by the memory controller . Read data is provided in response to a supplemental " burst read "command packet. Referring to FIG. 1, a core operation for a read operation includes outputting a page of data read from a block of memory banks to a data register block 32. To read data from the data register block 32, a burst read operation is performed. In step 710, the result information pertaining to the second instruction is provided. The result information from both memory banks is eventually returned to the memory controller. Although the embodiment of FIG. 10 shows simultaneous operation of two memory banks, the method is applicable to simultaneous operation of two or more memory banks of a memory device.

Figures 11-15 are sequence diagrams illustrating examples of concurrent operations that may be performed by a flash memory device of the type described in U.S. Patent Application 11 / 324,023. Figures 11 to 15 show the signal traces of CSI, Dn, DSI and Qn per hour for one memory device of Figure 4 or 5. [ The illustrated sequences are not intended to represent a particular timing value, but are intended to represent relative timing between signals. The command strobe input (CSI) is generated by the memory controller and acts as an indicator of the length of the command that is assembled and issued by the memory controller. For example, if the issued command packet is two bytes in length, the corresponding CSI has an active edge (the rising edge in this example) corresponding to the first bit of the instruction and an inactive edge corresponding to the last bit of the instruction packet . The CSI signal controls the memory device instruction register to latch the instruction data. A data strobe input signal (DSI) is also generated by the memory controller and acts as an indicator of the length of data provided by the memory device. For example, if the read data required by the memory controller is 8 bytes in length, the corresponding DSI generated by the memory controller will have an active edge corresponding to the first bit of read data and an inactive Edge. CSI and DSI are generated by the memory controller because they know the issued command bit length and the required read data bit length.

11 is a sequence diagram illustrating simultaneous read operations for two different banks of memory devices. The page read command packet 800 for bank 0 is latched by the memory device when CSI is at a high logic level. For example, as shown in Fig. 9, the page read command includes a 2-byte command and a 3-byte row address. Bank 0 of the memory device begins to perform a read operation for the designated row address after CSI falls to a low logic level at time t0. As an example, a read operation for a flash memory device includes activation of a word line such as WLi in Fig. 1 and sensing of bit line data of BL0 to BLj. As a result, the sensed data is latched or stored in the data register block 32. In one embodiment, a page read command packet 800 is passed to the subsequent memory device through its Qn output port. In another embodiment, the page read command packet 800 is prohibited from being forwarded to an additional memory device since this command packet 800 is addressed to the current memory device. For example, the page read command packet 800 provided at the Qn output may be set to a null value after being latched into the command register. This maintains power because no inter-rail signal switching of the signal lines is required.

The page read command packet 802 for bank 1 is latched by the memory device when CSI is at a high logic level. Bank 1 of the memory device begins to perform a read operation for a designated row address after CSI falls to a low logic level at time t1. Now, concurrent operations are being performed by memory banks 0 and 1. After a certain number of clock cycles, the data is ready to be read from bank 0 at time t2. To read data from bank 0, the memory controller issues a burst read command packet 804 that is received and latched when CSI is at a high logic level. As shown in FIG. 9, the burst read command packet includes a column address at which data is to be read. After the CSI corresponding to the command packet 804 falls to a low logic level, the DSI rises to a high logic level to enable the Qn output port buffer, thereby causing the output data for bank 0 to be read as a read data packet 806 ). 1, the output of data to the Qn output buffer begins at the column address specified in the burst read command packet 804 and ends when the DSI falls to a low logic level. As shown in FIG. Data for bank 1 is read ready at time t3 until the last bit of output data for bank 0 is output. After DSI falls to a low logic level, a burst read command packet 808 for bank 1 is received and latched by the memory device. Depending on the falling edge of CSI for the burst read command packet 808, the DSI is driven back to a high logic level for a predetermined period of time to output the read data from bank 1 as a read data packet 810 to the Qn output port.

Since the core operation of bank 0 between t0 and t2 and the core operation of bank 1 between t1 and t3 overlap each other almost at the same time, the total core operating time for both read operations is between times t0 and t3. In the prior art, both core operations are executed in order, meaning that the core operation for bank 1 starts in response to a second page read command packet received after the core operation for bank 0 is completed at t2. The benefits of performing concurrent operations as indicated above will be apparent to those skilled in the art.

12 is a sequence diagram illustrating concurrent programming operations for two different banks of memory devices. From this point forward, note that the command packet received at the Dn input port of the memory device is forwarded to its Qn output port shown in the Qn signal trace of FIGS. 11-15. To program the memory bank, program data is first programmed for a particular row after being loaded into a data register of a memory device based on a particular column address. In Figure 12, a burst data load instruction packet 820 for bank 0 is received with the program data, followed by a page program instruction packet 822. Both instruction packets 820 and 822 are latched when CSI is at a high logic level. After the page program packet 822 is latched and decoded by the memory device, the core operation of programming data into bank 0 begins at time t0. Now, a burst data command packet 824 for bank 1 is received with the program data, followed by a page program command packet 826. After page program packet 826 is latched and decoded by the memory device, the core operation of programming data into bank 1 begins at time t1.

If necessary, the memory controller may request the status of the memory device by issuing a read status command packet 828. [ This accesses the status register of the memory device whose data is to be output as read data packet 830 to the Qn output port when DSI is at a high logic level. Those skilled in the art will appreciate that the status register is internally updated by the memory device as the internal operation is performed. In this example, read data packet 830 indicates that programming for bank 0 is complete. The read state command packet 832 issued subsequently causes the read data packet 834 to provide a value of a status register that may indicate that programming for bank 1 is complete. Once again, considerable time is saved when compared to sequential programming of two banks, since the core programming operations of bank 0 and bank 1 overlap almost simultaneously.

Figure 13 is a sequence diagram illustrating simultaneous read and program operation for two different banks of memory devices. The page read command packet 840 for bank 0 is followed by a page program command packet 844 for bank 1 after it is latched by the memory device and followed by a burst data load start command packet 842 for bank 1. At time t0, a core operation for reading data from bank 0 starts, while at time t1 a core operation for programming data into bank 1 begins. Since the core operation for the page 0 read operation of bank 0 has been started first, the data is ready at time t2, while the core operation for programming data into bank 1 is in progress. Thus, a burst read command packet 846 is received and the DSI is asserted to output read data from bank 0 in read data packet 848. [ After the DSI is deasserted to finish outputting the read data from bank 0, a read status command packet 850 may be issued to check the programming state of bank 1. Since bank 1 has to complete the programming operation at time t3, the DSI is asserted again and a read data packet 852 is provided at the Qn output port, indicating the success or failure of the programming operation for bank 1. [

14 is a sequence diagram illustrating simultaneous block erase for two different banks of memory devices. A block erase address input command packet 860 for bank 0 is latched by the memory device and followed by an erase command packet 862 for bank 0. [ After the erase command packet 862 is latched, the core operation for bank 0 begins at time t0. Block erase address input command packet 864 for bank 1 is now latched by the memory device, followed by an erase command packet 866 for bank 1. After the erase command packet 866 is latched, the core operation for bank 1 begins at time t1. The structure of the block erase address input command and erase command is shown in Fig. A separate read state command packet 868 and 870 may be issued and latched by the memory device if the erase operation for bank 0 should be completed at time t2 and the erase operation of bank 1 should be completed at time t3. Corresponding read data packets 872 and 874 are provided to the Qn output port of the memory device, each of which provides the value of the status register.

In the sequence diagrams of Figures 11-14, different combinations of simultaneous operation are illustrated. An advantage of the modular command packet structure described in the previous embodiments is that different command packets can be issued at different times. As shown above, a page program command packet follows immediately after the burst data load instruction packet. However, this is not always necessary, and a page program command packet may be issued later if desired. When the command packets are used in combination with the command strobe signal (CSI) and the data strobe signal (DSI), a further advantage is realized, which is the ability to pause the operation of the memory device. As previously mentioned, the CSI strobe signal may be provided by the memory controller to indicate that the command data on the Dn input port is to be latched by the command register, and may have a duration corresponding to the length of the command packet being issued . It will be appreciated by those skilled in the art that a relatively long period of time is required to input or output such data amount, since the input data for programming the memory bank and the output data read from the memory bank may exceed 1000 bytes in length. According to the present embodiment, the CSI and DSI strobe signals can be deasserted as soon as program data is loaded or read data is output, and can be resumed at a later time.

Figure 15 is a sequence diagram illustrating simultaneous programming and read operations for two different banks of memory devices, with a pause and resume operation. The burst data load start command packet 880 for bank 1 is latched and the data payload in the data field of the command packet is latched by the memory device. At time t0, data loading into the memory device is paused when the memory controller deasserts the CSI. In this example, only 256 bytes of data are latched by the memory device and tracked by the memory controller. The page read command packet 882 for bank 0 is latched and the core operation for bank 0 starts at time tl. The suspended data loading operation of the command packet 880 is resumed at time t2 when a burst data load command packet 884 for bank 1 is received. The data payload in the data field of the command packet 884 contains the remaining 1856 bytes of data that have not yet been latched. The following is the page program command packet 886 for bank 1, and the core operation for programming the data in bank 1 begins at time t3. As a result, the core operation for bank 0 will be completed at time t4, and a burst read command packet 888 for bank 0 is issued by the memory controller and latched by the memory device. Read data is output as data read packet 890 when DSI is at a high logic level.

However, since a large amount of data is output, the host system may want to make sure that programming for bank 1 is complete, since the controller knows that the programming operation must be completed within a certain predetermined time, such as at time t6 . The output of the read data can be suspended at time t5 by deasserting the DSI, instead of waiting for all read data to be output before sending the read status request. When the data output operation is paused, a read status command packet 892 is issued by the memory controller and latched by the memory device. A corresponding read data packet 894 is then provided containing the status register value. After the DSI is deasserted at the end of the read data packet 894, the burst read can resume. This is accomplished by causing the MEMB to issue a burst read command packet 896 for bank 0 containing the address of the next bit to be output before the paused read at time t5. At time t7, the remaining 1600 bytes are output as the read data packet 898 from the Qn output port.

The example of the paused operation of FIG. 15 represents the advantage of a modular instruction structure that performs concurrent operations, and each of the concurrent operations can be paused and resumed to maximize utilization of the cores and channels.

The examples of sequences and operations in Figures 11-15 relies on the CSI and DSI strobe signals to provide information about the command packet or the read data packet. Since the command packet is variable in size and there is no header information for indicating the bit length of the command packet, the CSI strobe signal functions as a header of the command packet provided in parallel with the serial command packet. The CSI signal is active for the length of the instruction packet and is used by the memory device to latch the instruction packet data appearing on the Dn input port into the appropriate register. The DSI signal is active for the length of the expected read data packet that is known by the memory controller and moves in parallel with the read data packet. Thus, the active DSI signal serves as the header of the read data packet. Thus, the length of the command packet and the read data packet corresponds to the length of their respective CSI and DSI strobe signals.

Since both the read data packet and the instruction packet move along the same signal line connected between the Dn and Qn ports of adjacent memory devices, the presence of the CSI strobe with the data specifies the data as the command data packet, The presence of the DSI strobe having data designates the data as read data. Thus, the strobe signals also identify the type of data moving through the memory system. The memory controller tracks the DSI strobe that it issues so that the received read data packet and the expected data type match. For example, the read data packet may include status register information or data read from the memory array.

Considering the functional relationship of the CSI and DSI signals, a minimum separation time is inserted between any type of subsequent strobe signals. This ensures that all command packets and read data packets are defined separately and ensures that the appropriate type of data is latched by the memory device of the memory controller. There are four possible situations where separation is used. These are CSI-CSI separation (t CCS ), CSI-DSI separation (t CDS ), DSI-CSI separation (t DCS ), and DSI-DSI separation (t DDS ).

The CSI-CSI separation (t CCS ) is the minimum separation time during the clock period (t CK ) between successive command packets to the same or a different device. This isolation time allows the previous instruction to be cleared from the memory device, for example, by clearing the instruction register and resetting some instruction logic when preparing a new instruction. The DSI-DSI separation (t DDS ) is the minimum separation time during the clock period (t CK ) between consecutive read data packets to the same device. This isolation time causes the output buffer circuit to reset when it prepares the next data to be output. The DSI-CSI separation (t DCS ) is the minimum separation time during the clock period (t CK ) between the read data packet and the subsequent command packet to the same or a different device. The CSI-DSI separation (t CDS ) is the minimum separation time during the clock period (t CK ) between the command packet and the read data packet to the same device. These two isolation times ensure that the appropriate data types are latched by the memory device, since they can appear continuously on the Dn input port of the memory device. Since the memory controller issues the CSI and DSI signals to inform the instruction packet or the data packet bit length, the instruction packets and the data packets themselves are guaranteed to be separated by the same minimum time as the strobe signals.

Examples of these separation times are annotated in Figures 11-14 and the minimum separation time can be one data latching edge of the clock, which may be part of a clock period depending on the data rate structure employed. For example, in a single data rate structure (SDR) where data is latched at the rising edge of the clock, the minimum separation time is one clock cycle or period. In a double data rate structure (DDR) where data is latched on both the rising and falling edges of the clock, the minimum separation time is 0.5 of the clock period. 11 to 15 are examples of simultaneous operation in a single memory device and do not clearly show the relationship of CSI-DSI isolation or DSI-CSI isolation. 16 is a sequence diagram showing the relationship between CSI-DSI and DSI-CSI separation.

16 is an example of a scenario in which the first memory device outputs its read data from its Qn output port and the second memory device receives the command packet after the read data is output from the first memory device. The two memory devices mentioned in this example can correspond, for example, to those shown in Figures 4 and 5. Signal traces for the DSI_1, CSI_1, DSO_1, CSO_1 and Qn_1 ports are shown for a first memory device, where the appended "_1" represents the port of the first memory device. The signal traces for DSI_2, CSI_2, and Dn_2 are shown for the second memory device, where the appended "_2" represents the port of the second memory device. It is assumed that the first memory device is already receiving one or more instruction packets for reading data. As a result, DSI_1 receives the strobe signal 902 to output the data as the read data packet 902 to the Qn_1 port. The read data packet 902 is labeled "Qn_1 Read DATA ". Since the read data and the strobe signal are transferred serially from the first memory device to the second memory device, DSO_1 transfers the strobe signal 900 received from the DSI_1 port to the DSI_2 port of the second memory device. Similarly, the read data packet 902 is transferred from the Qn_1 port of the first memory device to the DN_2 port of the second memory device.

The memory controller now issues a CSI strobe signal 906 accompanied by a command packet 904 labeled "Dn_2 CMD DATA " addressed to the second memory device. The strobe signal 906 is transferred to the first memory device via CSI_1 and the instruction packet is transferred to the Dn input port of the first memory device (not shown in FIG. 16) and output via the Qn_1 output port. The first memory device ignores the command packet 904 because the command packet 904 is addressed to the second memory device. The first memory device then transfers the strobe signal 906 from its CSO_1 to the CSI_2 port of the second memory device and transfers the command packet 904 from its Qn_1 output port to the CSI_2 port of the second memory device . A minimum separation t CDS between the falling edge of the strobe signal 900 and the rising edge of the strobe signal 906 and a minimum separation between the last bit of the read data packet 902 and the first bit of the command packet 904 The second memory device reliably latches the instruction packet 904 in the appropriate register. On the other hand, if the instruction packet 904 and its corresponding strobe signal 906 are issued without any separation t CDS , then the second memory device will read the read data bits of the read data packet 902 as part of the instruction packet 904 It can be latched. Thus, the minimum separation ensures that there is no mix of data types.

Memory devices, particularly non-volatile memory devices, in the memory system described above have the advantage of being able to retain stored data in the absence of power supplied to the memory device. However, the transition between full power operation and no power or transition between power saving levels can jeopardize the integrity of the stored data.

17A shows a flash memory device to which embodiments of the present invention can be applied. 17A, the flash memory 1010 includes a logic circuit such as a control circuit 1012 for controlling various functions of a flash circuit, an address register 1012a for storing address information, a data register An instruction register 1012c that stores instruction data information, a high voltage circuit that generates the necessary program and erase voltages, and a core memory circuit that accesses the memory array 1014. [ The control circuit 1012 includes logic for executing internal flash operations such as an instruction decoder and read, program and erase functions. Those skilled in the art will appreciate that these operations are performed in combination with the address data and program data stored in each address register 1012a and data register 1012b in response to the instruction data stored in instruction register 1012c, I will understand. The command data, the address data, and the program data are issued by the memory controller and latched into the corresponding registers by the flash memory 1010. The basic functions of the illustrated circuit blocks of flash memory 1010 are well known in the art. Those skilled in the art will understand that the flash memory 1010 shown in Figure 17A represents one possible flash memory configuration among many possible configurations.

For proper operation of the flash memory 1010, the register storing the address, data, and instruction information must be reliable. Improper values stored in the register result in device malfunction. For example, the variable supply voltage can cause the register to randomly change the state of the information stored in the instruction register 1012c, thereby generating a bit pattern corresponding to the received program or erase instruction. In such a case, the pseudo-program operation causes the random data in data register 1012b to be programmed with the random address of address register 1012a of memory array 1014. [ If data is present at this address, the memory cell corresponding to that address is subject to the programming voltage, and its threshold voltage may change. The pseudo-erase operation may cause erasure of existing data in the memory array 1014. [ Since the memory controller does not recognize the pseudo operation performed by the flash memory 1010, the lost data can not be retrieved.

The register of the flash memory 1010 is generally designed as a flip-flop circuit having two stable states. The D flip-flop is a circuit known in the art, as shown in Figure 17B. The D flip-flop 1050 has a D-input that receives input data D_IN internally latched at the active edge of the clock signal CLK, such as the rising edge of CLK. When latched, the Q-output provides D_OUT corresponding to the logic state of D_IN while the complementary Qb output provides D_OUTb corresponding to the inverted logic state of D_IN. The reset input clears the latch while signal RESET is at an active logic level, e. G. , V SS or ground. Each flip-flop circuit accordingly stores one bit of data and instruction register 1012c includes a plurality of flip-flop circuits. As is known to those skilled in the art, a flip-flop latch circuit may include a pair of crossed inverting circuits.

18 shows a sequence of a voltage source ( Vcc ), an active low logic level reset signal (RST #), and an active low logic level chip enable signal CE # during power up and power down operations in a general flash memory 1010 Fig. During a power-up operation, the supply voltage (V CC ) starts transitioning from a low GND or V SS voltage level to a high V CC voltage level when turned on (t ON ). V CC voltage level rises, and at time t ST, and reach a stable voltage level V ST, that is, the flash memory 1010 can be operated when. As a result, the V CC voltage level reaches the maximum V CC level at time t V. And a reset device is received from an associated memory controller enable signal (RST # and CE #) is high, but at the same time in each time t ON inert driven to a logic level to be in accordance with the rise of the voltage V CC. If RST # is deasserted or is at an inactive logic level, the device is in a "ready " state and is operable to receive an instruction from the memory controller. Optionally, the controller deasserts the CE # signal at time t ON by driving it to an inactive high logic level while the device is in the reset state. Since V CC rises toward its maximum voltage level, CE # follows V CC rise. The CE # signal can be asserted at time t CEOff to bring the device into normal operation. The time t CEOff occurs after at least the time interval of t CE # elapses after the RST # signal is deasserted or driven to an inactive high logic level (i.e., after time t V ). When the device enters the normal running state, the initializing operation can be executed at both the device level and the system level. However, during the V CC transition from time t ON to time t V , or at least until time t ST , the control signal to the register can not be accurately controlled. This can lead to pseudo information being stored in several registers of the flash memory 1010, which can result in improper programming or erasure of data resulting in loss of data integrity in the flash memory 1010. [

The loss of data integrity due to unintentional program / erase operations during power transfer requires a gradual increase in speed and a reduction in size as well as a demand for lower power consumption may result in the flash memory device having a lower V CC voltage level It is exacerbated by the current generation of flash devices that need to be routinely operated. The lower operating V CC level expands the problem associated with the pseudo-information stored in the various registers of the flash device, which adversely affects data reliability.

A method of protecting data during a power transition such as a power rise and a power fall operation in a nonvolatile memory device will be described. Before any power transitions are asserted, a reset signal is asserted to disable the function of the memory device. The reset signal is maintained during the preset time, during which the device voltage is expected to stabilize. During this time, all internal registers, such as the device's instruction register, are set to default values to prevent data loss due to the pseudo program / erase instruction being executed by the device.

FIG. 19 is a timing chart showing a voltage source ( Vcc ), an active low logic level reset signal (RST #), and an active low logic level chip enable signal ( Vcc ) during power up and power down operations in a nonvolatile memory device according to an embodiment of the present invention. (CE #). As previously described, the V CC voltage transitions from a low GND or V SS voltage level to a high V CC voltage level at time t ON . Alternatively, the V CC voltage level may transition from the low power mode to the V CC voltage level. The V CC voltage level may rise at timely and at time t ST , exceeding the stable voltage level V ST , at which time the flash memory 1010 may be operated. As a result, the V CC voltage level reaches the maximum V CC level at time t V. However, in order to prevent device malfunctions due to the pseudo information being latched into the command register, a controller such as a memory controller associated with the non-volatile memory device must be able to detect at least the time required for the V CC voltage level to reach a stable V ST voltage level and keeps the RST # signal at the active low logic level to disable all functions of the device during the waiting period, from t ON to t ST . In the embodiment shown in FIG. 19, the RTS # signal is at an active low logic level during an extended time t RST from t ON to t ST + at least V CC level up to time t 1 after reaching a stable voltage level V ST maintain. All internal registers of the device will therefore remain in the default or reset state while the RTS # signal is at the active low logic level.

Eventually, the controller will deassert RTS # after time t RST as shown in FIG. After this time, the power is stabilized, and then the device components can prepare or initialize themselves for operation. Optionally, the controller deasserts the CE # signal at time t ON by driving the CE # signal to an inactive high logic level while the device is in the reset state. Since V CC rises to its maximum voltage level, CE # follows V CC rise. The CE # signal can be asserted at time t CEOff to bring the device into normal operation. CEOff time t occurs after the RST # signal is at least a time period t 2 has passed since the drive to the deasserted, or inactive high logic level. When the device enters the normal running state, the initializing operation can be executed at both the device level and the system level. Careful maintenance of the device in a reset state for a predetermined amount of time during a power transition operation prevents pseudo information from being stored or latched in the various registers of the device. The device is thereby protected against improper and careless programming or erasure of data, ensuring data integrity during power transfer.

A similar procedure to ensure data protection can be achieved by asserting RST # at a predefined time before t OFF when V CC is turned off and driven to a low GND or V SS voltage level or by asserting RST # Lt; / RTI > during the power down operation.

A flowchart illustrating a method of protecting data during power transfer in a nonvolatile memory device according to an embodiment of the present invention is shown in FIG. A memory controller that controls non-volatile memory devices, such as flash memory devices, keeps RST # low prior to any power transition to place the device in a reset state (step 1100). During this time, the internal registers of the device are set to the default or reset state. The controller then transitions power (step 1102) and waits for a predetermined amount of time to stabilize the device's internal voltage (step 1104). The standby time corresponds to t RST shown in Fig. 19, and at least the time required for the V CC voltage level to reach the stable V ST voltage level (the time from t ON to t ST ) + at least the V CC level becomes stable voltage level It is time t 1 after reaching V ST . The time t 1 may be determined based on device characteristics such as operating voltage and process technology. For example, the total time that RST # is kept low, that is, t RST , may be 10 s or more. During this time, various components of the device are stabilized, the clock becomes operational, and the frequency and phase become stable.

After the elapse of the time t RST , the controller asserts the RST # high signal when the device is expected to be in the "ready " state (step 1106). 19, the controller asserts the CE # signal at time t ON while the device is in the reset state and sends the signal to the disabled state after RST # is deasserted so that the memory device is in the reset state . The CE # signal is deasserted at time t CEOff to bring the device into normal operation. The time t CEOff is after at least t 2 has elapsed since the RST # signal was asserted. When the device enters a normal running state, an initializing operation may be performed at both device level and system level (step 1108). Similar to time t 1 , time t 2 can be determined based on device characteristics and changes from one memory system to another. For example, t 2 may be greater than or equal to 100 s.

Figure 21 illustrates the steps followed by the device during power transfer to ensure data protection in accordance with one embodiment of the present invention. The non-volatile memory device receives the RST # low signal before any power transition from the memory controller that controls the device (step 1200). The device then receives power from the controller to activate the device component (step 1202). This received power may be from VSS voltage or from a low power mode voltage level to a full VCC operating voltage level. Due to the low RST # signal, the device is placed in a reset state. During this time, the internal registers of the device and some finite state machine are set to the default or reset state and are maintained (step 1204). Thereafter, the controller waits for a predetermined time to stabilize the internal voltage of the device before RST # is asserted high. After elapse of time t RST , the controller asserts the RST # high signal when the device is expected to be in the "ready " state. The device receives the RST # high signal and places the device in the "ready" state (step S1206). The controller asserts the CE # signal at time t CEOff to bring the device into normal operation. As previously described, if the device enters a normal running state, an initialization operation may be performed at the device level (step 1208).

A method of data protection during power transition in the memory system 200 of FIG. 4 will now be discussed. At power up, the memory controller 202 keeps the reset (RST #) low to keep all the memory devices 204, 206, 208, and 210 in reset while the power stabilizes and the device is preparing for its operation do. RST # is kept low by the controller 202 for a minimum time of t 1 (e.g., 20 s) after V CC has stabilized, as shown in FIG. While RST # remains low, all finite state machines in memory are initialized, and some configuration and status registers are reset to their default or reset state. Before RST # is deasserted to a high logic level, the clock becomes operational and the frequency and phase are stabilized. As previously described for FIG. 19, the controller 202 asserts the CE #, after the device has asserted the media CE # signal at time t ON while the reset state and, RST # is deasserted. The VCE # signal is asserted at time t CEOff to bring the device into normal operation. The time t CEOff is after the time interval of at least t 2 elapses after the RST # signal is asserted. When the device enters the normal running state, the initializing operation can be executed at both the device level and the system level. Examples of initialization operations include device address and identifier generation and allocation for each device in a serial connection. Various methods for generating device addresses and identifiers are disclosed in co-pending U.S. Patent Application 11 / 622,828; 11 / 750,649; 11 / 692,452; 11 / 692,446; 11 / 692,326; And 11 / 771,023.

By ensuring that the device is in a reset state for a predetermined amount of time during a power transition operation, it prevents pseudo information from being stored or latched in various registers of the device. The device is thereby protected against improper programming or erasure of data, ensuring data integrity during power transfer.

In the foregoing description, for purposes of explanation, numerous specific details are set forth in order to provide an understanding of embodiments of the invention. However, it will be apparent to those skilled in the art that these specific details are not required to practice the invention. In other instances, well-known electrical configurations and circuits are shown in block diagram form in order to facilitate clarity of the invention. For example, no specific details are provided as to whether embodiments of the invention described herein are implemented as software routines, hardware circuits, firmware, or combinations thereof.

Embodiments of the invention may be practiced with other types of computer-readable media, such as computer readable media (also referred to as computer usable media having computer readable program code embodied in a computer readable medium, Products. The machine-readable medium may be any suitable type of storage medium, including magnetic, optical, or electrical storage media including diskettes, compact disk read only memory (CD-ROM), memory devices (volatile or nonvolatile) Lt; / RTI > The machine-readable medium may include various sets of instructions, code sequences, configuration information, or other data that cause the processor to perform the steps of the method in accordance with an embodiment of the invention. Those skilled in the art will appreciate that other instructions and operations necessary to realize the described invention may be stored in a machine-readable medium. Software running from a machine-readable medium may interface with the circuitry to execute the tasks described.

The embodiments of the present invention described above are intended to be examples only. Modifications, alterations, and modifications may be made by those skilled in the art to the particular embodiments, without departing from the scope of the invention as set forth solely by the claims appended hereto.

Claims (55)

  1. A controller having a serial channel output port for providing a serial bitstream command packet, a control output port for providing a data output control signal, and a serial channel input port for receiving a serial bit stream read data packet, An operation code and a device address;
    A memory device having an input port for receiving the serial bitstream instruction packet from the controller and for executing the operation code when the device address corresponds to a memory device and a control input port for receiving the data output control signal, Providing a bitstream command packet via an output port and then providing the serial bitstream read data packet in response to the data output control signal through the output port if the operation code corresponds to a read function; And
    A memory expansion module and an expansion link between the controller and the memory device into which one of the jumpers is insertable.
  2. The memory device of claim 1, further comprising at least one intervening memory device coupled in series between the memory device and the controller, wherein the at least one intervening memory device receives the serial bitstream command packet and forwards it to the memory device The input bit having an input port and then providing the serial bit stream read data packet if the device address corresponds to the memory device and the operation code corresponds to a read function.
  3. 3. The memory system of claim 2, wherein a complementary clock signal is provided in parallel to the memory device and the at least one intervening memory device.
  4. 3. The memory system of claim 2, wherein a complementary clock signal is provided to the at least one intervening memory device and communicated to the memory device by the at least one intervening memory device and to the controller by the memory device.
  5. delete
  6. 3. The memory system of claim 2, wherein the at least one intervening memory device is part of the memory expansion module having connection means configured for electrical connection with the expansion link.
  7. The memory device of claim 2, wherein the memory device and the at least one intervening memory device each comprise a native memory core and a serial interface and control logic for controlling the native memory core in response to the serial bitstream instruction packet. ≪ / RTI >
  8. 8. The memory system of claim 7, wherein the memory device native memory core and the at least one intervening memory device native memory core are NAND flash based.
  9. 8. The memory system of claim 7 wherein the memory device native memory core and the at least one intervening memory device native memory core are different.
  10. 3. The memory system of claim 2, wherein the native memory core comprises one of DRAM, SRAM, NAND flash, and NOR flash memory core.
  11. The memory system of claim 1, wherein the serial bitstream instruction packet has a modular structure in which the size of the serial bitstream instruction packet is variable.
  12. 12. The system of claim 11, wherein the serial bitstream instruction packet comprises an instruction field providing the operation code and the device address.
  13. 13. The memory system of claim 12, wherein the command field comprises a first sub-field providing the operation code and a second sub-field providing the device address.
  14. 12. The memory system of claim 11, wherein the serial bitstream instruction packet comprises an instruction field providing the operation code and the device address, and an address field providing one of a row address and a column address.
  15. 12. The system of claim 11, wherein the serial bitstream instruction packet comprises an instruction field providing the operation code and the device address, an address field providing one of a row address and a column address, and a data field providing write data. Memory system.
  16. 12. The memory system of claim 11, wherein the controller provides an instruction strobe in parallel with the serial bitstream instruction packet, the instruction strobe having an activity level equal to the length of the serial bitstream instruction packet.
  17. 17. The memory system of claim 16, wherein the controller provides a data input strobe in parallel with a serial bit stream read data packet, wherein the data input strobe has an active level that matches the length of the serial bit stream read data packet.
  18. 19. The memory system of claim 17, wherein the memory device latches the serial bitstream instruction packet in response to the active level of the instruction strobe when the device address corresponds to the memory device.
  19. 19. The memory system of claim 18, wherein the memory device input port is enabled in response to the activation level of the data input strobe.
  20. 21. The system of claim 19, wherein the instruction strobe and the data input strobe are non-overlapping signals.
  21. 21. The memory system of claim 19, wherein the instruction strobe and the data input strobe are separated by at least one data latching clock edge.
  22. 21. The system of claim 19, wherein the instruction strobe is separated from an adjacent instruction strobe by at least one data latching clock edge.
  23. 21. The memory system of claim 19, wherein the data input strobe is separated from an adjacent data input strobe by at least one data latching clock edge.
  24. delete
  25. delete
  26. delete
  27. delete
  28. A plurality of memory devices;
    A controller for controlling the apparatus,
    The controller having an output port for providing a bitstream command packet to a first one of the plurality of memory devices and a control output port for providing a data output control signal, the bitstream command packet including an operation code and a device address ,
    Each of the plurality of memory devices receiving the bitstream command packet and the data output control signal from one of the controller and the preceding memory device and executing the opcode if the device address corresponds thereto, Each of the plurality of memory devices providing the bitstream command packet to one of the next memory device and the controller, and wherein the bitstream read data packet is responsive to the data output control signal if the operation code corresponds to a read function, The controller being provided to the controller from a final one of the memory devices; And
    An expansion configured to insert one of a jumper and a memory expansion module as at least one expansion link connected between one of the plurality of memory devices and the controller or between two adjacent ones of the plurality of memory devices, ≪ / RTI > link.
  29. 29. The memory system of claim 28, wherein the plurality of memory devices are connected in series and the first and last memory devices are connected to the controller.
  30. 29. The memory system of claim 28, wherein the controller sends a bit stream data packet to the first one of the plurality of memory devices.
  31. 32. The memory system of claim 30, wherein the bitstream data packet and the bitstream read data packet from the controller comprise a serial bit stream.
  32. 32. The memory system of claim 30, wherein the bitstream data packet and the bitstream read data packet from the controller comprise a parallel bitstream.
  33. 29. The memory system of claim 28, wherein the plurality of memory devices comprises a mixture of memory devices of the same type or different types.
  34. The memory system of claim 1, wherein the memory expansion module receives the serial bitstream instruction packet and transfers the serial bitstream instruction packet to the controller or the memory device.
  35. 35. The memory system of claim 34, wherein the memory expansion module comprises at least one intervening memory device for receiving the serial bitstream instruction packet and outputting the serial bit stream instruction packet.
  36. The memory system of claim 1, wherein the jumper and the memory expansion module are removably held on at least one of the expansion links.
  37. 37. The memory system of claim 36, wherein the jumper is inserted into at least one of the expansion links of the first configuration of the memory system, and wherein the memory expansion module has a memory capacity greater than And wherein the one or more expansion links are inserted into one of the expansion links.
  38. 37. The system of claim 36, wherein at least one of the expansion links comprises a first terminal receiving the serial bitstream instruction packet and a second terminal providing the serial bitstream instruction packet, And electrically connect the first terminal to the second terminal when inserted into the second terminal.
  39. The memory system of claim 1, wherein at least one of the expansion links comprises at least two expansion links connected in series between the memory device and the controller.
  40. 29. The memory system of claim 28, wherein the memory expansion module receives the bitstream command packet and delivers the bitstream command packet to the controller or one of the plurality of memory devices.
  41. 41. The memory system of claim 40, wherein the memory expansion module comprises at least one intervening memory device for receiving the bitstream instruction packet and outputting the bit stream instruction packet.
  42. 29. The memory system of claim 28, wherein the jumper and the memory expansion module are removably held on at least one of the expansion links.
  43. 43. The memory system of claim 42, wherein the jumper is inserted into at least one of the expansion links of the first configuration of the memory system, and wherein the memory expansion module has a memory capacity greater than And wherein the one or more expansion links are inserted into one of the expansion links.
  44. 43. The system of claim 42, wherein at least one of the expansion links comprises a first terminal receiving the bitstream command packet and a second terminal providing the bitstream command packet, wherein the jumper inserts into at least one of the extension links And to electrically connect the first terminal to the second terminal when the second terminal is connected to the second terminal.
  45. 29. The memory system of claim 28, wherein at least one of the expansion links comprises at least two expansion links connected in series between the memory device and the controller or between the two adjacent memory devices.
  46. delete
  47. delete
  48. delete
  49. delete
  50. delete
  51. delete
  52. delete
  53. delete
  54. delete
  55. delete
KR1020097005767A 2006-08-22 2007-08-22 scalable memory system KR101476463B1 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
US83932906P true 2006-08-22 2006-08-22
US60/839,329 2006-08-22
US86877306P true 2006-12-06 2006-12-06
US60/868,773 2006-12-06
US90200307P true 2007-02-16 2007-02-16
US60/902,003 2007-02-16
US89270507P true 2007-03-02 2007-03-02
US60/892,705 2007-03-02
US11/840,692 2007-08-17
US11/840,692 US7904639B2 (en) 2006-08-22 2007-08-17 Modular command structure for memory and memory system

Publications (2)

Publication Number Publication Date
KR20090045366A KR20090045366A (en) 2009-05-07
KR101476463B1 true KR101476463B1 (en) 2014-12-24

Family

ID=39106444

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020097005767A KR101476463B1 (en) 2006-08-22 2007-08-22 scalable memory system
KR1020127021608A KR101476515B1 (en) 2006-08-22 2007-08-22 Scalable memory system

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1020127021608A KR101476515B1 (en) 2006-08-22 2007-08-22 Scalable memory system

Country Status (7)

Country Link
EP (1) EP2062261A4 (en)
JP (2) JP5575474B2 (en)
KR (2) KR101476463B1 (en)
CN (2) CN102760476A (en)
CA (1) CA2659828A1 (en)
TW (1) TWI437577B (en)
WO (1) WO2008022454A1 (en)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7865756B2 (en) 2007-03-12 2011-01-04 Mosaid Technologies Incorporated Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices
US8467486B2 (en) 2007-12-14 2013-06-18 Mosaid Technologies Incorporated Memory controller with flexible data alignment to clock
US8781053B2 (en) 2007-12-14 2014-07-15 Conversant Intellectual Property Management Incorporated Clock reproducing and timing method in a system having a plurality of devices
JP2012504263A (en) * 2008-09-30 2012-02-16 モサイド・テクノロジーズ・インコーポレーテッド Serially connected memory system with output delay adjustment
US7957173B2 (en) * 2008-10-14 2011-06-07 Mosaid Technologies Incorporated Composite memory having a bridging device for connecting discrete memory devices to a system
EP2359372B1 (en) * 2008-12-18 2020-04-08 NovaChips Canada Inc. Error detection method and a system including one or more memory devices
US20110002169A1 (en) 2009-07-06 2011-01-06 Yan Li Bad Column Management with Bit Information in Non-Volatile Memory Systems
US20110258366A1 (en) * 2010-04-19 2011-10-20 Mosaid Technologies Incorporated Status indication in a system having a plurality of memory devices
WO2011134051A1 (en) * 2010-04-26 2011-11-03 Mosaid Technologies Incorporated Serially connected memory having subdivided data interface
US8856482B2 (en) * 2011-03-11 2014-10-07 Micron Technology, Inc. Systems, devices, memory controllers, and methods for memory initialization
US9239806B2 (en) 2011-03-11 2016-01-19 Micron Technology, Inc. Systems, devices, memory controllers, and methods for controlling memory
US9342446B2 (en) 2011-03-29 2016-05-17 SanDisk Technologies, Inc. Non-volatile memory system allowing reverse eviction of data updates to non-volatile binary cache
CN102508797B (en) * 2011-10-27 2015-02-11 忆正存储技术(武汉)有限公司 Flash memory control expanding module, controller, storage system and data transmission method thereof
TWI581267B (en) 2011-11-02 2017-05-01 諾瓦晶片加拿大公司 Flash memory module and memory subsystem
US8825967B2 (en) 2011-12-08 2014-09-02 Conversant Intellectual Property Management Inc. Independent write and read control in serially-connected devices
US8966151B2 (en) * 2012-03-30 2015-02-24 Spansion Llc Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal
US9760149B2 (en) 2013-01-08 2017-09-12 Qualcomm Incorporated Enhanced dynamic memory management with intelligent current/power consumption minimization
KR20150110918A (en) 2014-03-21 2015-10-05 에스케이하이닉스 주식회사 Semiconductor memory device
JP6453718B2 (en) * 2015-06-12 2019-01-16 東芝メモリ株式会社 Semiconductor memory device and memory system
KR20170102730A (en) 2016-03-02 2017-09-12 한국전자통신연구원 Memory interface apparatus
US10372330B1 (en) * 2018-06-28 2019-08-06 Micron Technology, Inc. Apparatuses and methods for configurable memory array bank architectures

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040148482A1 (en) * 2003-01-13 2004-07-29 Grundy Kevin P. Memory chain
US20060031593A1 (en) * 2004-08-09 2006-02-09 Sinclair Alan W Ring bus structure and its use in flash memory systems

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07327179A (en) * 1994-05-31 1995-12-12 Canon Inc Changeover device for plural video images
US5729683A (en) * 1995-05-18 1998-03-17 Compaq Computer Corporation Programming memory devices through the parallel port of a computer system
US6144576A (en) * 1998-08-19 2000-11-07 Intel Corporation Method and apparatus for implementing a serial memory architecture
JP3853537B2 (en) * 1999-04-30 2006-12-06 株式会社日立アドバンストデジタル Semiconductor memory file system
US6449308B1 (en) * 1999-05-25 2002-09-10 Intel Corporation High-speed digital distribution system
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
TW504694B (en) * 2000-01-12 2002-10-01 Hitachi Ltd Non-volatile semiconductor memory device and semiconductor disk device
JP2001266579A (en) * 2000-01-12 2001-09-28 Hitachi Device Eng Co Ltd Non-volatile semiconductor memory device and semiconductor disk device
US6754129B2 (en) * 2002-01-24 2004-06-22 Micron Technology, Inc. Memory module with integrated bus termination
US20040022022A1 (en) * 2002-08-02 2004-02-05 Voge Brendan A. Modular system customized by system backplane
JP2004110849A (en) * 2003-12-01 2004-04-08 Toshiba Corp Semiconductor system and memory card

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040148482A1 (en) * 2003-01-13 2004-07-29 Grundy Kevin P. Memory chain
US20060031593A1 (en) * 2004-08-09 2006-02-09 Sinclair Alan W Ring bus structure and its use in flash memory systems

Also Published As

Publication number Publication date
JP2012226786A (en) 2012-11-15
CN101506895A (en) 2009-08-12
TWI437577B (en) 2014-05-11
JP5575474B2 (en) 2014-08-20
KR20090045366A (en) 2009-05-07
KR101476515B1 (en) 2014-12-24
KR20120110157A (en) 2012-10-09
CA2659828A1 (en) 2008-02-28
TW200828338A (en) 2008-07-01
CN102760476A (en) 2012-10-31
JP2010501916A (en) 2010-01-21
WO2008022454A1 (en) 2008-02-28
EP2062261A4 (en) 2010-01-06
EP2062261A1 (en) 2009-05-27
CN101506895B (en) 2012-06-27

Similar Documents

Publication Publication Date Title
US9218284B2 (en) Storage device command interval controller
US8675408B2 (en) Non-volatile memory device having configurable page size
US8223562B2 (en) Method and system for a serial peripheral interface
KR101089409B1 (en) Memory array error correction apparatus, systems, and methods
US9159427B2 (en) Memory devices and their operation with different sets of logical erase blocks
US7542357B2 (en) Semiconductor device
US6317812B1 (en) Device and method for controlling solid-state memory system
EP1929480B1 (en) Daisy chain cascading devices
US7515485B2 (en) External clock tracking pipelined latch scheme
KR100990541B1 (en) Efficient read, write method for pipeline memory
US7801696B2 (en) Semiconductor memory device with ability to adjust impedance of data output driver
US6577553B2 (en) Semiconductor memory device
KR101507628B1 (en) System and method for data read of a synchronous serial interface nand
KR101373793B1 (en) Flash memory control interface
US7019556B2 (en) Semiconductor memory device capable of adjusting impedance of data output driver
US5297029A (en) Semiconductor memory device
US7609553B2 (en) NAND flash memory device with burst read latency function
US9570123B2 (en) Non-volatile memory serial core architecture
KR0170006B1 (en) Semiconductor storage device
US9257161B2 (en) Mechanism for enabling full data bus utilization without increasing data granularity
TWI512755B (en) Method and system to access memory
JP2011018372A (en) Flash memory system capable of inputting/outputting data sector-by-sector at random
US20120198265A1 (en) Circuit
US10223003B2 (en) Method and system for accessing a flash memory device
US8619493B2 (en) Flexible memory operations in NAND flash devices

Legal Events

Date Code Title Description
A107 Divisional application of patent
A201 Request for examination
E902 Notification of reason for refusal
E90F Notification of reason for final refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20171117

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20181115

Year of fee payment: 5