JP3853537B2 - Semiconductor memory file system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a file system using a semiconductor having no rotating mechanism, and more particularly to a semiconductor file system suitable for increasing the capacity.
[0002]
[Prior art]
A file system using a semiconductor memory is configured using an electrically erasable nonvolatile memory, thereby enabling low power consumption and space saving. Although the capacity of semiconductor memory is increasing due to miniaturization of semiconductor processes, it is necessary to connect a large number of semiconductor memories to a large capacity such as a hard disk. An IC select signal is prepared, or an IC address setting terminal is prepared in the memory IC to reduce the IC select signal. Such a prior art is disclosed in, for example, US Patent 540859 Jul. 4, 1995.
[0003]
[Problems to be solved by the invention]
When configuring a space-saving large-capacity file system using a semiconductor memory, the data capacity of the semiconductor memory is one digit or more smaller than that of the hard disk system, and thus it is necessary to use a large number of semiconductor memories. .
[0004]
When connecting a large number of semiconductor memories to a semiconductor memory, a controller, and semiconductor memories using a common signal line, the drive capacity of the controller and the output buffer of the semiconductor memory is usually about 10 or more. The limit is considered to be about 16 or 20, and in order to use more semiconductor memories than this, it is necessary to divide the connection into a plurality using a buffer IC or the like.
[0005]
However, the use of the buffer IC limits the number of semiconductor memories that can be mounted by the buffer IC in a small device such as a PC card with a small mounting area.
[0006]
Further, when the controller IC for controlling the semiconductor memory is divided into a plurality of parts, the number of terminals of the controller IC is increased, the package size of the controller IC is increased, and as a result, the number of semiconductor memories is limited.
[0007]
The present invention has been made in view of the above-described problems, and an object thereof is to provide a semiconductor memory file system having a configuration advantageous for increasing the capacity.
[0008]
Another object of the present invention is to provide a semiconductor memory file system in which a buffer for data and control signals is built in a semiconductor memory.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a semiconductor memory file including a controller including a microprocessor and a control device that perform an operation in accordance with a command issued from a host, and a first semiconductor memory connected to the controller. The system further includes a plurality of semiconductor memories in addition to the first semiconductor memory, wherein the first semiconductor memory includes a buffer for at least one of data and control signals, and the plurality of semiconductor memories The controller is connected to the controller by a signal distributed from the first semiconductor memory.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIG.
[0011]
For example, as shown in FIG. 2, the semiconductor memory file system in the present embodiment includes a controller 2 including a microprocessor 3 and a control unit 4 and a memory 10 to which a data signal control signal is connected from a HOST 1.
[0012]
Various commands are issued from the HOST 1, and data corresponding to the commands issued from the HOST 1 is exchanged between the HOST 1 and the controller 2. The microprocessor 3 interprets the command issued from the HOST 1 and instructs the controller 2 to perform an operation corresponding to the issued command.
[0013]
As an example, when the command issued from the HOST 1 is a Read command, the microprocessor 3 reads out the data in the memory 10 corresponding to the address of the Read command issued by the HOST 1 from the memory 10 through the controller 2 and reads the data. The data is sequentially output in accordance with the read operation of HOST1. If the command issued by HOST1 is a Write command, the data written to the controller 2 by HOST1 is written to the address of the memory 10 corresponding to the address designated by HOST1.
[0014]
An example of the internal block configuration of the individual memory 100a used in the present invention is shown in FIG. The memory 100a constitutes the memory 10 of FIG. 2 and includes a memory unit 11, a command control unit 12, a command register 13, a chip address register 14, a comparator 15, a chip address setting register 16, and a SEL 17. . The memory 100a is a command issuing type memory having DI200, CKI300, and CMDI400 as main input terminals, and DO201, CKO301, and CMDO401 as output terminals. In addition, there is a reset terminal that performs initialization when the nonvolatile memory 100a is powered on.
[0015]
DI200 is sent in synchronization with CKI300. CMD400 is a signal indicating a delimiter of data sent from the DI200. As shown in FIG. 4, the DI200 is output from the controller 2 in response to an instruction from the microprocessor 3, and has a chip address 2000, command 2100, data address 2300, data 2200. Are sent in the order. Data address 2300 and data 2200 are omitted when the issued command is not required.
[0016]
In the example shown in FIG. 4, first, the command control unit 12 in FIG. 1 detects that the CMD 400 output from the controller 2 is asserted from the “L” level to the “H” level, and inputs the DI 200 to the chip address register 14. The control signal 24 is asserted, the chip address 2000 is fetched into the chip address register 14, and the input control signal 24 is negated at the end of fetching the chip address 2000 from the DI 200.
[0017]
The comparator 15 compares the values of the chip address register 14 and the chip address setting register 16 and outputs a comparison result 25 to the command control unit 12.
[0018]
Further, the command control unit 12 captures the value of the comparison result 25 between the chip address register 14 and the chip address setting register 16 at the end of the capture of the chip address 2000 and holds it as the internal status of the command control unit 12. From command 2100, the command register control signal 23 is asserted and taken into the command register 13.
[0019]
Normally, if the values of the chip address register 14 and the chip address setting register 16 match, the command control unit 12 performs an operation according to the fetched command, but compares the values of the chip address register 14 and the chip address setting register 16 For commands that are not necessary, ignore the comparison result and perform the operation according to the imported command.
[0020]
The CE 700 is controlled to output a value from the DO 201, CKO 301, and CMDO 401 after the CE 700 is asserted by the chip enable input of the memory, and the DO 201, CKO 301 is received by negating the CE 700. The output of the CMDO 401 is controlled to be in the “Hi-z” state.
[0021]
FIG. 6 shows an internal block configuration example of the memory 100b when the DI 200 and DO 201 in FIG. 1 are changed from serial to a plurality of bit widths.
[0022]
The memory 100b of this example basically has a circuit configuration similar to that of the memory 100a having the configuration shown in FIG. The difference is that the data width of DI200 and DO201 is from 1 bit to many bits.
[0023]
For this reason, in the memory 100b of this example, the command register 13, the chip address register 14, and the chip address setting register 16 are shift register configurations in FIG. 1 but are registers of a format for loading data in parallel. However, when the number of bits of the command register 13, the chip address register 14, and the chip address setting register 16 is larger than the number of bits of DI200 and DO201, the data is loaded in multiple times.
[0024]
FIG. 3 shows a connection example between the controller 10 and the memory 10 having the memories 100 to 159 having the configuration shown in FIG.
[0025]
3, CKO 300, CMDO 400, and DO 200 are connected to the corresponding DI, CKI, and CMDI inputs of memories 100, 110, 120,..., 159, and CE 0 is connected to memories 100, 101, 102,. .., to the CE input of 109, from the controller 2 to the CE input of the memories 110, 111, 112,..., 119, and from the controller 2 to the CE 2 of the memories 120, 121, 122,. Connected to CE input.
[0026]
As shown in FIG. 3, in this example, the memories 100, 101, 102,..., 109 are connected in columns, and similarly, the memories 110, 111, 112,. , ..., 129, memories 150, 151, 152, ..., 159 are also connected in series, and the DO outputs of the memories 109, 119, 129, ..., 159 are wired-connected, and the DI input of the controller 2 Similarly, the CKO outputs of the memories 109, 119, 129,..., 159 are also wired-connected and output to the CKI input of the controller 2.
[0027]
At this time, the memory 109, 119, 129,..., DO309 and CKO 209 of the memory 109 output only the data 2201 to the controller 2 as shown in FIG. , 159 output becomes "Hi-z"
By connecting the memories in the column in this way, the connection of the signal lines between the memories connected in the column becomes one-to-one. Therefore, the arrangement of the signal terminals of the memory can be optimized, the signal wiring length when mounted on the substrate can be shortened, and equal-length wiring can be simplified.
[0028]
In FIG. 3, when the memories are connected in a column, the skew generated between the data or command or address data input to the controller 2 or the DI of each memory and the clock signal input to the CKI input passes through the memory. Since it increases every time, it is necessary to consider the frequency of the clock and the number of memories connected in series.
[0029]
Basic commands issued to the memory 100 include "Read", "Write", "Erase", "Status Read", etc. In the present invention, in addition to the above, the chip address is reset in the chip address register 16 of FIG. Has a command that can.
[0030]
The “chip address reset” command, which is a feature of the present invention, will be described with reference to FIGS. Unless otherwise specified in the description of the timing chart in this specification, the “Hi” level of the waveform in the timing chart is expressed as an asserted state or assertion, and the “Lo” level is expressed as a negated state or negation.
[0031]
In FIG. 5, a DI 200 input in synchronization with the CKI 300 is sequentially input with a chip address 2000, a “chip address reset” command as a command 2100, and a new address as data 2200. Here, the loading of the chip address 2000 and the chip address register 14 and the comparison of the chip address, and the loading of the command 2100 into the command register 13 are performed in the same manner as described above.
[0032]
When the command 2100 detects that the command 2100 is a chip address reset command, the command control unit 12 asserts the control signal 26 to fetch the new chip address 2200, which is data following the command 2100, into the chip address setting register 16, and the chip address setting register At the same time that the new chip address is fetched into 16, the old chip address 2201 before fetching the new chip address 2200 is output from DO201.
[0033]
1 and FIG. 6, the value of the chip address setting register 16 of the memory 100 is initialized to “1” by resetting the memory when the power is turned on. Here, the chip address setting process of the memory in FIG. 3 will be described assuming that the number of bits of the chip address register 14 and the chip address setting register 16 in FIG. 1 or FIG. 6 is 8 bits.
[0034]
The memory reset signal is not shown in FIG. 3 for simplicity, but the values of the chip address setting registers 16 in all the memories 100, 101, 102,... Becomes "FF". Hereinafter, "1B" is expressed as "0x1B" in hexadecimal.
[0035]
First, the setting of the chip addresses of the memories 100, 101, 102,..., 109 in FIG. 3 will be described with reference to FIG.
[0036]
After the memory is reset, the value of the chip address setting register 16 of each of the memories 100, 101, 102,..., 109 is “0xFF”. First, the microprocessor 3 in FIG. 1 instructs the controller 2 to assert only CE0 among CE0 to CEn. As a result, the memories 100 to 109 are operable, and the output terminals of the memories 110 to 159 are “Hi-z”.
[0037]
Next, the microprocessor 3 instructs the controller 2 to issue a “reset chip address” command to the memory. At this time, the chip address 2000 is given “0xFF”, and the new chip address 2200 is given a unique value other than “0xFF”, for example, “0x00”. With the above operation, the value of the chip address setting register 16 of the memory 100 is changed from “0xFF” to “0x00”, and “0xFF” is output as the old chip address 2201 from the DO 201 of the memory 100. Therefore, since the new chip address “0xFF” is input after the memory 101, the value of the chip address setting register 16 after the memory 101 remains “0xFF”.
[0038]
Similarly, the chip address setting register 16 of the memory 101 is reset by issuing the “chip address resetting” command again with a new value other than “0xFF” as the value of the new chip address 2200. At this time, since the memory 100 has already been reset to a new chip address, it does not respond to the current command, and the value of the chip address setting register 16 of the memory 100 does not change.
[0039]
In the same manner, the chip address up to the memory 109 can be set by issuing a “chip address reset” command sequentially with the new chip address 2200 value as a new value.
[0040]
Here, while the “chip address reset” command is issued to the memories from the memory 100 to the memory 109, the new address 2200 returns “0xFF” to the DI input of the controller 2. On the other hand, if the “chip address reset” command is issued more than the number of memories from memory 100 to memory 109, the number of times the “chip address reset” command is issued exceeds the number of memories. The value returned to the DI input of the controller 2 is not "0xFF", but the value to be reset is returned. By counting the number of issued times using this, the number of memories including the memory 100 and the memory 109 from the memory 100 to the memory 109 can be known.
[0041]
Thereafter, the memory 110 to the memory 119, the memory 120 to the memory 129,..., And the memory 150 to the memory 159 are similarly set.
[0042]
In this way, by increasing the number of terminals connected to the memory of the controller 2, it is possible to minimize the increase in the number of terminals that are connected to the memory of the controller 2. Below, the effect by this embodiment is demonstrated about the case where 16x16 = 256 memories are connected.
[0043]
Normally, the limit of about 16 memories that can be connected to one data bus is considered. Therefore, to connect 256 memories, 16 data buses are required. In such a case, the number of signal lines of the conventional memory controller requires 16 lines × 8 bits = 128 terminals. This would normally require 256 memory CEs.
[0044]
However, according to the connection method shown in FIG. 3 of the present embodiment, the memory controller can connect 16 memories to the DO output and 16 memories to the DI input. Here, the memory shown in FIG. 3 is arranged in a matrix state. Therefore, according to the present embodiment, only (8 + 8) + 16 = 32 terminals are required, with 8 + 8 = 16 terminals for the data bus and 16 terminals for the CE.
[0045]
Therefore, according to the connection method shown in FIG. 3 of the present embodiment, the number of terminals required for the memory controller can be reduced to a much smaller number than in the case of the prior art even if the CE terminals are included. It has a great effect.
[0046]
Further, when used together with the CE 700, the signal output from the memory while the CE 700 is in the negated state can be set to “Hi-z”, the current consumed by the output can be suppressed, and the power consumption of the entire memory can be suppressed.
[0047]
In the above description, the setting of the chip address of the memory has been described. Next, the setting of the chip address by another method will be described.
[0048]
Although omitted in FIGS. 1, 3, and 6, when the memory is initialized after the power is turned on, the reset signal output to the memory is asserted. The reset signal and the level of CMDO output from the controller 2 are asserted. The chip address is set in combination.
[0049]
That is, when the reset signal is asserted and the CMDO signal is negated, the memory is initialized, and when the reset signal is asserted and the CMDO signal is asserted, the memory chip address setting mode is set. Hereinafter, a description will be given with reference to FIG. 7, the reset is output from the controller 2 in FIG. 3 or the microprocessor 3 in FIG. 2 to the memories 100, 101,. However, since the number of memories increases, the same wiring method as the CMDO output from the controller 2 in FIG. 3 is used.
[0050]
In FIG. 7, first, each memory is initialized by asserting a reset signal, and the values of the chip address setting registers 16 of all the memories are set to “0xFF”.
[0051]
Next, the reset signal is asserted, CMDO is asserted to enter the chip address setting mode, and CE0 is asserted in order to set the chip addresses of the memories 100, 101,. As a result, the DO 201 of the memories 100, 101,..., 109 selects and outputs the value of the chip address setting register 16. In this state, the addresses set in the memories 100, 101,..., 109 are output from the DO output of the controller 2 in synchronization with the CKO output from the controller 2.
[0052]
As for the data output from the DO output of the controller 2 to the memory, first, a value other than “0xFF” (here “0x00”) initialized to the address setting register by resetting is output, and thereafter, as shown in FIG. The value obtained by subtracting one value from "0xFF" is output.
[0053]
The memory 100 fetches the DO output from the controller 2 into the chip address setting register 16 at the rising edge of CKO, and outputs the fetched data to the DO 201 of the memory 100 via the SEL 17 at the falling edge of CKO. Similarly, the data is shifted from the memories 101, 102,..., 109 and the controller 2 until the data input to the DI input of the controller 2 of the memory 109 DO output destination changes from “0xFF” to “0x00”. The clock is sequentially output from the data subtracted from the DO output by 1 and the CKO output.
[0054]
As a result, the value of the chip address setting register 16 for the memories 100 to 109 is set to “0xFF” in the memory 109, and a value obtained by subtracting one by one from the memory 109 to the memory 100 is set. And 256 memories can be physically connected, and if 256 are connected, the values of the chip address setting register 16 of the memories 100, 101, 102 in FIG. 7 are "0x00", "0x01" , "0x02" is set.
[0055]
Thereafter, CE0 is negated, and the setting of the chip address setting register 16 in the memories 100 to 109 is completed. Similarly, the chip address setting register 16 is set for the memories 110 to 119, the memories 120 to 129,. Thereafter, the chip address of each memory is reset to a desired value using the chip address setting command.
[0056]
Next, a memory 100c that can handle a bidirectional data bus in the memory of FIG. 6 will be described with reference to FIGS. It is assumed that all the memories shown in FIG. 9 have the configuration shown in FIG.
[0057]
8 includes an OE input 800, a WE input 900, an SI input 600, an SO output 601, an IN input 500, an OUT output 501, and a SEL19 as compared to FIG. A bidirectional data bus can be handled.
[0058]
OE input 800 and WE input 900 are used for input / output control of DI 200 and DO 201, and the data bus connected to D of controller 2 is connected to DI of memories 100, 110, 120,. , Distributed from the DO of each memory 100, 110, 120, 150.
[0059]
That is, the memories 100, 110, 120, 150 have the function of a bus buffer in addition to the function as a memory, and the data bus distributed from the DO of the memory 100 includes the memories 101, 102, 103, .., 109 connected to the DI of the memory 110 and distributed from the DO of the memory 110 to the DI of the memories 111, 112, 113,. Are connected to the DIs of the memories 151, 152, 153,.
[0060]
The control signals CE, OE, WE, CKO, and CMDO output from the controller 2 are distributed using IN and OUT of each memory as shown in FIG.
[0061]
When SI500 and SO501 in FIG. 8 use a bi-directional data bus as shown in FIG. 9, the input data bus and the output data bus are not separated. The "Set" command is not available. Therefore, in this example, as shown in FIG. 9, the SO output of the controller 2 is connected to the SI input of the memory 100, and the SI input of the memory 101 sequentially from the SO output of the memory 100. The chip address setting register after initialization of the memory at power-on, etc. by connecting to the SI input of 2 and having a mode in which the chip address setting register 16 from the memory 100 to the memory 159 is configured as one shift register Used for setting.
[0062]
According to such a configuration, the entire chip address setting registers of all memories can be substantially functioned as one shift register.
[0063]
As described above, by incorporating a buffer such as a bus buffer for distributing the data bus and an independent buffer used for distributing the control signal as shown in FIGS. In addition, a buffer IC for the control signal is not required, and the number of signal lines connected to the controller 2 can be minimized. Therefore, when the controller 2 or the control unit 4 is made into an IC, since the number of terminals connected to the memory can be reduced, the IC package can be reduced, which is advantageous for high-density mounting.
[0064]
FIG. 10 shows an example of a detailed configuration of the comparator 15 in the memory 100 in FIGS. 1, 6, and 8.
[0065]
As shown in FIG. 10, the comparator 15 compares the values of corresponding bits in the chip address register 14 and the chip address setting register 16 with ENOR31, and when all the bits match, that is, the output of ENOR31 is It is detected by ANDing with the AND 32 that all have become “Hi” level, the chip address coincidence output 25 is asserted and transmitted to the command control unit 12.
[0066]
The address group setting register 18 and the OR-AND 33 are functions that work effectively in the memories 109, 119, 129, 159, and 159 in FIG. 3 and the memories 100, 110, 120,. Even if CE0 and CE1, CE2,..., CEn, etc. output from the controller 2 at the same time are asserted at the same time, if the command issued by the controller 2 is a command for the memory 101, the memory 109 stores the memory 100. Is used for recognizing that the command is issued to the memory 109, and the DO output from the memory 109 is validated.
[0067]
As an example, for the values set in the chip address setting register 16 of the memory 100 from the memory 100 in FIG. 3, the memory 100 is “0x00”, the memory 101 is “0x01”, the memory 102 is “0x02”, and the memory 109 is “ The value of the chip address setting register 16 of each memory in FIG. 3 is “0x07”, the memory 110 is “0x08”, the memory 111 is “0x09”, the memory 112 is “0x0A”, and the memory 119 is “0x0F”. The values of the bits of the chip address setting register 16 of the memories connected in a column are set so as to be common values. In the above case, for example, for memory 100 to memory 109, 3 bits from bit 0 to bit 2 are set to different values, and 5 bits from bit 3 to bit 7 are set to a common value.
[0068]
Here, it is assumed that the memory 100 is set to the memory 119 as described above, and CE0 and CE1 are asserted simultaneously. In such a case, the address group setting register 18 in FIG. 10 sets the address group setting of the memories 100 to 119 by issuing a command to set “0x07” from the controller 2 for the memories 100 to 119 in FIG. Set register 18 to "0x07".
[0069]
In this state, when a “Read” command for reading the memory contents from the controller 2 to the memory 102 is issued, the chip address 2000 of the “Read” command to be issued becomes “0x02” and is taken into the chip address register 14 of each memory. It is. In FIG. 10, the output 25 of the comparator 15 is "Hi" level and is asserted only in the memory 102, and the output 34 of the comparator 15 is "Hi" level only from the memory 100 to the memory 109 in FIG. It becomes.
[0070]
In addition, the command control unit 12 of the memory 109 performs control so that signal output permission is given to each output of the DO 201, the CKO 301, and the CMDO 501. In addition, since the output 34 of the comparator 15 of the memory 119 is not asserted in the memory 119, the command control unit 12 of the memory 119 controls the output to “Hi-z” with respect to DO201, CKO301, and CMDO501. Simultaneous output with the output of the memory 109 can be avoided.
[0071]
In the above example, the values of the chip address setting register 16 are set in ascending order of “0x00”, “0x01”, “0x02”, and so on from the memory 100, but they may be set in descending order.
[0072]
Also, as shown below, "0x00" in memory 100, "0x10" in memory 101, "0x20" in memory 102, "0x70" in memory 109, "0x80" in memory 110, "0x90" in memory 111, memory It is possible to set "0xA0" to 112, "0xF0" to memory 119, "0x01", etc. to memory 120. In this case, set the value of address group setting register 18 of each memory to "0x70" By doing so, the same operation as described above can be performed.
[0073]
Also in FIG. 9, the address group setting register 18 is used for output control to the data bus of the memory connected to the controller 2.
[0074]
In FIG. 9, the memory 100 is “0x00”, the memory 101 is “0x01”, the memory 102 is “0x02”, the memory 109 is “0x07”, the memory 110 is “0x08” Memory 111 is "0x09", Memory 112 is "0x0A", Memory 119 is "0x0F", Memory 150 is "0xF8", Memory 151 is "0xF9", Memory 152 is "0xFA", Memory 159 is “0xFF”, the chip address of the memory is set in the chip address setting register 16 of each memory, and “0x07” is set in the address group setting register 18 of each memory.
[0075]
As an example, a case where data is written from the controller 2 to the memory 102 will be described with reference to FIG. FIG. 11 is an example of input / output timings in each memory for a command issued from the controller 2 when connected as shown in FIG. In the example shown in FIG. 11, a chip address 2000, a command 2100, and a data address 2300 issued from the controller 2 are input to the DI 200 of the memory together with the WE 900. The chip address 2000 is stored in the chip address register 14 of the memory, the command 2100 is stored in the command register 16, and the memory 102 performs write transfer of the data 2200 and stores it in the memory unit 11 of the memory 102.
[0076]
Further, when the controller 2 reads the data in the memory 102, as shown in FIG. 11, in order to read the data from the memory 102, the WE900 is not asserted at the place where the data 2200 is read, but the OE800 is asserted. The memory 102 outputs data 2200. Further, the memory 100 has the output 34 from the comparator 15 asserted by the group address setting register 18 of FIG. 10, and the memory 100 is data 2201 from the memory 102 which is one of the memories connected to the DO 201 of the memory 100. Is output to the controller 2.
[0077]
Here, in the memories 110, 150, which distribute data other than the memory 100, the output 34 of the comparator 15 built in each memory is not asserted, so the data for the controller 2 is in the “Hi-z” state.
[0078]
As described above, the group address setting register 18 can execute the data read process without causing the output of the data of each memory to the controller 2 to collide with each other.
[0079]
Also in FIG. 9, by dividing the CE into each bus group as shown in FIG. 3, it is possible to reduce the number of active memories when a plurality of memories are connected, and the SI 600 and SO 601 are shown in FIG. By connecting like DI and DO, the number of memories connected to each bus group can be counted individually.
[0080]
In FIG. 3, the memories 109, 119, 129, and 159 are distinguished from other memories, and the memories 100, 110, and 150 in FIG. By providing one or a plurality of inputs for distinguishing operation functions and distinguishing them by combinations of input levels, one memory can have a plurality of functions or operation modes.
[0081]
In the following, an implementation example that enables setting by a method different from the shift register structure used as the chip address address setting method after initialization of the chip address setting register 16 in FIG. 8 will be described with reference to FIG. To do.
[0082]
In the example of FIG. 8, SI600 and SO601 used for directly setting the value of the chip address setting register 16 after the initialization of the memory 100c are not connected to the chip address setting register 16, and the command control unit 12 SI600 is used as a setting permission signal for the chip address setting register 16, and SO601 is used as an output indicating that the chip address setting register 16 after initialization of the memory 100 is set by the controller 2.
[0083]
On the other hand, the connection of the memory in FIG. 12 can be configured as shown in FIG. 9 described with reference to the memory in FIG. 8. In FIG. A chip address setting signal of the register 16 is output, and a signal notifying that the setting of the chip addresses of all the memories in FIG. 9 is completed is input to the SI input of the controller 2.
[0084]
A setting example of the chip address setting register 16 of each memory in FIGS. 9 and 12 will be described with reference to FIG. In this example, the setting mode of the chip address setting register 16 after initialization by memory reset is set using a clock and data synchronized with the clock.
[0085]
In FIG. 13, the control unit of all memories is initialized by asserting reset, and then CMDO is asserted by the controller 2 to set the setting mode of the chip address setting register 16. After asserting CEO and SO, the controller 2 outputs the value set in the chip address setting register 16 from DO in synchronization with CKO.
[0086]
In FIG. 12, in the setting mode of the chip address setting register 16, when the CE 100 and SI 600 inputs of the memory 100 are asserted and the SO output of the memory 100 is negated, the memory 100 receives the CKI input of the memory 100. At the falling edge, the value input to DI of the memory 100 is taken into the chip address setting register 16.
[0087]
In FIG. 9, after entering the setting mode of the chip address setting register 16 after reset, the CE800 and SI600 inputs of the memory 100 are asserted and the SO output of the memory 100 is negated at the first falling CKO of the controller 2. Therefore, the DO data “0x00” of the controller 2 is taken into the chip address setting register 16 of the memory 100.
[0088]
After fetching, the memory 100 asserts the SO output or outputs the value of the SI input of the memory 100. At the first falling edge of CKO of the controller 2, since the SI input after the memory 101 is negated after the memory 101, the chip address setting register 16 after the memory 101 is not fetched.
[0089]
Next, at the second falling edge of CKO of the controller 2, the memory 100 is not fetched into the chip address setting register 16 because the SO output is asserted, and the SI 600 of the memory 101 is asserted and the SO output is negated. Fetches data “0x01” from the DO of the controller 2 into the chip address setting register 16.
[0090]
Thereafter, similarly, the data from the DO of the controller 2 is sequentially fetched from the memory 103 to the chip address setting register 16 of each memory, and is fetched into the last memory 159 of FIG. The value of the SI input of 159 is output, and the controller 2 is informed that the setting of the chip address setting register 16 of all the memories in FIG.
[0091]
The controller 2 can know the number of memories shown in FIG. 9 by counting the number of data set in the chip address setting register 16 for each memory output until the SI input of the controller 2 is asserted.
[0092]
FIG. 14 is a timing chart showing an operation example of a setting example of the chip address setting register 16 of the memory in the connection configuration of FIG. 12 and the memory of FIG.
[0093]
In this example, the chip address setting register 16 of each memory in FIG. 9 is initialized to “0xFF” by resetting the memory after power-on or the initialization command of the chip address setting register 16, and the SO601 output of each memory is output. Negate. Here, each memory in FIG. 9 does not accept commands from the controller 2 even if the chip addresses match unless the SI600 input and CE700 input of each memory are asserted.
[0094]
After asserting the SO output of the controller 2, the controller 2 first outputs a chip address 2000 “0xFF”, a chip address reset command 2100 and a new chip address 2200 (here “0x00”) from the DO of the controller 2. The chip address reset command is issued to the memory with the chip address “0xFF”.
[0095]
Here, in FIG. 9, the chip address setting register 16 of each memory is initialized to “0xFF”, and the SO output is negated by initialization. Therefore, the chip address reset command issued first by the controller 2 after initialization. Memory 100 is the only memory that accepts issuance.
[0096]
The value of the chip address setting register 16 of the memory 100 is set to “0x00”, and the SO601 output of the memory 100 is asserted or the value input to the SI 600 of the memory 100 is output. Here, as an example, the value set in the memory 100 is “0x00”, but in practice, a value other than the value initialized by reset is set in the chip address setting register 16.
[0097]
Next, a chip address 2001, a chip address reset command 2101 and a new chip address 2201 are output from the DO output of the controller 2 as the second chip address reset command. By the way, at this time, the value of the chip address setting register 16 of the memory 100 is already set to a value other than “0xFF”. Therefore, the memory 100 does not accept the command, the memory 101 accepts the second chip address reset command, sets the new chip address in the chip address setting register 16, and asserts the SO601 output of the memory 101 after setting the new chip address. Or, the value input to SI600 is output.
[0098]
Thereafter, similarly, the chip address setting register 16 of each memory is sequentially set, and after setting the chip address setting register 16 of the last memory 159, the memory 159 asserts SO601 or outputs the value input to SI600, Informs the controller 2 that the chip address has been completed.
[0099]
Since the number of bits of the chip address setting register 16 is 8 bits here, if the memory 159 is the 256th memory, the value set in the chip address setting register 16 is “0xFF”.
[0100]
According to this processing example, as in the case of FIG. 13, the controller 2 can know the number of memories by a method such as counting the number of times the command has been issued.
[0101]
In FIG. 9, for example, when the functions of the memory 100 and the memory 101 are realized by the same memory, the operation function setting terminal is provided as described above. Here, the level of the operation function setting terminal is read for each memory. By having a command, the controller 2 can grasp the function of each memory, and if a certain rule determines which memory the SO signal of the controller 2 returns to the SI of the controller 2 through, Even if the number of mounted memories is different for each semiconductor memory system, it is possible to estimate which bus group each memory belongs to.
[0102]
Therefore, the number of memories connected to each bus group can be grasped, and the values of the chip address setting register 16 and the address group setting register 18 of each memory can be set to optimum values.
[0103]
In the memory connection in FIG. 3, a configuration example in which an OC terminal is added as a data output control terminal to each memory will be described with reference to FIG.
[0104]
In this example, each OC terminal of each memory connected in a column is connected as shown in FIG. The OC terminals of the memories 109 and 119 function as inputs, and the OC terminals other than the memories 109 and 119 function as output terminals. This function switching uses the input for distinguishing the memory functions described above.
[0105]
In FIG. 15, the memory OC terminals other than the memories 109 and 119 functioning as outputs are wired-connected for each bus group, and are input to the OC terminals of the memory 109 and the memory 119 as data output control signals 1001 and 1101, respectively. The Here, the OC terminal functioning as an output outputs a signal as an open drain or 3-state output for wired connection, and pull-up resistors 1002 and 1102 are connected to the data output control signals 1001 and 1101.
[0106]
When the controller 2 reads data from the memory 101, the memory 101 outputs data corresponding to the issued read command from the DO in response to the read command issued from the controller 2, and also outputs a data output control signal from the OC terminal. Is asserted. At this time, the OC output of memories other than the memory 101 is “Hi-Z”.
[0107]
In response to the assertion of the data output control signal input to the OC terminal, the memory 109 outputs the data input to the DI of the memory 109 to DO.
[0108]
FIG. 15 shows another configuration example in which an OC terminal is added as a data output control terminal to each memory in the memory connection in FIG. 9 in the same manner as described above.
[0109]
In this configuration example, each OC terminal of each memory connected in a column is connected as shown in FIG. 16, and the OC terminal of the memory 100 functions as an input, and the OC terminals of the memory 101 to the memory 109 function as an output. As described above, the switching of the function of the OC terminal uses the input for distinguishing the function of the memory described above.
[0110]
The operation in this configuration example is the same as that described in FIG. 15, and the memories 109 and 119 in FIG. 15 correspond to the memory 100 in FIG.
[0111]
By providing the data output control terminal as described above, the memory does not require the address group setting register 18 of FIG. For this reason, the circuit scale of the comparator 15 is reduced, and the value set in the chip address setting register 14 of each memory can be set freely.
[0112]
【The invention's effect】
As described above, according to the present invention, it is not necessary to add a buffer IC for data and control signals by incorporating a buffer for data and control signals in the memory. Therefore, only the area occupied by the buffer IC is eliminated. The memory can be increased, which is advantageous for increasing the capacity of the memory file system.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an internal configuration of a memory according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a block configuration of a system to which the present invention is applied.
FIG. 3 is a block diagram showing an example of a method for connecting a memory and a controller.
FIG. 4 is a timing chart of commands issued by a controller.
FIG. 5 is a timing chart of commands issued by the controller.
FIG. 6 is a block diagram showing an internal configuration of a memory according to another embodiment of the present invention.
FIG. 7 is a timing chart when a memory chip address is set.
FIG. 8 is a block diagram showing an internal configuration of a memory according to another embodiment of the present invention.
FIG. 9 is a block diagram showing another example of a method for connecting a memory and a controller.
FIG. 10 is a block diagram showing an internal configuration of a comparator.
FIG. 11 is a timing chart at the time of data read / write.
FIG. 12 is a block diagram showing an internal configuration of a memory according to another embodiment of the present invention.
FIG. 13 is a timing chart at the time of setting a memory chip address;
FIG. 14 is a timing chart when a memory chip address is set.
FIG. 15 is a block diagram illustrating an example of a memory connection method.
FIG. 16 is a block diagram illustrating another example of a memory connection method.
[Explanation of symbols]
2 ... Controller, 3 ... Microprocessor, 4 ... Control part, 10 ... Memory, 11 ... Memory part, 12 ... Command control part, 13 ... Command register, 14 ... Chip address register, 15 ... Comparator, 16 ... Chip address setting Register, 17 ... selector.

Claims (17)

In a semiconductor memory file system having a controller including a microprocessor and a control device that performs an operation according to a command issued from a host, and a first semiconductor memory connected to the controller,
In addition to the first semiconductor memory, further comprising a plurality of semiconductor memories,
The first semiconductor memory includes a buffer for at least one of command and data ,
The controller outputs a data signal line for outputting at least one of a command and data to the first semiconductor memory and a clock output used for synchronization of the data signal line to the first semiconductor memory having the buffer incorporated therein. connection,
The first semiconductor memory transmits at least one of the command and data buffered by the built-in buffer and the synchronization clock to a data signal line to a first semiconductor memory of the plurality of semiconductor memories, and Output as clock output,
Outputting at least one of a command and data input to the first semiconductor memory and a synchronization clock as a data signal line and a clock output to a second semiconductor memory of the plurality of semiconductor memories; At least one of the command and data input to the second semiconductor memory and a synchronization clock are output as a data signal line and a clock output to the third semiconductor memory, and so on. By outputting at least one of the command and data input to the semiconductor memory and the data signal line and clock output to the mth semiconductor memory, the first semiconductor memory and the plurality of semiconductor memories are arranged in a column. connection,
Data signal from the mth semiconductor memory connected at the end of the column connection
A line and a synchronization clock are connected to the data input and clock input of the controller;
In addition, a series of n semiconductor memory groups in which the semiconductor memories are connected in a column (hereinafter referred to as one column of semiconductor memory groups) are arranged in parallel.
The data signal line and clock output output from the controller are respectively connected to a first semiconductor memory of the semiconductor memory group of each column,
The data signal line and the clock output of the last semiconductor memory of the semiconductor memory group of each column are respectively wired- connected to the corresponding signals and connected to the data input and clock input of the controller,
Each of the semiconductor memories included in the plurality of arranged semiconductor memory groups in each column further includes a memory selection signal input,
The buffer output corresponding to the data and control signal input of the semiconductor memory has each output in a “Hi-z” state when the memory selection signal input is in a negated state, and when the memory selection signal input is in an asserted state. Outputs a valid value,
The memory selection signal input of the semiconductor memory in each column is connected to a common memory selection signal output corresponding to each column output from the controller.
A semiconductor memory file system. The semiconductor memory file system according to claim 1 ,
The data output from the controller includes at least one of a memory address for specifying each semiconductor memory, a command for instructing the operation to the corresponding semiconductor memory, and an address and data for specifying the address of the data in the corresponding semiconductor memory. Using an instruction format consisting of
Each of the semiconductor memories includes a memory unit that stores data, a command register that captures the command, a command control unit that controls an operation according to the contents of the command register, a memory address register that captures the memory address, A memory address setting register for storing a unique address of the semiconductor memory, and a comparator for comparing values of the memory address register and the memory address setting register,
The semiconductor memory file system, wherein the command control unit performs an operation according to a command only when a comparison result of the comparator matches. The semiconductor memory file system according to claim 2 .
The semiconductor memory file system operates when a predetermined specific command is issued from the controller, regardless of whether the comparison result of the memory address matches. The semiconductor memory file system according to claim 2 or 3 ,
The value of the memory address setting register of the semiconductor memory is initialized to all 1 bits by initialization at power-on, and a predetermined specific command issued from the controller (hereinafter referred to as a memory address reset command) The value of the memory address setting register can be reset by
Semiconductor memory reconfiguration Ru performed of the memory address setting register, data corresponding to the memory address setting value to be set again in the register included in the memory address resetting command, resetting the memory address setting register The semiconductor memory file system is characterized in that it is changed to a value before being output and output to a subsequent semiconductor memory. The semiconductor memory file system according to claim 1 ,
The memory address setting register of each semiconductor memory of the semiconductor memory group of the same column is set so that the value of a plurality of bits is common among the bits and the value of the common bit is different for each column. ,
Even if the memory selection signals to be output to the semiconductor memories in each column are asserted at the same time, as long as the memory address of the command issued from the controller does not match the common bit of each column, the last semiconductor memory in each column is the controller Only when the data signal and clock to be output to are not valid output and remain "Hi-z", and the memory address of the command matches the common bit of each column, the last semiconductor memory of each column is the controller Enable the data signal and clock to be output to
A semiconductor memory file system comprising: an input for distinguishing that the last semiconductor memory of each column is the last semiconductor memory of the column. The semiconductor memory file system according to any one of claims 1 to 5 , further comprising a memory address setting signal input for setting an address of the memory address setting register of the semiconductor memory,
When the memory address setting input is asserted, the value of the address setting register is sequentially output from the data output of the semiconductor memory to the next-stage semiconductor memory, and the memory address setting register of the semiconductor memory as a whole A semiconductor memory file system which functions as a shift register and sets a set value of a memory address from the controller while shifting in synchronization with a clock. In a semiconductor memory file system having a controller including a microprocessor and a control device that performs an operation according to a command issued from a host, and a first semiconductor memory connected to the controller,
In addition to the first semiconductor memory, further comprising a plurality of semiconductor memories,
The semiconductor memory further includes a bus buffer that distributes a data bus, and an independent buffer that is not affected by a control signal input to the semiconductor memory,
A plurality of first semiconductor memories connected to the data bus connected from the controller;
Each of the plurality of first semiconductor memories distributes the data bus, and a plurality of semiconductor memories that do not distribute the data bus are connected to each of the distributed data buses. Including a semiconductor memory group,
The semiconductor memory file system, wherein the control signal is buffered and distributed by an independent buffer included in a semiconductor memory of the semiconductor memory group. The semiconductor memory file system according to claim 7 .
The data output from the controller includes at least one of a memory address that specifies each semiconductor memory, a command that instructs the semiconductor memory to operate, and an address and data that specify an address of data in the semiconductor memory. Use an instruction format consisting of one side,
The semiconductor memory includes a memory unit for storing and holding data, a command register for capturing the command, a command control unit for controlling an operation according to the contents of the command register, a memory address register for capturing the memory address, A memory address setting register for storing a unique address of the semiconductor memory, and a comparator for comparing the values of the memory address register and the memory address setting register,
The semiconductor memory file system, wherein the command control unit performs an operation according to a command only when a comparison result of the comparator matches. The semiconductor memory file system according to claim 8 .
The semiconductor memory file system is characterized in that when a predetermined specific command is issued from the controller, the semiconductor memory operates regardless of a match of the comparison result of the memory address. The semiconductor memory file system according to claim 8 or 9 ,
A memory address setting signal input for setting a value of the memory address setting register of the semiconductor memory, a serial data input, and a serial data output;
When the memory address setting input is asserted, the serial data output from the controller is connected to the serial input of the address setting register of the semiconductor memory via the serial input of the semiconductor memory, and the address setting The serial output of the register is output from the serial data output of the semiconductor memory to the serial input of the next stage semiconductor memory,
Similarly, the series of semiconductor memories are connected in columns,
The serial output of the last semiconductor memory in the column is connected to the serial input of the controller,
The memory address setting value from the controller is shifted and set so that the memory address setting register of each semiconductor memory functions as one shift register as a whole in synchronization with the clock,
The semiconductor memory file system characterized in that the controller can count the number of a series of semiconductor memories connected in the column. The semiconductor memory file system according to claim 8 or 9 ,
The semiconductor memory includes a memory address setting signal input for setting a value of the memory address setting register of the semiconductor memory, and a memory address setting completion signal output indicating that the value of the memory address setting register is set,
The memory address setting signal from the controller is connected to the memory address setting signal input of the first semiconductor memory, and the memory address setting completion signal output of the first semiconductor memory is connected to the memory address setting signal input of the second semiconductor memory. The memory address setting completion signal output of the second semiconductor memory is connected to the memory address setting signal input of the third semiconductor memory, and the same signal is connected thereafter, and the memory of the last semiconductor memory in a series of semiconductor memory groups Connect the address setting completion signal output to the memory address setting completion input of the controller,
The semiconductor memory negates the memory address setting completion signal output after initialization of the register in the semiconductor memory,
The semiconductor memory is synchronized with the clock output from the controller only when the memory address setting signal input is asserted, the memory address setting completion signal output is negated, and the memory selection signal input is asserted. After the memory address setting register data output from the controller to the data bus is taken into the memory address setting register, the memory address setting completion signal output is asserted or the memory address setting signal input level is output. A semiconductor memory file system, wherein a memory address is set in a memory address setting register of a series of semiconductor memory groups. The semiconductor memory file system according to claim 11 .
The value of the memory address setting register after initialization of the semiconductor memory is set using a memory address reset command issued from the controller, and can be set in the memory address setting register of the semiconductor memory. A semiconductor memory having a memory address at which a memory address setting signal input is asserted and specified by the memory address reset command,
Memory address setting signal input for setting the value of the memory address setting register of the semiconductor memory after setting of the memory address setting register of the semiconductor memory, and completion of memory address setting indicating that the value of the memory address setting register is set With signal output,
The memory address setting signal from the controller is connected to the memory address setting signal input of the first semiconductor memory, and the memory address setting completion signal output of the first semiconductor memory is connected to the memory address setting signal input of the second semiconductor memory. Then, the memory address setting completion signal output of the second semiconductor memory is connected to the memory address setting signal input of the third semiconductor memory, and the same signal is connected thereafter, so that the last semiconductor memory of a series of semiconductor memory groups Connecting the memory address setting completion signal output to the memory address setting completion input of the controller,
The semiconductor memory negates the memory address setting completion signal output after initialization of the register in the semiconductor memory,
The semiconductor memory uses a clock output from the controller only when the memory address setting signal input is asserted and the memory address setting completion signal output is negated and the memory selection signal input is asserted for the semiconductor memory. Synchronously, the memory address setting register data output from the controller to the data bus is taken into the memory address setting register, and then the memory address setting completion signal output is asserted or the level of the memory address setting signal input is output. Thus, a memory address is set in a memory address setting register of the series of semiconductor memory groups. The semiconductor memory file system according to claim 1 ,
A data output control input and a data output control output are provided to each of the semiconductor memories connected in series from the controller,
The data output control terminal input of the last semiconductor memory of the semiconductor memories connected in the column receives a data output control signal output from the data output control output of another semiconductor memory,
When the data output control signal is asserted, it has a function of outputting data and a clock input inputted to the last semiconductor memory of the semiconductor memories connected in the column to the controller,
The data output control output of the other semiconductor memory among the semiconductor memories connected in the column is issued from the controller when the controller reads data from the semiconductor memory or the state of the semiconductor memory as data. A semiconductor memory file having a function of asserting the data output control signal from the data output control output when the semiconductor memory designated corresponding to the Read command outputs data corresponding to the issued command system. The semiconductor memory file system according to any one of claims 7 to 12 ,
The semiconductor memory is provided with a data output control input and a data output control output,
A semiconductor memory that distributes a data bus connected to the controller in the series of semiconductor memory groups to the other semiconductor memories in the semiconductor memory group is controlled by the data output control input of the semiconductor memory. Receiving a data output control signal from, and when the data output control signal is asserted, has a function of outputting data from the semiconductor memory that has asserted the data output control signal to the controller,
The data output control output of the other semiconductor memory is a semiconductor specified in response to a Read command issued from the controller when the controller reads data from the semiconductor memory or the state of the semiconductor memory as data. A semiconductor memory file system having a function of asserting the data output control signal from the data output control output when the memory outputs data corresponding to the issued command. In a semiconductor memory file system having a controller including a microprocessor and a control device that performs an operation according to a command issued from a host, and a first semiconductor memory connected to the controller,
A plurality of semiconductor memories in addition to the first semiconductor memory;
The first semiconductor memory includes a buffer for at least one of command and data ,
The controller outputs a data signal line for outputting at least one of a command and data to the first semiconductor memory and a clock output used for synchronization of the data signal line to the first semiconductor memory having the buffer incorporated therein. connection,
The first semiconductor memory transmits at least one of the command and data buffered by the built-in buffer and the synchronization clock to a data signal line to a first semiconductor memory of the plurality of semiconductor memories, and Output as clock output,
Outputting at least one of a command and data input to the first semiconductor memory and a synchronization clock as a data signal line and a clock output to a second semiconductor memory of the plurality of semiconductor memories; At least one of the command and data input to the second semiconductor memory and a synchronization clock are output as a data signal line and a clock output to the third semiconductor memory, and so on. By outputting at least one of the command and data input to the semiconductor memory and the data signal line and clock output to the mth semiconductor memory, the first semiconductor memory and the plurality of semiconductor memories are arranged in a column. connection,
Data signal from the mth semiconductor memory connected at the end of the column connection
A line and a synchronization clock are connected to the data input and clock input of the controller;
The data output from the controller includes a memory address for specifying a semiconductor memory in the semiconductor group including the first semiconductor and the plurality of semiconductors, a command for instructing the semiconductor memory to operate, and the semiconductor Use an instruction format consisting of at least one of address and data that identifies the address of the data in the memory,
Each semiconductor memory in the semiconductor group includes a memory unit that stores and holds data, a command register that captures the command, a command control unit that controls operations according to the contents of the command register, and a memory that captures the memory address An address register, a memory address setting register for storing a unique address of the semiconductor memory, and a comparator for comparing values of the memory address register and the memory address setting register,
The command control unit performs an operation according to the command only when the comparison result of the comparator matches,
In addition, a series of n semiconductor memory groups in which the semiconductor memories are connected in a column (hereinafter referred to as one column of semiconductor memory groups) are arranged in parallel.
The data signal line and clock output output from the controller are respectively connected to a first semiconductor memory of the semiconductor memory group of each column,
The data signal line and the clock output of the last semiconductor memory of the semiconductor memory group of each column are respectively wired- connected to the corresponding signals and connected to the data input and clock input of the controller,
Each of the semiconductor memories included in the plurality of arranged semiconductor memory groups in each column further includes a memory selection signal input,
The buffer output corresponding to the data and control signal input of the semiconductor memory has each output in a “Hi-z” state when the memory selection signal input is in a negated state, and when the memory selection signal input is in an asserted state. Outputs a valid value,
The memory selection signal input of the semiconductor memory in each column is connected to a common memory selection signal output corresponding to each column output from the controller.
A semiconductor memory file system. The semiconductor memory file system according to claim 15 , wherein
Each semiconductor memory in the semiconductor group operates regardless of the coincidence of the comparison result of the memory address when a predetermined specific command is issued from the controller. The semiconductor memory file system according to claim 15 or 16 ,
A memory address setting signal input for setting a value of the memory address setting register of the semiconductor memory, a serial data input, and a serial data output;
When the memory address setting input is asserted, the serial data output from the controller is connected to the serial input of the address setting register of the semiconductor memory via the serial input of the semiconductor memory, and the address setting The serial output of the register is output from the serial data output of the semiconductor memory to the serial input of the next stage semiconductor memory,
Similarly, the series of semiconductor memories are connected in columns,
The serial output of the last semiconductor memory in the column is connected to the serial input of the controller,
The memory address setting value from the controller is shifted and set so that the memory address setting register of each semiconductor memory functions as one shift register as a whole in synchronization with the clock,
The semiconductor memory file system characterized in that the controller can count the number of the semiconductor memories connected in the column.

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