GB2454809B - Cache memory system - Google Patents

Cache memory system

Info

Publication number
GB2454809B
GB2454809B GB0821079.1A GB0821079A GB2454809B GB 2454809 B GB2454809 B GB 2454809B GB 0821079 A GB0821079 A GB 0821079A GB 2454809 B GB2454809 B GB 2454809B
Authority
GB
United Kingdom
Prior art keywords
cache memory
memory system
cache
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0821079.1A
Other versions
GB2454809A (en
GB0821079D0 (en
Inventor
Andrew Michael Jones
Stuart Ryan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Research and Development Ltd
Original Assignee
STMicroelectronics Research and Development Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB0722707.7A external-priority patent/GB0722707D0/en
Application filed by STMicroelectronics Research and Development Ltd filed Critical STMicroelectronics Research and Development Ltd
Publication of GB0821079D0 publication Critical patent/GB0821079D0/en
Publication of GB2454809A publication Critical patent/GB2454809A/en
Application granted granted Critical
Publication of GB2454809B publication Critical patent/GB2454809B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB0821079.1A 2007-11-19 2008-11-18 Cache memory system Expired - Fee Related GB2454809B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0722707.7A GB0722707D0 (en) 2007-11-19 2007-11-19 Cache memory
US12/284,332 US9208096B2 (en) 2007-11-19 2008-09-19 Cache pre-fetching responsive to data availability

Publications (3)

Publication Number Publication Date
GB0821079D0 GB0821079D0 (en) 2008-12-24
GB2454809A GB2454809A (en) 2009-05-20
GB2454809B true GB2454809B (en) 2012-12-19

Family

ID=40194828

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0821079.1A Expired - Fee Related GB2454809B (en) 2007-11-19 2008-11-18 Cache memory system

Country Status (1)

Country Link
GB (1) GB2454809B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0722707D0 (en) 2007-11-19 2007-12-27 St Microelectronics Res & Dev Cache memory

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010011330A1 (en) * 1997-06-09 2001-08-02 John H. Hughes Dma driven processor cache
US20040148473A1 (en) * 2003-01-27 2004-07-29 Hughes William A. Method and apparatus for injecting write data into a cache
US20040199727A1 (en) * 2003-04-02 2004-10-07 Narad Charles E. Cache allocation
US20060075142A1 (en) * 2004-09-29 2006-04-06 Linden Cornett Storing packet headers
US20060085602A1 (en) * 2004-10-15 2006-04-20 Ramakrishna Huggahalli Method and apparatus for initiating CPU data prefetches by an external agent
US20060123195A1 (en) * 2004-12-06 2006-06-08 Intel Corporation Optionally pushing I/O data into a processor's cache

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010011330A1 (en) * 1997-06-09 2001-08-02 John H. Hughes Dma driven processor cache
US20040148473A1 (en) * 2003-01-27 2004-07-29 Hughes William A. Method and apparatus for injecting write data into a cache
US20040199727A1 (en) * 2003-04-02 2004-10-07 Narad Charles E. Cache allocation
US20060075142A1 (en) * 2004-09-29 2006-04-06 Linden Cornett Storing packet headers
US20060085602A1 (en) * 2004-10-15 2006-04-20 Ramakrishna Huggahalli Method and apparatus for initiating CPU data prefetches by an external agent
US20060123195A1 (en) * 2004-12-06 2006-06-08 Intel Corporation Optionally pushing I/O data into a processor's cache

Also Published As

Publication number Publication date
GB2454809A (en) 2009-05-20
GB0821079D0 (en) 2008-12-24

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20141118