Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/30604—Chemical etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/30604—Chemical etching
  • H01L21/30608—Anisotropic liquid etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/10—Measuring as part of the manufacturing process
  • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67017—Apparatus for fluid treatment
  • H01L21/67063—Apparatus for fluid treatment for etching
  • H01L21/67075—Apparatus for fluid treatment for etching for wet etching
  • H01L21/6708—Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67098—Apparatus for thermal treatment
  • H01L21/67115—Apparatus for thermal treatment mainly by radiation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention relates to a method and an apparatus for leveling a semiconductor wafer by means of an etching treatment with locally different material removal.
• a semiconductor wafer in particular a monocrystalline silicon wafer for use in the semiconductor industry, must have a high flatness, in particular in order to take into account the requirements for the manufacture of integrated circuits.
• a generally accepted rule of thumb is that the SFQR max value of a semiconductor wafer must not be greater than the line width of the components to be fabricated on the semiconductor wafer.
• the required flatness must also be ensured as close as possible to the edge of the front, the front being defined as the side on which the components are to be produced. This means that the flatness measurement has to be performed with very little edge exclusion and the specified flatness values must be fulfilled not only for the so-called fill sites but also for the partial sites. (Fill sites are all surface elements on which complete building elements can be manufactured. Partial sites are the surface elements on the edge of the window on which no complete building elements can fit.)
• the local evenness refers to a limited area on the wafer, which generally corresponds to the area of the device to be built thereon.
• SFQR site front surface referenced least squares / ranks
• SFQR ma * gives the highest SFQR value for all For SFQR, always indicate which area the declared value refers to, for example an area of 26 x 8 mm 2 according to the ITRS Roadmap.
• nanotopography This is defined as the peak-to-valley deviation in a given area element, eg. B. 2 x 2 mm 2 .
• Nanotopography is measured using gauges such as ADE CR 83 SQM, ADE PhaseShift Nanomapper or KLA Tencor SNT.
• edge roll off The flatness in the edge region of the semiconductor wafer is decisively influenced by the so-called "edge roll off".
• edge roll off The edge roll off can occur both on the front side and on the back side of the semiconductor wafer.
• An edge roll off is particularly troublesome in the case of semiconductor wafers, which, for example for the production of SOI wafers, are bonded (bonded) to a further semiconductor wafer because the edge roll off of the wafers to be joined together are large Influence on the quality of the bond on the edge of the window.
• semiconductor wafers serving as a substrate for the fabrication of microelectronic devices are typically fabricated according to the following conventional process sequence: sawing, lapping and / or grinding, wet chemical Etching, stock removal polishing and end polishing (English, mirror polishing). It has been shown that this process sequence is not able to guarantee the flatness required for the constantly decreasing line widths.
• EP961314A1 a similar method is given in which, after sawing, grinding, PACE and final polishing, GBIR values of at best 0.14 ⁇ m and SFQR max values of at most 0.07 ⁇ m are achieved.
• Hydrophobizing step can be reduced immediately before the PACE.
• PACE must be carried out in a vacuum, which makes the process technically complex.
• the semiconductor wafer is contaminated with the decomposition products of the gases used for the etching, which necessitates an additional purification step, as described in EP1100117A2.
• this process is not carried out over the entire surface, but by scanning the semiconductor wafer. On the one hand, this is very time-consuming and, on the other hand, leads to problems with regard to nanotopography in the overlapping region of the scanning as well as problems with regard to flatness (SFQRm a x and edge roll off) in the outer region of the semiconductor wafer up to a distance of approx Disc edge.
• One possible cause is the increased suction effect at the edge of the semiconductor wafer and thus reduction of the etching medium, since working in a vacuum. Due to the necessary overlap when scanning, in particular the nanotopography deteriorates at the overlapping positions. The larger the diameter of the nozzle with which the etching medium is supplied, the more pronounced the deterioration. However, for economic reasons, the nozzle diameter can not be chosen arbitrarily small.
• the methods known in the art are unable to meet the geometric requirements for devices having line widths equal to or less than 65 ⁇ m, ie SFQR max values of at most 65 ⁇ m.
• the most serious problems occur in the edge region of the semiconductor wafer, since the edge exclusion of currently 3 mm (with line widths of 90 nm) is reduced to 2 mm or 1 mm or less at the future line widths of 65 nm and the partial sites in the assessment of evenness.
• SOI disks These semiconductor wafers have a semiconductor layer which is located on a surface of a carrier wafer ("base wafer” or “handle wafer”).
• the thickness of the semiconductor layer varies depending on the components to be processed. In general, a distinction is made between so-called “thin layers” (less than 100 nm thick) and so-called “thick layers” (from 100 nm to about 80 ⁇ m).
• the carrier disk can either consist entirely of an electrically insulating material (for example glass, quartz, sapphire) or it can consist, for example, of a semiconductor material, preferably of silicon, and be separated from the semiconductor layer only by an electrically insulating layer.
• the electrically insulating layer may for example consist of silicon oxide.
• the semiconductor layer of an SOI disc must have a very homogeneous thickness to the outermost edge region. Especially For semiconductor layers having a thickness of 100 nm or less, the transistor characteristics, such as. As the threshold voltage, in the case of inhomogeneous layer thicknesses very strong. The absolute thickness tolerance for SOI disks with thin and thick semiconductor layers depends on the layer thickness.
• the prior art discloses processes for the post-treatment of an SOI wafer with the aim of improving the layer thickness homogeneity. These are generally local etching processes with scanning of the SOI disk, whereby a higher etching removal is provided at locations of higher layer thickness: According to US2004 / 0063329A1, the surface of the SOI disk is scanned with a nozzle in a dry etching process, via which a gaseous etching medium is supplied locally.
• EP488642A2 and EP511777A1 describe processes in which the semiconductor layer of the SOI wafer is exposed over its entire area to an etching medium. However, this etching medium must be activated locally by scanning the surface by means of a laser beam or a light beam of a light source focused with an optical system (photochemical etching).
• a layer thickness homogeneity of 10 nm is achieved without specification of an edge exclusion according to EP488642A2.
• a layer thickness homogeneity of 8 nm is achieved at a layer thickness of 108 nm without specifying an edge exclusion.
• the invention is therefore based on the object of providing a semiconductor wafer with improved flatness (in particular in the edge area) and nanotopography, which is suitable for the production of components with line widths of 65 nm or less.
• semiconductor wafer also encompasses an SOI wafer, a further object of which is to provide an SOI wafer with improved layer thickness homogeneity, in particular in the edge region.
• the object is achieved by a method for the treatment of a semiconductor wafer, comprising the following steps in the order given: a) location-dependent measurement of a parameter characterizing the semiconductor wafer in order to determine the location-dependent value of this parameter over an entire surface of the semiconductor wafer, b) application of an etching medium c) etching treatment of this entire surface of the semiconductor wafer by the action of the etching medium with simultaneous exposure of this entire surface, the removal rate of the etching treatment being dependent on the light intensity at the surface of the semiconductor wafer , and wherein the light intensity is determined location-dependent so that the differences in the location-dependent values of the parameter measured in step a) are reduced by the location-dependent removal rate, and d) removal of the etching medium from the surface of the semiconductor wafer.
• the invention relates to a method for etching a semiconductor wafer with an etching medium having a viscosity of 50 mPas to 2000 mPas.
• the surface of the semiconductor wafer in the case of an SOI wafer, the semiconductor layer
• the locally different etching removal required for the correction is achieved by a locally different removal rate and this in turn by a locally different light intensity.
• Distribution of light intensity is determined by the local values of the previously measured parameter.
• the parameter to be optimized in the method according to the invention is measured in step a).
• the resulting measured values are used in step c) to control the local light intensity.
• the localized light thickness is measured in step a) and the local light intensity is controlled in step c) so that a high removal rate is achieved at locations of large layer thickness and a low removal rate at locations of small layer thickness becomes.
• step a) the deviation of the wafer front side from an ideal plane defined by the wafer rear side is determined and in step c) the local light intensity is controlled such that a high removal rate occurs at local elevations and at locations local depressions a low removal rate is achieved.
• step a) the deviation of the wafer front side from an ideal plane related to a specific measurement window, for example the size 26 ⁇ 8 mm 2 , and in step c) the local light intensity are determined controlled that a high removal rate is achieved at local elevations and a low removal rate at locations of local wells.
• the necessary etching removal is determined for each point on the surface of the semiconductor wafer. From the light intensity dependent Abtragsrate that achieves the etching medium used in the respective semiconductor material, both the required duration of the etching treatment in step c) and for each point on the surface of the wafer calculate the required light intensity.
• the invention makes use of the dependence of the removal rates of certain etching reactions on the charge carrier concentration in the semiconductor material, which in turn can be influenced by the intensity of the incident light. This will be described concretely below using the example of silicon. However, the invention is also applicable to other semiconductor materials.
• the etching of silicon always consists of a two-stage reaction: In the first step, silicon is oxidized, in acid to silicon oxide (SiCb), in the alkaline to SiO 3 2 " In the second step, the removal of the silicon oxide by hydrogen fluoride (HF), in the alkaline, the Si ⁇ 3 2 " anion goes into solution. If an etching medium of suitable composition is selected, the etching reaction can be controlled such that the oxidation step becomes the rate-determining step. In acidic terms, this can be achieved, for example, by using hydrogen fluoride in excess in relation to the oxidizing agent.
• the present invention takes advantage of the fact that by irradiating light, the chemical potential and the concentration of the charge carriers in silicon or other semiconductor materials can be influenced.
• the rate of the oxidation reaction depends on the light intensity.
• the light intensity affects the etching rate.
• Light with a wavelength below 1100 nm is absorbed by silicon, resulting in pairs of charge carriers (electrons and holes).
• the absorption coefficient is strongly dependent on the wavelength of the light.
• Light with a wavelength near 1100 nm penetrates deeply into the silicon, silicon is transparent for light of even longer wavelengths.
• the method has the advantage that it works locally correcting to the edge of the semiconductor wafer, so that the required quality is achieved up to the wafer edge. In particular, it is possible the required flatness or
• Layer thickness at an edge exclusion of 2 mm or less and including the partial sites to achieve Since the method according to the invention does not require a vacuum, it is possible to avoid changes in the concentration of the etching medium at the edge of the semiconductor wafer, which are caused by the suction according to the prior art. If systematic inhomogeneities in the etching removal occur at certain positions of the semiconductor wafer, for example near the edge, these can be taken into account and compensated in the calculation of the location-dependent light intensity.
• the method is suitable both for removing inhomogeneities of the semiconductor layer of an SOI disk as
• the semiconductor wafers treated by means of the method according to the invention are also eminently suitable for bonding to a further semiconductor wafer, since the bond quality is particularly at the edge of the SFQR values and of the edge roll off is influenced.
• the big economic advantages lie in the higher usability of the disk surface for the production of components. This has a particularly strong effect on SOI discs due to the significantly higher production costs.
• no polishing is carried out in order not to worsen the flatness again.
• the method is at a by transmission of a
• the inventive method may in the case of a SOI disc with one or more thermal processes for
• FIG. 1 shows schematically the structure of a device which is suitable for carrying out the method according to the invention.
• FIG. 2 shows a radial thickness profile of the silicon layer of an SOI wafer produced according to the prior art.
• Fig. 3 shows the radial thickness profile of the silicon layer of the SOI wafer shown in Fig. 2 after being subjected to the process of the present invention.
• a device for treating a semiconductor wafer 7 is particularly suitable, comprising: a measuring device 11 for location-dependent measurement of a parameter characterizing the semiconductor wafer 7,
• a holding device 12 for the semiconductor wafer 7 rotatably mounted about its center axis
• controllable exposure device 1 which is arranged so that it can expose one side of the semiconductor wafer 7 located on the holding device 12 with a location-dependent light intensity
• control unit 10 for converting the values of the parameter determined by the measuring device 11 into instructions for controlling the exposure device 1 and relaying the instructions to the exposure device 1.
• the controllable exposure device 1 preferably comprises a light source 2 with a defined power and wavelength, an optic 4 which allows a full-area exposure 5 of the semiconductor wafer 7, and a device 3 for adjusting the local light intensity.
• the device further comprises a holding device 12, which receives the semiconductor wafer, for. B. by the Sucking in the semiconductor wafer with vacuum (so-called "vacuum chuck"), adjusting the position of the semiconductor wafer and covering the part of the semiconductor wafer which is not to be etched, for example the back side,
• the holding device is mounted rotatably about its central axis and connected to a drive
• the semiconductor wafer is placed concentrically on the fixture such that the semiconductor wafer also rotates about its central axis when the fixture is rotated.
• the system 9 for supplying and removing the etching medium comprises, for example, a nozzle via which the
• Semiconductor disk optionally in step b) the etching medium and in step d) a cleaning liquid can be supplied.
• the holding device 12 and the system 9 for supplying and removing the etching medium can be mounted in a closed etching chamber 6. This is preferred, for example, when the etching medium releases hazardous or corrosive gaseous constituents to the environment.
• the control unit 10 can control, in addition to the exposure device 1, further functions of the device, such as the loading and unloading of semiconductor wafers 7 by means of a robot, the application and removal of the etching medium by the system 9, the rotational speed of the semiconductor wafer holding device 12 or the parameters the etching treatment, such as temperature and duration of the etching treatment.
• Step a) - Measurement The method according to the invention is applicable to all semiconductor wafers without a layer structure, the wafers preferably containing one or more substances selected from the group: silicon, germanium, silicon carbide, III / V compound semiconductors and II / VI compound semiconductors. If the flatness of the front side of such a semiconductor wafer is to be improved, the height deviation from a defined ideal level, as described above, is suitable as a parameter measured in step a) of the method. This height deviation can be determined with a conventional geometry measuring device.
• the method according to the invention is also applicable to all SOI panes, wherein the semiconductor layer of the SOI pane preferably contains one or more substances selected from the group consisting of silicon, germanium, silicon carbide, III / V compound semiconductors and II / VI compound semiconductors , If the layer thickness homogeneity of the semiconductor layer is to be improved, this layer thickness is measured in step a) of the method according to the invention.
• the thickness of the semiconductor layer can be measured in a location-dependent manner, for example, using an ellipsometer, interferometer or reflectometer.
• the number and position of the measuring points depends on the desired resolution.
• the number of maximum possible measurement points depends on the size of the probe.
• the size of the measuring probe in the ADE 9500 for semiconductor wafers with a
• Diameter of 200 mm Diameter of 200 mm
• ADE AFS for semiconductor wafers with a diameter of 300 mm 2 x 2 mm 2 .
• the required local light intensity is then calculated from the measured values.
• a suitable method is used in
• the geometry measuring device measures a complete measurement with a probe of size AxA (typically 4 x 4 mm 2 or 2 x 2 mm 2 )
• the thickness t is the height deviation from an ideal plane defined by the backside of the semiconductor wafer.
• This data can be transferred as raw data from the geometry measuring device to a computer. If one now inserts a Cartesian coordinate system through the center of the semiconductor wafer, then for each point x, y there exists a value of the thickness, t (x, y).
• x and y are varied in the raster of the measurement window size, which means that t (x, y) is the average of the thickness across the square defined by xA / 2 to x + A / 2 and yA / 2 to y + A / 2 to understand.
• the exposure device has a resolution of BxB pixels, for example 1024 ⁇ 1024.
• each matrix element M (a, b) is assigned the corresponding value from the original thickness matrix:
• the magnitude function is applicable because typically the resolution of the exposure device is greater than that of the original thickness data. In the opposite case, a geometric averaging of the original data is to be carried out.
• the averaging radius R exists as the control parameter.
• the pixel with the coordinates i, j is assigned the mean value from all pixels which lie in a circle with radius R around the point i, j.
• a point x, y lies in a circle around i, j if and only if the following condition is met:
• Msmooth (i, j) average (M (xi, yi), M (x 2 / y 2 ), M (x 3 / y 3 ), ... M (x n / y n ))
• R based on the original coordinate system, is typically between 0.1 cm and 2 cm and serves as a tuning parameter.
• the maximum value Max M and minimum value Min M of the matrix M smooth allow the generation of the grayscale matrix for the exposure of the semiconductor wafer:
• step c) particularly thin areas of the semiconductor wafer are shown as transparent, so that these areas are exposed in step c) with a high light intensity.
• the thickest points are displayed in black and thus exposed in step c) or only with a low light intensity.
• the calculation is suitable for the case that the material removal decreases with increasing light intensity.
• the opposite case can be calculated analogously.
• step c) The calculation of the locally different light intensity to be used in step c) became associated with the underlying measurement made in step a) explained. However, it may be done at any time between the measurement in step a) and the start of the etching treatment in step c).
• the etching medium is applied to the semiconductor wafer.
• the etching medium has a viscosity of from 50 mPas to 2000 mPas and contains inter alia the reactive compounds required for etching the semiconductor material. It is particularly preferred to use a gel for this purpose.
• gel is meant a semi-rigid mass of lyophilic sol in which the dispersion medium is completely absorbed by the sol particles.
• gels are known in which the molecules of the lyophilic sol form a three-dimensional network.
• the viscosity of the etching medium is adjusted according to the invention so that it can be spin-coated onto the semiconductor wafer and maintains its dimensional stability during the duration of the etching treatment in step c).
• the etching medium therefore has a viscosity in the range from 50 mPas to 2000 mPas, more preferably from 100 mPas to 1000 mPas.
• the composition of the etching medium, in particular with regard to the reactive compounds required for etching, is to be selected in combination with the light wavelength range used in step c) and in dependence on the semiconductor material such that there is a sufficiently strong dependence of the removal rate of the etching reaction on the light intensity.
• etching media used in the invention may serve conventional etching solutions, which are suitable for etching the semiconductor material.
• Acid etching solutions which can be used are aqueous solutions which contain hydrofluoric acid (HF) and an oxidizing agent, for example nitric acid (HNO 3 ), ozone (O 3 ) or hydrogen peroxide (H 2 O 2 ).
• HF hydrofluoric acid
• HNO 3 nitric acid
• O 3 ozone
• H 2 O 2 hydrogen peroxide
• For uniform wetting when using an acidic etching medium is the addition of substances which reduce the surface tension of the etching medium, for example surfactants or acetic acid.
• alkaline etching solutions aqueous solutions containing one or more of potassium hydroxide (KOH), sodium hydroxide (NaOH), tetramethylammonium hydroxide (N (CH 3 ) 4 O, TMAH), ammonium hydroxide (NH 4 OH) or ammonium fluoride (NH 4 F ) contain.
• the alkaline etching solutions may contain other additives such as hydrogen peroxide (H 2 O 2 ).
• an acidic solution is used which contains hydrofluoric acid (HF) and hydrogen peroxide (H 2 O 2 ).
• thickening agents are preferably added to these conventional etching solutions, these substances should change only the viscosity of the solution. Further changes of the solution or a reaction with the species contained in the solution or with the semiconductor wafer should preferably not take place.
• the dimensional stability of the viscous solution should also persist during the etching treatment in step c).
• the thickening agent should be chosen so that the resulting viscous etching medium is transparent in the wavelength range chosen for the irradiation in step c).
• Preferred thickeners are cellulose derivatives from the group of hydrocolloids. These are soluble or dispersible in water and swell to form viscous solutions or gels.
• the best known class is that of carboxymethylcelluloses (CMC), which includes, for example, xanthan.
• CMC carboxymethylcelluloses
• Carboxymethyl celluloses are commercially available in high purity and do not react with the
• the gels that can be produced thereby have a very high viscosity and are particularly temperature-stable.
• This method is suitable for thickening aqueous solutions of virtually any pH and also with high concentrations of the reactive with respect to the etching reaction species.
• As a thickener for gel production are also natural resins and artificial polymers such.
• polymethyl methacrylate polytetrafluoroethylene and polyvinyl fluoride.
• the viscous etching medium exhibits substantially the same etching properties as the underlying liquid etching solution. Only the speed of the etching reaction is subject to a diffusion limitation, which changes the time course of the etching rates. The comparatively small volume of the layer of the etching medium additionally limits the total amount of the dissolved semiconductor material.
• a gel based on an aqueous solution containing hydrofluoric acid and hydrogen peroxide and thickened with xanthan wherein a weight fraction of xanthan from 0.3 to 1.0% is particularly preferred. All percentages are by weight.
• step b) of the method according to the invention is carried out for example by
• the etching medium is applied to the surface to be treated of the semiconductor wafer and the Semiconductor disk simultaneously or subsequently in rapid rotation, for example, with a speed of 2000 to 3000 revolutions per minute, offset.
• a film consisting of the etching medium forms rapidly on the surface of the semiconductor wafer, for example within a few milliseconds. The thickness of this film depends on the viscosity of the etching medium and should preferably be in the range of 0.1 to 0.5 mm.
• the spinning is preferably carried out with the apparatus shown in Fig. 1: This is equipped with a rotatable around its central axis holding device 12. While the semiconductor wafer 7 mounted on the holding device is set in rapid rotation, etching medium is simultaneously applied to the upper side of the semiconductor wafer by the system 9, which comprises, for example, a nozzle.
• the system 9 provides the etching medium in the required quantity, dosage and quality. Due to the fast rotation, the etching medium is rapidly and very evenly distributed over the entire surface of the semiconductor wafer.
• etching medium with a viscosity of 50 mPas to 2000 mPas has some significant advantages over low-viscosity etching solutions: Thus, phenomena that are caused by the immersion of the semiconductor wafer in a dipping bath or by the removal from the dipping bath can be avoided. Thus, when immersing the semiconductor wafer, the flow of the wafer edge can lead to increased or weakened etching of the wafer surface in the region near the edge. When removed from the dipping bath, droplets remaining on the surface of the disc can have an after-effect and leave etch spots on the surface of the disc.
• the spin-on process allows to treat only the front or back of the wafer.
• the other side is protected by the holding device.
• suitable viscosity of the etching medium and speed of the semiconductor wafer and the wetting of the edges can be suppressed, which at low-viscosity liquids is not possible. This is particularly relevant if the pane edge already has the final quality in terms of shape and surface finish before the application of the method according to the invention and thus a change by the method is undesirable.
• the contact angle between the gel and the surface is kept small, which can be achieved by the addition of surfactants to the etching medium or by a hydrophilic surface of the semiconductor wafer, even structured surfaces can be completely wetted.
• the process can also be modified by applying several viscous layers.
• the lowermost layer which is in direct contact with the semiconductor wafer is preferably free of reactive species.
• At least one of the upper layers consists of the etching medium with a viscosity of 50 mPas to 2000 mPas.
• thermal, electrical or mechanical treatment of the viscous layers diffusion of reactive species from overlying layers to the semiconductor surface can be induced. If the viscous layers are exposed, for example, in such a way with location-dependent adaptation of the light intensity that only a part of the surface is heated so that there is sufficient diffusion of reactive species into the lowest layer, then it can be achieved that the etching reaction only at this part of the Disc surface takes place. In this way, the location dependence of ⁇ tzabtrags can be increased.
• step c) the matrix of the gray levels calculated on the basis of the measurement carried out in step a) is sharply projected onto the surface of the semiconductor wafer covered with the etching medium by the exposure apparatus with the aid of suitable optics and thus used in step c) for controlling the local light intensity .
• the spectral dependence of the light absorption of the semiconductor material is important for the selection of a suitable light source.
• arc lamps are characterized by a wide spectrum and high intensities, so they are well usable for the exposure of whole semiconductor wafers.
• filters high-pass, low-pass
• all light sources can be used which lead to the desired charge carrier concentration at the surface of the semiconductor wafer and to the desired depth profile of the charge carrier concentration.
• mercury or sodium vapor lamps, lasers or LEDs are also suitable.
• the light source 2 (FIG. 1), it is also possible, for example, to use a halogen lamp which emits light in a wavelength range from 200 nm to 1100 nm, so that an irradiation intensity of 1 to 100 mW / cm 2 impinges on the surface of the semiconductor wafer to be exposed.
• the wavelength range can be narrowed by one or more solid filters and adapted to the semiconductor material to be processed.
• the optic 4 is preferably designed so that the surface to be treated of the semiconductor wafer 7 is exposed as homogeneously as possible over the entire surface, d. H. preferably with deviations of less than ⁇ 10% when there is no filter 3 between the light source and the semiconductor wafer.
• exposure inhomogeneities caused by the light source or the optics can be taken into account in the algorithm for the calculation of the gray levels and thus compensated.
• the measurement results of a semiconductor wafer obtained in step a) are used to produce a filter 3 (FIG. 2) which is adapted precisely to this semiconductor wafer and which is subsequently used in step c). is used for the exposure of this one semiconductor wafer.
• a filter 3 (FIG. 2) which is adapted precisely to this semiconductor wafer and which is subsequently used in step c). is used for the exposure of this one semiconductor wafer.
• the filter must have particularly high or very low light transmission in the wavelength range used in areas where particularly high etching erosion is required exhibit.
• the gray levels of the filter can be calculated using the algorithm described above.
• the filter itself can be produced in various ways, for example by producing a filter film in the printing process or by using an LCD filter with many individually controllable LCD elements. In principle, however, all filter types are suitable which allow a transmission of approximately 0 to 100% and allow a suitable local resolution.
• the filter 3 is suitably mounted between the light source 2 and the semiconductor wafer 7 in the exposure apparatus 1 so as to expose the semiconductor wafer 7 for which it has been produced such that the filter 3 is imaged exactly on the surface of the semiconductor wafer 7 covered with the etching medium.
• a gray level map is calculated with the aid of the control unit 10, preferably a computer.
• the algorithm described above can be used.
• the exposure of the semiconductor wafer 7 in step c) is carried out by a projection device which displays an image of this gray scale map the surface of the semiconductor wafer 7 is projected.
• the exposure device 1 in this case is a projection device that can project the image of the grayscale map directly onto the wafer without using a fixed filter or mirror.
• the projection device operates preferably on the principle of a data or video projector (so-called "beamer”) .
• the light of the projection lamp 2 is passed either through a controllable transparent LCD unit 3 or via a controllable mirror chip (a matrix of many hundreds of thousands of microscopically small mirrors on a few cm 2 large chip)
• the projection apparatus as currently available commercially enables control of light transmittance in a range of 0 to 100% with a resolution of 1024 x 768 dots. This results in a density of about 6.5 points / mm 2 on the surface of a semiconductor wafer to be treated with a diameter of 300 mm.
• a heating or cooling can be used to set a defined, homogeneous temperature.
• the temperature is preferably chosen as a function of the semiconductor material and the required removal of material so that suitable removal rates are achieved.
• step c) An in-situ measurement of the material removal during the etching treatment in step c) is possible through the use of an integrated measuring system for measuring the parameter to be optimized, wherein the current measurement data can be immediately forwarded to the control unit 10 and processed.
• an etching treatment of the entire surface of the semiconductor wafer is carried out without exposure or with simultaneous exposure of the entire surface, the light intensity being constant over the entire surface of the semiconductor wafer, so one constant, location-independent material removal is achieved.
• This step if necessary, causes thinning of the semiconductor wafer or the semiconductor layer of an SOI wafer to a target target thickness. In this two-step process, only the measured inhomogeneities of the parameter are taken into account when calculating the locally different light intensity.
• the semiconductor wafer or semiconductor layer is reduced to the desired thickness in step c).
• the combination of homogenization and thinning can also be carried out as a one-step process.
• the required total removal up to the desired final thickness is taken into account.
• the etching medium is removed from the surface of the semiconductor wafer.
• the removal is carried out by applying a cleaning liquid to the layer of the etching medium, whereby the etching medium is diluted and rinsed.
• the cleaning liquid is a solvent, for example water.
• this step is also carried out in the device shown in FIG. 1, namely with the holding device 12 rotating. A simultaneous action of ultrasound can assist the rinsing out of the etching medium.
• the inventive method allows the production of semiconductor wafers with excellent flat surface and SOI wafers with excellent layer thickness homogeneity.
• the inventive method allows the production of semiconductor wafers whose front side has a GBIR of at most 0.09 ⁇ m, a SFQRm 3x in a measuring window of size 26 x 8 mm 2 including partial sites of not more than 0.05 ⁇ m with an edge exclusion of 2 mm and an edge roll off on the front of at most 0.2 ⁇ m, measured in a range between 1 mm and 3 mm from the edge the semiconductor wafer, have.
• the semiconductor wafers produced according to the invention are distinguished even by an SFQR m3x in a measuring window of size 26 ⁇ 8 mm 2 including partial sites of at most 0.03 ⁇ m with an edge exclusion of 2 mm.
• the invention also allows the production of semiconductor wafers, the front of which have a nanotopography (peak to valley) in a measuring window of size 2 x 2 mm 2 of at most 16 nm with an edge exclusion of 2 mm.
• High-level semiconductor wafers produced according to the invention are suitable for use in the semiconductor industry, in particular for the fabrication of electronic components with line widths of 65 nm or less. They are also particularly well suited as donor discs or carrier discs for the production of bonded SOI discs, in particular, since the flatness including edge roll off is ensured even with a very small edge exclusion of only 2 mm.
• the invention also makes it possible to produce an SOI wafer comprising a semiconductor layer and a carrier wafer, wherein the semiconductor layer has a thickness of less than 100 nm and the relative standard deviation of the average thickness of the semiconductor layer with an edge exclusion of 2 mm is at most 3%.
• the relative standard deviation of the thickness of the semiconductor layer is also referred to below as layer thickness homogeneity.
• the SOI discs produced according to the invention are even distinguished at a layer thickness of at most 100 nm by a layer thickness homogeneity of at most 1% with an edge exclusion of 2 mm.
• an SOI disk produced in this way has a GBIR of at most 0.1 ⁇ m and an SFQR m3x in a measuring window of size 26 ⁇ 8 mm 2 including partial sites of at most 53 nm with an edge exclusion of 2 mm and an Edge Roll Off on the front of at most 0.25 ⁇ m measured in a range between 1 mm and 3 mm from the edge of the wafer.
• the method according to the invention can also be applied to SOI disks with a thick semiconductor layer, it also permits the production of SOI disks comprising a semiconductor layer and a carrier disk, wherein the semiconductor layer has a thickness in the range from 0.1 ⁇ m to 80 ⁇ m and the relative standard deviation of the mean thickness of the
• Semiconductor layer with an edge exclusion of 2 mm is not more than 4%.
• SOI wafers with a thick semiconductor layer produced according to the invention are distinguished even by a layer thickness homogeneity of not more than 2% with an edge exclusion of 2 mm.
• the SOI disk is made thicker Semiconductor layer additionally with a GBIR of at most 0.11 ⁇ m and a SFQR m3x in a measurement window of size 26 x 8 mm 2 including partial sites of at most 55 nm with an edge exclusion of 2 mm and an edge roll off on the front of at most 0, 3 ⁇ m, measured in a range between 1 mm and 3 mm from the edge of the SOI disk.
• an SOI disk with a thick or thin semiconductor layer produced according to the invention preferably has one
• Nanotopography peak to valley in a measuring window of size 2 ⁇ 2 mm 2 of at most 16 nm, preferably of at most 8 nm and particularly preferably of at most 2 nm with an edge exclusion of 2 mm.
• Treated is a 200 mm diameter SOI disk made by transferring a silicon layer from a donor disk to a carrier disk.
• the thickness of the disc is 730 ⁇ m
• the thickness of the silicon oxide layer is 120 nm
• the target thickness of the silicon layer on the silicon oxide layer is 60 nm.
• step a the thickness of the silicon layer is exactly measured by means of an interferometer depending on location.
• the measurement with 4000 measurement points and an edge exclusion of 1 mm results in a mean layer thickness of 67.5 nm with a standard deviation of 3.5 nm and a difference of 8.8 nm between maximum and minimum layer thickness.
• FIG. 2 shows a thickness profile along a diameter, ie the thickness t S0I of the silicon layer, measured in the unit nm, as a function of the radial position r, measured in the unit mm.
• Thickness readings are stored in a computer and converted into a grayscale map. Places with a higher layer thickness result in a lower transparency on the Grayscale map, so that at these locations a lower exposure takes place and thus a higher removal rate is achieved and vice versa.
• an etching medium in the form of a gel is applied by spin-coating on the surface of the silicon layer.
• the etching medium consists of an aqueous solution containing 5% HF and 10% H 2 O 2 and which is thickened with 0.7% xanthan gum to a gel. (All percentages are by weight.)
• the gel has a viscosity of about 900 mPas.
• spin-coating the etching medium forms a homogeneous film about 0.3 mm thick over the entire area of the silicon layer.
• the SOI disk is fully exposed, so the removal rate is very low.
• the previously calculated grayscale map is projected in step c) by means of a beamer in the correct orientation and size on the silicon layer of the SOI disc. In this way, the surface of the
• Silicon layer irradiated with locally different light intensity is Silicon layer irradiated with locally different light intensity.
• the wavelength range used is 250-400 nm, the light intensity varies on the disk locally between about 5 and 100 mW / cm 2 .
• the etching treatment takes 5.5 minutes at room temperature, the average etching rate is 1.4 nm / min.
• the SOI disk is then immediately rinsed with deionized water to remove the etching medium from the surface of the silicon layer and stop the etching process. Thereafter, the SOI disc is removed from the device and dried according to the prior art.
• Example 2 With the same thickness measuring method as before the etching treatment, again, the location-dependent thickness of the silicon layer is measured.
• the mean layer thickness is now 60.4 nm with a standard deviation of 0.5 nm and a difference of 2.6 nm between maximum and minimum layer thickness.
• the thickness profile along the diameter, Fig. 3, shows the significant leveling of the silicon layer.
• the local flatness becomes measured.
• the measuring device ADE 9900 E + is used, the size of the surface elements is 26 x 8 mm 2 .
• Table 1 shows the measured SFQR max values (in nm) including partial sites.
• the raw data (individual readings) of the ADE measurement are stored in a computer and converted into a grayscale map. Subsequently, the silicon wafers are treated individually analogously to Example 1.
• etching medium an aqueous solution is used which contains 10 mol / dm 3 of ammonium fluoride and 1 mol / dm 3 of hydrogen peroxide and which is thickened with 0.7% xanthan gum to a gel.
• the gel has a viscosity of about 900 mPas and forms a homogeneous film of about 0.3 mm thickness during spin coating, which covers the entire top surface of the silicon wafer.
• the etching treatment using a beamer as in Example 1 takes about 9 minutes, with the local light intensity varying in a range of about 5 to 50 mW / cm 2 .
• each silicon wafer is freed from the etching medium analogously to Example 1, dried, and the local flatness is measured again.
• Table 1 shows that the SFQR max values (in nm) were significantly reduced by the etching treatment according to the invention.

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