TWI281723B - Method for detecting defect of silicon wafer - Google Patents

Abstract

This invention provides a method for detecting a defect of a silicon wafer in a short time comprising a removing step in which a surface layer of a silicon wafer (10) is almost evenly removed with a predetermined removal allowance and a defect detecting step in which a defect, if any, on a new surface (18) exposed after the surface removal is detected; characterized in that the removing step is a spin etching step in which an etching liquid (25) is supplied to the surface of a rotated silicon wafer (10) to remove the surface layer, and that in the defect detecting step a MOS structure having an oxide film (15) and an electrode (16) is formed on the exposed new surface (18) and a defect, if any of silicon wafer (10) is detected based on the current-voltage characteristics obtained by applying a voltage to the MOS structure.

Description

1281723 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) [Technical Field to Be Invented] The present invention relates to a defect detecting method for a germanium wafer. [Prior Art] A defect-free layer (DZ: denuded zone) having a predetermined thickness without defects such as C〇P (crystal originated particle) and BMD (bilk micro defect), and a defect-containing substrate located at the lower portion ( The high quality 矽 wafer (hereinafter referred to as wafer) of the bu 1 k ) layer is well known in the industry.

Fig. 7 shows a side cross-sectional view of a wafer 10 of the prior art. In Fig. 7, the wafer 10 is provided with a defect-free layer 1 1 and a substrate layer 12, and a BMD defect 13 and a COP defect 14 are mixed in the inside of the substrate layer 12. The wafer 10 having such a defect-free layer 11 is directed to the wafer 10 including the BMD defect 13 and the COP defect 14 in the entire thickness direction, and is 11 气氛 in an atmosphere containing hydrogen gas, argon gas or the like. It is manufactured by annealing at ~1250 °C. Thereby, the BMD defect 13 and the COP defect 14 of the layer near the surface of the wafer iq are removed by being driven away, thereby forming the defect-free layer 11. Hereinafter, the thickness of the defect-free layer 不含 containing no defects 丨3 and 丨4 is expressed by the defect-free depth t of the wafer 10. Component manufacturers that manufacture components such as LSIs will require wafers to provide wafer defects with a defect-free depth t. The defect-free degree is, for example, 5 a m or the like, and is generally required to be in units of 丨# m. This % 'defect-free depth t is changed by the temperature and time of annealing'. In order to smash the defect-free layer to a predetermined defect-free depth t, it is necessary

1281723 V. INSTRUCTIONS (2) It is necessary to correctly derive the relationship between 退im η (10) fire, service and time of retreat *, and four 。. Also, for the annealed wafer 10, it is necessary to perform an order check for the county e v i $-------------------------- From the above-mentioned reasons, the defect-free depth t is a technique that is focused on the nine-speed and accurately measures the wafer 10 from the amaranth industry. fiQflOff 2: The method of detecting the number of defects is to irradiate the wafer 1 使用 using, for example, the wavelength #2'm, and then according to the scattered t of the laser light, the defect-free depth of the circle 10B曰10 t. However, since the method infers the depth value based on the detection of the size, there is a problem that the accuracy is not very good. _ In view of this, among the defects 13, U, in order to be able to accurately measure the ... The degree t is, for example, the measurement method disclosed in International Publication No. WO 01/166041. 歼Ί, 唬, that is, after polishing a surface of the wafer 1 by a predetermined thickness, and then exposing the new A MOS structure k composed of an oxide film and an electrode is formed on the surface. Then, a voltage is applied to the m〇s structure, and the defect-free depth t is measured by measuring (3) I (the oxide film and the t-pressure characteristic). The measurement method of the defect-free depth seven according to the prior art is illustrated. In FIG. 8, an oxide film 15 is designed on the new surface t 1 8 of the wafer defect exposed by the polishing, and then the oxide film is formed thereon. Electrodes 16A and 16B made of polycrystalline stone or the like are formed on the crucible 5. When the electrodes 16A and 16B and the substrate layer 12 are alternately applied, the voltage v is applied via the variable voltage power sources 17A and 17B, so that nine currents i A and i B are generated to flow. * In Fig. 8 In the field l to the left of the middle line, in the shallow area of the wafer 1

7054-5727-PF(Nl); Jack>.ptd 1281723 V. Description of the invention (3) There is a COP defect 14A in memory. The COP defect 14A appears on the new surface 18 of the wafer 10 via grinding. On the other hand, in the field R to the left of the middle line of Fig. 8, the COP defect 14 in the shallow region is eliminated by annealing, and after the grinding, the c〇p defect 14B does not appear on the wafer 1〇. The new surface is on the 18th. Figure 9 is shown in the field R on the new surface 18 where the c〇p defect 14B is not present on the wafer 1 , and the different voltage v is applied from the variable voltage source 1 7 B to the % of the electrode 16 B The current i (gate current a) - the electric field e (gate electric field MV / cm) curve.

As shown in Fig. 9, when the voltage v is converted into an electric field value of about 1 Mv/c [^, the current i is also increased when the voltage V is increased. Then, the current i is gradually increased until the electric field value is changed to 6 to 7 MV/cm. Thereafter, when the overshoot is converted into an electric field value of 6 to 7 MV/cm, it is rapidly increased to 12 MV/cm. θ On the other hand, as in the case of the field L, in the case where the COP defect 14 Β appears on the new surface 18 of the wafer 10, insulation breakdown occurs before the arrival voltage v is converted into an electric field value of about 8 MV/cm. . Therefore, before the voltage v is applied to, for example, 8 MV/cm, the presence or absence of defects can be caused by whether or not insulation breakdown occurs. Figure 10 shows a plan view of wafer 1 。. As shown in the figure, on the oxide film i 5 designed on a new surface (not shown) of the wafer 10, there are 100 or more electrodes 16 having an area of about 10 mm 2 . Hereinafter, the oxide film 丨5 under the electrode 16 and the wafer 16 are referred to as the element two, and the corresponding electrode is applied to the electrode 16 as shown in Fig. 8.

7054-5727-PF(Nl); Jacky.ptd 1281723, invention description (4) The voltage V of the field value, and then the ratio 7 of the elements which are not destroyed in all the elements is expressed as the oxide film yield (or yield). In general, the depth of the yield rate of 疋9〇% or more is regarded as the defect-free depth t. [Problems to be Solved by the Invention] Therefore, the above-described conventional techniques have the following problems. That is, in the prior art, the surface layer of the wafer crucible is removed by grinding. In the grinding process, there is a rough grinding process that requires the use of coarse abrasive particles, and a final grinding process that requires fine grinding of the particles and the slurry. However, if the rough grinding process is performed only without performing the final grinding process, the slight damage caused by the rough grinding will cause the measurement during the GO I measurement.

The component has a low withstand voltage. Therefore, the measured value in the above case does not accurately represent the characteristics of the wafer 1 。. On the other hand, if the wafer 1 is rubbed and removed by a final polishing process (for example, 9 #m), it takes a lot of time to grind it. Therefore, it is necessary to use both. However, in order to perform a rough polishing process and a final polishing process on one wafer 1 , for example, it is replaced by setting the wafer to the same grinder.

Attachment, or moving the wafer 1 to a different grinder is necessary. Figure 11 is a flow chart showing a prior art process. First, the wafer 1 is moved to the wafer 1 by s 11 ), and the wafer 1 is coarsely ground for the defect-free depth t (step S1 2), after which

7054-5727-^(^%]) ;Jacky .p:i Page 7 1282723 DESCRIPTION OF THE INVENTION (5) The fifth grinder finally grinds the wafer 1G (step S13), then: GOI ::: generation 10, The time required for the replacement of the appendage or the transfer of the wafer during polishing becomes longer, and the measurement of the defect-free depth t is required, and the inspection cost of the wafer 10 is increased. The above-mentioned high-quality wafer 10 of the layer 11 is capable of measuring the wafer 10 0. The P?1 boundary is expected to be able to measure the defect-free depth t of the Japanese yen 1 U in a short time. Therefore, it is necessary to study the method of removing the 曰m η μ 2 正确 correctly from the ancient and the earth, and it is enough to be able to do it in a short time, and the surface of the a 1 〇 is a quantitative amount. Wafer U : ί ί : f U, : The coarse abrasive particles used will be on the surface (da.age), and after the final grinding of θ i , there will still be residual = the reason for the wide G() I measurement error . In order to be able to remove the surface layer of the wafer after grinding, it is usually passed through the rough grinding and finally the desired thickness, and then the most: = ; = If you have a small residence. However, the more it is to avoid such a situation, the damage is also necessary to increase the damage, so it is necessary to take the thick reading removed by grinding, and also during the measurement or inspection time. The grinding machine used in manufacturing engineering is used for measuring J: it is usually used to match the current high-quality wafer round grinding machine. However, if you want to increase, you need to be special. Page 8 7054-5727-PF(Nl); Jacky.pid 1281723

(Explanation of the Invention) (6) However, the crucible 1 is used to remove the polishing machine for the surface layer for measurement. This high-priced research:: Machine 2::? Circle I,:: Measurement Wafer Purchase The invention has an increase in the inspection cost of the #0 circle. Look at the problem mentioned above, and the detection of the defect from the economic point of view = Ϊ = the wafer can be detected in a short time [invention content] To achieve the above purpose, remove the removal system of the specified 4 疋The defect of the defect on the surface is removed by etching to remove the surface layer of the wafer to remove the surface layer of the wafer. The misidentification of the trapped surface of the crucible wafer. Further, the above etching precision is within ±5 (4), and thus it is possible to meet the requirements of the component factory. Further, the enamel wafer of the present invention can be etched by the etchant to shorten the invention required for the measurement. This involves uniformly laminating the surface of the wafer and detecting the new inspection process that is exposed after removal. The removal process is performed by etching the surface of the arm. In this case, because the method can be compared with the coarse grinding by etching, the method can be used in a short time, and since the damage is relatively difficult, the damage is not considered to be a deficiency. The depth of the surface layer of the wafer is measured to a defect-free depth of 1 // m units, which is required by the manufacturer. φ| The removal process is a rotary etch, that is, the surface layer is removed by rotating and spraying on the surface of the stone wafer. It is possible to remove the surface layer of the germanium wafer at a high speed. And because the accuracy of the removal is correct,

7054.5727.ρρίΝ1);τ,^ pt, page 9 1281723 V. Inventive Note (7) Therefore, the surface roughness after removal is small, and the measurement of the defect-free depth is made correct. Further, the present invention immediately applies a rinse liquid to the surface of the germanium wafer exposed after the etching to stop the etching after the foregoing etching. In this way, after the supply of the engraving liquid is stopped, the progress of the surname is reduced to reduce the roughness of the surface of the crucible wafer and reduce the surface haze. As a result, when the defect is detected, the occurrence of the withstand voltage failure of the element due to the haze is reduced, so that the detection result is more correct. Further, the present invention can further have a final polishing process for performing final polishing on the surface of the previously exposed Shishi wafer. After the description of the money, the new surface of the 矽 吁 @ @ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , There is also a first stop in the show, and to detect the lack of traps. Also, after sprinkling on the twin crystal, the surface is rounded and the detection result is more correct. The gate oxide film withstand voltage characteristics are measured. The voltage of the MOS structure on which the oxide film and the electrode are formed on the surface is applied. The resulting current _ clothing plus voltage process. &Real and GO I test & and can accurately and quickly determine the lack of! ί : 一边 while rotating the wafer - while etching the etchant = the process of the surface layer, and the engraved name The incoming and outgoing Shi Xijing must be π washing process. By this,

7054-5727-PF(Nl);Jacky.ptd Page 10 1281723 V. Description of invention (8) After stopping the lingering of your supply and "mouth, the rest of the time is combined = surface mist (haze ) reduce, so flat = less and make Shi Xi crystal face. The tenth month of the wafer new table embodiment The third embodiment of the present invention will be described in detail with reference to the drawings. ^The method of non-defective deep (four) determination of the method -= by the type 2 = spin-on side machine, and then the thickness is determined (step - whirl surface to remove the thickness of the surface layer; by: etch: liquid spray On the surface of the wafer circle, the smooth %1 table is exposed: thus the 'the crystal can be uniformly removed and then the GOI measurement process for the thickness of the removed surface layer (step S22).

Surface 18: In the same manner as shown in Fig. 8, after removing the exposed new watch, the structure of the chamber formed by the film 15 and the electrode 16 is applied. The I measurement was performed, and the =(9)-electrode oxide film at a certain depth was detected) ι§Ιφ. Hereinafter, one of the spin-on type engraving machines will be described in detail with reference to Fig. 2. Fig. 2 shows an example of the spin-on type engraving machine 22. It is applied to this page 11 7054.5727. PF (Ni); jack 5. Inventive Note (9) An example of the spin-on etching machine 22 of the embodiment is, for example, RST2Q〇 manufactured by ESUIZETTO Co., Ltd., Japan. device. The spin-on type insect engraving machine 2 2 in Fig. 2 has a turntable 23 that can be rotated at a high speed via a motor 28. The upper portion of the turntable 23 has a support structure (not shown) (for example, a clamp using the principle of white work (Bem〇ulli) and is used to hold the surface of the wafer 10 upward and approximately horizontally. The spin coater 22 is also The etching liquid supply pipe 24 is provided. The etching liquid 25 containing nitric acid (HN〇3), hydrofluoric acid (HF), and sulfuric acid (IS in K ^ : is supplied from the upper portion of the wafer 经由 through the etching liquid supply pipe 24 As for the crystal, the cleaning process of the 6-side surface of the cleaning liquid tube stops at the center of the money engraved 2 5 . It is supplied with the same thickness enough to be on the wafer 1 〇 wafer 10 at this time, the rotation speed and The amount of the etching is removed. When the spin-on type is removed, the cleaning solution is neutralized and etched. On one side, the surface is diffused from the etched wafer 10 to the surface of the crystal, and the thickness of the layer is passed through the unetched liquid. The j micro-"wafer also has a cleaning liquid for supplying pure water, and the like, and the etching tube 2 is supplied with a cleaning liquid such as pure water to clean the wafer 1 to clean the wafer. 10 0, while the etchant 25 is supplied to the center portion of the etchant supply tube 24 approximately vertically, by the table of the circle 1 〇 Through this, the eclipse is performed at the same speed, and the uniformity can be achieved. The command of the controller can adjust the amount of crystal supply, and the wafer i can be controlled to the surface of the wafer, and the engraving process can be performed. Evenly removing the fill of the circle 10 is desired to be etched by a certain amount of the surface layer of the wafer 10

1281723 V. INSTRUCTION OF THE INVENTION (10) Immediately, the supply of the liquid 25 is supplied from the cleaning liquid pipe 26 to the neutralization of the surviving liquid 2, and the wafer 1 is cleaned and stopped. Thereafter, the wafer after the etching is transferred to the wafer, and the wafer is cleaned with pure water or the like, and then the wafer is dried. In the conventional spin-on etching technique, it is not a good time to proceed. For example, in a state where the etching liquid 25 remains in the process of not supplying the cleaning liquid 27 from the cleaning liquid pipe 26 after a certain period of time, the wafer i is cleaned or washed. Homework. However, if the cleaning liquid 27 is supplied after the supply of the etching liquid 25 is stopped, uneven etching is performed after the stop of the remaining surface of the wafer. Through the exposure, the exposed surface 1 of the wafer 1 becomes rough. The cloud of haze is generated on the surface of a large area (haze) which can be visually observed, and the haze makes the gloss. Such a mist (haze) is a general requirement, and when a flat surface is required for the purpose of etching for the purpose of removing an oxide film or the like, it is said that the mist is measured at the time of GOI measurement. Haze) and (3)p lack insulation breakdown to cause the electric field E to drop, and decrease Q q I. For this, as shown in this embodiment, the liquid 27 is stopped. In this way, the cleaning process is sent to the cleaning device 2, and the dry cleaning solution 27 (not shown) is to be in the cleaning liquid 27, or 'so that the wafer 1 is transported to the cleaning device without promptly supplying money. The engraving 25, in the case of such a moment, there will be a so-called thin. This mist new surface 1 8 lost is not a big problem, but, in the case of G Ο I (large problem. That is, trapping 1 4 produces the same precision. Stop money 2 2 for the supply

1281723 V. INSTRUCTION OF THE INVENTION (11) Immediately after the supply of the cleaning liquid 2 7 is supplied, the process of the remaining process is stopped, so that a smooth new surface 18 with little haze can be obtained. This makes it clear from the visual field that the area of the cloud-like area is reduced. Thereby, the cause of the error in the measurement of GO I can be reduced. In this way, for a wafer wafer that has been quantitatively removed from the surface layer, the GOI measurement can be performed accurately by the method shown in FIG. 8 to accurately measure the defect-free depth of the wafer 1 t. . Next, the effect of etching and polishing on the GO I measurement will be described in detail. In the case where the G 〇 I measurement is performed on the wafer 1 which is removed by etching, whether or not the same precision as in the case of removing the surface layer by polishing can be obtained, and the following is determined experimentally. The experimental conditions are as follows. Take 3 wafers of 1 牧 as a group, and prepare 1 晶圆 wafer 1 〇. Then, it was heated at 1 1 Torr X: ~1 2 0 0 °C under an atmosphere of 100% hydrogen, and the heating time was in the range of 1 to 4 hours, and various annealing processes were performed for each group. As a result, the three wafers 1 which were annealed under the same conditions were regarded as one set, and thus 20 sets of annealed wafers 1 were obtained.

Further, one of the three wafers 1 of the same group was removed by polishing (rough polishing and final polishing) to remove the surface layer having a thickness of 9/zm, and the other two were removed by a surname of 9/. The surface of zm. For these wafers 10 from which the surface layer has been removed, a wafer having a plurality of elements is formed as in the first drawing, and then GO I measurement is performed on each element. Then, when the electric field of about 8 MV/cm is applied, the ratio of the number of components that does not cause dielectric breakdown to the total number of components is regarded as

7054-5727-PF(Nl); Jacky.ptd Page 14 1281723

Yield rate. In Fig. 3, there is a wafer crucible which is subjected to spin coating etching, and the third ^ GO I measurement is _. f L soil ~ 121 bamboo -, negative not both of them after passing through the 疋. . The comparison of the rates is experimentally $. In the third figure, the Japanese yen 10 corresponds to - the measurement point (丨), the ~', the 'implanted two wafers i 0, i 0 good; flat) the average spin-on-money wafer 10 The yield rate. The 杈-axis system indicates that the results have been studied, for example, as shown in the measurement point 29, for the conditionally processed wafer 1 逸, the drawbar wire coating 4, the 'u fire; the smear-coating etching and the grinding Γ = = ί:: ί is about 57%. Also, it can be found that there is a great correlation between the relationship between the two. I illusion: It is known that the correct G0! measurement result can be obtained by using a spin-on button to replace the polishing to remove the surface layer. π rot and the following application examples, the results of the application of spin-on etching of the wafer. The ^true=times of the j-relationships are first made separately. There are high-density wafer groups A with low density and a large c〇p defect 1 circle group 10B with low density. Also, regarding the size and density of the c〇p defect 14 during the pulling process of the wafer 10, the stretching speed or the atmospheric temperature may be predicted first. Therefore, the above-mentioned wafer groups 10A and 10B are annealed under different annealing conditions in a 1% by mass atmosphere. Annealing ° Oxygen is as described in the following four conditions. /, , conditions

1281723

V. Description of invention (13) 1) 1100 °c, 1 hour 2) 1150 °C, 1 hour 3) 1 200 °C, 1 hour 4) 1 2 0 0 °C, 2 hours then 'in order to investigate the annealing conditions and The relationship between the defect-free depths t is subjected to spin-on etching of the wafer groups 1 〇A and 丨〇B which have been annealed under respective conditions, and then subjected to G0 I measurement. The amount of spin-off silver engraving removed, 丨, 3, 6, 9 # m. There is also a comparison with each other for the wafer 未 which has not been surface removed. Regarding the G 〇 I measurement, an oxide film thickness of 2 4 n m was made up to an electric field of 8 MV/cm, and then the unbroken element was evaluated. 'In order to proceed, the piece of work is >· First, the results of the experiment regarding the presence of a wafer group 10 A with a high density of small COP defects 14 are as follows. Fig. 4 is for the wafer group 10A, the horizontal axis is removed, and the vertical axis is the yield. In the wafer group 10A as shown in Fig. 4, it can be found that the wafer annealed by the strips 3), 4) 120 ° C, even if the surface depth up to 9 is removed, the yield is still over 90%.

For wafers 1〇A for the presence of high-density small COP defects14, it can be found that wafers annealed for more than 1 hour by applying 1200 °C are deep f up to 9 // m Defects can be removed. Next, regarding the wafer group 10B in which the large COP defect 14 having a low density exists, the experimental results are explained below. Figure 5 shows the wafer group 10B, the horizontal axis removal, and the vertical axis representation.

V. INSTRUCTIONS (14) In the wafer group 1〇B of the second IS, it can be found that only the wafer that has been annealed by the hour is 10, after removing 2 I ΐ 1 / up to 3 // m, the yield is still Beyond 90%, however, until the 6 曰 / wood and then 'the yield rate is only 8〇% 〇 ^ other aspects, except for the condition 4), even if the removal amount is 1 # m, regardless of the annealing conditions of the wafer It can't exceed 90%. Therefore, in order to remove the large CGP defect 14, it is necessary to perform a high-temperature and long-time annealing process. Therefore, in order to obtain a wafer defect having a defect-free depth of 9 #m, it is necessary to explore a more suitable annealing condition.

In this manner, by removing the surface layer of the wafer crucible by spin-on etching and then performing the GOI measurement, the relationship between the parameters of the annealing and the distribution in the depth direction of the c〇p defect can be maintained. X The greatest effect of the present invention is that the defect detection time of the wafer can be shortened. For example, if a conventional polishing method is used, in order to remove the surface layer of the wafer 1 9 by an amount of 9 // m, it is necessary to integrate the rough polishing and the final grinding, so that one piece is equivalent to about 12 minutes. On the other hand, if the spin-on etching of the invention is used, it can be completed in about 8 minutes. In this way, the defect detection time of the wafer can be shortened. Also, since the spin-on etching of the present invention is to remove the surface layer by chemical change, almost no scar or stress is generated on the surface of the wafer 丨0. Moreover, the method can positively remove the desired amount as compared to other etching methods. Moreover, the roughness of the new surface is also small. Therefore, the measurement results for the GOI measurement can be made very high.

1281723 V. Description of invention (15) The general component manufacturer is stipulated that the general non-defective == two is the basic unit. Therefore, the dimensional accuracy of the .1 field = Chenli through the spin-on type must be controlled within ± 0 · 5 // m. If you have a better than the grinding of the pepper r, and can meet the accuracy can be controlled within ± 5 m. 5 / m within the conditions of the line of the ancient j ^, ,, .. ^ "method of the live, then not here In particular, it is a spin-on etching, and other etching methods are also possible. 蛉# Ϊ Ϊ The spin-on etching of the present embodiment is to stop the supply of the etching liquid 25, and to supply the cleaning liquid 27, The etch process is stopped for one month to prevent haze from being formed on the new surface 18. _钃ΓίΗ: Mesh/two by % This is caused by the mist on the new surface 18. Therefore, the yield t = - the error will be reduced, and the measurement without defects will be performed more correctly. That is, the second:: 旋 spin-on etching machine is much cheaper than the grinding machine, so =疋.', The worker 1 is used as a special machine for inspection and measurement, and the added cost is also more cost-effective than buying a grinder. Second Embodiment Next, a second embodiment of the present invention will be described. The determination of the defect-free depth of the second embodiment of the present invention is as follows: η/牛二二,图。 First, '35 is rotated by a surname 22 and the surname is etched. Step S3 ) ' Then transfer the wafer 1 to the final grinder (step bd Z j ' and then take it through the final machine 4 4 π, the original machine dare to finish the wafer 1 〇 (step S33), and then proceed G Ο I is measured (step s 3 4 ). If the right side is removed by 9 //m, then the step in step S31 is

V. DESCRIPTION OF THE INVENTION (16) The depth of etching is removed by about 8 m, and then in step 33, final gas is removed to remove 1/im to expose a new surface. If the coarse grinding is used to remove 8"^, then the depth of 8 μm can be removed by spin-on etching. This can be achieved in a short time by the father. Therefore, even if the rough grinding is replaced by spin-on etching, In addition, in the first embodiment, if the supply of the cleaning liquid 27 is not immediately performed after the supply of the etching liquid 25 is stopped, a thin film is formed. (haz°e) On the new surface 18, part of the haze causes an error in the pressure resistance and the GOI measurement.

Further, as a method of detecting a defect of the wafer 1 ,, in addition to the G 〇丨 measurement method, for example, a c 〇p defect 14 on the new surface 18 is measured using a particle W counter. However, as described above, even if spin-on etching is used, there may be a little haze on the surface of the wafer crucible, and the particle detector also calculates the number of haze. Therefore, there is a greater detection error than the G〇I measurement. Therefore, according to the second embodiment of the present invention, even if the final polishing is performed by the spin-on etching, the haze can be removed more reliably, and even if the measurement method other than the G0I measurement method is used, it is possible to correct it. Line defect detection. Also, since the spin-on etching removes the watch by chemical changes, it does not cause the damage of the wafer 10 as is the case with the conventional coarse grinding shoe. The error caused by the measurement of 〇〇1. Therefore, even for the removal of the wafer i layer, grinding and etching require approximately the same time, and the etching still has the advantage that the defect detection error is small and can be correctly detected. /formula

1281723 V. INSTRUCTIONS (17) ? There is a final polishing that can more accurately control the surface layer of the wafer than the etching. As mentioned above, the manufacturer of the component is. :? The defect-free depth t is based on ^. However, the accuracy of the required size of the removal must be controlled within ±^5_3, m: in the case of 'there is no easy to achieve the purpose in the singular manner', as described in this embodiment. After the final grinding, it can be removed _ in the red-coated etching, and the spin-on type 22:=:; is also often: compared with the "style", so the first need to use silk cold Ribs but the time required r "final grinding" can still be more

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart showing an example of a method for measuring a defect-free depth according to a first embodiment of the present invention; FIG. 2 is an explanatory view showing an example of a spin-on etching machine; Comparison chart of GO I measurement results obtained by grinding and etching; FIG. 4 is a comparison chart showing annealing conditions and yield; FIG. 5 is a comparison chart showing annealing conditions and yield; FIG. 6 is a second drawing according to the present invention. A flowchart of a method for measuring a defect-free depth of an embodiment; FIG. 7 is a cross-sectional view of a wafer according to a conventional technique, and FIG. 8 is an explanatory diagram of a method for measuring a defect-free depth according to a conventional technique. 9 is a current-electric field graph according to a conventional technique; FIG. 10 is a plan view of a wafer; and FIG. 11 is a flow chart of a method for measuring defect-free depth according to a conventional technique [symbol description] 1 0~ Wafer; 1 2 ~ bottom layer; 14 ~ COP defect; 1 6 ~ electrode; 1 8 ~ new surface; 2 1 ~ cleaning device 1 1 ~ defect-free layer; 13 ~ BMD layer; 1 5 ~ oxide film; ~ Variable voltage power supply 1 9 ~ center line; 2 2 ~ spin coating Etching

7054-5727-i¥(Nl):Jacky.pid Page 21 1281723 Schematic description 23~ turntable; 2 5~ etchant; 2 7~washing solution; 2 9~ measuring point. 2 4 ~ etching solution supply tube 2 6 ~ cleaning liquid tube; 2 8 ~ motor;

7054-5727-PF(Nl);Jacky.ptd Page 22

Claims (1)

1281723 '' -^ VI. Applying for the patent scope to modify the surface of the Tai (1〇) surface to reveal the new watch: The removal layer; the new defect of the Shi Xijing wafer (1 〇) exposed by the removal system Detecting the oxide film (1 5 ), and then the pressure characteristics to detect the gate oxide film resistance 2 · as in the application method 'where the etch etching removes the twin crystal 3 · as in the application method, wherein the etch (2 5 ) is supplied to the stone 4. In the application method, the defect detecting method for exposing 0 kinds of germanium wafers after the etching is performed, including uniformly removing the germanium wafer from the quantitative removal process, and detecting the located behind the removal (18) Defective defect detection process, characterized in that the process of removing the germanium wafer (1〇) through the rice cooking process in the late course further includes a final polishing process for performing the final polishing process via the silver engraved (10) surface. And exposing the surface of the crucible (18); the process includes a MOS fabrication of the MOS structure formed by the electrode (16) on the exposed new surface (18), and the MOS structure is applied according to the applied voltage. The resulting current - calcium carbide wafer (1 0) Applying a voltage having defects, the works of the pressure characteristic measured. The defects detection procedure of the germanium wafer described in the first paragraph of the patent range is capable of removing the surface layer of the inner circle (10) with a precision of ± 0.5 # m. The flaw detection side of the item is rotated by the Shi Xi wafer (10) while the remaining side of the remaining liquid is detected by the defect detector side of the Shi Xi wafer (10) 』t:: t liquid (27) to the surface, And stop the progress of the etching process 7054-5727-PF3(Nl).ptc Page 23 1281723 The private 'where' defect detection process includes a new surface exposed first (丨8) 5 · A method for detecting defects in the stone wafer, including uniformly removing the surface layer of the germanium wafer (〇) A defect detection system that quantitatively removes the process and detects defects on the new surface (1 g ) that is removed after removal, and is constructed of M〇S composed of an oxide film (15) and an electrode (16). A MOS manufacturing process' and then a gate oxide film withstand voltage characteristic measurement process for voltage application engineering in which a defect of a germanium wafer (i 〇) is detected based on a current-voltage characteristic obtained by applying a voltage to the MOS structure. 6 · The defect detection method of the Shishi wafer, including uniformly removing the surface layer of the Shixi wafer (10) by etching to remove a predetermined amount of the removal process, and the germanium wafer exposed after the etching (1 〇) a final polishing process in which the surface is finally ground to expose a new surface (18) of the germanium wafer (10), and a defect detecting process for detecting defects on the new surface (18) exposed after removal, wherein The defect detecting process includes a M0S manufacturing process in which an M〇s structure composed of an oxide film (15) and an electrode (16) is first formed on an exposed new surface (丨8), and then applied to the crucible according to an applied voltage. The current-voltage characteristic obtained by the 〇s structure is used to detect the defect of the Shixi wafer (10), and the gate oxide film withstand voltage characteristic measurement project with voltage application engineering. 7054-5727-PF3(Nl).ptc第24页