WO2007094227A1 - プラズマディスプレイパネル駆動回路およびプラズマディスプレイ装置 - Google Patents
プラズマディスプレイパネル駆動回路およびプラズマディスプレイ装置 Download PDFInfo
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- WO2007094227A1 WO2007094227A1 PCT/JP2007/052202 JP2007052202W WO2007094227A1 WO 2007094227 A1 WO2007094227 A1 WO 2007094227A1 JP 2007052202 W JP2007052202 W JP 2007052202W WO 2007094227 A1 WO2007094227 A1 WO 2007094227A1
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- voltage
- plasma display
- circuit
- display panel
- capacitor
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Classifications
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
- G09G3/2965—Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/293—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
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- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
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- G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
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Definitions
- the present invention relates to a plasma display panel drive circuit and a plasma display device used for a wall-mounted television or a large monitor.
- An AC surface discharge type plasma display panel (hereinafter abbreviated as "PDP"), which is representative of an AC type, has a front plate having a glass substrate force formed by arranging scan electrodes and sustain electrodes for performing surface discharge.
- the back plate which has a glass substrate force formed by arranging the data electrodes, is arranged opposite to each other in parallel so that both electrodes form a matrix, and the force also forms a discharge space in the gap, and the outer peripheral portion is made of glass frit, etc. It is configured by sealing with a sealing material.
- a discharge cell partitioned by a partition is provided between both the front plate and the back plate, and a phosphor layer is formed in the cell space between the partitions.
- ultraviolet rays are generated by gas discharge, and the phosphors of each color of red (R), green (G), and blue (B) are excited by the ultraviolet rays to emit light. It is carried out.
- Patent Document 2 A technique for reducing power is disclosed (for example, see Patent Document 2).
- the electrode drive circuit configuration disclosed in Patent Document 2 is a power circuit. The first discharge is generated when the current is supplied from the collecting unit to the panel by LC resonance, and then the voltage clamp unit applies the voltage value Vsus to the panel to generate the second discharge. By performing the discharge twice in succession, the peak value of the required amount of current can be reduced compared to a single discharge, thus reducing power consumption.
- Patent Document 2 also discloses a technique for changing the timing of two discharges by the lighting rate of the screen (a value obtained by dividing the number of pixels to emit light by the total number of pixels).
- a technique for reducing power consumption in the writing period is also disclosed. Since the data electrode is also capacitive like the scan electrode or the sustain electrode, the data electrode drive circuit is provided with a circuit similar to the recovery circuit section provided in the scan electrode or the sustain electrode drive circuit, so that it can be stored in the panel during the writing period. It is possible to collect the generated charges. In addition, a circuit that adds a new circuit to the recovery circuit unit and further reduces power consumption has been proposed (for example, see Patent Document 3).
- the PDP device disclosed in Patent Document 3 also includes means for solving the problem that the writing operation that occurs with the increase in the screen size and the definition of the panel cannot be performed correctly. In other words, if the PDP has a larger screen and higher definition, the address discharge current increases, a large voltage drop occurs in the scan pulse, and the writing operation becomes unstable. Therefore, the PDP device disclosed in Patent Document 3 uses means for changing the timing of the data application voltage by the data electrode in order to prevent the write operation from becoming unstable.
- Patent Document 1 Japanese Patent Publication No. 7-109542
- Patent Document 2 Japanese Patent Laid-Open No. 2002-132212
- Patent Document 3 Japanese Patent Laid-Open No. 2005-49823
- Patent Document 1 The PDP device according to the related art disclosed in Patent Document 1 is superior in that it has a recovery circuit that recovers and reuses the charge of the panel, paying attention to the fact that the panel is a capacitive load. Has a loss reduction effect.
- the charge recovery method is uniquely determined, the gradation or brightness cannot be changed by the operation of the recovery circuit, regardless of the lighting rate.
- the PDP device uses the first discharge by using two discharges, that is, the discharge from the power recovery unit and the discharge of the voltage clamp unit force during the sustain period. Power consumption is reduced compared to technology. In addition, the power consumption is further reduced by changing the time interval between the power recovery unit and the voltage clamp unit according to the lighting rate.
- the first discharge supplies current through the inductor of the power recovery unit, the current supply amount is determined by the inductor. In other words, the intensity of the first discharge varies depending on the lighting rate, that is, the number of pixels to be discharged. Therefore, in the PDP device disclosed in Patent Document 2, the first light emission luminance of each pixel changes according to the lighting rate.
- the PDP device according to the prior art disclosed in Patent Document 3 includes a recovery circuit unit in the data electrode driving circuit, and therefore reduces power consumption compared to the conventional technology without the recovery circuit unit. It is effective for. Furthermore, the PDP device disclosed in Patent Document 3 Since a current limiting circuit is provided so that the panel capacity can be recovered more than the recovery circuit unit, it is desirable to further reduce power consumption. However, if the voltage of the recovery capacitor exceeds the set voltage, the PDP device disclosed in Patent Document 3 consumes the recovered power with a resistor so that the voltage of the recovery capacitor falls within the set voltage. . It can be said that it is desirable to effectively use the recovered surplus power without consuming it with resistors.
- the technique of shifting the write operation of the data electrode drive circuit in the write period in time is effective in stabilizing the write operation.
- this time-shifting operation weakens the discharge strength of the address discharge, causing another problem that the address operation becomes unstable (see Fig. 9). That is, in the data electrode (for example, Dm2 in FIG. 9) whose data voltage application timing is late, the period from the application of the scan pulse (SCn in FIG. 9) to the application of the data voltage (in FIG. 9).
- tl to t2 a state in which a low data voltage (voltage in the vicinity of Vm2L in FIG. 9) is applied continues for a long time.
- the wall charge formed in the initialization operation decreases with time.
- the wall charge is already low, and the discharge intensity of the address discharge may become weak.
- the present invention has been made to solve the above-described problems.
- the plasma display panel drive circuit according to claim 1 of the present invention is
- an inductive element, a switch, and a capacitor are temporarily connected to the display panel in order to supply and recover power to the load capacity of the display panel.
- It is a plasma display panel drive circuit that forms an LC resonant circuit.
- the plasma display panel driving circuit includes a control circuit that varies the voltage of the capacitor.
- a plasma display panel drive circuit according to claim 2 of the present invention is a plasma display panel drive circuit according to claim 2 of the present invention.
- a plasma display panel drive circuit according to claim 3 according to the present invention is a plasma display panel drive circuit according to claim 3 according to the present invention.
- An inductive element having one end connected to the capacitor
- a transistor having a collector terminal connected to the other end of the inductive element and an emitter terminal connected to a negative-side power source of the sustain voltage;
- a plasma display panel drive circuit according to claim 4 according to the present invention is a plasma display panel drive circuit according to claim 4 according to the present invention.
- An inductive element having one end connected to the capacitor
- a first transistor in which a collector terminal is connected to the other end of the inductive element, and an emitter terminal is connected to a negative power source of a sustain voltage;
- a first diode having a force sword side connected to the collector terminal of the first transistor and an anode side connected to the emitter terminal;
- An emitter terminal connected to the collector terminal of the first transistor, and a collector terminal connected to the positive power source of the sustain voltage;
- a second diode having a force sword side connected to the collector terminal of the second transistor and an anode side connected to the emitter terminal
- a plasma display panel drive circuit according to claim 5 of the present invention is a plasma display panel drive circuit according to claim 5 of the present invention.
- any one of claims 1 to 4 wherein the control circuit varies the voltage of the capacitor in accordance with a lighting rate.
- a plasma display panel drive circuit according to claim 7 of the present invention includes:
- a plasma display panel drive circuit according to claim 8 of the present invention is a plasma display panel drive circuit according to claim 8 of the present invention.
- a plasma display panel drive circuit according to claim 9 of the present invention is a plasma display panel drive circuit according to claim 9 of the present invention.
- a control circuit is connected to the LC resonance circuit connected to at least one of a sustain electrode and a scan electrode. 10. It is.
- a plasma display panel drive circuit according to claim 10 according to the present invention is a plasma display panel drive circuit according to claim 10 according to the present invention.
- a plasma display panel drive circuit according to claim 11 according to the present invention is a plasma display panel drive circuit according to claim 11 according to the present invention.
- control circuit varies the voltage of the capacitor in accordance with a change in logic level between adjacent pixels for address discharge.
- a plasma display panel drive circuit according to claim 12 according to the present invention is a plasma display panel drive circuit according to claim 12 according to the present invention.
- control circuit holds the voltage of the capacitor during an address period in one subfield.
- a plasma display device according to claim 13 according to the present invention comprises: A plasma display device comprising the plasma display panel drive circuit according to claim 9 or 10.
- a plasma display device according to claim 14 according to the present invention
- a first control circuit connected to the first LC resonant circuit comprising at least two LC resonant circuits connected to the data electrode;
- a second control circuit connected to the second LC resonant circuit
- a plasma display device according to claim 15 of the present invention provides:
- the first control circuit and the second control circuit are operated so that a capacitor voltage of the first LC resonance circuit and a capacitor voltage of the second LC resonance circuit are different from each other.
- Item 15 The plasma display device according to Item 14.
- a plasma display device according to claim 16 of the present invention comprises:
- a capacitor voltage of the first LC resonance circuit is smaller than a capacitor voltage of the second LC resonance circuit.
- a plasma display device includes:
- the luminance during the sustain period can be reduced, so that the gradation can be increased and a plasma display device with high image quality can be provided.
- the first discharge can be controlled stably even if the lighting rate changes, the second discharge is also stabilized and the display quality is improved.
- the light emission form of PDP is also stabilized, so that the current consumed is also stabilized and the power consumption can be reduced.
- the plasma display device As described above, even when the power recovery circuit is provided on the data electrode side and the timing of the write operation is varied in the write period, the data electrode The voltage during the period until the voltage is applied can be reduced. As a result, the wall charge can be prevented from decreasing during this period, so that the writing operation is stabilized and the display quality is further improved.
- FIG. 1 is a perspective view showing a configuration of a plasma display panel according to an embodiment of the present invention.
- FIG. 2 is a diagram showing an electrode arrangement of the plasma display panel according to the embodiment of the present invention.
- FIG. 3 is a voltage waveform diagram applied to each electrode of the plasma display panel according to the embodiment of the present invention during one sub-field period.
- FIG. 4 is a block configuration diagram showing the plasma display device according to the embodiment of the present invention for each functional block.
- FIG. 5 is a specific circuit diagram of a scan electrode drive circuit and a sustain electrode drive circuit in the plasma display device according to the first exemplary embodiment of the present invention.
- FIG. 6 is a specific circuit diagram of a sustain pulse generating circuit of the plasma display panel driving circuit according to Embodiment 2 of the present invention.
- FIG. 7 is a specific circuit diagram of a data voltage generation circuit of a plasma display panel drive circuit according to Embodiment 3 of the present invention.
- FIG. 8 is a specific circuit diagram of a data voltage generation circuit of a plasma display panel drive circuit according to Embodiment 4 of the present invention.
- FIG. 9 is a diagram showing temporal changes in voltages applied to scan electrodes and data electrodes during a writing period in plasma display devices according to Embodiments 5 and 6 of the present invention. Explanation of symbols
- FIG. 1 is a perspective view showing a structure of a PDP 10 according to an embodiment of the present invention.
- a plurality of display electrodes which are paired with a stripe-shaped scanning electrode 22 and a stripe-shaped sustaining electrode 23 are formed.
- a dielectric layer 24 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 25 is formed on the dielectric layer 24.
- a plurality of stripe-shaped data electrodes 32 covered with a dielectric layer 33 are formed on the back plate 30 serving as the second substrate so as to cross the scanning electrode 22 and the sustain electrode 23 three-dimensionally. ing.
- a plurality of barrier ribs 34 are disposed on the dielectric layer 33 in parallel with the data electrodes 32, and a phosphor layer 35 is provided on the dielectric layer 33 between the barrier walls 34. Further, the data electrode 32 is disposed at a position between the adjacent partition walls 34.
- the front plate 20 and the back plate 30 are arranged opposite to each other with a minute discharge space so that the scan electrode 22, the sustain electrode 23, and the data electrode 32 are orthogonal to each other, and the outer periphery thereof is made of glass. It is sealed with a sealing material such as a frit.
- a mixed gas of neon (Ne) and xenon (Xe) is sealed as a discharge gas.
- the discharge space is The partition walls 34 are partitioned into a plurality of sections, and in each section, phosphor layers 35 that emit red (R), green (G), and blue (B) light are sequentially disposed.
- a discharge cell is formed at the intersection of the scan electrode 22 and the sustain electrode 23 and the data electrode 32, and one adjacent pixel is formed by three adjacent discharge cells on which the phosphor layer 35 that emits light of each color is formed. Is done. An area where the discharge cells constituting this pixel are formed becomes an image display area, and the periphery of the image display area becomes a non-display area where no image display is performed, such as an area where a glass frit is formed.
- FIG. 2 is an electrode array diagram of the PDP 10 according to the embodiment of the present invention.
- N rows of scan electrodes SC 1 to SCn (scan electrode 22 in FIG. 1) and n rows of sustain electrodes SU 1 to SUn (sustain electrode 23 of FIG. 1) are alternately arranged in the row direction, and m in the column direction.
- the data electrodes Dl to Dm (data electrode 32 in FIG. 1) in the column are arranged.
- the total number of is (m X n).
- color display is performed by generating ultraviolet rays by gas discharge and exciting the phosphors of R, G, and B colors with the ultraviolet rays to emit light. Further, the PDP 10 divides one field period into a plurality of subfields and performs gradation display by being driven by a combination of subfields that emit light. Each subfield consists of an initialization period, an address period, and a sustain period. In order to display image data, different signal waveforms are applied to each electrode in the initialization period, the address period, and the sustain period.
- FIG. 3 is a diagram showing waveforms of driving voltages applied to the electrodes of the PDP 10 according to the embodiment of the present invention.
- each subfield has an initialization period, an address period, and a sustain period.
- each subfield performs substantially the same operation except that the number of sustain pulses in the sustain period is changed in order to change the weight of the light emission period, and the operation principle in each subfield is also substantially the same.
- the initialization period for example, a positive pulse voltage is applied to all the scan electrodes SCl to SCn, and the protective layer 25 on the dielectric layer 24 covering the scan electrodes SCl to SCn and the sustain electrodes SU1 to SUn. Further, necessary wall charges are accumulated on the phosphor layer 35.
- the data electrodes Dl to Dm and the sustain electrodes SU1 to SUn are held at O (V), respectively, and the scan electrodes SCl to SCn have data electrodes Dl to Dm.
- a ramp waveform voltage that gradually rises from the voltage Vil below the discharge start voltage to the voltage Vi2 exceeding the discharge start voltage is applied. While this ramp waveform voltage rises, the first weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm.
- Negative wall voltage is accumulated on scan electrodes SCl to SCn, and positive wall voltage is accumulated on data electrodes Dl to Dm and sustain electrodes SU1 to SUn.
- the wall voltage at the top of the electrode represents the voltage generated by the wall charge accumulated on the dielectric layer covering the electrode.
- sustain electrodes SUl to SUn are maintained at positive voltage Ve, and scan electrodes SCl to SCn are discharged from voltage Vi3 that is equal to or lower than the discharge start voltage with respect to sustain electrodes SUl to SUn. Apply a ramp waveform voltage that gradually decreases toward the voltage Vi4 that exceeds the start voltage.
- the second weak initializing discharge occurs between the scan electrodes SCl to SCn, the sustain electrodes SU1 to SUn, and the data electrodes D1 to Dm.
- the negative wall voltage above scan electrodes SC1 to SCn and the positive wall voltage above sustain electrodes SUl to SUn are weakened, and the positive wall voltage above data electrodes Dl to Dm is adjusted to a value suitable for the write operation. Is done.
- This completes the initialization operation (hereinafter, the drive voltage waveform applied to each electrode during the initialization period is abbreviated as “initialization waveform”).
- scanning is performed by sequentially applying negative scanning pulses to all the scanning electrodes SCl to SCn. Then, while scanning the scan electrodes SCl to SCn, a positive write pulse voltage is applied to the data electrodes D1 to Dm based on the display data. Thus, an address discharge is generated between scan electrodes SCl to SCn and data electrodes D1 to Dm, and wall charges are formed on the surface of protective layer 25 on scan electrodes SCl to SCn.
- scan electrodes SCl to SCn are held at voltage Vscn.
- the scan electrode S The scan pulse voltage Vad is applied to Cp, and the data electrode Dq corresponding to the video signal to be displayed in the p-th row of the data electrodes Dl to Dm (Dq is selected based on the video signal from Dl to Dm. Apply positive write pulse voltage Vd to data electrode.
- an address discharge is generated in the discharge cells Cp, q corresponding to the intersection between the data electrode Dq to which the write pulse voltage is applied and the scan electrode SCP to which the scan pulse voltage is applied.
- scan electrodes SCl to SCn are returned to 0 (V) and then sustain electrodes SU1 to SUn are returned to O (V). Thereafter, positive sustain pulse voltage Vsus is applied to scan electrodes SCl to SCn.
- Vsus positive sustain pulse voltage
- the voltage between the upper part of the scan electrode SCp and the upper part of the sustain electrode SUp in the discharge cell Cp, q in which the address discharge has occurred is reverted to the positive sustain pulse voltage Vsus.
- the wall voltage accumulated in the upper part of SUp is added and becomes higher than the discharge start voltage, and the first sustain discharge occurs.
- the discharge cells Cp, q that have generated the sustain discharge a negative voltage is accumulated on the scan electrode SCp so as to cancel the potential difference between the scan electrode SCP and the sustain electrode SUp when the sustain discharge occurs, and a positive voltage is accumulated on the sustain electrode SUp. Voltage is accumulated.
- the first sustain discharge is completed.
- the scan electrodes SCl to SCn are returned to O (V), and then Vsus is applied to the sustain electrodes SU1 to SUn.
- the discharge cell Cp, q in which the first sustain discharge has occurred the voltage between the upper part of the scan electrode SCp and the upper part of the sustain electrode SUp is added to the positive sustain pulse voltage Vsus in the first sustain discharge.
- the wall voltage accumulated in the upper part of scan electrode SCp and upper part of sustain electrode SUp is added and becomes higher than the discharge start voltage, and a second sustain discharge occurs. Thereafter, similarly, scan electrodes SCl to SCn and sustain electrode S By alternately applying sustain pulses to U 1 to SUn, the sustain discharge is continuously performed for the number of sustain pulses for the discharge cells Cp, q in which the address discharge has occurred.
- FIG. 4 is a block diagram showing an electrical configuration of the plasma display device incorporating the PDP 10 according to the embodiment of the present invention.
- the plasma display device shown in FIG. 4 includes an AD converter 1, a video signal processing circuit 2, a subfield processing circuit 3, a data electrode drive circuit 4, a scan electrode drive circuit 5, a sustain electrode drive circuit 6, and a PDP 10.
- the AD converter 1 converts the input analog video signal into a digital video signal.
- the video signal processing circuit 2 displays the input digital video signal on the PDP 10 by combining multiple subfields with different light emission period weights. Therefore, the video signal processing power of 1 field is a subfield that controls each subfield. Convert to data.
- the subfield processing circuit 3 receives the control signal for the data electrode drive circuit, the control signal for the scan electrode drive circuit, and the control signal for the sustain electrode drive circuit from the subfield data created by the video signal processing circuit 2. And output to the data electrode drive circuit 4, the scan electrode drive circuit 5, and the sustain electrode drive circuit 6, respectively.
- One pixel is composed of three discharge cells that are formed and emit light in red, green, and blue colors.
- the data electrode drive circuit 4 drives each data electrode Dj independently based on the data electrode drive circuit control signal.
- Scan electrode drive circuit 5 includes sustain pulse generation circuit 51 (A, B) for generating sustain pulses to be applied to scan electrodes SCl to SCn during the sustain period, and each of scan electrodes SC1 to SCn is provided. Each can be driven independently. Then, each of the scan electrodes SC1 to SCn is driven independently based on the control signal for scan electrode drive circuit.
- Sustain electrode drive circuit 6 internally includes sustain pulse generation circuit 61 for generating sustain pulses to be applied to sustain electrodes SUl to SUn during the sustain period, and collects all sustain electrodes SUl to SUn of PDP10. Can be driven. Then, sustain electrodes SU1 to SUn are driven based on the sustain electrode drive circuit control signal.
- FIG. 5 is a circuit diagram of the scanning electrode drive circuit 5 and the sustain electrode drive circuit 6 provided with the power recovery unit in the PDP device according to Embodiment 1 of the present invention.
- the power recovered from the PDP 10 is reused to apply the sustain pulse voltage to the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn in the sustain period, Reduction of power consumption can be realized by reducing the power consumed during the maintenance period.
- sustain pulse generating circuit 51 A includes a resonant circuit including an inductor, that is, a power recovery unit, and is stored in the capacitive load of PDP 10 (the capacitive load generated in scan electrodes SCl to SCn). The power consumption is reduced by collecting the collected power and reusing the collected power as drive power for the scan electrodes SCl to SCn.
- Sustain pulse generation circuit 61 is also equipped with a similar power recovery unit that recovers the power stored in the capacitive load of PDP10 (capacitive load generated at sustain electrodes SU1 to SUn) and collects the recovered power. May be configured to be reused as drive power for the sustain electrodes SUl to SUn, so as to reduce power consumption. The details will be described below.
- Scan electrode drive circuit 5 includes sustain pulse generation circuit 51 A, initialization waveform generation circuit 52, and scan pulse generation circuit 53.
- Sustain pulse generating circuit 51A switches between the power recovery unit and the voltage clamp unit by switching each of the switch elements Sl, S2, S5, and S6, and generates a sustain pulse to be applied to scan electrodes SCl to SCn. appear.
- the sustain pulse generation circuit 51 A using LC resonance power is supplied by the power recovery unit until the sustain pulse voltage reaches a maximum value, and then the voltage is switched to the voltage clamp unit, so that the theoretical power consumption is reduced. It is possible to drive using the power recovery unit that is 0 to the maximum, and to reduce the power consumption of the scan electrode drive circuit 5.
- Sustain pulse generation circuit 51A of scan electrode drive circuit 5 will be described in detail later.
- the initialization waveform generating circuit 52 also has a generally known element force for performing a switching operation of a MOSFET or an IGBT. It has an initializing positive pulse switch element S21, an initializing negative pulse switch element S22, a constant voltage power source V2 having a voltage value Vset, and a constant voltage power source V3 having a negative voltage value Vad. Then, power is supplied from the constant voltage power supply V2 to the scan electrodes SCl to SCn via the initialization positive pulse switch element S21, and from the constant voltage power supply V3 to the scan electrode SCl via the initialization negative pulse switch element S22. Supply a negative potential to ⁇ SCn to generate an initialization waveform.
- the initialization positive pulse switch element S21 has its body diode (in the case of IGBT) when the initialization positive pulse switch element S21 is cut off (hereinafter referred to as “off” to cut off the switch element).
- the main discharge path (sustain pulse generation circuit) from the constant-voltage power supply V2 through a diode with a power sword connected to the collector terminal and an anode connected to the emitter terminal (hereinafter referred to as an antiparallel diode) 51A, initialization waveform generation circuit 52, and scan pulse generation circuit 53 are connected in common, and current does not flow into the power supplied to scan electrodes SCl to SCn and the path through which recovered power from scan electrodes SCl to SCn flows)
- the initialization negative pulse switch element S22 is placed in the direction of its body diode when the initialization negative pulse switch element S22 is off (antiparallel in the case of IGBT). It is arranged in such a direction that current does not flow into the constant voltage power supply V3 through the column
- the initialization waveform generation circuit 52 generates the initialization waveform as described above.
- the discharge start voltage is changed from the voltage Vil below the discharge start voltage to the data electrodes Dl to Dm.
- a voltage exceeding Vi2 that is, a ramp waveform that gently rises toward Vset, is generated, and in the latter half of the initialization period, the voltage that exceeds the discharge start voltage below the discharge start voltage for sustain electrodes SU1 to SUn exceeds the discharge start voltage from Vi3 Vi4, that is, a ramp waveform that gently descends toward Vad.
- the scan pulse generation circuit 53 includes a generally known element force that performs switch operation of MOSFETs, IGBTs, etc., a side scan switch element S31, a low side scan switch element S32, and a constant voltage power source having a voltage value Vscn. Prevents current flowing into V4 and constant voltage power supply V4 Scanning voltage back-flow prevention diode D31, scanning voltage capacitor C31, and two input ports that output one of the power input to the two input ports by switch operation. It has IC31 which is a driver.
- the non-side scanning switch element S31 is made conductive (hereinafter referred to as “on” to make the switch element conductive), and the scanning voltage backflow prevention diode D31 and the non-side scanning are supplied from the constant voltage power supply V4.
- the power of the voltage value Vscn supplied via the switch element S31 is input to one input port of the IC31.
- the low-side scanning switch element S22 of the initialization waveform generating circuit 52 is turned on, and the negative voltage value Vad supplied from the constant voltage power supply V3 via the low-side scanning switch element S22 is supplied to the other input terminal of the IC31. To enter.
- either one of the power supplied from the constant voltage power supply V4 and the power supplied from the constant voltage power supply V3 is selected by the IC 31 and supplied to the scan electrodes SCl to SCn.
- the IC 31 performs a switch operation so that power from the constant voltage power supply V3 is supplied to the scan electrodes SCl to SCn at the timing when the negative scan pulse is applied, and power from the constant voltage power supply V4 is supplied at other times.
- a first separation switch is provided between sustain pulse generation circuit 51A and initialization waveform generation circuit 52.
- the element S9 and the second separation switch element S10 are inserted in series, and the body diodes are inserted in opposite directions.
- Sustain pulse generation circuit 61A of sustain electrode drive circuit 6 will also be described in detail later. [0069] [Sustain pulse generation circuit in scan electrode driving circuit]
- the sustain pulse generation circuit 51A includes a first inductor L1, a first recovery capacitor C1, a first node, a side recovery switch element Sl, and a first low side recovery.
- Power recovery unit having switch element S2, first high-side recovery diode D1, first port one-side recovery diode D2, first high-side sustain switch element S5, first low-side sustain switch element S6 and voltage Including a voltage clamp section having a constant voltage power supply VI of value Vsus.
- the power recovery unit collects and supplies power by performing LC resonance between the capacitive load of the PDP 10 (capacitive load generated in the scan electrodes SCl to SCn) and the first inductor L1.
- the power stored in the capacitive load generated in the scan electrodes SCl to SCn is transferred to the first recovery capacitor C via the first low-side recovery diode D2 and the first low-side recovery switch element S2. Move to 1.
- the power stored in the first recovery capacitor C1 is transferred to the PDP10 (scan electrodes SC1 to SCn) via the first high-side recovery switch element S1 and the first high-side recovery diode D1. Move.
- the scan electrodes SCl to SCn are driven in the sustain period. Therefore, since the power recovery unit drives the scan electrodes SCl to SCn by LC resonance without power supplied from the power source during the sustain period, the power consumption is theoretically zero.
- the voltage clamp unit supplies power to the scan electrodes SCl to SCn from the constant voltage power source VI having the voltage value Vsus via the first no-side sustaining switch element S5, thereby connecting the scan electrodes SC1 to SCn.
- the scan electrodes SCl to SCn are driven by clamping to the voltage value Vsus and clamping the scan electrodes SCl to SCn to the ground potential via the first low-side sustain switch element S6. Therefore, when the scan electrodes SCl to SCn are driven by the voltage clamp unit, the power supply impedance is very small and the rising and falling power ⁇ of the sustain pulse becomes steep, but the power supply power is also consumed due to power supply. Electric power is generated.
- each of the switch elements Sl, S2, S5, and S6 also has a generally known element force for performing a switch operation of a MOSFET or the like.
- a MOSFET is a parasitic diode (a diode generated parasitically in the MOSFET structure), which is generally called a body diode.
- the anode and the force sword are generated in parallel to the part that performs the switch operation and in the opposite direction to the part that performs the switch operation (hereinafter, such a configuration is referred to as “reverse parallel”). Therefore, the switch element can pass a forward current to the body diode even when the switch operation is in a cut-off state.
- an element that performs switching operation such as IGBT, may be used and a reverse parallel diode may be provided separately.
- sustain pulse generating circuit 51A includes a control circuit.
- the control circuit includes a third inductor L3, a third low side recovery switch element S13, and a third recovery diode D6.
- One end of the third inductor L3 is connected to the connection point between the first recovery capacitor C1 and the drain terminal of the first high-side recovery switch element S1, and the other end is connected to the drain terminal of the third low-side recovery switch element S13 (
- the third low-side recovery switch element S13 is connected to the collector terminal in the case of a transistor such as an IGBT.
- the source terminal (or emitter terminal) of the third low-side recovery switch element S13 is connected to the GND terminal.
- the anode side of the third recovery diode D6 is connected to the drain terminal (or collector terminal) of the third low-side recovery switch element S13, and the force sword side of the third recovery diode D6 is connected to the constant voltage power supply VI. Connected to.
- the third low-side recovery switch element S13 performs a PWM operation of turning on and off at a specific cycle according to a determined on / off ratio.
- the period for performing the PWM operation is generally in the range of about 2 microseconds to 50 microseconds, and may be a fixed period or a variable period.
- the voltage Vcl of the first recovery capacitor C1 is compared with the reference voltage Vcs. If Vcl is greater than the reference voltage Vcs, the ratio of the on-off time of the third low-side recovery switch element S13 is increased (the ON time is increased). Longer and shorter off time). Conversely, if the reference voltage Vcs is greater than the direction force Vcl, decrease the on-off ratio (shorten the on-time and lengthen the off-time). By performing such an operation at a specific period, the voltage Vcl of the first recovery capacitor C1 is controlled to become the reference voltage Vcs.
- the on / off ratio is set to a maximum value in advance and is limited to be less than or equal to the maximum value. Its maximum value is set to a value between 60% and 90%. It is preferable.
- the minimum value of the on / off ratio is 0%.
- the detection means for the voltage Vcl, the comparison means for the voltage Vcs, and the operation signal generation means for the third low-side recovery switch element S 13 may be formed by an analog circuit such as an operational amplifier. Further, it may be formed of an integrated circuit such as a microcomputer or a control IC, or a combination thereof.
- the control algorithm may be a known control algorithm such as proportional control, proportional integral control, proportional integral derivative control, etc.
- the reference voltage Vcs is set high. On the other hand, if the number of discharge pixels decreases, set the reference voltage Vcs low. Since the voltage Vcl of the first recovery capacitor C1 is controlled to be equal to the reference voltage Vcs, when the recovery operation is performed by forming a resonance circuit during the sustain discharge period, if the reference voltage Vcs is increased, The current through the inductor L1 increases, and the current through the first inductor L1 decreases when the reference voltage Vcs is lowered.
- the first discharge has a problem in that the discharge intensity varies depending on the number of discharge pixels because the current is defined (limited) by the inductor.
- the first embodiment for example, when the number of discharge pixels is large, the current flowing through the inductor can be increased by setting the reference voltage Vcs high. As a result, a sufficient discharge current can be supplied to each discharge pixel, and the discharge intensity does not decrease even when the number of discharge pixels increases. Conversely, when the number of discharge pixels is small, the current flowing through the inductor can be reduced by setting the reference voltage Vcs low. As a result, it is possible to supply the minimum necessary discharge current to each discharge pixel, and the discharge intensity does not increase even if the number of discharge pixels decreases.
- the discharge intensity in the first discharge for supplying the inductor discharge current becomes constant regardless of the number of discharge pixels. Therefore, the discharge intensity is stable even in the second discharge in which the current flows to the PDP 10 via the high-side sustain switch element, and as a result, there is no variation in luminance and a high-quality image can be displayed. .
- the image to be displayed is ⁇ or an image, etc., set a large number of gradations to reduce the luminance difference of the image. If as many as possible are set, the reference voltage Vcs is set to be small especially in the low gradation subfield. According to the present invention, it is possible to reduce the light emission luminance so that an image can be displayed even when the PDP 10 having a high light emission efficiency with a strong discharge intensity is used. Therefore, in the low gradation subfield, it is possible to display a high-quality image by reducing the light emission luminance itself. In addition, by reducing the capacitor voltage in the low gradation subfield and simultaneously reducing the number of sustain pulses in the high gradation subfield, an extra time in one field is generated.
- the present invention can provide a plasma display panel driving apparatus and a plasma display apparatus with higher image quality.
- the sustain pulse generating circuit 61 in the sustain electrode driving circuit 6 includes the second recovery inductor L2, the second recovery capacitor C2, the second high side recovery switch element S3, the second low side recovery switch element S4, A power recovery unit having a second high-side recovery diode D3 and a second low-side recovery diode D4; a second node, a second-side sustaining switch element; a second low-side sustaining switch element S8; and a constant voltage power source having a voltage value Vsus V5, and a second recovery capacitor by resonating the inductance of the capacitive load of PDP10 (the capacitive load generated in sustain electrodes SU1 to SUn) and second inductor L2. In this configuration, power is collected in C2.
- sustain pulse generating circuit 61 in sustain electrode drive circuit 6 is changed to sustain pulse in scan electrode drive circuit 5 described above. It may be the same as the generation circuit 51A.
- the plasma display panel driving circuit according to the second embodiment of the present invention is a modification of the control circuit of the sustain pulse generating circuit 51A described in the first embodiment. Therefore, the plasma display panel driving circuit and the plasma display device included in the present invention are the same as those in Embodiment 1 except for the control circuit of sustain pulse generating circuit 51A. Since the configuration may be the same as that in FIG.
- FIG. 6 is a circuit diagram of sustain pulse generation circuit 51B having a control circuit according to Embodiment 2 of the present invention.
- the specific circuit configuration and connection configuration of the first low-side recovery diode D2, the first high-side sustain switch element S5, and the first low-side sustain switch element S6 are the sustain pulse generating circuit according to the first embodiment 51. Same as A (see Figure 5).
- the control circuit of sustain pulse generating circuit 51B according to Embodiment 2 of the present invention includes a third inductor L3, a third low-side recovery switch element SI3, and a third high-side recovery switch element S. Including 12.
- One end of the third inductor L3 is connected to the connection point between the first recovery capacitor C1 and the drain terminal of the first high-side recovery switch element S1, and the other end is the drain of the third low-side recovery switch element S13.
- the source terminal of the third low-side recovery switch element S13 (emitter terminal in the case of IGBT) is connected to the GND terminal.
- the source terminal (emitter terminal) of the third high-side recovery switch element S12 is connected to the drain terminal (collector terminal) of the third low-side recovery switch element S13, and the third high-side recovery switch element S12.
- the drain terminal (collector terminal) is connected to the constant voltage power supply VI.
- the third high-side recovery switch element S12 and the third low-side recovery switch element S13 perform a PWM operation that turns on and off at a specific cycle according to a predetermined on / off ratio.
- the cycle of turning on and off when performing the PWM operation is generally in the range of about 2 microseconds to 50 microseconds, and may be a fixed cycle or a variable cycle.
- one of the switch elements S 12 and S 13 is always off, and there is no period during which both are on at the same time. It is preferable that the switch element S13 is off during the period in which the switch element S12 is performing the PWM operation at a certain on / off ratio.
- the on / off ratio of the third high-side recovery switch element S12 is increased.
- the third low-side recovery switch element S13 is operating at an on / off ratio that is not 0%, the on / off ratio of S13 is reduced to 0% and then the on / off ratio of S12 is increased. It is preferable to enlarge it.
- the voltage V cl of the first recovery capacitor C1 is controlled to become the reference voltage Vcs.
- the on-off ratio of the third low-side recovery switch element S13 is set in advance to a maximum value and is limited to be equal to or less than the maximum value.
- the maximum value is set to a value between 60% and 90%.
- the minimum value of the on / off ratio is 0%.
- the minimum value of the on-off ratio of the third non-side recovery switch element S 12 is 0%, and the maximum value is 100%.
- the means for detecting the voltage Vcl, the means for comparing with the voltage Vcs, and the operation signal generating means for the third high-side recovery switch element S 12 and the third low-side recovery switch element S 13 are calculated. It may be formed of an analog circuit such as an amplifier, an integrated circuit such as a microcomputer or a control IC, or a combination thereof.
- the control algorithm may be a known control algorithm such as proportional control, proportional-integral control, proportional-integral-derivative control. Further, the method for setting the reference voltage Vcs has been described in the first embodiment, and therefore will be omitted.
- the voltage Vcl of the first recovery capacitor C1 can follow the reference voltage Vcs at a higher speed.
- a plasma display panel driving circuit can be provided because of its followability. As a result, it is possible to create a video display with a more stable discharge intensity and high gradation.
- FIG. 7 is a circuit diagram of the data voltage generation circuit 41A according to the third embodiment of the present invention.
- the data voltage generation circuit 41A is included in the data electrode drive circuit 4 in the PDP device (see FIG. 4).
- the data voltage generation circuit 41A reduces the power consumption in the writing period.
- the data electrode drive circuit is provided with a circuit similar to the recovery circuit unit provided in the scan electrode (or sustain electrode) drive circuit. The charge stored in the panel during the writing period can be recovered.
- the plasma display panel driving circuit and the plasma display device according to Embodiment 3 of the present invention may have the same configuration as that of Embodiment 1 or Embodiment 2 except for the data voltage generation circuit 41A. Omitted.
- FIG. 7 is a circuit diagram of a data voltage generation circuit 41A having a control circuit according to Embodiment 3 of the present invention.
- the data voltage generation circuit 41A includes a data electrode drive inductor L41, a data electrode drive recovery capacitor C41, a data electrode drive high side recovery switch element S41, a data electrode drive low side recovery switch element S42, a data electrode drive high side recovery diode D41, A data electrode drive low side sustaining switch element S43 and a data electrode drive low side sustaining switch element S43 are provided.
- control circuit of the data voltage generation circuit 41A includes a second data electrode driving inductor L42, a second data electrode driving low side recovery switch element S47, and a data electrode driving diode. Includes D43.
- One end of the second data electrode driving inductor L42 is connected to the connection point between the data electrode driving recovery capacitor C41 and the drain terminal (collector terminal) of the first data electrode driving high side recovery switch element S41, and the other end is connected to the first terminal.
- Source terminal of second data electrode drive low side recovery switch element S47 Data terminal is connected to the GND terminal.
- the anode side of the data electrode drive diode D43 is connected to the drain terminal (collector terminal) of the second data electrode drive low side recovery switch element S47, and the power electrode side of the data electrode drive diode D43 is connected to the constant voltage power supply V6. Connected to.
- the second data electrode drive low-side recovery switch element S47 performs a PWM operation of turning on / off at a specific cycle according to a predetermined on / off time ratio.
- the period for performing the PWM operation is in the range of about 2 to 50 microseconds, and may be a fixed period or a variable period.
- the third low-side recovery switch element S13 in the drive circuit according to the first embodiment is replaced with the second data electrode drive low-side recovery switch element S47.
- the first recovery capacitor C1 is replaced with a data electrode drive recovery capacitor C41, the voltage Vc41 of the recovery capacitor C41 is detected and compared with the reference voltage Vc4s, and the result is fed back to the on / off ratio.
- the second data electrode drive low side recovery switch S47 may be driven. Furthermore, the maximum value and the minimum value of the on / off ratio are the same as those in the first embodiment. With this configuration, the voltage Vc41 of the data electrode drive recovery capacitor C41 is controlled to maintain the reference voltage Vc4s.
- the reference voltage Vc4s is set according to the number of address discharge pixels of each scan line in the address period.
- the relationship between the time until the start of the application of noise (hereinafter, this time is referred to as the write idle time) is expressed by an ideal equation that satisfies the conditions that reduce power consumption most.
- the capacitance on the data electrode side is the scan electrode Unlike the panel capacitance between the sustain electrodes, it changes depending on the logic state of the pixel to be discharged.
- the pixel Cij in Fig. 2 will be described as an example.
- the capacitance varies depending on whether or not adjacent pixels perform the write operation.
- a similar relationship is established with the pixel Cij + 1 on the right side of the pixel Cij.
- the capacitance between the adjacent data electrodes can be obtained by calculating the write operation for all the pixels of the PDP 10 between the adjacent pixels. Since this calculation can be performed by the video signal processing circuit 2 or the subfield processing circuit 3, the capacitance between the data electrodes can be obtained based on the calculation result.
- the capacitance changes depending on whether or not the writing operation is performed, and the number of changes is also the same in the video signal processing circuit 2 or the subfield processing circuit 3 as described above. Since it is possible to calculate, it is possible to determine the change in the capacitance in the vertical direction.
- the reference voltage Vc4s may be set. That is, If the result is increasing, the capacitance increases, so the reference voltage Vc4s should be set high. Conversely, if this result is a decreasing direction, the reference voltage Vc4s may be set low.
- the above setting is a setting of the ideal reference voltage Vc4s in the writing period.
- the reference voltage Vc4s during the writing period may be kept constant. If the power consumed by the operation of the control circuit itself is greater than the above-mentioned method of performing the switch operation by changing the ON / OFF ratio of the control circuit according to the number of discharge pixels, conversely This is because power loss increases. Therefore, set the reference voltage Vc4s to a constant value during the writing period.
- the value of the reference voltage Vc4s that should be kept constant in this way depends on the amount of change in the panel capacitance due to the change in the number of discharge pixels and the value of the panel capacitance itself, it cannot be set quantitatively. If the 50% force is set to a voltage value of about 90%, the power consumption can be greatly reduced. Of course, the setting value of the reference voltage Vc4s is not limited to this! /.
- the panel capacitance on the data electrode side can be properly recovered, and surplus power associated with the recovery can be determined without consuming the resistance. Since power can be regenerated in the voltage source, power loss can be reduced. Also, Since the voltage of the recovery capacitor can be controlled, the recovered power from the panel capacitance can be maximized, so that the power loss can be minimized. According to the present invention, a plasma display panel driving circuit and a plasma display device with low power consumption can be provided.
- the plasma display panel driving circuit according to the fourth embodiment of the present invention is a modification of the control circuit of the data voltage sustain pulse generating circuit 41A described in the third embodiment. Therefore, the plasma display panel driving circuit and the plasma display device included in the present invention have the same configuration as that of the third embodiment except for the control circuit of the data voltage sustain pulse generating circuit 41A. Description is omitted.
- FIG. 8 is a circuit diagram of a data voltage generation circuit 41B having a control circuit according to Embodiment 4 of the present invention.
- Data voltage generation circuit 41B includes data electrode drive inductor L41, data electrode drive recovery capacitor C41, data electrode drive high side recovery switch element S41, data electrode drive low side recovery switch element S42, data electrode drive high side recovery diode D41, data The electrode drive low side recovery diode D42, the data electrode drive high side sustain switch element S43, and the data electrode drive low side sustain switch element S4 4 are provided, and the circuit configuration and connection configuration are the data voltage sustain pulse generation circuit according to the third embodiment. The same as 41A.
- the control circuit of the data voltage generation circuit 41B according to Embodiment 4 of the present invention is the same as the control circuit of the sustain pulse generation circuit 51B according to Embodiment 2 described above. That is, the control circuit of the data voltage generation circuit 41B according to the fourth embodiment includes the second data electrode driving inductor L42, the second data electrode driving low side recovery switch element S47, and the second data electrode driving high side recovery switch element. Includes S46.
- One end of the second data electrode drive inductor L42 is connected to the connection point between the data electrode drive recovery capacitor C41 and the drain terminal (collector terminal) of the first data electrode drive high side recovery switch element S41, and the other end is the second. This is connected to the drain terminal of the data electrode drive low side recovery switch element S47.
- the source terminal (emitter terminal) of the second data electrode drive low-side recovery switch element S47 is connected to the GND terminal.
- the second data electrode drive low side recovery switch The source terminal (emitter terminal) of the second data electrode drive high-side recovery switch element S46 is connected to the drain terminal (collector terminal) of the switch element S47, and the drain terminal (collector terminal) is connected to the constant voltage power source V6. Connected.
- the setting of the ON / OFF ratio of the second data electrode drive high-side recovery switch element S46 and the second data electrode drive low-side recovery switch element S47 is the same as that described in the second embodiment. Description is omitted.
- the setting of the reference voltage Vc4s, which is the voltage target of the voltage Vc41 of the data electrode drive recovery capacitor C41, is the same as that described in the third embodiment, and thus the description thereof is omitted (see FIG. 7).
- the control circuit with the second data electrode driving high-side switch element S46, the voltage of the data electrode driving recovery capacitor C41 can follow the reference voltage with high accuracy. As a result, the power consumption can be further reduced.
- the plasma display device has at least two data electrode drive circuits according to Embodiment 3 or 4.
- the voltage application timing of the write operation is different.
- the two voltage application timings are, for example, in a state as shown in FIG. 9 described below.
- the plasma display device includes means for solving the problem that the writing operation that occurs with the increase in the screen size and the resolution of the panel cannot be performed correctly.
- the address discharge current increases as the screen becomes larger and the definition becomes higher, a large voltage drop occurs in the scan pulse, and the write operation becomes unstable when the write operation becomes unstable. Therefore, a means of changing the timing of the data application voltage is used to prevent the write operation from becoming unstable.
- FIG. 9 is a diagram showing the waveforms of the scan electrode voltage SCn in the address period and the data electrode voltages Dml and Dm2 at different timings.
- the high-side recovery switch element S41 of the data electrode recovery circuit is turned on and the data electrode voltage rises.
- Dml and time t2 when a predetermined time has elapsed from tl Meanwhile, the high-side recovery switch element S41 is turned on and the data electrode voltage rises.
- Two different data electrode drive circuits for Dm2 are provided. In this way, by varying the timing of the voltage applied to the data electrode, the time at which address discharge occurs is varied, resulting in a smaller address discharge current peak value and stable address operation.
- the gist of Embodiment 5 of the present invention is not only in the voltage application timing shift as described above, but in a plurality of data electrode drive circuits with different voltage application timings as shown in FIG.
- the reference voltage is set to control the recovery capacitor voltage.
- the set value of the reference voltage is different from that of the embodiment 3 or 4.
- the data electrode drive circuit for applying a voltage to the data electrode as in the voltage application waveform Dml may be the same as that for setting the reference voltage Vc4s shown in the third or fourth embodiment, but drives Dm2 with a slow voltage application timing.
- the data electrode driving circuit is different from that shown in the third or fourth embodiment.
- Vc4s of the data electrode drive circuit that drives Dm2 is set as follows: Dm2 voltage value Vm2L in the period from when the scan pulse is applied to when the data electrode voltage is applied until tl force t2 Do not decrease the force wall charge! /, It is only necessary to make the voltage value as low as possible.
- the voltage value Vm2L is high, and when the voltage of the recovery capacitor is low, the voltage value Vm2L is low. Therefore, the value of Vm2L that does not cause the address operation to become unstable may be obtained experimentally, for example, and the voltage value of the recovery capacitor may be determined to be equal to or greater than the obtained Vm2L.
- the recovery capacitor voltage at this time also changes depending on conditions such as the number of pixels to be lit, so Vc4s may be set according to the panel capacitance as in Embodiment 3, and during the writing period, It may be a constant value.
- the plasma display device has at least two data electrode drive circuits according to the third or fourth embodiment.
- the voltage application timing of the write operation is also different as in the fifth embodiment, and the two voltage application timings are also in, for example, the state shown in FIG. Will be.
- the gist of Embodiment 5 of the present invention is that a plurality of data electrode driving circuits having different voltage application timings as shown in FIG. This is to vary the inductance value of the data electrode drive inductor L41.
- the inductance value L41ml of the first data electrode drive inductor L41 used in the data electrode drive circuit that outputs the voltage application waveform Dml and the data electrode drive circuit that outputs the voltage application waveform Dm2 are used in the first.
- L41m2 should be set in the range of 1.5 to 4 times that of L41ml.
- the L41m2 direction force is set to a value larger than SL41ml.
- Each of the switch elements described in the first to fourth embodiments may be an IGBT, a MOSFET, a transistor using GaN or SiC, or the like.
- FIG. 5 to FIG. 8 are circuit diagrams with MOSFET in mind, and the description of the embodiment also has been described with MOSFET in mind, but the present invention is not limited to MOSFETs. However, in the case of a transistor such as an IGBT that does not include a parasitic diode inside, an antiparallel diode may be connected.
- the present invention relates to a plasma display panel driving circuit and a plasma display device, and as described above, has effects such as reduction in power consumption and improvement in image quality, and is thus industrially useful.
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- General Physics & Mathematics (AREA)
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Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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CN2007800069471A CN101390147B (zh) | 2006-02-13 | 2007-02-08 | 等离子显示面板驱动电路及等离子显示装置 |
US12/279,016 US20090219272A1 (en) | 2006-02-13 | 2007-02-08 | Plasma display panel drive circuit and plasma display device |
JP2008500462A JP4338766B2 (ja) | 2006-02-13 | 2007-02-08 | プラズマディスプレイパネル駆動回路 |
Applications Claiming Priority (4)
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JP2006-034816 | 2006-02-13 | ||
JP2006034816 | 2006-02-13 | ||
JP2006251162 | 2006-09-15 | ||
JP2006-251162 | 2006-09-15 |
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PCT/JP2007/052202 WO2007094227A1 (ja) | 2006-02-13 | 2007-02-08 | プラズマディスプレイパネル駆動回路およびプラズマディスプレイ装置 |
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US (1) | US20090219272A1 (ja) |
JP (1) | JP4338766B2 (ja) |
KR (1) | KR20080094051A (ja) |
CN (1) | CN101390147B (ja) |
WO (1) | WO2007094227A1 (ja) |
Cited By (1)
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WO2009098879A1 (ja) * | 2008-02-06 | 2009-08-13 | Panasonic Corporation | 容量性負荷駆動装置、それを搭載するプラズマディスプレイ装置、およびプラズマディスプレイパネルの駆動方法 |
Families Citing this family (6)
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CN101755297B (zh) * | 2007-07-19 | 2012-10-10 | 松下电器产业株式会社 | 等离子体显示面板的驱动装置、驱动方法及等离子体显示装置 |
WO2009013862A1 (ja) * | 2007-07-25 | 2009-01-29 | Panasonic Corporation | プラズマディスプレイ装置およびその駆動方法 |
KR101109842B1 (ko) * | 2007-08-08 | 2012-03-13 | 파나소닉 주식회사 | 플라즈마 디스플레이 패널의 구동 장치, 구동 방법 및 플라즈마 디스플레이 장치 |
JP5260002B2 (ja) * | 2007-08-20 | 2013-08-14 | 株式会社日立製作所 | プラズマディスプレイ装置 |
US20110109653A1 (en) * | 2007-09-03 | 2011-05-12 | Panasonic Corporation | Plasma display panel apparatus and driving method of plasma display panel |
JP5249325B2 (ja) | 2008-05-29 | 2013-07-31 | パナソニック株式会社 | 表示装置およびその駆動方法 |
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JP2001075528A (ja) * | 1999-09-02 | 2001-03-23 | Matsushita Electric Ind Co Ltd | 表示装置およびその駆動方法 |
JP2002156841A (ja) * | 2000-09-07 | 2002-05-31 | Bridgestone Corp | 転写ローラ及び画像形成装置 |
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JPH0845663A (ja) * | 1994-02-09 | 1996-02-16 | Nec Kansai Ltd | El素子点灯装置 |
KR0147590B1 (ko) * | 1994-06-03 | 1998-12-01 | 윤종용 | 매트릭스형 액정표시소자 구동 장치 및 방법 |
US5642018A (en) * | 1995-11-29 | 1997-06-24 | Plasmaco, Inc. | Display panel sustain circuit enabling precise control of energy recovery |
JP3399508B2 (ja) * | 1999-03-31 | 2003-04-21 | 日本電気株式会社 | プラズマディスプレイパネルの駆動方法及び駆動回路 |
DE60022481T2 (de) * | 1999-11-12 | 2006-06-08 | Matsushita Electric Industrial Co., Ltd., Kadoma | Plasmaanzeigevorrichtung und verfahren zu ihrer ansteuerung |
US7053869B2 (en) * | 2000-02-24 | 2006-05-30 | Lg Electronics Inc. | PDP energy recovery apparatus and method and high speed addressing method using the same |
JP4660026B2 (ja) * | 2000-09-08 | 2011-03-30 | パナソニック株式会社 | 表示パネルの駆動装置 |
JP4050724B2 (ja) * | 2003-07-11 | 2008-02-20 | 松下電器産業株式会社 | 表示装置およびその駆動方法 |
US20070205964A1 (en) * | 2004-04-12 | 2007-09-06 | Matsushita Electric Industrial Co., Ltd. | Plasma display panel display device |
JP4676957B2 (ja) * | 2004-05-31 | 2011-04-27 | パナソニック株式会社 | プラズマディスプレイ装置 |
US7633467B2 (en) * | 2004-11-24 | 2009-12-15 | Lg Electronics Inc. | Plasma display apparatus and driving method thereof |
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2007
- 2007-02-08 CN CN2007800069471A patent/CN101390147B/zh not_active Expired - Fee Related
- 2007-02-08 JP JP2008500462A patent/JP4338766B2/ja not_active Expired - Fee Related
- 2007-02-08 US US12/279,016 patent/US20090219272A1/en not_active Abandoned
- 2007-02-08 KR KR1020087019821A patent/KR20080094051A/ko not_active Application Discontinuation
- 2007-02-08 WO PCT/JP2007/052202 patent/WO2007094227A1/ja active Application Filing
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JP2001075528A (ja) * | 1999-09-02 | 2001-03-23 | Matsushita Electric Ind Co Ltd | 表示装置およびその駆動方法 |
JP2002156841A (ja) * | 2000-09-07 | 2002-05-31 | Bridgestone Corp | 転写ローラ及び画像形成装置 |
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WO2009098879A1 (ja) * | 2008-02-06 | 2009-08-13 | Panasonic Corporation | 容量性負荷駆動装置、それを搭載するプラズマディスプレイ装置、およびプラズマディスプレイパネルの駆動方法 |
Also Published As
Publication number | Publication date |
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JP4338766B2 (ja) | 2009-10-07 |
US20090219272A1 (en) | 2009-09-03 |
CN101390147B (zh) | 2010-09-29 |
JPWO2007094227A1 (ja) | 2009-07-02 |
KR20080094051A (ko) | 2008-10-22 |
CN101390147A (zh) | 2009-03-18 |
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